_ a FEATURES 5V + 10% write and erase JEDEC-standard EEPROM commands Minimum 1,000/10,000 write/erase cycles Fast access time: 100/120/150ns Sector erase architecture - 8 equal sectors of 128k bytes each - Sector erase time: 50ms typical Auto Erase and Auto Program Algorithms - Automatically erases any one of the sectors or the whole chip with Erase Suspend capability - Automatically programs and verifies data at specified addresses Status Register feature for detection of program or erase cycle completion * Low VCC write inhibit < 3.2V. Software and hardware data protection GENERAL DESCRIPTION The MX29F8100 is a 8-mega bit Flash memory organized as either 512K wordx16 or 1M bytex8. The MX29F8100 includes 8-128KB(131,072) blocks or 8-64KW(65,536) blocks. MXIC's Flash memories offer the most cost- effective and reliable read/write non-volatile random access memory. The MX29F8100 is packaged in 48-pin TSOP or 44-pin SOP. For 48-pin TSOP, CE2 and RY/BY are extra pins compared with 44-pin SOP package. This is to optimize the products (such as solid-state disk drives or flash memory cards) control pin budget. PWD is available in 48 -pin TSOP for low power environment. All the above three pins(CE2,RY/BY and PWD) plus one extra VCC pin are not provided in 44-pin SOP. it is designed to be reprogrammed and erased in-system or in-standard EPROM programmers. : The standard MX29F8100 offers access times as fast as 100ns, allowing operation of high-speed microprocessors without wait. To eliminate bus contention, the MX29F8100 has separate chip enables(CE1 and CE2)}, output enable (OE), and write enable (WE) controis. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29F8100 uses a command register to manage this functionality. The command register allows for 100% TTL level controi inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. SOREL MMARY MxX29SF84100 SM-BITII1M x 8/51 46 SINGLE VOLTAGE ELASH EEPROM * Page program operation - Internal address and data latches for 128 bytes/64 words per page - Page programming time: 3ms typical - Byte programming time: 16us in average * Low power dissipation - 50mA active current - 100uA standby current CMOS and TTL compatible inputs and outputs * Two independently Protected sectors * Deep Power-Down Current - 1A ICC typical * industry standard surface mount packaging - 48 lead TSOP, TYPE I - 44 lead SOP To allow for simpie in-system reprogrammability, the MX29F8100 does not require high input voltages for programming. Five-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading from an EPROM. MXC Flash technology reliably stores memory contents even after 1,000/10,000 erase and program cycles. The MXIC's cell is designed to optimize the erase and programming mechanisms. tn addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX29F8100 uses a 5V + 0% VCC supply to perform the Auto Erase and Auto Program algorithms. The highest degree of latch-up pratection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC +1V. PIN: PMQ-262 REV.7.6, SEP 25, 199648 TSOP(TY! PYPE 1) (12mm x 20mm) _ RYIBY. 1 4 we | o 44 NP ANG 20 8 aie | 2 43 | AIS a 3 46 |. AIT 3 42 AB MS 5 45 Ay 4 41 Ag AID 6 44 ag | 5 ao | AIG Att 7 3 as | 6 39 |. Att Ato. | 8 2 a4 7 38 Al2 Ag g 40 as | 3 3 a7 f Ala Ag: 0 2 2 |g 36 |. Ala A19 38 AI 10 & 3 | Ais w 8 MX29F8100 37 AO Yt GB ow] Als. ais | fa 36 cer | 12 NW 33 | BYTE AI? 15 36 cup | 13 3 a2} ano a7 16 9% OE 14 3t QU5IA-1 AB 17 32 oo 415 x | a7 AS 18 a QB 16 29 Qi4 Ad 19 at a i" 2a} O68 AS 30 0 as | 16 27 | ata a 39 28 a2 19 26 {| O5 nO 23 27 aro 20. 25 Qi2 vec | 24 26 os | 21 24 | . O 25 au 22 23 | vec (NORMAL TYPE) 48 PDIP No ft) ~ 4g} NC NC 2 47] NC san 48 We (3 46 | WE bee | a7 3 A18 4 45 AIS GND 46 13 AI7 .|5 aa As OISV/A-1 45 4 A7 16 4a ag a7 a4 5 46 7 427 Ato Qa | 4a 6 as (8 a:[ att os - 2 ? a a4 '|9 so}. At og" | 40 a az }10 ao}. aia . 3 L Qrw 39 10 az fit Boga Ata a4 | 38 i" Al 112) @ a7]. ANS veo. | 37 MX29F8100 12 Ao | 13 36 [ ate Qt 36 13 CE: =| 14 35 BYTE a3 35 14 GND :/15 Baa}. GND aio 34 18 OE [16 33} Q15A-1 q2 | 3 16 eo 17 ae} o7 Qa x v7 ae 118 sit: ats ar 14 ag f 30 19 at 19 30/- O68 go 29 20 og ] 20 29}. O13 of | 28 21 Q2 121 28 05 GND 27 22 Qin [22 27 |. are Cet 26 23 a3 (|2 26] Od CE2 25 24 ow |24 2s | vec : (REVERSE TYPE) FIN DESCRIPTION SYMBOL PIN NAME SYMBOL PIN NAME AQ-A18 = Address Input WE Write Enable Input Q0-Q14 Data Input/Output RY/BY Ready/Busy Output Q15/A-1 @15(Word mode)/LSB addr.(Byte mode) we Sector Write Protect Input CE1/CE2 Chip Enable Input BYTE Word/Byte Selection Input PWD Deep Power- Down input voc Power Supply OE GND Ground Pin Output Enable Input A19 : is suggested hard-wired to GND or VCC to minimize TTL current.BLOCK DIAGRAM we CEuCER pn, | CONTROL dE ; uo INPUT we Losic Pwd } BYTE ok ' " PAGE i 2 7 - & ! Qeaisiads < 7 | we | | | & | MX29F8100 | oI ones | 5 : FLASH | LATCH | a atgas 2S. ryvis ARRAY AoAIS OL AND | a Qo i BUFFER Ls 8 | Y-PASS GATE ; Lo) B | #1. ! 7 4 3 SO sO PGM | SENSE | | DAT _AMPLIFIER| | HV if -it 1 ' [PROGRAM Lo tot TALATCH| 1 DATA LATCH an WRITE STATE |- MACHINE i COMMAND INTERFACE REGISTER (CIR) / COMMAND! DATA | DECODER Le. St ee COMMAND | DATALATCH 58-3AO - AIS TYPE INPUT NAME AND FUNCTION ADDRESS INPUTS: for memory addresses. Addresssafe intemally latched during a write cycle, A19 don't care.(hard wired to VCC or GND is suggested) QO - Q7 INPUT/OUTPUT LOW-BYTE DATA BUS: Input data and commands during Command interface Register(CIR) write cycles. Outputs array,status and identifier data in the appropriate read mode. Floated when the chip is de-selected or the outputs are disabled. Q8 - Q14 INPUT/OUTPUT HIGH-BYTE DATA BUS: Inputs data during x 16 Data-Write operations. Outputs array, identifier data in the appropriate read mode; not used for status register reads. Floated when the chip is de-selected or the outputs are disabled. QI5/A -1 INPUT/OUTPUT Selects between _high-byte data INPUT/OUTPUT(BYTE = HIGH) and LSB ADDRESS(BYTE = LOW) CE1/CE2 INPUT CHIP ENABLE INPUTS: Activate the device's control logic, Input buffers, decoders and sense amplifiers. With either CE1 or CE2 high, the device is de- slectd and power consumption reduces to Standby level upon completion of any current program or erase operations. Both CE1,CE2 must be low to select the device. C&2 is not provided in 44-pin SOP package. All timing specifications are the.same for both signals. Device selection occurs with the latter falling edge of CE1 or CE2. The first rising edge of CE1 or CE2 disables the device. PWD INPUT POWER-DOWN: Puts the device in deep power-down mode. PWD is active low; PWD high gates normal operation. PWD also locks out erase or program operation when active low providing data protection during power transitions. INPUT OUTPUT ENABLES: Gates the device's data through the output buffers during a read cycle OE is active low. INPUT WRITE ENABLE: Conirols writes to the Command Interface Register(CIR). WE is active low. OPEN DRAIN OUTPUT READY/BUSY: Indicates the status of the internal Write State Machine(WSM). When low it indicates that the WSM is performing a erase or program operation. RY/BY high indicate that the WSM is ready for new commands, sector erase is suspended or the device is in deep power-down mode. R'Y/BY is always active and does not fleat to tristate off when the chip is deselected or data output are disabled. INPUT WRITE PROTECT: Top or Bottom sector can be protected by writing a non- volatile protect-bit for each sector. When WP is high, all sectors can be programmed or erased regardiess of the state of the protect-bits. The WP input buffer is disabled when PWD transitions low(deep power-down mode). BYTE INPUT BYTE ENABLE: BYTE Low places device in x8 mode. All data is then input or output on Q0-7 and Q8-14 float. AddressQ15/A-1 selects between the high and low byte. BYTE high places the device in x16 mode, and turns off the Q15/ A-1 input buffer. Address AO, then becomes the lowest order address. vec DEVICE POWER SUPPLY(5Vi10%) GND GROUNDM=zic | MxX298F8100 BUS OPERATION Flash memory reads, erases and writes in-system via the local CPU. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. Table 2.1 Bus Operations for Word-Wide Mode (BYTE = VIH) | Mode | Notes PWD) CEt| CE2 | GE | WE | AO | Ai | AS Q0-Q7 | O8-Q14 | O15/A-1 | RY/BY \ [Read 12,7; VIH | VIL] VIL | VIL | VIR | X x Xx DOUT DOUT DOUT x L OutputDisable 1.6.7 | VIH } VIL | VIL } VIR | VIR | xX x x High HighZ HighZ X ' Standby ; 16,7 | VIH: VIL |] VIH | X x xX : X xX Highz High2 HighzZ X VIH | VIL | ' i VIH_ | VIH co + DeepPower-Down! 1,3 | VIL x x Xx x x Xx x HighZ HighZ HighZ VOH af. ManufactureriID | 4,8 VIH | VIL | WL | VIL | VI | VIL | VIL | VID C2H OOH; 0B VOH DevicelD 48 VIH ? MIL | VIL EVIL | VIM | VIH FT VIL | VID 88H 00H 0B VOH 4. Write 15,6 | VIH | VIL | VIL |VIH | ViL | XxX x X BIN DIN DIN Xx Table2.2 Bus Operations for Byte-Wide Mode (BYTE = VIL) Mode Notes| PWD] GE1/CE2|OE | We | ao [at | ao | ao-a7 | as-a14 |a1s/a-1 | RYBY Read 1279] viH| vi | vi |vin| vin | x | xX | X | DOUT | Highz | VIVWIH x OutputDisable | 16,7] VIH | VIL; ViL |vIH| VIH | X | xX | X | HighZ | Highz x x Standby 16.7{ vin | vif vi] x | x 7 xX | xX | xX |) HighZ | Highz x x VIH | VIL ViH_ | VIH . | DeepPower-Down| 1,3 5 VIL x x Xi xX 1X x x HighZ HighZ x VOH ! ManufacturetD | 48 | VIH | VIL| VIL [VIL | VIH }VIL [VIL |; WiD| C2H | HighZ VAL VOH +. DevicelD 48 ) VIH;} vit| VIL |ViL i VIH [Vi | viL | vip | 88H HighZ vi. | ~VOH , t t Write 156| VIR| VL[ VU IVWIH) vii | x |x Xx DIN. | Highz | VILIH |X - L 1 i ee 1 Lo __t NOTES : 4.% can be VIH or VIL for address or control pins except for RY/BY which is either VOL orVOH. 2.RY/BY output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode, RY/BY will be at VOH if itis tied to VCC through a 1K ~ 100K resistor. When the RY/BY at VOH is independent of OE while a WSM operation is in progress. 3.PWD at GND + 0.2V ensures the iowest deep power-down current. 4, AO and A1 at VIL provide manutacturer !D codes, AQ at VIH and A1 at VIL provide device ID codes. AO at VIL, Ai at VIH and with appropriate sector addresses pravide Sector Protect Code.(Refer to Table 4} 5. Commands for different Erase operations, Data program operations or Sector Protect operations can only be successfully completed through proper command sequence. 6.Whife the WSM is running. RY/BY in Level-Mode stays at VOL until all operations are complete. RY/BY goes to VOH when the WSM is not busy orin erase suspend mode. 7. AY/BY may be at VOL while the WSM is busy performing various operations. For example, a Status register read during a write operation. 8. VID = 11.5V- 12.5V. 9. Q15/A-1 = VIL, QO - Q7 =DO-D7 out. Q15/A-1 = VIH, QO - Q7 = DB -D15 out. 58-5WRITE OPERATIONS Commands are written to the COMMAND INTERFACE REGISTER (CIR) using standard microprocessor write timings. The CIR serves as the interface between the microprocessor and the internal chip operation. The CIR can decipher Read Array, Read Silicon 1D, Erase and Program command. Inthe event ofa read comraand, the CIR simply points the read path at either the array or the silicon ID, depending on the specific read command given. For a program or erase cycle, the CIR informs the write state machine that a program or erase has been requested. During a program cycle, the write state machine will control the program sequences and the CIR TABLE 3. COMMAND DEFINITIONS Read/ Reset Silicon ID Read Write d 4 4 Bus Cycle Bus Cycle Bus Write Cycle Bus ! Bus Write Cycle Sixth Bus Write Cycle MX29F87180 will only respond to status reads. During a sector/chip erase cycle, the CIR will respond to status reads and erase suspend. After the write state machine has completed its task, it will allow the CIR to respond to its full command set. The CIR stays at read status register mode umtil the microprocessor issues another valid command sequence. Device operations are selected by writing commands into the CIR. Table 3 below defines 8 Mbit flash family command. (Erase Erase Read Resume {Status 3 4 58-6M= ic MxX29SF81 COMMAND DEFINITIONS(continue Table 3.) I Command Sector Sector Verify Sector Sleep Abort | Sequence Protection | Unprotect Protect ! Bus Write 6 6 4 3 3 Cycles Rea'd _| First Bus Addr 5555H_ 1 S555H BS555H 55554 55554 Write Cycle Data AAH AAH AAH AAH AAH Second Bus Addr 2AAAH 2AAAH ZAAAH 2AAAH 2AAAH | Write Cycle Data 55H 55H 55H 55H 55H : Third Bus Ager 5555H 5555 555H 5555H. 5555H Write Cycle Data 60H 60H 90H COH EOH | Fourth Bus Addr 5555H 5555H : __J Read/Write Cyclel Data AAH AAH C2H" Fifth Bus Addr 2AAAH 2AAAH {Write Cycle Data 55H 55H Sixth Bus Addr SA SA" _ Write Cycle Data 20H 40H Notes: 1.Address bit A15 -- A18 = X = Don't care for all address commands except for Program Address(PA) and Sector Address(SA). 5555H and 2AAAH address command codes stand for Hex number starting from AO to A14. 2. Bus operations are defined in Tabie 2. 3. RA = Address of the memory location to be read. PA = Address of the memory focation to be programmed. Addresses are latched on the falting edge of the WE pulse. SA = Address of the sector fo be erased, The combinatian of A16 -- A18 will uniquely select any sector. 4, RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of We. SRD = Data read from status register. 5. Only Q0-Q7 command data is taken, Q8-Q15 = Don't care. * Refer to Table 4, Figure 12. ** Only the top and the bottom sectors nave protect- bit feature. SA = (A18,A17,A16) = QOOB or 111B is valid. 58-7> ype MaIc DEVICE OPERATION SILICON ID READ The Silicon {D Read mode allows the reading out of a binary code from the device and will identify its manufacturer and type. This made is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID (11.5V~12.5V) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address AO from VIL to VIH. Alf addresses are don't cares except AO and At. The manufacturer and device codes may also be read via the command register, for instances when the MX2SF8100 MX29F8100 is erased or programmed in a system without access to high voltage on the AQ pin. The command sequence.is illustrated in Table 3. Byte 0 (AD=VIL) represents the manfacturer's code (MXIC=C2H) and byte 1 (AO=ViH) the device identifier code (MX29F8100=88H). Yo terminate the operation, it is necessary to write the read/reset command sequence into the-CIR. Pe Table 4. MX29F8100 Silion ID Codes and Verify Sector Protect Code Ag | Ai | Aye | A, | A, | Code(HEX) DQ,; DG, r DG, | DQ,) DQ,; DQ,; DG, | Da, : Manufacturer Code xX x X VIL | VIL C2H* 1 1 | 0 0 0 0 1 0 | MX29F8100 Device Code x Xx X VIL | VIH i 88H" 1 0 0 0 1 0 0 0 Verify Sector Protect Sector Address*** VI | VIL G2H** 1 1 0 0 0 0 1 0 * MX29F8100 Manufacturer Code = C2H, Device Code = 88H when BYTE = VIL MX29F8100 Manufacturer Code = 00C2H, Device Code = 0088H when BYTE = VIH ** Outputs C2H at protected sector address, OOH at unprotected scetor address. *Only the top and the bottom sectors have protect-bit feature. Sector address = ( A18,A17,A16) =O00B or 1118 58-3READ/RESET COMMAND The read or reset operation is initiated by writing the read/ reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabfed for reads until the CIR contents are altered by a valid command sequence. The device will automatically power-up in the read/reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. The MX29F8100 is accessed like an EPROM, When CE and OE are low and WE is high the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in.the high impedance state whenever CE or OE is high. This dual line contro} gives designers flexibility in preventing bus contention. CE stands for the combination of CE1 and CE2 in 48-pin TSOP package. CE stands for CEI in 44-pin SOP package. Note that the read/reset command is not valid when program or erase is in progress. PAGE PROGRAM To initiate Page program mode, a three-cycle command sequence is required. There are two " unlock" write cycles. These are followed by writing the page program command-A0H. Any attempt to write to the device without the three-cycle command sequence will not start the internal Write State Machine(WSM), no data will be written to the device. After three-cycle command sequence is given. a byte(word) load is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high, The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Maximum of 128 bytes of data may be loaded into each page by the same procedure as outlined in the page program section below. MX29F8100 BYTE-WIDE LOAD/WORD-WIDE LOAD Byte(word) loads are used to enter the 128 bytes(64 words) of a page to be programmed or the software codes for data protection. A byte toad(word load) is performed by applying alow. pulse on the: WE or CE input with CE or WE low (respectively) and OE high.. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Either byte-wide load or word-wide load is determined(Byte = VIL or VIH is latched) on the falling edge of the WE(or CE) during the 3rd command write cycle. PROGRAM Any page to be programmed should have the page in the erased state first, i.e. performing sector erase is suggested before page programming can be performed. The device is programmed on a page basis. If a byte(word). of data within a page is tobe changed, data for the entire page can be loaded into the device. Any byte(word) that is not loaded during the programming of its page will be still in the erased state (i.e. FFH). Once the bytes of a page are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data byte(word) has been loaded into the device, successive bytes(words} are entered in the same manner. Each new byte(word) to be programmed must have its high to low transition on WE (or CE) within 30us of the low to high transition of WE (or CE) of the preceding byte(word)}. A6 to A18 specify the page address, i.e., the device is page-aligned on 128 bytes(64 words)boundary. The page address must be valid during each high to low transition of WE or CE. A-7 to A5 specify the byte address within the page, AO to AS specify the word address withih the page. The byte(word) may be loaded in any order; sequential loading is not required. If a high to low transition of CE or WE is not detected whithin 100ps of the last low to high transition, the load period will end and the internal programming period will start. The Auto page program terminates when status on DQ7 is "t' at which time the device stays at read status register mode until the CIR contents are altered by a valid corymand sequence.(Refer to table 3,6 and Figure 17,8) 58-9CHIP ERASE. Chip erase is asix-bus cycle: operation. There are two "unlock" write cycles. These ar followed by writing the "set-up" command-80H. Two more*tinlock" write cycles are then: followed: by the chip erase comrnand-10H. Chip erase does not require the user'to program the device prior to erase. The automatic erase begins on the rising edge of the last WE pulse in the: command sequence and terminats when the status on DQ7is "1" at which-ime the device stays at read status.register mode. The device remains enabled for read status register mode until the CIR contents are altered by a valid command sequence. (Refer to table 3,6 and Figure 2,7,9) Table 5. MX29F8100 Sector Address Table (Byte-Wide Mode) A19)} A18| A17| A16: Address Range{A18, -1] . Q 0.1.0 Sao | Xx Q0000H--1FFFFH sar |X | 0] 0/4 20000H--3FFFFH SA2 |X | 0 | 1 | 0 | 40000H--SFFFFH saz} xj ofe4 | i 60000H--7FFFFH saa | x 80000H--9FFFFH sai7;x [1/4 / 4 E0000H--FFFFFH SECTOR ERASE Sector. erase is a-six-bus cycle operation.. There are two untock" write cycles. These.are followed by writing the set-up. command-80H.. Two more "unloek" write cycles are then followed by the sector erase, command-30H. The sector address is latched on the falling edge of WE, while the command (data) is latched on the rising. edge of WE. Sector erase does not-require the user to program the device prior to erase. The system is not required to provide any controls or timings during thse operations. The automatic sector erase begins. on: the fising edge of the last WE pulse in the command. sequence and terminates when the status n DQ7 is "1" at which time the device stays at read status register mode.. The device remains enabled for read status register mode until the CIR contents: are altred by a valid command sequence.(Refer to table 3, 6 and Figur.3,4,7,9)) ERASE SUSPEND This command only has meaning while the the WSM is executing SECTOR or CHIP erase operation, and therefore will only be responded to during SECTOR or CHIP erase operation. After this command has: been executed, the CIR will initiate the WSM to suspend erase Operations, and then returri to Read Status Register mode. The WSM will set the DQ6 bitte a"1". Onee the WSM has reached the Suspend state,the WSM will set the DQ7 bit to a"1", At this time, WSM allows the CIR to respond to the Read Array, Fiead Status Register, Abort and Erase-Resume commands: only. In this mode, the CIR will not resopnd to any other comands. The WSM will continue to run, idling in the SUSPEND state, regardless of the state-of all input control pins, with the exctusion of PWD. PWD low will immediately shut down the WSMand the remainder of the chip. ERASE RESUME This command will cause the CIR to clear the suspend state and set the DGS to a0, but only if an Erase Suspend command was previously issued. . Erase Resume will not have any effect in all other conditions. 58-10READ STATUS REGISTER The MXIC's 8 Mbit flash family contains a status register which may be read to determine when a program or erase operation is complete, and whether that operation completed successfully. The status register may be read at any time by writing the Read Status command to the CIR. After writing this command, all subsequent read operations output data from the status register until another valid command sequence is written to the CIR. A Read Array command must be written to the CIR to return to the Read Array mode. The status register bits are output on DQ2 - DQ7(table 6) whether the device is in the byte-wide (x8) or word-wide (x16) mode for the MX29F8100. In the word-wide mode the upper byte, DQ(8:15) is set to OOH during a Read Status command. in the byte-wide mode, DQ(8:14) are tri-stated and DQ15/A-1 retains the low order address function. DQ0-DQ1 is set to OH in either x8 or x16 mode. It should be noted that the contents of the status register are latched on the falling edge of OE or CE whichever occurs last in the read cycle. This prevents possible bus errors which might occur if the contents of the status register change while reading the status register. CE or OE must be toggled with each subsequent status read, or the completion of a program or erase operation will not be evident. The Status Register is the interface between the microprocessor and the Write State Machine (WSM). When the WSM is active, this register will indicate the status of the WSM, and will also hold the bits indicating whether or not the WSM was successful in performing the desired operation. The WSM sets status bits four through seven and clears bits six and seven, but cannot clear status bits four and five. If Erase fall or Program fail status bit is detected, the Status Register is not cleared until the Clear Status Register command is written. The MX29F8100 automatically outputs Status Register data when read after Chip Erase, Sector Erase, Page Program or Read Status Command write cycle. The default state of the Status Register after powerup and retum from deep power-down mode is (DQ7, DQ6, DO5, DQ4) = 1000B. DQ3=Cor 1 depends on sector-protect status, can not be changed by Clear Status Register Command cr Write State Machine. DQ2 = 0 or 1 depends on Sleep status. During Sleep mode or Abort mode DQ2 is sat to "1"; DQ2 is reset to O" by Read Array command. MxX28SF8100 CLEAR STATUS REGISTER The Eraes fail status bit (DQ5) and Program fail status bit ({DQ4) are set by the write state machine, and can only be reset by the system software. These bits can indicate various failure conditions(see Table 6). By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several pages or erasing multiple blocks in squence). The status register may then be read to determine if an error occurred during that programming or erasure series. This adds flexibility to the way the device may be programmed or erased. Additionally, once the program(erase) fail bit happens, the program (erase) operation can not be performed further. The program(erase) fail bit must be reset by system software before further page program or sector (chip) erase are attempted. To clear the status register, the Clear Status Register command is written to the CIR. Then, any other command may be issued to the CIR. Note again that before a read cycle can be initiated, a Read command must be written to the CIR to specify whether the read data is to come from the Array, Status Register or Silicon ID. 58-11TABLE 6. MX29F8100 STATUS REGISTER STATUS NOTES |DQ7 DQs D@3/ Daz IN PROGRESS PROGRAM 12,67 | 0 0. oft | Ov ERASE 13,67 | 0 oO o/t | ort SUSPEND (NOT COMPLETE) 14.6.7 | 0 0 ot | Of (COMPLETE) 1 0 on | 0 COMPLETE PROGRAM 1,2, 6,7 1 0 ov | O/1 ERASE 1,3, 6,7 1 0 on | 0/1 FAIL PROGRAM 1,5, 6,7 1 0 oft | Of ERASE 1,5, 6,7 1 1 of | Off AFTER CLEARING STATUS REGISTER 6,7 t 0 O14; * _ NOTES: 1. DQ7 : WRITE STATE MACHINE STATUS 1 = READY. 0 = BUSY DQ6 . ERASE SUSPEND STATUS 1 = SUSPEND, 0 = NO SUSPEND DOS : ERASE FAIL STATUS 1 = FAIL IN ERASE, 0 = SUCCESSFUL ERASE DOQ4 : PROGRAM FAIL STATUS 1 = FAIL IN PROGRAM, 0 = SUCCESSFUL PROGRAM DQ3 : SECTOR-PROTECT STATUS 1 = SECTOR 0 OR/AND 15 PROTECTED Q = NONE OF SECTOR PROTECTED DQ2: SLEEP STATUS 1 = DEVICE IN SLEEP STATUS 0 = DEVICE NOT IN SLEEP STATUS DQ1 - 0 = RESERVED FOR FUTURE ENHANCEMENTS. These bits are reserved for future use ; mask them out when polling the Status Register. 2. PROGRAM STATUS is for the status during Page Programming or Sector Unprotect mode. 3. ERASE STATUS is for the status during Sector/Chip Erase or Sector Protection mode. 4. SUSPEND STATUS is for both Sector and Chip Erase mode . 5. FAIL STATUS bit(DQ4 or DOS) is provided during Page Program or Sector/Chip Erase modes respectively. 6. DQ3 = 0 orl depends on Sector-Protect Status. 7. DQ2 = 0 or 1 depends on whether device is in the Sleep mode or not . * Once in the Sleep mode, DQ2 is set to 1", and is reset by read array command only.- 58-12MIC sence eee HARDWARE SECTOR PROTECTION The MX29F 8100 features sector protection. This feature wiil disable both program and erase operations in either the top or the bottom sector (0 or 7). The sector protection feature is enabled using system software by the user(Refer to table 3). The.device is shipped with both sectors unprotected. Alternatively, MXIC may protect sectors in the factory prior to shipping the device. SECTOR PROTECTION To activate this mode, a six-bus cycle operation is required. There are two unlock write cycles. These are followed by writing the set-up command. Two more unlock write cycles are then followed by the Lock Sector command - 20H. Sector address is latched on the falling edge of CE or WE of the sixth cycle of the command sequence. The automatic Lock operation begins on the rising edge of the last WE pulse in the command sequence and terminates when the Status on DQ7 is '1' at which time the device stays at the read status register mode. The device remains enabled for read status register mode until the CIA contents are altered by a valid command sequence (Refer to table 3,6 and Figure 10,12'). VERIFY SECTOR PROTECT To verify the Protect status of the Top and the Bottom sector, operation is initiated by writing Silicon ID read command into the command register. Following the command write, a read cycle from address XXX0OH retrieves the Manufacturer code of C2H. A read cycle from XXX1H returns the Device code 83H. A read cycle from appropriate address returns information as to.which sectors are protected. To terminate the operation, it is necessary to write the read/reset command sequence into the CIR. (Refer to table 3,4 and Figure 12) A few retries are required if Protect status can not be verified successfully after each operation. SECTOR UNPROTECT Itis also possible to unprotect the sector .same as the first MxX2SF8100 five write command cycles in activating sector protection mode followed by the Unprotect Sector command - 40H, the automatic Unprotect operation begins on the rising edge of the last WE puise in the command sequence and terminates when the Status on DG7 is 1' at which time the device stays af the read status register mode.(Refer to table 3,6 and Figure 11,12) The device remains enabied for read status register mode unti! the CiR contents are altered. by a valid command sequence. Either Protect or Unprotect sector mode is accomplished by keeping WP high, i.e. protect-bit status can only be changed with a valid command sequence and WP athigh. When WP is high, all sectors can be programmed or erased regardless of the state of the protect-bits. Protect- bit status will not be changed during chip/sector erase aperations. With WP at VIL, only unprotected sectorscan be programmed or erased. DEEP POWER-DOWN MODE The MXICs 8Mbit flash family supports a typical ICC of 1pA in deep power-down mode. One of the target markets for these devices is in protable equipment where the power consumption of the machine is of prime importance. When PWD is a logic low (GND + 0.2V), all circuits are turned off and the device typically draws 1A of ICC current. During read modes, the PWD pin going low deselects the memory and places the output drivers in a high impedance state. Recovery from the deep power-down state, requires a minimum of 700 nanoseconds to access valid data. During erase or program modes, PWD low will abort either erase or program operation. The contents of the memory are no longer valid as the data has been corrupted by the PWD function. As in the read mode above, all internal circuitry is turned off to achieve the 1pA current level. PWD transitions to VIL or turning power off to the device will clear the status register. PWD pin is not provided in 44-pin SOP package. 58-13SLEEP MODE The MX29F8100 features two software controlled iow- power modes : Sleep and Abort modes. Sleep mode is allowed during any current operations. except that once Suspend commandis issued, Sleep commandis ignored. Abort mode is excuted only during Page Program and Chip/Sector Erase mode. To activate Sleep mode, a three-bus cycle operation is required. The COH command (Refer to table 3) puts the device in the Sleep mode. Once in the Sleep mode and with CMOS input level applied, the power of the device is reduced to deep power-down current levels. The only power consuttied is diffusion leakage, transistor sub- threshold conduction, input leakage, and output leakage. The Sleep command allows the device to COMPLETE current operations before going into Sleep mode: Once current operation is done, device stays at read status register mode, RY/BY returns to ready state. The status registers are not reset during sleep command. Program or erase fail bit may have been set if during prograrmm/erase "mode the device retry exceeds maximum count. During Sleep mode, the status registers, Silicon iD codes : femain valid and can still be read. The Device Sleep Status bit - DQ2 will indicate that the device in the sleep mode. : Writing the Read Array command wakes up the device out of sleep mode. DQ2 is reset to "0" and Device returns to standby current level. ABORT MODE To activate Abort mode, a three-bus cycle operation is required. The EOH command (Refer to table 3) only stops Page program or Sector /Chip erase operation currently in progress and puts the device in Sleep mode. But unlike the sleep command, the program or erase operation will not be completed. Since the data in some page/sectors is no longer valid due to an incomplete program or erase operatidn, the program fait (DQ4) or erase fall (DQ5)bit will be set. After the abort command is. executed and with CMOS input level applied, the device current is reduced to the MxX29F8100 same level as in deep power-down or sleep modes. Device stays at read status register mode, RY/BY returns to ready state. During Abort modes, the status registers, Silicon ID codes remain valid and can stilf be read. The Device Sleep Status bit - DQ2 will indicate that the device in the sleep mode. Similar to the sleep mode, A read artay.command MUST be written to bring the device out of the abort state without incurring any wake up latency. Note that once device is waken up, Clear status register mode is required before a program or erase operation can be executed. RY/BY POLLING RY/BY is a full CMOS output that provides a hardware method of detecting page program and sector erase completion. [t transitions to VIL after a program or erase command sequence is written to the. MX29F8100, and returns to VOH when the WSM has finished executing the internal algorithm. PIN AND PROGRAM/ERASE RY/BY can be connected to the interrupt input of the system CPU or controlier.. it is active at all times, not tristated if the CE or OE inputs are brought to VIH. RY/ BY is also VOH when the device is in erase suspend or deep power-down modes. RY/BY pin is not provided in 44-pin SOP package. DATA PROTECTION The MX29F8100 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine in the Read Array made. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transitions or system noise.LOW VCC WRITE INHIBIT To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO(= 3.2V , typically 3.6V). If VCC < VLKO, the command register is disabled and all internal prograny | erase circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the user's responsibility to ensure that the control pins are logically correct to prevent unintentional write when VCC is above VLKO. WRITE PULSE "GLITCH" PROTECTION Noise pulses of less than 10ns (typical) on CE or WE will not initiate a write cycle. LOGICAL INHIBIT Writing is inhibited by holding any one of OE = VIL,CE = VIH or WE = VIH. To initiate _a write cycle CE and WE must be a logical zero while OE is a logical one. MX29F8100 58-15MI - Mx298F8100 Figure 1. AUTOMATIC PAGE PROGRAM FLOW CHART a _------- START ) t i t | Write Data AAH Address 5555H | i ' [ Write Data 5511 Address 2AAAH | { Y White Data AOH Address 5555H | Y 1 | | Write Prograr Data/Address aT 1 : a ~~ NO \ Loading Bn Ne YES iA a - . Wart 100us | wo ss Yo a Read Status Register og ar wo _. i YES A ____., a es { Page Program Completed >) \ Program Error ) ~ a ae ed t ee | To Continue Other Operanens. ves ~ Program ~~ | Do Clear S.R. Mode First another page? a ee NO | Operation Done. Device Stays At Read SR. Mode) Note : S.8. Stands for Status Register 58-16MxX28F8100 LO 7 , ( START } SN i tt I t - Write Data AAH Address 5554 , ed Wate Data 55H Address 2AAAH - .__Y___ | Write Data 80H Address 5555H 1 1 ene ae a er ee eee in ete el Write Data AAH Adcress 5555H f | | White Data SSH Address 2AAAH ae Write Data 10H Address 55554 _-_-_____ Read Status Ragister 1 : ! | v NO : | we ; To Execute YES | A, SRr = Suspend Mode ? . | Erase Suspend Flow ;Figure 4. o _ _ NN Ne YES r a , a NO < SRS = 6 a a a a Se YES Po _>~, Chip Erase Completed } { Erase Error ) NO NL _. / y tL Operation Done | To Continus Other Device Stays at ' Operations, Do Clear Reac S A. Mode i S.A. Mode First 58-17Figure 3. AUTOMATIC SECTOR ERASE FLOW CHART MX23F8100 rc / \ i START Y White Data AAH Address 55554 t Write Data SSH Andress 2AAAH _t Write Data 80H Address 5555H 1 Wnrte Data AAH Address 5555H White Data 55H Address 2AAAH Y Write Data 30H Sector Address y Read Status Register SR5=0 fc Sector Erase Completed , Operation Dane, Device Stays at Read SR. Mode 1 NO a Aotoeaie ves << Suspend Erase ? Ne Ne YS oo \ Erase Error ) a | To Cantinue Other Operations, Do Clear Le .R. Made First | | Erase Suspend Flow (Figure 4.) 58-18 1 o tf Werte Data AA Address 5555 poo ae Wile Data SSH Address 254A Ab oe ny Write Dale SGH Address 5355H { L Asad Status Register | Erase has completac x : Oparaton Lore. : Device Stays al b Read S.A Mode Wrie Data S6H Adarass 2AAAK ~~ [ Write Data FOH Agdress 55554 i ' a [ Read Array \ 5 NO Reaging ind * > ~ = ~ ol YES eee Winte Data AAH Address 5555H a J a 4 _-- [ Write Data SSH Address 2AAAM en Nene j Write Data DOH Adress S551 : _-] ( Centeue Erase ) a ) aed 58-19MAIS xzeFs100 ELECTRICAL SPECIFICATIONS NOTICE: tresses greater than those listed under ABSOLUTE ABSOLUTE MAXIMUM RATINGS MAXIMUM RATINGS may cause permanent damage to the RATING VALUE device. This is stress rating only and functional operational Ambient Operating Temperature QC to 70C sections of this specification is not implied. Exposure to - woe ee absolute maximum rating conditions for extended period may Storage Temperature -65C to 125C affect reliability. ee ee we . NOTICE: Applied Input Voltage -0.5V to 7.0V Specifications contained within the following tables are subject ne - a ce . to change. Applied Output Voltage -0.5V to 7.0V VCC to Ground Potential -0.5V to 7.0V AQ -0.5V to 13.5V CAPACITANCE TA = 25C, f = 1.0 MHz SYMBOL PARAMETER MIN. TYP. MAX. UNIT CONDITIONS CIN Input Capacitance 14 pF VIN = OV COUT Output Capacitance 16 pF VOUT = 0V SWITCHING TEST CIRCUITS f DEVICE 1.8KQO eee | ae i el A ee UNDER a ~ <k- + OS 2 +5V TEST : | i Vo I t, |. DIODES = IN3064 VY i OR EQUIVALENT a CL = 100 pF Including jig capacitance SWITCHING TEST WAVEFORMS r { 2.4V oo fo y 20 20 Ne TEST POINTS fo ~\. 0.8v arr 0.45V _ osv-/% XO INPUT OUTPUT AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". I Input pulse rise and fall times are < 10ns. 58-20DC CHARACTERISTICS = 0C to 70C, VCC = 5Vt10% MX29F8100 SYMBOL PARAMETER NOTES MIN. TYP. MAX. UNITS TEST CONDITIONS HL Input Load 1 +10 pA VCC = VCC Max Current VIN = VCC or GND ILO Output Leakage 1 +10 pA VCC = VCC Max Current VIN = VCC or GND {SB1 VCC Standby 1 50 100 HA VCC = VCC Max Current(CMOS) CE1, CE2. PWD = VCC +0.2V ISB2 VCC Standby 2 4 mA VCC = VCC Max Current(TTL) CE1, CE2, PWD = VIH IDP VCC Deep 1 1 20 BA PWD = GND +0.2V Power-Down Current IcC1 VCC Read 1 50 60 mA VCC = VCC Max Current CMOS: CE1, CE2 = GND + 0.2V BYTE = GND + 0.2V or VCC + 0.2V Inputs = GND +0.2V or VCC + 0.2V TTL : CE1, CE2 = VIL, BYTE = VIL or VIH Inputs = VIL or VIH, f = 10MHz, IOUT = 0 mA ICC2 VCC Read 1 30 35 mA VCC = VCC Max, Current CMOS: CEi, CE2 = GND +0.2V BYTE = VCC +0.2V or GND + 0.2V inputs = GND + 0.2V or VCC + 0.2V TTL: CE1, CE2 = VIL, BYTE = VIH or VIL Inputs = VIL or VIH, f =5MHz, IOUT = OmA IcC3 VCC Erase 1,2 5 10 mA CE1, CE2 = VIH Suspend Current BLock Erase Suspended Icc4 VCC Program 1 30 50 mA Program in Progress Current _ ICC5 VCC Erase Current 1 30 50 mA Erase in Progress VIL Input Low Voltage 3 -0.3 0.8 Vv VIH Input High Voltage 4 2.4 VCC+0.3 V ~ ~ ~ VOL Output Low Voltage 0.45 Vv IOL = 2.1mA VOH Output High Voltage 2.4 v [OH = -400pA 68-21DC CHARACTERISTICS = 0C to 70C, VCC = 5+10%(CONTINUE P.21) - NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0V, T= 25C. These currents are valid for all product versions (package and speeds). 2. ICC3 is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of !CC3 and ICC 1/2. 3. VIL min. = -1.0V for pulse width < 50ns. VIL min. = -2.0V for pulse width < 20ns. 4. VIH max. = VCC + 1.5V for pulse width < 20ns. If VIH is over the specified maximum value, read operation cannot be guaranteed. AC CHARACTERISTICS READ OPERATIONS 29F8300-10 29F8700-12 29F8100-15_ SYMBOL DESCRIPTIONS MIN. MAX. MIN. MAX. MIN. MAX. UNIT CONDITIONS tACC Address to Output Delay 100 120 150 ons CE-OE=VIL ECE wOulputDey = tC (stitiaCtC Cts SCE 10E OE toOutputDelay Sti tS BEHigh to Output Delay 0 8985 0tsiH_Cs (its Address toOuputhold = iting OSV BYTE to Output Delay _ 100 439 150 ons CE= OE=VIL tBHZ BYTE Low to Output in High Z 55 55 55 ns CE=VIL tDPR Deep Rower-Down Recovery 700 700 800 ns TEST CONDITIONS: NOTE: Input pulse levels: 0.45V/2.4V 1. tDF is defined as the time at which the output achieves the * Input rise and fall times: 10ns open circuit condition and data is no longer driven. * Outputload: 1TTL gate+100pF (Including scope and jig) Reference levels for measuring timing: 0.8V, 2.0V 58-22Figure 5. READ TIMING WAVEFORMS | dynamic switching of BYTE pin is not recommended. Standby Device and Outputs Enabled Standby Veco Power-up addrass selection Data valid Veco Power-down VIM ADUORESSES ADDRESSES STABLE VIL va /. NN fe a vit a f \ CE (1) _ i Vit [ae orn / \ / \ a VIL wy op ee OE (OF - ~ Vth f i a / \ WE viL OE me \ ~ ce ~ VOH - (OH HIGH Z f7 . DATA OUT ELL pata out valid yap p iene VOL \ a ~ 1ACT - 5.0V VCC / enn ~~ PR ~ VIH \ PWD vw _/ \ NOTE: 1.GE is defined as the latter of CE1 or CE2 going Low or the first of CEI or CE2 going High. 2.For real worid application, BYTE pin should be either static high(word mode) or static low(byte mode): 58-23ADDRESSES CE (1) DATA(DQ0-DQ7) DATA(DQ8-DQ15} NOTE: Vin VEIL VIH- VIL VOH VOL ADDRESSES STABLE j Vo Le (OF ~ ~ IBACC ~- = - \ ~ ~ 1OE < ICE m 10H HIGH Z f f HIGH Z Li was me} XV v \ Data Output 7 tac ~ YBHZ ~~ ~ HIGH 2 HIGH 2 Data Gutput 1.6E is defined as the latter of CE'1 or CE2 going Low or the first of CE1 or GE2 going High. 58-24Mx29F8100 AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS 29F8100-10 _29F 8100-12 29F8100-15 SYMBOL DESCRIPTION MIN. MAX. MIN. MAX. MIN, MAX. UNIT iwc Write Cycle Time 100 120 150 ns tAS Address Setup Time 0 0 0 ns tAH Address Hold Time 45 50 60 ns tDS Data Setup Time 45 50 60 ms tDH Data Hold Time 10 10 10 ns tOES Output Enable Setup Time 0 0 0 ns tcES CE Setup Time 0 0 0 ns tGHWL Read Recover TimeBefore Write G 0 0 tcs CE Setup Time 0 0 0 ns tCH CE Hold Time 0 0 0 ns tWwP Write Pulse Width 45 50 60 ns tWPH Write Pulse Width High 50 50 50 ns tBALC Byte(Word) Address Load Cycle 0.3 30 0.3 30 0.3 30 HS {BAL Byte(Word) Address Load Time 100 100 100 HS tSRA Status Register Access Time 100 120 150 ns iCESR CE Setup before S.R. Read 100 100 100 ns tWHRL WE High to RY/BY Going Low 100 100 100 ns [WHRLP WE High to RY/BY Going Low 100.1 100.1 100.1 us (in Page Program mode) {PHWL PWD High Recovery to WE Going Low 1 1 1 us : VCS VCC Setup Time 2 2 20 usFigure 7. COMMAND WRITE TIMING WAVEFORMS . OE ad ~ we WE eeet*=n ~~. 'GHWL ~ / tWPH ~ ADDRESSES HIGH Z _ DATA -_-- a. a Cw) Bogan | voc Ses PwD : - tPHWL NOTE: 2.BYTE pin is sampled on the falling edge of WE or CE during the 3rd command write bus cycle; for real world application. BYTE pin should be either static high(word mode) or static low{byte mode). 58-26Poe MxX29F8700 { AO~AS ( NY 55H HO Word offset \y" NY vord ae we Epa ae i fe Address Ha f LowiHigh ON Last Low/Higl \ Byte Seiect Byte Select (byte mode only) | | At Ve r sso Xan) MSH X Page Address AB~A14 A . | AS tar . i ?: i <= ~ | i . rs i : P. Ad AIS~A1B \ Page Aaaress 1 i ewe = tBALC 1BAL i = > - i CE} oT y my oot oN. ms oo, fo : I i we | IWPH _. > ae i ; ; , f ! VS Sf __ Nou of wae | ICES : { = 1 | ro \ a f \ / i \ OF a aes ; tWHALP . > i RY/BY crm } ee ce ee 10S : <P> 1DH ' -_ : tSRA i co, ee, ~~ _ fo owne \ Sf bast Wie 5 DATA BAK {SSH DC Aa CE pT cee SRD | PHWL : ~ ~< i ' i _/ t Pwo | | i ! NOTE: i . _ < i 1.CE 1s defined as the Jatter of CE1 or CE2 going low, or the first of CE1 of CE2 going high. { 2.Pigase rater to page 9 for detail page program operation. i 58-27Figure 9. AUTOMATIC SECTOR/CHIP ERASE TIMING WAVEFORMS A0~A14 A1S AI6-A1B CE# WE AYBY DATA PWD : . = 5555M x 2AAAH x 5555H x 5555H Xx 2AAAH aS iAH ot a ol LS NS NS NS NS we OEP a > ~<aP NS NS VS VS oN SNS OO f ( /S555H 1CESR _ \ fo < wwe ~ tceSs a f oo _/ / YY TWHRL = \, \ 1S <~s tor tSRA ~~ - + { Aa \ 55H re BOH ey AAH yt 55H (eonson){"_ sap) {PHWL > _ _/ NOTES: 1.CE# is defined as the latter of CEt or CE2 going tow, or the first of CE1 or CE2 going high. 2."*" means "don't Care" in this diagram. 3."SA" means Sector Adddress".MxX29F8100. Figure 10. SECTOR PROTECTION ALGORITHM z Sy ( stant, * PLSCNT=-0 / Se ! Write Data AAF Address 55551. ' a Wnite Data 55H Address 2AAAH L bo -_--_* Waite Data 60H Address 5555H r Write Data AAH Adaress 5555H at i increment PLSCNT, To Protect Sector Again i nae i Write Data 20H Sector Address Write Data SSH Address 2AAAH | Read Status Register [tremens Ves NO : : a, | Protect Sector x PLSCNT YES ; ; Operation Tenminated ae, =257 To XL oN. oN, aA To YES | aN ps <" Venfy Protect Verity Protect Status Flow pata s._siatus 7-7 (Figure 12) SA 20H? _ a NO 1 Y8s a is nt ee a jt 4 f me sane at 5 Sector Protected Cperaton | a __. ead S.A. Mode / Dona, Device Stays at : Vernty Sector Protect Made : NOTE : "Only the Tap or the Bottom Sector Address ts vaild in this feature ie. Sector Address = (A18,A17.A16) = 000B or 111B 58-29Figure 11. SECTOR UNPROTECT ALGORITHM . S, { START. | \-PLSCNT=0 ee a i i Write Data AAH Address 5555H t : Write Dala 55H Address 2ASAH YES 4 ay | Device Failed | __. ' Write Dala 60H Address 55551 | ' i | Write Data AAH Address 5555H ' ! : Y White Data 55H Address 2AAAH lacrement PLSCNT To Unprotect Sector Again 1 i Wine Data 49H Sector Address y Read Status Register . i AY | ~~ ' NO grr et > ? a - YES NO Y uo. a ~ Unprotest Sector x B_SCNT : Operation Terminated me 225? : . \ , oO, " tT; ~~ YES ae , <x Verify Protect Verily Protect Status Flow C Daia ._ Status 7 Figura 12) ~ = OOH ? NO 1 YES { Device Stays at } Sactor Unpretected.Operation ~ Read S.R. Mode ra Done, Davice Stays at Venty Sector Protect Made NOTE : Only the Top or the Bottom Sector Address is vaild in this feature. ie. Sector Address = (A18,A17,A16) = 0008 or 111B 58-30Mx<x29Fe8.1 t ! Wrie Data AAH Address 5555H | r Write Data 55H Address 2AAAH | Wiite Data 90H, Address 5555H Low 24 yo ( f Ptoect Status Read* } Me _ 41. Protect Status: Data Outputs C2H as Protected Sector Verified Code. Data Outputs OOH as Unprotected Sector Verified Code. 2. Sepecified address will be either (A18.A17,A16,A1,A0) = (00010) or (11110), the rest of the address pins ate don't care. 3. Silicon {D can be read via this Flow Chart. Refer to Table 4. 58-31Figure 13. COMMAND WRITE TIMING WAVEFORMS(Alternate CE Controlied) - t OE ADDRESSES DATA (D/Q) VCC PWD NOTE: 1.BYTE pin is treated as Address pin. All timing specifications for BYTE pin are the same as those for address pin. 2.BYTE pin is sampled on the falling edge of WE or GE during the 3rd command write bus cycle; for real world application. \ WH \ -< - ~\ OES ~ - ows = ~ 7 f ee iwc > 1GHWL a ya ICPH - - HIGH Z BIN BYTE pin should be either static high(word mode) or static low(byte mode).= f Ward attset AQ~A5 AAM H i VL Xs 58 Xie X Act Last CowlHigh\ 4 ((Byte Mode Only} _____/ "Bye Select 4 fi \7 AB~A14 A 55H y 24H XK 55H is Page Address AS tAH =a ~ - i A15~A1B8 Page Address f WC nr : ~ ~ tBALC WE ~~. H aN f i ff a : . , \ foON J i \ | Vf NY NY NY NLL | ! c 1CPH a BA ' CE(1) ~ \ mm ; oo, mo / r / o~ [TN ae YS \ \_ Sd ee WK / eS tcES i f \ / OE a Vf 4 i tWHRLP . _-_ | RY/BY OS oH : ' i - ISRA : ~ { Nf pen ee ee f ie" * om ! DATA --{ AAH 55H} { fe bast Wines \ KAAH {SSH po AH OE SRO / tPHWL | ~~ <_< | : / i i a / | PWD i i NOTE: 1.GE is defined as the latter of CE1 or CE2 going ow, or the first of CE1 or CE2 going high. 2.Please refer to page 9 for detail page program operation. 58-33ERASE AND PROGRAMMING PERFORMANCE LIMEFS PARAMETER MIN. TYP. MAX. UNITS Chip/Sector Erase Time 50 300 ms Page Programming Time 3 9 ms t Chip Programming Time 17 33 sec Erase/Program Cycles + 1,000/10,000 i Cycles i | Byte Program Time | 16 | HS ; | LATCHUP CHARACTERISTICS MIN. | MAX. + Input Voltage with respect to GND on all pins except I/O pins -1.0V 13.5V Input Voltage with respect to GND on all 1/O pins -1.0V Vcc + 1.0V Current -100mA +100mA Includes ali pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time. Note. Revision History Revision# Description 1.6 fast access time : 100ns