JULY 2004
DSC-6468/00
1
©2004 Integrated Device Technology, Inc.
Features
512K x 8 advanced high-speed CMOS Static RAM
JEDEC Center Power / GND pinout for reduced noise
Equal access and cycle times
Commercial and Industrial: 10/12/15ns
Single 3.3V power supply
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
TTL-compatible
Low power consumption via chip deselect
Available in 36-pin, 400 mil plastic SOJ package and
44-pin, 400 mil TSOP.
Functional Block Diagram
Description
The IDT71V424 is a 4,194,304-bit high-speed Static RAM organized
as 512K x 8. It is fabricated using IDT’s high-perfomance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs.
The IDT71V424 has an output enable pin which operates as fast as
5ns, with address access times as fast as 10ns. All bidirectional inputs and
outputs of the IDT71V424 are TTL-compatible and operation is from a
single 3.3V supply. Fully static asynchronous circuitry is used, requiring
no clocks or refresh for operation.
The IDT71V424 is packaged in a 36-pin, 400 mil Plastic SOJ and 44-
pin, 400 mil TSOP.
ADDRESS
DECODER 4,194,304-BIT
MEMORY ARRAY
I/O CONTROL
A
0
A
18
8
8
I
/O
0
-I/O
7
8
CONTROL
LOGIC
WE
OE
CS
6468 drw 01
3.3V CMOS Static RAM
4 Meg (512K x 8-Bit) IDT71V424YS
IDT71V424YL
6.42
2
IDT71V424YS, IDT71V424YL, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A
5
N
C
N
C
A
9
A
8
A7
W
E
I
/0
3
I
/0
2
V
SS
V
D
D
I
/0
1
I
/0
0
C
S
A
2
A
1
A
0
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
A15
OE
I/0
7
I/0
6
V
SS
V
D
D
I/0
5
I/0
4
A14
A13
A11
A10
NC
NC
NC
NC
A12
SO44-
2
6468 drw 11
N
C
N
C
A
3
A
4
A6
A16
A17
A18
A0
A1
A2
A3
CS
I
/O 0
V
DD
V
SS
I
/O 2
WE
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
A18
A17
A16
OE
I/O 7
I/O 6
V
SS
V
DD
I/O 5
A14
A13
A12
A11
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
SO36-1
17
18 19
20
I
/O 1
I
/O 3 I/O 4
NC
A8
A9 A10
A15
6468 drw 02
SOJ
Top View
Pin Configuration
Truth Table(1,2)
Capacitance
(TA = +25°C, f = 1.0MHz, SOJ package)
Pin Configuration
TSOP
Top View
A
0
– A
18
Address Inputs Input
CS Chip Se le c t Inp ut
WE Write Enable Input
OE Outp ut Enab l e Inp ut
I/ O
0
- I/O
7
Data Inp ut/ Outp ut I/ O
V
DD
3.3V Po wer Po wer
V
SS
Gro und Gnd
6468 tb l 02
Pin Description
Symbol Parameter(1) Conditions Max. Unit
C
IN
Inp ut Cap ac i tanc e V
IN
= 3dV 7 pF
C
I/O
I/ O Ca p ac i tanc e V
OUT
= 3dV 8 pF
6468 tb l 03
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
CS OE WE I/O Function
LLHDATA
OUT Re ad D ata
LXLDATA
IN Write Data
L H H Hig h-Z Outp ut Dis ab le d
H X X Hig h-Z De se le cted - Stand b y (ISB)
VHC(3) X X High-Z Deselecte d - Standby
(ISB1)
6468 tbl 01
NOTES:
1 . H = VIH, L = VIL, x = Don't care.
2. VLC = 0.2V, VHC = VDD -0.2V.
3 . Other inputs VHC or VLC.
6.42
3
IDT71V424YS, IDT71V424YL, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1) Recommended Operating
Temperature and Supply Voltage
Recommended DC Operating
Conditions
DC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
DC Electrical Characteristics(1, 2, 3)
(VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability. NOTES:
1. VIH (max.) = VDD+2V a.c. (Pulse Width < 5ns) for I < 20mA.
2. VIL (min.) = –2V a.c. (Pulse Width < 5ns) for I < 20mA.
NOTES:
1. All values are maximum guaranteed values.
2. All inputs switch between 0.2V (Low) and VDD - 0.2V (High).
3. Power specifications are preliminary.
4. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
5. Standard power 10ns (S10) speed grade only.
Symbol Rating Value Unit
V
DD
Sup ply Vo ltag e Relative
to V
SS
-0.5 to +4.6 V
V
IN
, V
OUT
Te rminal Vo ltage Re lativ e
to V
SS
-0.5 to V
DD
+0.5 V
T
BIAS
Te m pe rature Und e r Bi as -55 to + 125
o
C
T
STG
Sto rag e Te mp e rature -55 to + 125
o
C
P
T
Power Dissipation 1 W
I
OUT
DC Output Curre nt 50 mA
6468 tbl 04
Symbol Parameter Min. Typ. Max. Unit
V
DD
Supply Vo ltag e 3. 0 3.3 3.6 V
V
SS
Ground 0 0 0 V
V
IH
Input High Voltage 2.0
____
V
DD
+0.3
(1)
V
V
IL
Inp ut Low Vo ltage -0.3
(2)
____
0.8 V
6468 tbl 06
Grade Temperature V
SS
V
DD
Comme rcial C to +70° C 0V Se e Be lo w
Ind ustrial –40° C to + 85° C 0V Se e Be lo w
6468 tb l 05
Symbol Parameter Test Condition
IDT71V424
Min. Max. Unit
|I
LI
| Input Leakag e Current V
DD
= Max ., V
IN
= V
SS
to V
DD ___
A
|I
LO
| Outp ut Le ak age Curre nt V
DD
= Max., CS = V
IH
, V
OUT
= V
SS
to V
DD ___
A
V
OL
Outp ut Lo w Vo ltag e I
OL
= 8mA, V
DD
= Min.
___
0.4 V
V
OH
Outp ut Hig h Vo ltag e I
OH
= -4mA, V
DD
= Min. 2.4
___
V
6468 tb l 07
Symbol Parameter
71V424YS/YL 10 71V424YS /YL 12 71V424YS/ YL 15 Unit
Com'l. Ind.
(5)
Com'l. Ind.
(5)
Com'l. Ind.
(5)
I
CC
Dynamic Operating Current
CS < V
LC
, Outputs Open, V
DD
= Max., f = f
MAX
(4)
S 180 180 170 170 160 160 mA
L 165
___
155 155 145 145 mA
I
SB
Dynamic Standby Power Sup ply Current
CS > V
HC
, Outputs Open, V
DD
= Max., f = f
MAX
(4)
S606055555050mA
L55
___
50 50 45 45 mA
I
SB1
Full S tand b y Po we r Sup p ly Curre nt (s tati c)
CS > V
HC
, Outputs Open, V
DD
= Max., f = 0
(4)
S202020202020mA
L10
___
10 10 10 10 mA
6468 tb l 08
6.42
4
IDT71V424YS, IDT71V424YL, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges
AC Test Loads
AC Test Conditions
Figure 1. AC Test Load
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
Figure 3. Output Capacitive Derating
*Including jig and scope capacitance.
6468 drw 04
320
3505pF*
D
ATA
OUT
3.3V
1
2
3
4
5
6
7
20 40 60 80 100 120 140 160 180 200
t
AA,
t
ACS
(Typical, ns)
CAPACITANCE (pF)
8
6468 drw 05
·
+
1
.
5
V
50
/O Z
0
=50
6468 drw 03
30pF
Input Pulse Levels
Inp ut Ris e /F all Tim e s
Inp u t Ti mi ng R e fe renc e Lev e l s
Outp ut Refe re nce Le ve ls
AC Test Load
GND to 3.0V
1.5ns
1.5V
1.5V
See Figure 1, 2 and 3
6468 tbl 09
6.42
5
IDT71V424YS, IDT71V424YL, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges
71V424S/L10(2) 71V424S/L12 71V424S/L15
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
READ CYCLE
t
RC
Re ad Cyc le Ti me 10 ____ 12 ____ 15 ____ ns
t
AA
Address Access Time ____ 10 ____ 12 ____ 15 ns
t
ACS
Chip Select Access Time ____ 10 ____ 12 ____ 15 ns
t
CLZ
(1) Chip Se lect to Output in Low-Z 4 ____ 4____ 4____ ns
t
CHZ
(1) Chi p De s e l e c t to O utp ut in Hig h -Z ____ 5____ 6____ 7ns
t
OE
Ou tp ut E nab l e to O utp ut Val id ____ 5____ 6____ 7ns
t
OLZ
(1) O utp ut E nabl e to O utp ut in Lo w-Z 0 ____ 0____ 0____ ns
t
OHZ
(1) Output Disable to Output in High-Z ____ 5____ 6____ 7ns
t
OH
Output Ho ld fro m Ad dres s Change 4 ____ 4____ 4____ ns
t
PU
(1) Chip Se le c t to Po we r Up Tim e 0 ____ 0____ 0____ ns
t
PD
(1) Ch ip De s e l e c t to P owe r Do wn Ti m e ____ 10 ____ 12 ____ 15 ns
WR IT E C YC L E
t
WC
Write Cycle Time 10 ____ 12 ____ 15 ____ ns
t
AW
Address Valid to End of Write 8 ____ 8____ 10 ____ ns
t
CW
Chip Sele ct to End o f Write 8 ____ 8____ 10 ____ ns
t
AS
Address Set-up Time 0 ____ 0____ 0____ ns
t
WP
Write Pulse Width 8 ____ 8____ 10 ____ ns
t
WR
Write Re co v e ry Tim e 0 ____ 0____ 0____ ns
t
DW
Data Valid to End of Write 6 ____ 6____ 7____ ns
t
DH
Data Ho l d Time 0 ____ 0____ 0____ ns
t
OW
(1) Outp ut Ac tive fro m End o f Wri te 3 ____ 3____ 3____ ns
t
WHZ
(1) Write Enable to Output in High-Z ____ 6____ 7____ 7ns
6468 tb l 10
NOTES:
1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
2. 0ºC to +70ºC temperature range only for low power 10ns (L10) speed grade.
AC Electrical Characteristics
(VCC = 3.3V ± 10%, Commercial and Industrial Temperature Ranges)
6.42
6
IDT71V424YS, IDT71V424YL, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 2(1, 2, 4)
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
Timing Waveform of Read Cycle No. 1(1)
ADDRESS
6468 drw 06
OE
C
S
DATA
OUT
(5) (5) (5)
(5)
DATA
OUT
VALID
HIGH IMPEDANCE
t
AA
t
RC
t
OE
t
ACS
t
OLZ
t
CHZ
t
CLZ
(3)
t
OHZ
V
CC
SUPPLY
CURRENT
t
PU
t
PD
I
CC
I
SB
DATA
OUT
A
DDRESS
6468 drw 07
t
RC
t
AA
t
OH
t
OH
DATA
OUT
VALIDPREVIOUS DATA
OUT
VALID
6.42
7
IDT71V424YS, IDT71V424YL, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1, 2, 4)
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1, 4)
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and
data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse
is the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4 . If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS must be active during the tCW
write period.
5. Transition is measured ±200mV from steady state.
A
DDRESS
C
S
WE
DATA
OUT
DATA
IN
6468 drw 08
(5)
(2)
(5) (5)
DATA
IN
VALID
HIGH IMPEDANCE
t
WC
t
AW
t
AS
t
WHZ
t
WP
t
CHZ
t
OW
t
DW
t
DH
t
WR
(3)(3)
C
S
A
DDRESS
DATA
IN
6468 drw 09
t
AW
t
WC
t
CW
t
AS
t
WR
t
DW
t
DH
DATA
IN
VALID
WE
6.42
8
IDT71V424YS, IDT71V424YL, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges
Ordering Information
X
Power
XX
Speed
XXX
Package
X
Process/
Temperature
Range
Blank
ICommercial (0°C to +70°C)
Industrial (–40°C to +85°C)
Y
PH 36-pin 400 mil SOJ (SO36-1)
44-pin TSOP Type II (SO44-2)
10*
12
15
71V424
Device
Type
I
DT
Speed in nanoseconds
6468 drw 10
S
LStandard Power
Low Power
* Commercial only for low power 10ns (L10) speed grade.
X
Die
Revision
YSecond Generation die step
X
GRestricted hazardous substance device
6.42
9
IDT71V424YS, IDT71V424YL, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges
Datasheet Document History
07/16/04 Released new datasheet
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
CORPORATE HEADQUARTERS for SALES: for Tech Support:
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San Jose, CA 95138 408-284-8200 800-345-7015
fax: 408-284-2775
www.idt.com