CY7C374I83JC - CYPRESS SEMICONDUCTOR

UltraLogic™ 128-Macrocell Flash CPLD

CY7C374i

Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600

Document #: 38-03031 Rev. *A Revised April 19, 2004

Features

• 128 macrocells in eight logic blocks

• 64 I/O pins

• Five dedicated inputs including four clock pins

• In-System Reprogrammable™ (ISR™) Flash technology

— JTAG interface

• Bus Hold capabilities on all I/Os and de di ca ted inputs

• No hidden dela y s

•High speed

—f

MAX = 125 MHz

—t

PD = 10 ns

—t

S = 5.5 ns

—t

CO = 6.5 ns

• Fully PCI-compliant

• 3.3V or 5.0V I/O operation

• Available in 84-pin PLCC, 84-pin CLCC, and 100-pin

TQFP packages

• Pin-compatible with the CY7C373i

Functional Description

The CY7C374i is an In-System Reprogrammable Complex

Programmable Logic Device (CPLD) and is part of the

FLASH370i™ family of high-density, high-speed CPLDs. Like

all members of the FLASH370i family, the CY7C374i is

designed to bring the ease of use as well as PCI Local Bus

Specification support and high performance of the 22V10 to

high-density CPLDs.

Like all of the UltraLogic™ FLASH370i devices, the CY7C374i

is electrically erasable and In-System Reprogrammable (ISR),

which simplifies both design and manufacturing flows, thereby

reducing costs. The Cypress ISR function is implemented

through a JTAG serial interface. Data is shifted in and out

through the SDI and SDO pin. The ISR interface is enabled

using the programming voltage pin (ISREN). Additionally,

because of the superior routability of the FLASH370i devices,

ISR often allows users to change existing logic desi gns while

simultaneously fixing pinout assignments.

The 128 macrocells in the CY7C374i are divided between

eight logic blocks. Each logic block incl udes 16 macrocells, a

72 x 86 product term array, and an intelligent product term

allocator.

Selection Guide

7C374i–125 7C374i–100 7C374i–83 7C7374iL–83 7C374i–66 7C374iL–66 Unit

Maximum Propagation Delay[1], tPD 10 12 15 15 20 20 ns

Minimum Set-up, tS5.5 6 8 8 10 10 ns

Maximum Clock to Output[1], tCO 6.5 7 8 8 10 10 ns

Typical Supply Current, ICC 125 125 125 75 125 75 mA

Note:

1. The 3.3V I/O mode timing adder, t3.3IO, must be added to this specification when VCCIO = 3.3V.

Logic Block Diagram

PIM

INPUT

MACROCELL

Clock

Inputs

4 4

16 16

LOGIC

BLOCK 36

16 16

8 I/Os

36 36

16 16

32 32

41 INPUT/CLOCK

MACROCELLS

I/O

–I/O

Inputs

LOGIC

BLOCK

LOGIC

BLOCK

LOGIC

BLOCK

LOGIC

BLOCK

LOGIC

BLOCK

LOGIC

BLOCK

LOGIC

BLOCK

I/O

–I/O

I/O

–I/O

I/O

–I/O

I/O

–I/O

I/O

–I/O

I/O

–I/O

I/O

–I/O

8 I/Os

CY7C374i

Document #: 38-03031 Rev. *A Page 2 of 15

Pin Configurations

I/O

I/O14

I/O15 I/O48

Top View

PLCC

98 67 5

4948

4746

34 3736 38 4241 43

84 8182 8021 79 GND

I/O

GND

I/O

GND

I/O55

I/O54/SDI

I/O53

I/O52

I/O51

GND

I/O49

CLK3/I4

VCCIO

CLK2/I3

I/O45

I/O44

GND

I/O

I/O8

I/O9

I/O10/SCLK

I/O11

I/O12

I/O13

CLK0/I0

VCCIO

CLK1/I1

I/O16

I/O17

I/O18

I/O19

I/O20

53525150

I/O

57 I/O43

I/O42

I/O41

I/O40

7778 76 75

I/O21

I/O22

I/O23

GND

I/O

I/O50

I/O47

I/O46

GND

I/O25

/SMODE

I/O27

I/O28

I/O29

I/O30

I/O31

VCCIO

VCCINT

I/O32

I/O33

I/O34

I/O35

I/O36

I/O37

I/O38I/O39

GND

VCCIO

I/O0

VCCINT

I/O62

ISREN

I/O26

/SDO

35 39 44 45

GND

I/O5

I/O6

I/O4

I/O3

I/O2

I/O0

VCC GND

I/O62

I/O54 I/O52

I/O51 I/O50

I/O48 CLK3

/I4

I/O45 GND

I/O46 I/O47

I/O43 I/O44

I/O40 I/O42

I/O41

GND

I/O37

I/O38

I/O36

I/O35

I/O34

I/O32

I/O33

I/O30

I/O31

I/O27

I/O28

I/O24

I/O26

I/O25

I/O21

I/O22

I/O20

I/O19

I/O18

I/O16

CLK1

/I1

CLK0

/I0

I/O17

I/O14

I/O15

I/O11

I/O12

I/O8

I/O10

I/O9

GND

PGA

Bottom View

VCC

I/O63 I/O60 I/O58 I/O57

I/O59 I/O56 GND I/O53

12345678910

I/O23 I/O39

I/O55

I/O7

I/O1VCC ISREN

GNDVCC

I/O29

I/O49

VCC

CLK2

/I3

GND

VCC

I/O13

I/O61

SMODE

SDO

SDISCLK

CY7C374i

Document #: 38-03031 Rev. *A Page 3 of 15

Pin Configurations (continued)

Top View

TQFP

100 9798 96

4241

4039

95 94

27 28 3029 31 32 3534 36 3833

89 88 8687 8593 92 84 SDI

VCCIO

I/O55

I/O54

I/O53

I/O52

CLK3/I4

I/O50

I/O48

GND

I/O47

I/O46

I/O49

GND

SMODE

SCLK

GND

I/O8

I/O9

I/O10

I/O11

I/O15

VCCIO

GND

CLK1/I1

I/O16

I/O17

CLK0/I0

9091

I/O51

VCCIO

CLK2/I3

I/O14

N/C

I/O12

I/O13

I/O45

I/O44

I/O43

I/O42

I/O41

I/O40

GND

I/O18

I/O19

I/O20

I/O21

I/O22

I/O23

VCCIO

83 82 81 80 79 78 77 76

43 44 45 46 48 49 50

GND

I/O24

I/O25

I/O26

I/O27

I/O28

I/O29

I/O30

I/O31

VCCIO

VCCINT

I/O32

I/O33

I/O34

I/O35

I/O36

I/O37

I/O38

I/O39

VCCIO

SDO

I/O

GND

I/O

VCCIO

I/O0

VCCINT

I/O62

VCCIO

ISREN

37 47

I/O

I/O14

I/O15 I/O48

Top View

CLCC

98 67 5

4948

34 3736 38 4241 43

84 8182 8021 79 GND

I/O

GND

I/O

GND

I/O55

I/O54/SDI

I/O53

I/O52

I/O51

GND

I/O49

CLK3/I4

VCC

CLK2/I3

I/O45

I/O44

GND

I/O

I/O8

I/O9

I/O10/SCLK

I/O11

I/O12

I/O13

CLK0/I0

VCC

CLK1/I1

I/O16

I/O17

I/O18

I/O19

I/O20

53525150

I/O

57 I/O43

I/O42

I/O41

I/O40

7778 76 75

I/O21

I/O22

I/O23

GND

I/O

I/O50

I/O47

I/O46

GND

I/O25

/SMODE

I/O27

I/O28

I/O29

I/O30

I/O31

VCC

I/O32

I/O33

I/O34

I/O35

I/O36

I/O37

I/O38I/O39

GND

VCC

I/O0

VCC

I/O62

ISREN

I/O26

/SDO

35 39 44 45

CY7C374i

Document #: 38-03031 Rev. *A Page 4 of 15

Functional Description

The logic blocks in the FLASH370i architecture are connected

with an extremely fast a nd predictable routing resource—the

Programmable Interconnect Matrix (PIM). The PIM brings

flexibility, routability, speed, and a uniform delay to the inter-

connect.

Like all members of the FLASH370i family , the CY7C374i is rich

in I/O resources. Every two macrocells in the device feature

an associated I/O pin, resulting in 64 I/O pins on the

CY7C374i. In addition, there is one dedicated input and four

input/clock pins.

Finally, the CY7C374i features a very simple timing model.

Unlike other high-density CPLD architectures, there are no

hidden speed delays such as fanout effects, interconnect

delays, or expander delays. Regardless of the number of

resources used or the type of application, the timing param-

eters on the CY7C374i remain the same.

Logic Block

The number of logic blocks d istinguishes the membe rs of the

FLASH370i family. The CY7C374i includes eight logic blocks.

Each logic block is constructed of a product term array, a

product term allocator, and 16 macrocells.

Product Term Array

The product term array in the FLASH370i logic block incl udes

36 inputs from the PIM and outputs 86 product terms to the

product term allocator. The 36 inputs from the PIM are

available in both positive and negative polarity, making the

overall array size 72 x 86. This large array in each logic block

allows for very complex functions to be implemented in single

passes through the device.

Product Term Allocator

The product term allocator is a dynamic, configurable resource

that shifts product terms to macrocells that require them. Any

number of product terms between 0 and 16 inclusive can be

assigned to any of the logic block macrocells (this is called

product term steering). Furthermore, product terms can be

shared among multiple macrocells. This means that product

terms that are common to more than one output can be imple-

mented in a single product term. Product term steering and

product term sharing help to increase the effective density of

the FLASH370i CPLDs. Note that product term allocation is

handled by software and is invisible to the user.

I/O Macrocell

Half of the macrocells on the CY7C374i have I/O pins

associated with them. The input to the macrocell is the sum of

between 0 and 16 product terms from the product term

allocator. The I/O macrocell includes a register that can be

optionally bypassed, polarity control over the input sum-term,

and two global clocks to trigger the register. The macrocell

also features a se parate feed b ack path to the PIM so that the

Buried Macrocell

The buried macrocell is very similar to the I/O macrocell.

Again, it includes a regi ster that can be configured as combi-

natorial, as a D flip-flop, a T flip-flop, or a latch. The cl ock for

this register has the same options as described for the I/O

macrocell. One difference on the buried macrocell is the

addition of input register capability. The user can program the

buried macrocell to act as an input register (D-type or latch)

whose input comes from the I/O pin associated with the neigh-

boring macrocell. The output of all buried macrocells is sent

directly to the PIM regardless of its configuration.

Programmable I nterconnect Matrix

The Programmable Interconnect Matrix (PIM) connects the

eight logic blocks on the CY7C374i to the inputs and to each

other. All inpu ts (including feedbacks) travel through the PIM.

There is no speed penalty incurred by signals traversing the

PIM.

Programming

For an overview of ISR programming, refer to the FLASH370i

Family data sheet and for ISR cable and software specifica-

tions, refer to ISR data sheets. For a detailed description of

ISR capabilities, refer to the Cypress application note, “An

Introduction to In System Reprogramming with FLASH370i.”

PCI Compliance

The FLASH370i family of CMOS CPLDs are fully compliant with

the PCI Local Bus Speci fication publishe d by the PCI Sp ecial

Interest Group. The simple and predictable timing model of

FLASH370i ensures compliance with the PCI AC specifications

independent of the design. On the other hand, in CPLD and

FPGA architectures without simple and predictable timing, PCI

compliance is dependent upon routing and product term distri-

bution.

3.3V or 5.0V I/O Operation

The FLASH370i family can be configured to operate in both

3.3V and 5.0V systems. All devices have two sets of VCC pin s:

one set, VCCINT, for internal operation and input buffers, and

another set, VCCIO, for I/O output drivers. VCCINT pins must

always be connected to a 5.0V power supply. However, the

VCCIO pins may be connected to either a 3.3V or 5.0V powe r

supply, depending on the output requirements. When VCCIO

pins are connected to a 5.0V source, the I/O voltage levels are

compatible with 5.0V systems. When VCCIO pins are

connected to a 3.3V source, the input voltage levels are

compatible with both 5.0V and 3.3V systems, while the output

voltage levels are compatible with 3.3V systems. There will be

an additional timing delay on all output buffers when operating

in 3.3V I/O mode. The added flexibility of 3.3V I/O capability is

available in commercial and industrial temperature ranges.

Bus Hold Capabilities on all I/Os and Dedicated Inputs

In addition to ISR capability , a new feature called bus-hold has

been added to all FLASH370i I/Os and dedicated input pins.

Bus-hold, which is an improved version of the popular internal

pull-up resistor , is a weak latch connected to the pin that does

not degrade the device’s performance. As a latch, bus-hold

recalls the last state of a pin when it is three-stated, thus

reducing system noise in bus-interface applications. Bus-hold

additionally allows unused device pins to remain unconnected

on the board, which is particularly useful during prototyping as

designers can route new signals to the device withou t cutting

trace connections to VCC or GND.

Design Tools

Development software for the CY7C371i is available from

Cypress’s Warp™, Warp Professional™, and Warp Enter-

prise™ software packages. Please refer to the data sheets on

these products for more details. Cypress also actively

supports almost all third-party design tools. Please refer to

third-party tool support for further information.

CY7C374i

Document #: 38-03031 Rev. *A Page 5 of 15

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature ............. ....................–65°C to +150°C

Ambient Temperature with

Power Applied........ ... ... ...............................–55°C to +125°C

Supply Voltage to Ground Potential...............–0.5V to +7.0V

DC Voltage Applied to Outputs

in High-Z State....... ... ... ..................................–0.5V to +7.0V

DC Input Voltage................ ... .. .......................–0.5V to +7.0V

DC Program Voltage............. .. ......................................12.5V

Output Current into Outputs ........................................16 mA

Static Discharge V o ltage...........................................> 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current.....................................................> 200 mA

Operating Range

Range Ambient

Temperature VCC VCCINT VCCIO

Commercial 0°C to +70°C5V ± 0.25V 5V ± 0.25V or

3.3V ± 0.3V

Industrial −40°C to +85°C5V ± 0.5V 5V ± 0.5V or

3.3V ± 0.3V

Military[2] –55°C to +125°C 5V ± 0.5V

Electrical Characteristics Over the Operating Range[3, 4]

Parameter Description Test Conditions Min. Typ. Max. Unit

VOH Output HIGH Voltage VCC = Min. IOH = –3.2 mA (Com’l/Ind)[5] 2.4 V

IOH = –2.0 mA (Mil) V

VOHZ Output HIGH V oltage with

Output Disabled[9] VCC = Max. IOH = 0 µA (Com’l /I nd)[5, 6] 4.0 V

IOH = –50 µA (Com’l/Ind)[5, 6] 3.6 V

VOL Output LOW Voltage VCC = Min. IOL = 16 mA (Com’l/Ind)[5] 0.5 V

IOL = 12 mA (Mil) V

VIH Input HIGH V olt age Guaranteed Input Logical HIGH voltage for all inputs[7] 2.0 7.0 V

VIL Input LOW Voltage Guaranteed Input Logical LOW voltage for all inputs[7] –0.5 0.8 V

IIX Input Load Current VI = Internal GND, VI = VCC –10 +10 µA

IOZ Output Leakage Current VCC = Max., VO = GND or VO = VCC, Output Disabled –50 +50 µA

VCC = Max., VO = 3.3V, Outp ut Disabled[6] 0 –70 –125 µA

IOS Output Short

Circuit Current[8, 9] VCC = Max., VOUT = 0.5V –30 –160 mA

ICC Power Supply Current VCC = Max., IOUT = 0 mA, Com’l/Ind. 125 200 mA

f = 1 MHz, VIN = GND, VCC[10] Com’l “L” –66 75 125 mA

Military 125 250 mA

IBHL Input Bus Hold LOW

Sustaining Current VCC = Min., VIL = 0.8V +75 µA

IBHH Input Bus Hold HIGH

Sustaining Current VCC = Min., VIH = 2.0V –75 µA

IBHLO Input Bus Hold LOW

Overdrive Current VCC = Max. +500 µA

IBHHO Input Bus Hold HIGH

Overdrive Current VCC = Max. –500 µA

Notes:

2. TA is the “instant on” case temperature.

3. See the last page of this specification for Group A subgroup testing information.

4. If VCCIO is not specified, the device can be operating in either 3.3V or 5V I/O mode; VCC=VCCINT.

5. IOH = –2 mA, IOL = 2 mA for SDO.

6. When the I/O is three-stated, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered significantly

by a small leakage current. Note that all I/Os are three-sta ted during ISR programming. Refer to the application note “Understanding Bus Hold” for additional

information.

7. These are absolute values with respect to device ground. All ove rshoots due to system or tester noise are included.

8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test

problems caused by tester ground degradation.

9. Tested initially and after any design or process changes that may affect these parameters.

10.Measured with 16-bit counter programmed into each logic block.

CY7C374i

Document #: 38-03031 Rev. *A Page 6 of 15

Notes:

11. CI/O for the CLCC package are 12 pF Max

12.CI/O for dedicated Input s, and for I/O pins with JTAG functionality is 12 pF Max., and for ISREN is 15 pF Max.

13.tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.

Capacitance[9]

Parameter Description Test Conditions Min. Max. Unit

CI/O[11, 12] Input Capacitance VIN = 5.0V at f = 1 MHz 8 pF

CCLK Clock Signal Capacitance VIN = 5.0V at f = 1 MHz 5 12 pF

Inductance[9]

Parameter Description Test Conditions 100-PinTQFP 84-Lead PLCC 84-Lead CLCC Unit

L Maximum Pin Inductance VIN = 5.0V at f = 1 MHz 8 8 5 nH

Endurance Characteristics[9]

Parameter Description Test Conditions Max. Unit

N Maximum Reprogramming Cycles Normal Programming Conditions 100 Cycles

AC Test Loads and Waveforms

Parameter[13] VXOutput Waveform Measurement Level

tER(–) 1.5V

tER(+) 2.6V

tEA(+) 1.5V

tEA(–) Vthc

90%

10%

3.0V

GND

90%

10%

ALL INPUT PULSES

OUTPUT

35 pF

INCLUDING

JIG AND

SCOPE

OUTPUT

5 pF

INCLUDING

JIG AND

SCOPE

(a) (b)

<2ns

OUTPUT

238Ω(COM'L)

319Ω(MIL)

170Ω(COM'L)

236Ω(MIL)

99Ω(COM'L)

136Ω(MIL)

Equivalent to: THÉ VENIN EQUIVALENT

2.08V (COM'L)

2.13V (MIL)

238Ω(COM'L)

319Ω(MIL)

170Ω(COM'L)

236Ω(MIL)

(c)

<2ns

VOH –0.5V VX

VOH

–0.5V VX

–0.5V VOH

CY7C374i

Document #: 38-03031 Rev. *A Page 7 of 15

Switching Characteristics Over the Operating Range [14]

Parameter Description 7C374i–125 7C374i–100 7C374i–83

7C374iL–83 7C374i–66

7C374iL–66 UnitMin. Max. Min. Max. Min. Max. Min. Max.

Combinatorial Mode Parameters

tPD Input to Combinatorial Output[1] 10 12 15 20 ns

tPDL Input to Output Through Transparent Input or

Output Latch[1] 13 15 18 22 ns

tPDLL Input to Output Through Transparent Input and

Output Latches[1] 15 16 19 24 ns

tEA Input to Output Enable[1] 14 16 19 24 ns

tER Input to Output Disable 14 16 19 24 ns

Input Registered/Latched Mode Parameters

tWL Clock or Latch Enable Input LOW Time[9] 3345ns

tWH Clock or Latch Enable Input HIGH Time [9] 3345ns

tIS Input Register or Latch Set-Up Time 2 2 3 4 ns

tIH Input Register or Latch Hold Time 2 2 3 4 ns

tICO Input Register Clock or Latch Enable to

Combinatorial Output[1] 14 16 19 24 ns

tICOL Input Register Clock or Latch Enable to Output

Through Transparent Output Latch[1] 16 18 21 26 ns

Output Registered/Latched Mod e Parameters

tCO Clock or Latch Enable to Output[1] 6.5 7 8 10 ns

tSSet-Up Time from Input to Clock or Latch Enable 5.5 6 8 10 ns

tHRegister or Latch Data Hold Time 0 0 0 0 ns

tCO2 Output Clock or Latch Enable to Output Delay

(Through Memory Array)[1] 14 16 19 24 ns

tSCS Output Clock or Latch Enable to Output Clock

or Latch Enable (Through Memory Array) 8101215ns

tSL Set-Up Time from Input Through Transp arent

Latch to Output Register Clock or L atch Enable 10 12 15 20 ns

tHL Hold T ime for Input Through Transparent Latch

from Output Register Clock or Latch Enable 0000ns

fMAX1 Maximum Frequency with Internal Feedback

(Least of 1/tSCS, 1/(tS + tH), or 1/tCO)[9] 125 100 83 66 MHz

fMAX2 Maximum Frequency Data Path in Output

Registered/Latched Mode (Lesser of 1/(tWL +

tWH), 1/(tS + tH), or 1/tCO)

158.3 143 125 100 MHz

fMAX3 Maximum Frequency with External Feedback

(Lesser of 1/(tCO + tS) and 1/(tWL + tWH)) 83.3 76.9 67.5 50 MHz

tOH–tIH

37x Output Data Stable from Output Clock Minus

Input Register Hold Time for 7C37x[9, 15] 0000ns

Pipelined Mode Paramete rs

tICS Input Register Clock to Output Register Clock 8 10 12 15 ns

fMAX4 Maximum Frequency in Pipelined Mode (Least

of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH),

or 1/tSCS)

125 100 83.3 66.6 MHz

Notes:

14.All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.

15.This sp ecifi catio n is in tended to gua rantee int erface compatibility o f the other member s of the CY7 C370i fa mily with t he CY 7C374i . This specif icatio n is me t for

the devices operating at the same ambient temperature and at the same power su pply voltage.

CY7C374i

Document #: 38-03031 Rev. *A Page 8 of 15

Reset/Preset Parameters

tRW Asynchronous Reset Width[9] 10 12 15 20 ns

tRR Asynchronous Reset Recovery Time[9] 12 14 17 22 ns

tRO Asynchronous Reset to Output[1] 16 18 21 26 ns

tPW Asynchronous Preset Width[9] 10 12 15 20 ns

tPR Asynchronous Preset Recovery Time[9] 12 14 17 22 ns

tPO Asynchronous Preset to Output[1] 16 18 21 26 ns

Tap Controller Parameter

fTAP Tap Controller Frequency 500 500 500 500 kHz

3.3V I/O Mode Parameters

t3.3IO 3.3V I/O mode timing adder 1 1 1 1 ns

Switching Characteristics Over the Operating Range (continued)[14]

Parameter Description 7C374i–125 7C374i–100 7C374i–83

7C374iL–83 7C374i–66

7C374iL–66 UnitMin. Max. Min. Max. Min. Max. Min. Max.

Switching Waveforms

Combinatorial Output

tPD

INPUT

COMBINATORIAL

OUTPUT

Registered Output

INPUT

CLOCK

tCO

REGISTERED

OUTPUT

CLOCK

tWL

tWH

Latched Output

INPUT

LATCH ENABLE

tCO

LATCHED

OUTPUT

tPDL

CY7C374i

Document #: 38-03031 Rev. *A Page 9 of 15

Switching Waveforms (continued)

Registered Inpu t

tIS

REGISTERED

INPUT

INPUT REGISTER

CLOCK

tICO

COMBINATORIAL

OUTPUT

tIH

CLOCK

tWL

tWH

Latched Input

tIS

LATCHED INPUT

LATCH ENABLE

tICO

COMBINATORIAL

OUTPUT

tIH

tPDL

LATCH ENABLE

tWL

tWH

tICS

LATCHED INPUT

OUTPUT LATCH

ENABLE

LATCHED

OUTPUT

tPDLL

LATCH ENABLE

tWL

tWH

tICOL

INPUT LATCH

ENABLE

tSL tHL

LatchedInput and Output

CY7C374i

Document #: 38-03031 Rev. *A Page 10 of 15

Switching Waveforms (continued)

Asynchronous Reset

INPUT

tRO

REGISTERED

OUTPUT

CLOCK

tRR

tRW

INPUT

tPO

REGISTERED

OUTPUT

CLOCK

tPR

tPW

Asynchronous Preset

Output Enable/Disable

INPUT

tER

OUTPUTS

tEA

Ordering Information

Speed

(MHz) Ordering Code Package

Name Package Ty pe Operating

Range

125 CY7C374i–125AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C374i–125JC J83 84-Lead Plastic Leaded Chip Carrier

100 CY7C374i–100AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C374i–100JC J83 84-Lead Plastic Leaded Chip Carrier

CY7C374i–100AI A100 100-Pin Thin Quad Flat Pack Industrial

CY7C374i–100JI J83 84-Lead Plastic Leaded Chip Carrier

83 CY7C374i–83AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C374i–83JC J83 84-Lead Plastic Leaded Chip Carrie r

CY7C374i–83AI A100 100-Pin Thin Quad Flat Pack Industrial

CY7C374i–83JI J83 84-Lead Plastic Leaded Chip Carrier

CY7C374i–83GMB G84 84-Pin Ceramic Pin Grid Array Military

CY7C374i–83YMB Y84 84-Pin Ceramic Leaded Chip Carrier

CY7C374iL–83AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C374iL–83JC J83 84-Lead Plastic Leaded Chip Carrier

CY7C374i

Document #: 38-03031 Rev. *A Page 11 of 15

MILITARY SPECIFICATIONS

Group A Subgroup Testing

66 CY7C374i–66AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C374i–66JC J83 84-Lead Plastic Leaded Chip Carrie r

CY7C374i–66AI A100 100-Pin Thin Quad Flat Pack Industrial

CY7C374i–66JI J83 84-Lead Plastic Leaded Chip Carrier

CY7C374i–66GMB G84 84-Pin Ceramic Pin Grid Array Military

CY7C374i–66YMB Y84 84-Pin Ceramic Leaded Chip Carrier

CY7C374iL–66AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C374iL–66JC J83 84-Lead Plastic Leaded Chip Carrier

Ordering Information

Speed

(MHz) Ordering Code Package

Name Package Ty pe Operating

Range

DC Characteristics

Parameter Subgroups

VOH 1, 2, 3

VOL 1, 2, 3

VIH 1, 2, 3

VIL 1, 2, 3

IIX 1, 2, 3

IOZ 1, 2, 3

ICC1 1, 2, 3

Switching Characteristics

Parameter Subgroups

tPD 9, 10, 11

tPDL 9, 10, 11

tPDLL 9, 10, 11

tCO 9, 10, 11

tICO 9, 10, 11

tICOL 9, 10, 11

tS9, 10, 11

tSL 9, 10, 11

tH9, 10, 11

tHL 9, 10, 11

tIS 9, 10, 11

tIH 9, 10, 11

tICS 9, 10, 11

tEA 9, 10, 11

tER 9, 10, 11

CY7C374i

Document #: 38-03031 Rev. *A Page 12 of 15

Package Diagrams

100-Pin Thin Plastic Quad Flat Pack (TQFP) A100

51-85048-*B

CY7C374i

Document #: 38-03031 Rev. *A Page 13 of 15

Package Diagrams (continued)

84-Pin Grid Array (Cavity Up) G84

51-80015-*A

84-Lead Plastic Leaded Chip Carrier J83

51-85006-*A

CY7C374i

Document #: 38-03031 Rev. *A Page 14 of 15

of any circ uitry other than ci rcuitry embodied in a Cypress S emiconductor produc t. Nor does it con vey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor product s in life-support syste ms applicat ion implies th at th e manu fac turer assu mes all risk of such use and in doing so ind emnifie s Cypress Semicondu ctor ag ainst all charges.

ISR, UltraLogic, FLASH370, FLASH370i, Warp, Warp Professional, and Warp Enterprise are trademarks of Cypress Semiconductor

Corporation. All product and company names mentioned in this document are trademarks of their respective hol ders.

Package Diagrams (continued)

84-Pin Ceramic Leaded Chip Carrier Y84

51-80095-*A

CY7C374i

Document #: 38-03031 Rev. *A Page 15 of 15

Document History Page

Document Title: CY7C374i UltraLogic™ 128-Macrocell Flash CPLD

Document Number: 38-03031

REV. ECN NO. Issue Date Orig. of

Change Description of Ch ange

** 106376 07/11/01 SZV Ch anged from Spec number: 38-00496 to 38-03031

*A 213375 See ECN FSG Added no te to title page: “Use Ultra37000 For All New Designs”