APPLICATION
NOTE
AP-377
December 1995
16-Mbit Flash Product Family
Software Drivers
28F016SA, 28F016SV,
28F016XS, 28F016XD
TAYLOR GAUTIER
MCD APPLICATIONS ENGINEERING
PATRICK KILLELEA
MCD APPLICATIONS ENGINEERING
SALIM FEDEL
MCD APPLICATIONS ENGINEERING
Order Number: 292126-003
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoev-
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or call 1-800-879-4683
COPYRIGHT ©INTEL CORPORATION, 1995
16-Mbit FLASH PRODUCT FAMILY
SOFTWARE DRIVERS
CONTENTS PAGE
INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 1
28F016SA C DRIVERS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4
28F016SA ASM86 DRIVERS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 26
APPENDIX A: FUNCTION CHANGES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ A-1
APPENDIX B: GLOSSARY OF TERMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ B-1
APPENDIX C: ADDITIONAL INFORMATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ C-1
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INTRODUCTION
ABOUT THE CODE
This application note provides example software code
for word writing, block erasing, and otherwise control-
ling Intel’s 28F016SA, 28F016SV, 28F016XS and
28F016XD (hereafter referred to as 28F016SA) 16
Mbit symmetrically blocked memory components. Two
programming languages are provided: high-level ‘‘C’’
for broad platform support, and more optimized
ASM86 assembly. In many cases, the driver routines
can be inserted ‘‘as is’’ into the main body of code being
developed by the system software engineer. Extensive
comments are included in each routine to facilitate
adapting the code to specific applications.
The internal automation of the 28F016SA makes soft-
ware timing loops unnecessary and results in platform-
independent code. The following example code is de-
signed to be executed in any type of memory and with
all processor clock rates. C code can be used with many
microprocessors and microcontrollers, while ASM86
assembly code provides a solution optimized for Intel
microprocessors and embedded processors.
The 28F016SA, like the 28F008SA, is divided into 64
Kbyte blocks. Since the GSR and BSR are defined rela-
tive to the nearest preceding block beginning address, I
often refer to this ‘‘block base’’ address in the com-
ments.
Assumptions:
#Pointers (in C) or EDI offsets (in ASM86) are four
(4) bytes long, providing a flat addressing space over
the entire 28F016SA device. This implies the use of
386 or higher machines. If the code is to be run on a
machine with a smaller address space, the code must
be modified to include some sort of ‘‘windowing’’
scheme which maps segments of flash into system
memory. The Intel 82365 is commonly used for this
purpose.
#‘‘Ints’’ are 16 bit and ‘‘longs’’ 32 bit in C.
#It is assumed that these pointers return a value equal
to what they are pointing to. In other words, even
though the pointer may be four (4) bytes long, this
does not imply that incrementing the pointer by one
will move the pointer four (4) bytes in memory. It is
entirely dependent upon what the pointer is pointing
to that determines how the increment will be effect-
ed. In the case of four (4) byte pointers and 16-bit
ints, incrementing the pointer by one will effectively
move the pointer two (2) bytes.
#There exists a function ‘‘setÐpin’’ which can set an
individual 28F016SA pin, given the pin number.
#There exists a function ‘‘getÐpin’’ which can return
the value of an individual 28F016SA pin, given the
pin number.
#The C code can access a function which derives the
corresponding block base address from any given
address.
#BYTEÝpin on the device determines whether ad-
dressing refers to words or bytes. I assume word
writes/reads to a single device. With minor modifi-
cations this code can be adapted for a pair of
28F016SAs in Byte mode.
#28F016SA commands can be written to any address
in the block or device to be affected by that com-
mand.
Both the C and ASM86 code in this document contain
the following routines, in this order:
CSRÐwordÐbyteÐwrites(compatiblewith28F008SA)
CSRÐblockÐerase(compatible with 28F008SA)
CSRÐeraseÐsuspendÐtoÐread(compatible with
28F008SA)
lockÐblock
lockÐstatusÐuploadÐtoÐBSR
updateÐdataÐinÐaÐlockedÐblock
addÐdataÐinÐaÐlockedÐblock
ESRÐwordÐwrite
twoÐbyteÐwrite
ESRÐpageÐbufferÐwrite
ESRÐblockÐerase
ESRÐeraseÐallÐunlockedÐblocks
ESRÐsuspendÐtoÐreadÐarray
ESRÐautomaticÐeraseÐsuspendÐtoÐwrite
ESRÐfullÐstatusÐcheckÐforÐdataÐwrite
ESRÐfullÐstatusÐcheckÐforÐerase
singleÐloadÐtoÐpagebuffer
sequentialÐloadÐtoÐpagebuffer
uploadÐdeviceÐinformation
RYBYÐreconfiguration
pageÐbufferÐswap
The names of these routines have been changed to more
closely match the algorithms presented in the
28F016SA User’s Manual (Order Number 297372).
Please see Appendix A for a table documenting these
changes.
ABOUT THE 28F016SA
Companion product datasheets for the 28F016SA
should be reviewed in conjunction with this application
note for a complete understanding of the device.
The example code makes extensive use of bit-masking
when interpreting the status registers. As a quick re-
view, note that any bit in a register can be tested by
bitwise ANDing the register with the appropriate pow-
er of two. Since all of the bits other than the one being
1
AP-377
tested are masked out, testing the resulting byte for
truth is the same as testing the desired bit for truth. For
example, if a register contains 01001010, the test for bit
3 would be ANDing the register with 00001000, or hex
8, and testing the result for truth:
Binary Hex
01001010 4A Register
& 00001000 & 08 Mask for bit 3
e00001000 e08 Result
In this case the result byte is true, indicating that bit 3
in the register was a 1.
The meanings of the individual bits of these registers is
presented here for reference. Note that there are two
status register spaces, both of which are distinct from
the flash memory array address space. In the CSR
space, the CSR is mapped to every address. In the ESR
space, the GSR is mapped two words above the base of
each 64K byte block, i.e. to addresses 2, 8002H,
10002H, etc. (in word mode), while each BSR is simi-
larly mapped one word above the base of each 64K byte
block to locations 1, 8001H, 10001H, etc. (in word
mode), each BSR reflecting the status of its own block.
CSR.7 Write State Machine 1eready
Status 0ebusy
CSR.6 Erase-suspend Status 1eerase suspended
0eerase in progress/
completed
CSR.5 Erase Status 1eerror in block
erase
0esuccessful block
erase
CSR.4 Data-write Status 1eerror in data write
0esuccessful data
write
CSR.3 VPP Status 1eVPP low detect/
operation aborted
0eVPP OK when
operation occurred
CSR.2 Reserved for future use
CSR.1 Reserved for future use
CSR.0 Reserved for future use
GSR.7 Write State Machine 1eready
Status 0ebusy
GSR.6 Operation-suspend 1eoperation
Status suspended
0eoperation in
progress/
completed
GSR.5 Device Operation 1eoperation
Status unsuccessful
0eoperation
successful or
running
GSR.4 Device Sleep Status 1edevice in sleep
0edevice not in
sleep
GSR.3 Queue Status 1equeue full
0equeue available
GSR.2 Page Buffer 1eone/two page
Availability buffers available
0eno page buffers
available
GSR.1 Page Buffer Status 1eselected page
buffer ready
0eselected page
buffer busy
GSR.0 Page Buffer Select 1epage buffer 1
Status selected
0epage buffer 0
selected
BSR.7 Block Status 1eready
0ebusy
BSR.6 Block-lock Status 1eblock unlocked
for write/erase
0eblock locked to
write/erase
BSR.5 Block Operation 1eerror in block
Status operation
0esuccessful block
operation
BSR.4 Block Operation Abort 1eblock operation
Status aborted
0eblock operation
not aborted
BSR.3 Queue Status 1edevice queue full
0edevice queue
available
BSR.2 VPP Status 1eVPP low detected
0eVPP OK when
operation
occurred
BSR.1 Reserved for future
use
BSR.0 Reserved for future
use
2
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28F016SA Commands
The 28F016SA command set is a superset of the
28F008SA command set, giving existing 28F008SA
code the ability to run on the 28F016SA with minimal
modifications.
28F008SA-Compatible Commands
00 invalid/reserved
20 single block erase
40 word/byte write
50 clear status registers
70 read CSR
90 read ID codes
B0 erase suspend
D0 confirm/resume
FF read flash array
28F016SA Performance-Enhancement
Commands
0C page buffer write to flash
71 read GSR and BSRs (i.e. the ESR)
72 page buffer swap
74 single load to page buffer
75 read page buffer
77 lock block
80 abort
96,xx RY/BYÝreconfiguration and SFI
configuration (28F016XS)
97 upload BSRs with lock bit
99 upload device information
A7 erase all unlocked blocks
E0 sequential load to page buffer
F0 sleep
FB two-byte write
28F016XD and 28F016XS Feature Sets
The following features are not supported on the
28F016XD and 28F016XS Fast Flash memories (as
compared to the 28F016SA/SV/32SA FlashFileTM
memories):
#All page buffer operations (read, load, program, Up-
load Device Information)
#Command queuing
#Erase All Unlocked Blocks and Two-Byte Write
#Software Sleep and Abort
#RY/BYÝreconfiguration via the Device Configu-
ration command
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APPENDIX A
FUNCTION CHANGES
OLD FUNCTION NAME NEW FUNCTION NAME
compatibleÐblockÐerase CSRÐblockÐerase
compatibleÐsuspendÐtoÐread CSRÐeraseÐsuspendÐtoÐread
compatibleÐbyteÐwrite CSRÐwordÐbyteÐwrites
ESRÐblockÐerase N/C
ESRÐstatusÐcheckÐafterÐerase*ESRÐfullÐstatusÐcheckÐforÐerase
ESRÐstatusÐcheckÐafterÐwrite*ESRÐfullÐstatusÐcheckÐforÐdataÐwrite
ESRÐsuspendÐtoÐread ESRÐsuspendÐtoÐreadÐarray
ESRÐwordÐwrite N/C
eraseÐallÐunlockedÐblocks ESRÐeraseÐallÐunlockedÐblocks
lockÐblock N/C
statusÐupload lockÐstatusÐuploadÐtoÐBSR
pagebufferÐwriteÐtoÐflash ESRÐpagebufferÐwrite
sequentialÐpagebufferÐload sequentialÐloadÐtoÐpagebuffer
singleÐpagebufferÐload singleÐloadÐtoÐpagebuffer
twoÐbyteÐwrite N/C
writeÐduringÐerase ESRÐautomaticÐeraseÐsuspendÐtoÐwrite
NOTE:
*code added in Rev 2.0.
A-1
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APPENDIX B
Glossary of Terms
BSR: Block Status Register. Each BSR reflects the status of its 64KB block.
CSR: Compatible Status Register. The CSR reflects the status of the entire device and is identical in format
to the Status Register of the 28F008SA.
EDI: Extended Data Index register on 80386 and higher CPUs.
ESR: Extended Status Registers. The GSR and BSRs.
GSR: Global Status Register. The GSR provides additional information about entire device status.
RY/BYÝ: Output pin from the 28F016SA indicating status of current operation.
VPP: Voltage necessary to program the 28F016SA (12V).
WSM: Write State Machine. On-board processor automating write, erase and other functions.
B-1
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APPENDIX C
ADDITIONAL INFORMATION
Order Number Document
290489 28F016SA Datasheet
292124 AP-375 Upgrade Considerations from the 28F008SA to the 28F016SA
297372 16-Mbit Flash Product User’s Manual
292127 AP-378 System Optimization Using the Enhanced Features of the 28F016SA
294016 ER-33 Flash Memory Technology ETOX IV
290528 28F016SV Datasheet
292144 AP-393 28F016SV Compatibility with 28F016SA
REVISION HISTORY
Number Description
001 Original Version
002 Updated Version of C and ASM code, compatible with 28F016SV/XS/XD
003 Added 28F016XS and 28F016XD Feature Set notice
C-1
