DS2404
EconoRAM Time Chip
DS2404
020998 1/25
FEATURES
4096 bits of nonvolatile dual–port memory including
real time clock/calendar in binary format, program-
mable interval timer, and programmable power–on
cycle counter
1–WireTM interface for MicroLANTM communication
at 16.3k bits per second
3–wire host interface for high–speed data commu-
nications at 2M bits per second
Unique, factory–lasered and tested 64–bit registra-
tion number (8–bit family code + 48–bit serial number
+ 8–bit CRC tester) assures absolute traceability
because no two parts are alike
Memory partitioned into 16 pages of 256–bits for
packetizing data
256–bit scratchpad with strict read/write protocols
ensures integrity of data transfer
Programmable alarms can be set to generate inter-
rupts for interval timer, real time clock, and/or cycle
counter
16–pin DIP, SOIC and SSOP packages
Operating temperature range from –40°C to +85°C
Operating voltage range from 2.8 to 5.5 Volts
PIN ASSIGNMENT
CLK
NC
GND
GND
DQ
RST
IRQ
16–PIN DIP (300 MIL)
16–PIN SOIC (300 MIL)
16–PIN SSOP (300 MIL)
See Mechanical Drawings Section
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
NC
VCC
I/O
X1
X2
VCC
VBATO
VBATB
1HZ
PIN DESCRIPTION
VCC 2.8 to 5.5 Volts
IRQ Interrupt Output
RST 3–Wire Reset Input
DQ 3–Wire Input/Output
I/O 1–Wire Input/Output
CLK 3–Wire Clock Input
NC No Connection
GND Ground
VBATB Battery Backup Input
VBATO Battery Operate Input
1 Hz 1 Hz Output
X1,X2 Crystal Connections
ORDERING INFORMATION
DS2404 16–pin DIP
DS2404S 16–pin SOIC
DS2404B 16–pin SSOP
DESCRIPTION
The DS2404 EconoRAM T ime Chip offers a simple so-
lution for storing and retrieving vital data and time in-
formation with minimal hardware. The DS2404 con-
tains a unique lasered ROM, real–time clock/calendar,
interval timer, cycle counter, programmable interrupts
and 4096–bits of SRAM. Two separate ports are pro-
vided for communication, 1–Wire and 3–wire. Using the
1–Wire port, only one pin is required for communication,
and the lasered ROM can be read even when the
DS2404 is without power. The 3–wire port provides high
speed communication using the traditional Dallas Semi-
conductor 3–wire interface. With either interface, a strict
protocol for accessing the DS2404 insures data integri-
ty . Utilizing backup energy sources, the data is nonvola-
tile and allows for stand-alone operation.
The DS2404 features can be used to create a stop-
watch, alarm clock, time and date stamp, logbook, hour
meter, calendar, system power cycle timer, expiration
timer, and event scheduler.
DS2404
020998 2/25
DETAILED PIN DESCRIPTION
PIN SYMBOL DESCRIPTION
1, 16 VCC Power input pins for VCC operate mode. 2.8 to 5.5 volts operation. Either
pin can be used for VCC. Only one is required for normal operation. (See
VBATO pin description and “Power Control” section).
2 IRQ Interrupt output pin: Open drain.
3 RST Reset input pin for 3–wire operation. (See “Parasite Power” section.)
4 DQ Data input/output pin for 3–wire operation.
5 I/O Data input/output for 1–Wire operation: Open drain. (See “Parasite Power”
section.)
6 CLK Clock input pin for 3–wire operation.
7, 12 NC No connection pins.
8, 13 GND Ground pin: Either pin can be used for ground.
9 VBATB Battery backup input pin: Battery voltage can be 2.8 to 5.5 volts. (See
VBATO pin description and “Power Control” section.)
10 VBATO Battery operate input pin for 2.8 to 5.5 volt operation. The VCC & VBATB
pins must be grounded when this pin is used to power the chip. (See “Power
Control” section.)
11 1Hz 1 Hz square wave output: Open drain.
14, 15 X1, X2Crystal pins. Connections for a standard 32.768 kHz quartz crystal, Daiwa
part number DT–26S (be sure to request 6 pF load capacitance).
NOTE: X1 and X2 are very high impedance nodes. It is recommended that
they and the crystal be guard–ringed with ground and that high frequency
signals be kept away from the crystal area. See Figure 18 and Application
Note 58 for details.
OVERVIEW
The DS2404 has four main data components: 1) 64–bit
lasered ROM, 2) 256–bit scratchpad, 3) 4096–bit
SRAM, and 4) timekeeping registers. The timekeeping
section utilizes an on–chip oscillator that is connected to
an external 32.768 kHz crystal. The SRAM and time-
keeping registers reside in one contiguous address
space referred to hereafter as memory . All data is read
and written least significant bit first.
Two communication ports are provided, a 1–Wire port
and a 3–wire port. A port selector determines which of
the two ports is being used. The communication ports
and the ROM are parasite-powered via I/O, RST, or
VCC. This allows the ROM to be read in the absence of
power. The ROM data is accessible only through the
1–Wire port. The scratchpad and memory are accessi-
ble via either port.
If the 3–wire port is used, the master provides one of
four memory function commands: 1) read memory, 2)
read scratchpad, 3) write scratchpad, or 4) copy
scratchpad. The only way to write memory is to first
write the scratchpad and then copy the scratchpad data
to memory. (See Figure 6.)
If the 1–Wire port is used, the memory functions will not
be available until the ROM function protocol has been
established. This protocol is described in the ROM func-
tions flow chart (Figure 9). The master must first provide
one of five ROM function commands: 1) read ROM, 2)
match ROM, 3) search ROM, 4) skip ROM or 5) search
interrupt. After a ROM function sequence has been suc-
cessfully executed, the memory functions are accessi-
ble and the master may then provide any one of the four
memory function commands (Figure 6.)
The “Power Control” section provides for two basic pow-
er configurations, battery operate mode and VCC oper-
ate mode. The battery operate mode utilizes one supply
connected to VBATO. The VCC operate mode may utilize
two supplies; the primary supply connects to VCC and a
backup supply connects to VBATB.
DS2404
020998 3/25
DS2404 BLOCK DIAGRAM Figure 1
64–BIT
LASERED
ROM
INTERNAL REGISTERS
AND COUNTERS
ROM FUNCTION
CONTROL
PORT
SELECTOR
MEMORY
FUNCTION
CONTROL
256–BIT
SCRATCHPAD
POWER
CONTROL 4096–BIT
SRAM
32.768 kHz
OSCILLATOR
IRQ
1 Hz
I/O
RST
CLK
DQ
VCC
VBATB
VBATO
GND
X1
X2
HOLDING REGISTERS
TIMEKEEPING
FUNCTIONS
PARASITE–
POWERED
CIRCUITRY
MEMORY
3–WIRE
PORT
1–WIRE
PORT
COMMUNICATION PORTS
T wo communication ports are provided, a 1–Wire and a
3–wire port. The advantages of using the 1–Wire port
are as follows: 1) provides access to the 64– bit la-
sered ROM, 2) consists of a single communication sig-
nal (I/O), and 3) multiple devices may be connected to
the 1–Wire bus. The 1–Wire bus has a maximum data
rate of 16.3k bits/second and requires one 5kexternal
pull–up.
The 3–wire port consists of three signals, RST, CLK,
and DQ. RST is an enable input, DQ is bi–directional se-
rial data, and the CLK input is used to clock in or out the
serial data. The advantages of using the 3–wire port are
1) high data transfer rate (2 MHz), 2) simple timing, and
3) no external pull–up required.
Port selection is accomplished on a first–come, first-
serve basis. Whichever port comes out of reset first will
obtain control. For the 3–wire port, this is done by bring-
ing RST high. For the 1–Wire port, this is done on the
first falling edge of I/O after the reset and presence
pulses. (See “1–Wire Signalling” section.) More
information on how to arbitrate port access is found in
section “Device Operation Modes” later in this docu-
ment.
DS2404
020998 4/25
PARASITE POWER
The block diagram (Figure 1) shows the parasite–pow-
ered circuitry . This circuitry “steals” power whenever the
I/O, RST, or VCC pins are high. When using the 1–Wire
port in battery operate mode, RST and VCC provide no
power since they are low . However, I/O will provide suf-
ficient power as long as the specified timing and voltage
requirements are met. The advantages of parasite pow-
er are two–fold: 1) by parasiting off these pins, battery
power is conserved and 2) the ROM may be read in ab-
sence of normal power. For instance, in battery–operate
mode, if the battery fails, the ROM may still be read nor-
mally.
In battery–backed mode, if VCC fails, the port switches
in the battery but inhibits communication. The ROM
may still be read normally over the 1–Wire port if RST
is low.
64–BIT LASERED ROM
Each DS2404 contains a unique ROM code that is 64
bits long. The first eight bits are a 1–Wire family code
(DS2404 code is 04h). The next 48 bits are a unique se-
rial number. The last eight bits are a CRC of the first 56
bits. (See Figure 2.)
The 1–Wire CRC is generated using a polynomial gen-
erator consisting of a shift register and XOR gates as
shown in Figure 3. The polynomial is X8 + X5 + X4 + 1.
Additional information about the Dallas 1–Wire Cyclic
Redundancy Check is available in Application Note 27,
“Understanding and Using Cyclic Redundancy Checks
with Dallas Semiconductor iButton Products”.
The shift register bits are initialized to zero. Then start-
ing with the least significant bit of the family code, one bit
at a time is shifted in. After the 8th bit of the family code
has been entered, then the serial number is entered.
After the 48th bit of the serial number has been entered,
the shift register contains the CRC value. Shifting in the
eight bits of CRC should return the shift register to all
zeros.
64–BIT LASERED ROM Figure 2
DS2404 F AMILY
CODE
SERIAL
NUMBER
CRC
04h
48–BIT
UNIQUE
NUMBER
8 BITS
LSB
MSB
1–WIRE CRC CODE Figure 3
1ST
STAGE 2ND
STAGE 3RD
STAGE 4TH
STAGE 5TH
STAGE 6TH
STAGE 7TH
STAGE 8TH
STAGE
X0X1X2X3X4X5X6X7X8
Polynomial = X8 + X5 + X4 + 1
XORXOR XOR
INPUT
DS2404
020998 5/25
MEMORY MAP Figure 4
0000h
0020h
0040h
0060h
0080h
00A0h
00C0h
00E0h
0100h
0120h
0140h
0160h
0180h
01A0h
01C0h
01E0h
0200h
PAGE 0
PAGE 1
PAGE 2
PAGE 3
PAGE 4
PAGE 5
PAGE 6
PAGE 7
PAGE 8
PAGE 9
PAGE 10
PAGE 11
PAGE 12
PAGE 13
PAGE 14
PAGE 15
PAGE 16
PAGE
SCRATCHPAD
STATUS REGISTER
CONTROL REGISTER
REAL–TIME
COUNTER REGISTERS
INTERVAL TIME
COUNTER REGISTERS
CYCLE
COUNTER REGISTERS
REAL–TIME
ALARM REGISTERS
INTERVAL TIME
ALARM REGISTERS
CYCLE
ALARM REGISTERS
PAGE 17
TIMEKEEPING REGISTERS
0200h
0201h
0202h
0207h
020Ch
0215h
021Ah
0210h
STATUS REGISTER
X CCE ITE RTE CCF ITF RTFX 0200h
DSEL STOP
START AUTO
MAN OSC RO WPC WPI WPR 0201h
76543210
76543210
CONTROL REGISTER
MEMORY
NOTE: Each page is 32 bytes (256 bits). The hex values
represent the starting address for each page or register.
DS2404
020998 6/25
MEMORY
The memory map in Figure 4 shows a page (32 bytes)
called the scratchpad and 17 pages called memory.
Pages 0 through 15 each contain 32 bytes which make
up the 4096–bit SRAM. Page 16 has only 30 bytes
which contain the timekeeping registers.
The scratchpad is an additional page of memory that
acts as a buffer when writing to memory. Data is first
written to the scratchpad where it can be read back.
After the data has been verified, a copy scratchpad
command will transfer the data to memory. This process
insures data integrity when modifying the memory.
TIMEKEEPING
A 32.768 kHz crystal oscillator is used as the time base
for the timekeeping functions. The oscillator can be
turned on or off by an enable bit in the control register.
The oscillator must be on for the real time clock, interval
timer, cycle counter and 1 Hz output to function.
The timekeeping functions are double buffered. This
feature allows the master to read time or count without
the data changing while it is being read. To accomplish
this, a snapshot of the counter data is transferred to
holding registers which the user accesses. This occurs
after the eighth bit of the Read Memory Function com-
mand.
Real–Time Clock
The real–time clock is a 5–byte binary counter. It is in-
cremented 256 times per second. The least significant
byte is a count of fractional seconds. The upper four
bytes are a count of seconds. The real–time clock can
accumulate 136 years of seconds before rolling over.
Time/date is represented by the number of seconds
since a reference point which is determined by the user.
For example, 12:00A.M., January 1, 1970 could be a
reference point.
Interval Timer
The interval timer is a 5–byte binary counter . When en-
abled, it is incremented 256 times per second. The least
significant byte is a count of fractional seconds. The in-
terval timer can accumulate 136 years of seconds be-
fore rolling over. The interval timer has two modes of op-
eration which are selected by the AUT O/MAN bit in the
control register . In the auto mode, the interval timer will
begin counting after the I/O line has been high for a
period of time determined by the DSEL bit in the control
register. Similarly, the interval timer will stop counting af-
ter the I/O line has been low for a period of time deter-
mined by the DSEL bit. In the manual mode, time accu-
mulation is controlled by the STOP/START bit in the
control register.
NOTE: For auto mode operation, the high level on the
I/O pin must be greater than or equal to 70% of VCC or
VBATO.
Cycle Counter
The cycle counter is a 4–byte binary counter. It incre-
ments after the falling edge of the I/O line if the appropri-
ate I/O line timing has been met. This timing is selected
by the DSEL bit in the control register. (See “Status/
Control” section).
NOTE: For cycle counter operation, the high level on
the I/O pin must be greater than or equal to 70% of VCC
or VBATO.
Alarm Registers
The alarm registers for the real–time clock, interval tim-
er, and cycle counter all operate in the same manner.
When the value of a given counter equals the value in its
associated alarm register , the appropriate flag bit is set
in the status register. If the corresponding interrupt en-
able bit(s) in the status register is set, an interrupt is gen-
erated. If a counter and its associated alarm register are
write protected when an alarm occurs, access to the de-
vice becomes limited. (See “Status/Control”, “Inter-
rupts”, and the “Programmable Expiration” sections.)
STATUS/CONTROL REGISTERS
The status and control registers are the first two bytes of
page 16 (see “Memory Map”, Figure 4).
Status Register
76 5 4 321 0
0200hX X CCE ITE RTE CCF ITF RTF
Don’t care bits Read Only
RTF
ITF
CCF
0
1
2
Real–time clock alarm flag
Interval timer alarm flag
Cycle counter alarm flag
DS2404
020998 7/25
When a given alarm occurs, the corresponding alarm
flag is set to a logic 1. The alarm flag(s) is cleared by
reading the status register.
RTE
ITE
CCE
3
4
5
Real–time interrupt enable
Interval timer interrupt enable
Cycle counter interrupt enable
Writing any of the interrupt enable bits to a logic 0 will al-
low an interrupt condition to be generated when its cor-
responding alarm flag is set (see “Interrupts” section).
Control Register
WPI WPROSC
AUTOSTOP
START MAN.
DSEL RO WPC
76 543210
WPR
WPI
WPC
0
1
2
Write protect real–time clock/alarm registers
Write protect interval timer/alarm registers
Write protect cycle counter/alarm registers
0201h
Setting a write protect bit to a logic 1 will permanently
write protect the corresponding counter and alarm reg-
isters, all write protect bits, and additional bits in the
control register . The write protect bits can not be written
in a normal manner (see “Write Protect/Programmable
Expiration” section).
3Read OnlyRO
If a programmable expiration occurs and the read only
bit is set to a logic 1, then the DS2404 becomes read
only. If a programmable expiration occurs and the read
only bit is a logic 0, then only the 64–bit lasered ROM
can be accessed (see “Write Protect/Programmable
Expiration” section).
4Oscillator EnableOSC
This bit controls the crystal oscillator. When set to a logic
1, the oscillator will start operation. When the oscillator
bit is a logic 0, the oscillator will stop.
AUTO/MAN5Automatic/Manual Mode
When this bit is set to a logic 1, the interval timer is in au-
tomatic mode. In this mode, the interval timer is enabled
by the I/O line. When this bit is set to a logic 0, the inter-
val timer is in manual mode. In this mode the interval tim-
er is enabled by the STOP/START bit.
STOP/START6Stop/Start (in Manual Mode)
If the interval timer is in manual mode, the interval timer
will start counting when this bit is set to a logic 0 and will
stop counting when set to a logic 1. If the interval timer is
in automatic mode, this bit has no effect.
DSEL7Delay Select Bit
This bit selects the delay that it takes for the cycle count-
er and the interval timer (in auto mode) to see a transi-
tion on the I/O line. When this bit is set to a logic 1, the
delay time is 123 + 2 ms. This delay allows communica-
tion on the I/O line without starting or stopping the inter-
val timer and without incrementing the cycle counter.
When this bit is set to a logic 0, the delay time is 3.5
±0.5 ms.
MEMORY FUNCTION COMMANDS
The “Memory Function Flow Chart” (Figure 6) describes
the protocols necessary for accessing the memory.
T wo examples follow the flowchart. Three address reg-
isters are provided as shown in Figure 5. The first two
registers represent a 16–bit target address (TA1, T A2).
The third register is the ending offset/data status byte
(E/S).
The target address points to a unique byte location in
memory . The first five bits of the target address (T4:T0)
represent the byte of fset within a page. This byte offset
points to one of 32 possible byte locations within a given
page. For instance, 00000b points to the first byte of a
page where as 11111b would point to the last byte of a
page.
The third register (E/S) is a read only register. The first
five bits (E4: E0) of this register are called the ending off-
set. The ending offset is a byte offset within a page. Bit 5
(PF) is the partial byte flag. Bit 6 (OF) is the overflow flag.
Bit 7 (AA) is the authorization accepted flag.
DS2404
020998 8/25
ADDRESS REGISTERS Figure 5
TARGET ADDRESS (TA1)
TARGET ADDRESS (TA2)
ENDING ADDRESS WITH
DATA STATUS (E/S)
(READ ONLY)
7543210
T7 T6 T5 T4 T3 T2 T1 T0
6
T15 T14 T13 T12 T11 T10 T9 T8
AA OF PF E4 E3 E2 E1 E0
Write Scratchpad Command [0Fh]
After issuing the write scratchpad command, the user
must first provide the 2–byte target address, followed by
the data to be written to the scratchpad. The data will be
written to the scratchpad starting at the byte offset
(T4:T0). The ending offset (E4: E0) will be the byte offset
at which the host stops writing data. The maximum end-
ing offset is 11111b (31d). If the host attempts to write
data past this maximum offset, the overflow flag (OF)
will be set and the remaining data will be ignored. If the
user writes an incomplete byte and an overflow has not
occurred, the partial byte flag (PF) will be set.
Read Scratchpad Command [AAh]
This command may be used to verify scratchpad data
and target address. After issuing the read scratchpad
command, the user may begin reading. The first two
bytes will be the target address. The next byte will be the
ending offset/data status byte (E/S) followed by the
scratchpad data beginning at the byte offset (T4: T0).
The user may read data until the end of the scratchpad
after which the data read will be all logic 1’s.
Copy Scratchpad [55h]
This command is used to copy data from the scratchpad
to memory. After issuing the copy scratchpad com-
mand, the user must provide a 3–byte authorization pat-
tern. This pattern must exactly match the data contained
in the three address registers (T A1, T A2, E/S, in that or-
der). If the pattern matches, the AA (Authorization Ac-
cepted) flag will be set and the copy will begin. At this
point, the part will go into a TX mode, transmitting a logic
1 to indicate the copy is in progress. A logic 0 will be
transmitted after the data has been copied. Any attempt
to reset the part will be ignored while the copy is in prog-
ress. Copy typically takes 30 µs.
The data to be copied is determined by the three ad-
dress registers. The scratchpad data from the begin-
ning offset through the ending offset, will be copied to
memory, starting at the target address. Anywhere from
1 to 32 bytes may be copied to memory with this com-
mand. Whole bytes are copied even if only partially writ-
ten. The AA flag will be cleared only by executing a write
scratchpad command.
Read Memory [F0h]
The read memory command may be used to read the
entire memory. After issuing the command, the user
must provide the 2–byte target address. After the two
bytes, the user reads data beginning from the target ad-
dress and may continue until the end of memory, at
which point logic 1’s will be read. It is important to realize
that the target address registers will contain the address
provided. The ending offset/data status byte is unaf-
fected.
The hardware of the DS2404 provides a means to
accomplish error–free writing to the memory section. T o
safeguard reading data in the 1–Wire environment and
to simultaneously speed up data transfers, it is recom-
mended to packetize data into data packets of the size
of one memory page each. Such a packet would typi-
cally store a 16–bit CRC with each page of data to insure
rapid, error–free data transfers that eliminate having to
read a page multiple times to determine if the received
data is correct or not. (See the Book of DS19xx iButton
Standards, Chapter 7 for the recommended file struc-
ture to be used with the 1–Wire environment.)
DS2404
020998 9/25
MEMORY FUNCTION FLOW CHART Figure 6
MASTER TX MEMORY
FUNCTION COMMAND
0Fh
WRITE
SCRATCHPAD
AAh
READ
SCRATCHPAD
55h
COPY
SCRATCHPAD
F0h
READ
MEMORY
NNN
MASTER TX
TA1 (T7:T0) MASTER RX
TA1 (T7:T0) MASTER TX
TA1 (T7:T0)
MASTER TX
TA2 (T15:T8) MASTER RX
TA2 (T15:T8) MASTER TX
TA2 (T15:T8)
MASTER TX
TA1 (T7:T0)
MASTER TX
TA2 (T15:T8)
DS2404 SETS SCRATCHPAD
OFFSET=(T4:T0) AND
CLEARS (PF, OF, AA)
MASTER RX ENDING
OFFSET/DATA
STATUS BYTE (E/S)
MASTER TX
E/S BYTE
AUTHORIZATION
CODE MATCH
?
AA=1
DS2404
TX “1”s
DS2404 COPIES
SCRATCHPAD
DATA TO MEMORY
DS2404
TX “0”s
MASTER TX
RESET
DS2404 SETS
SCRATCHPAD
OFFSET=(T4:T0)
MASTER RX DATA
BYTE FROM
SCRATCHPAD
OFFSET
MASTER TX
RESET
SCRATCHPAD
OFFSET
=11111b
MASTER
RX “1”s
INCREMENT
SCRATCHPAD
OFFSET
MASTER TX DATA BYTE
TO SCRATCHPAD OFFSET
DS2404 SETS
(E4:E0)=SCRATCHPAD
OFFSET
MASTER TX
RESET
SCRATCHPAD
OFFSET
=11111b
MASTER TX
DATA
INCREMENT
SCRATCHPAD
OFFSET
PARTIAL
BYTE
WRITTEN
OF=1
MASTER TX
RESET
PF=1
1–WIRE
PORT
SELECTED
?
DS2404 TX PRESENCE
PULSE (SEE FIGURE 9)
MASTER TX
RESET
DS2404 SETS
MEMORY
ADDRESS=(T15:T0)
MASTER RX DATA
BYTE FROM
MEMORY ADDRESS
MASTER TX
RESET
INCREMENT
MEMORY
ADDRESS
MEMORY
ADDRESS
=21Dh
MASTER
RX “1”s
YYYN
Y
Y
N
N
Y
Y
N
NY
N
Y
N
N
Y
Y
N
Y
N
Y
Y
N
Y
N
N
Y
NY
DS2404
020998 10/25
MEMORY FUNCTION EXAMPLES
Example 1: W rite one page of data to page 15
Read page 15 (3–wire port)
MASTER MODE DATA (LSB FIRST) COMMENTS
TX Reset Master pulses RST low
TX 0Fh Issue “write scratchpad” command
TX E0h TA1, beginning offset=0
TX 01h T A2, address=01E0h
TX <32 data bytes> Write 1 page of data to scratchpad
TX Reset Master pulses RST low
TX AAh Issue “read scratchpad” command
RX E0h Read TA1, beginning offset=0
RX 01h Read TA2, address=01E0h
RX 1Fh Read E/S, ending offset=31d, flags=0
RX <32 data bytes> Read scratchpad data and verify
TX Reset Master pulses RST low
TX 55h Issue “copy scratchpad” command
TX E0h TA1
TX 01h TA2
TX 1Fh E/S
RX <busy indicator> W ait until DQ=0 (~30 µs typical)
TX Reset Master pulses RST low
TX F0h Issue “read memory” command
TX E0h TA1, beginning offset=0
TX 01h T A2, address=01E0h
RX <32 data bytes> Read memory page 15 and verify
TX Reset Master pulses RST low, done
NOTE: The ROM function commands do not apply to the 3–wire port. After RST is at a high level, the device expects to
receive a memory function command.
AUTHORIZATION CODE
DS2404
020998 11/25
Example 2: Write two data bytes to memory locations 0026h and 0027h (the seventh and eighth byte of page 1).
Read entire memory (1–Wire port).
MASTER MODE DATA (LSB FIRST) COMMENTS
TX Reset reset pulse (480–960 µs)
RX Presence presence pulse
TX CCh Issue “skip ROM” command
TX 0Fh Issue “write scratchpad” command
TX 26h T A1, beginning of fset=6
TX 00h T A2, address=0026h
TX <2 data bytes> Write 2 bytes of data to scratchpad
TX Reset reset pulse
RX Presence presence pulse
TX CCh Issue “skip ROM” command
TX AAh Issue “read scratchpad” command
RX 26h Read TA1, beginning offset=6
RX 00h Read TA2, address=0026h
RX 07h Read E/S, ending offset=7, flags=0
RX <2 data bytes> Read scratchpad data and verify
TX Reset reset pulse
RX Presence presence pulse
TX CCh Issue “skip ROM” command
TX 55h Issue “copy scratchpad” command
TX 26h TA1
TX 00h TA2
TX 07h E/S
TX Reset reset pulse
RX Presence presence pulse
TX CCh Issue “skip ROM” command
TX F0h Issue “read memory” command
TX 00h T A1, beginning of fset=0
TX 00h T A2, address=0000h
RX <542 bytes> Read entire memory
TX Reset reset pulse
RX Presence presence pulse, done
AUTHORIZATION CODE
DS2404
020998 12/25
WRITE PROTECT/PROGRAMMABLE
EXPIRATION
The write protect bits (WPR, WPI, WPC) provide a
means of write protecting the timekeeping data and lim-
iting access to the DS2404 when an alarm occurs (pro-
grammable expiration).
The write protect bits may not be written by performing a
single copy scratchpad command. Instead, to write
these bits, the copy scratchpad command must be per-
formed three times. Please note that the AA bit will be
set, as expected, after the first copy command is suc-
cessfully executed. Therefore, the authorization pat-
tern for the second and third copy command should
have this bit set. The read scratchpad command may
be used to verify the authorization pattern.
The write protect bits, once set, permanently write pro-
tects their corresponding counter and alarm registers,
all write protect bits, and certain control register bits as
shown in Figure 7. The time/count registers will contin-
ue to count if the oscillator is enabled. If the user wishes
to set more than one write protect bit, the user must set
them at the same time. Once a write protect bit is set it
cannot be undone, and the remaining write protect bits,
if not set, cannot be set.
The programmable expiration takes place when one or
more write protect bits have been set and a correspond-
ing alarm occurs. If the RO (read only) bit is set, only the
read scratchpad and read memory function commands
are available. If the RO bit is a logic “0”, no memory
function commands are available. The ROM functions
are always available.
WRITE PROTECT CHART Figure 7
WRITE PROTECT BIT SET: WPR WPI WPC
Data Protected from Real Time Clock Interval T imer Cycle Counter
User Modification: Real T ime Alarm Interval T ime Alarm Cycle Counter Alarm
WPR WPR WPR
WPI WPI WPI
WPC WPC WPC
RO RO RO
OSC*OSC*OSC*
STOP/START** DSEL
AUTO/MAN
* Becomes write “1” only, i.e., once written to a logic “1”, may not be written back to a logic “0”.
** Forced to a logic “0”.
1–WIRE BUS SYSTEM
The 1–Wire bus is a system which has a single bus mas-
ter and one or more slaves. In most instances the
DS2404 behaves as a slave. The exception is when the
DS2404 generates an interrupt due to a timekeeping
alarm. The discussion of this bus system is broken down
into three topics: hardware configuration, transaction
sequence, and 1–Wire signalling (signal types and
timing).
HARDWARE CONFIGURATION
The 1–Wire bus has only a single line by definition; it is
important that each device on the bus be able to drive it
at the appropriate time. To facilitate this, each device
attached to the 1–Wire bus must have open drain or
3–state outputs. The 1–Wire port of the DS2404 (I/O pin
5) is open drain with an internal circuit equivalent to that
shown in Figure 8. A multidrop bus consists of a 1–Wire
bus with multiple slaves attached. The 1–Wire bus has a
maximum data rate of 16.3k bits per second and
requires a pull–up resistor of approximately 5kΩ.
The idle state for the 1–Wire bus is high. If for any reason
a transaction needs to be suspended, the bus MUST be
left in the idle state if the transaction is to resume. If this
does not occur and the bus is left low for more than
120 µs, one or more of the devices on the bus may be
reset.
DS2404
020998 13/25
HARDWARE CONFIGURATION Figure 8
DS2404 1–WIRE PORT
RX
TX
100 OHM
MOSFET
5k
TYP. RX
TX
RX = RECEIVE
TX = TRANSMIT
5 µA
Typ.
BUS MASTER
PIN–5
I/O
VPUP
OPEN DRAIN
PORT PIN
TRANSACTION SEQUENCE
The protocol for accessing the DS2404 via the 1–Wire
port is as follows:
Initialization
ROM Function Command
Memory Function Command
Transaction/Data
INITIALIZATION
All transactions on the 1–Wire bus begin with an initial-
ization sequence. The initialization sequence consists
of a reset pulse transmitted by the bus master followed
by presence pulse(s) transmitted by the slave(s).
The presence pulse lets the bus master know that the
DS2404 is on the bus and is ready to operate. For more
details, see the “1–Wire Signaling” section.
ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can is-
sue one of the five ROM function commands. All ROM
function commands are eight bits long. A list of these
commands follows (refer to flowchart in Figure 9):
Read ROM [33h]
This command allows the bus master to read the
DS2404’s 8–bit family code, unique 48–bit serial num-
ber , and 8–bit CRC. This command can only be used if
there is a single DS2404 on the bus. If more than one
slave is present on the bus, a data collision will occur
when all slaves try to transmit at the same time (open
drain will produce a wired–AND result). The resultant
family code and 48–bit serial number will usually result
in a mismatch of the CRC.
Match ROM [55h]
The match ROM command, followed by a 64–bit ROM
sequence, allows the bus master to address a specific
DS2404 on a multidrop bus. Only the DS2404 that ex-
actly matches the 64–bit ROM sequence will respond to
the following memory function command. All slaves that
do not match the 64–bit ROM sequence will wait for a
reset pulse. This command can be used with a single or
multiple devices on the bus.
Skip ROM [CCh]
This command can save time in a single drop bus sys-
tem by allowing the bus master to access the memory
functions without providing the 64–bit ROM code. If
more than one slave is present on the bus and a read
command is issued following the Skip ROM command,
data collision will occur on the bus as multiple slaves
transmit simultaneously (open drain pull–downs will
produce a wired–AND result).
Search ROM [F0h]
When a system is initially brought up, the bus master
might not know the number of devices on the 1–Wire
bus or their 64–bit ROM codes. The search ROM com-
mand allows the bus master to use a process of elimina-
tion to identify the 64–bit ROM codes of all slave devices
on the bus. The search ROM process is the repetition of
a simple 3–step routine: read a bit, read the complement
of the bit, then write the desired value of that bit. The bus
master performs this simple, 3–step routine on each bit
of the ROM. After one complete pass, the bus master
knows the contents of the ROM in one device. The
remaining number of devices and their ROM codes may
be identified by additional passes. See Chapter 5 of the
Book of DS19xx iButton Standards for a comprehensive
discussion of a search ROM, including an actual
example.
Search Interrupt [ECh]
This ROM command works exactly as the normal ROM
Search, but it will identify only devices with interrupts
that have not yet been acknowledged.
DS2404
020998 14/25
ROM FUNCTIONS FLOW CHART (1–WIRE PORT ONLY) Figure 9
N
Y
Y
Y
DS2404 TX
PRESENCE PULSE
33h
READ ROM
COMMAND
?
55h
MATCH ROM
COMMAND
?
F0h
SEARCH ROM
COMMAND
?
CCh
SKIP ROM
COMMAND
?
DS2404 TX FAMILY
CODE
1 BYTE
BIT 0
MATCH? BIT 0
MATCH?
BIT 1
MATCH
?
BIT 1
MATCH
?
BIT 63
MATCH
?
BIT 63
MATCH
?
DS2404 TX
SERIAL NUMBER
6 BYTES
DS2404 TX
CRC BYTE
NNN
YYY
NN
Y
NN
Y
YY
DS2404 TX BIT 0
DS2404 TX BIT 0
DS2404 TX BIT 1
DS2404 TX BIT 1
DS2404 TX BIT 63
DS2404 TX BIT 63
MASTER TX BIT 1
MASTER TX BIT 0
MASTER TX BIT 0
MASTER TX BIT 1
MASTER TX BIT 63
MASTER TX BIT 63
MASTER TX
RESET PULSE
MASTER TX ROM
FUNCTION COMMAND
MASTER TX MEMORY
FUNCTION COMMAND
(SEE FIGURE 6)
NN
Y
Y
ECH
SEARCH INT.
COMMAND
?
BIT 0
MATCH?
BIT 1
MATCH
?
BIT 63
MATCH
?
N
Y
N
Y
DS2404 TX BIT 0
DS2404 TX BIT 0
DS2404 TX BIT 1
DS2404 TX BIT 1
DS2404 TX BIT 63
DS2404 TX BIT 63
MASTER TX BIT 0
MASTER TX BIT 1
MASTER TX BIT 63
N
Y
INTERRUPT
?
N
N
DS2404
020998 15/25
1–WIRE SIGNALING
The DS2404 requires strict protocols to insure data in-
tegrity. The protocol consists of five types of signaling on
one line: Reset Sequence with reset pulse and pres-
ence pulse, write 0, write 1, Read Data and interrupt
pulse. All these signals except presence pulse and
interrupt pulse are initiated by the bus master.
The initialization sequence required to begin any com-
munication with the DS2404 is shown in Figure 10. A re-
set pulse followed by a presence pulse indicates the
DS2404 is ready to send or receive data given the cor-
rect ROM command and memory function command.
The bus master transmits (TX) a reset pulse (tRSTL,
minimum of 480 µs). The bus master then releases the
line and goes into receive mode (RX). The 1–Wire bus is
pulled to a high state via the pull–up resistor. After de-
tecting the rising edge on the date line, the DS2404
waits (tPDH, 15–60 µs) and then transmits the presence
pulse (tPDL, 60 - 240 µs). There are special conditions if
interrupts are enabled where the bus master must
check the state of the 1–Wire bus after being in the RX
mode for 480 µs. These conditions will be discussed in
the “Interrupt” section.
READ/WRITE TIME SLOTS
The definitions of write and read time slots are illustrated
in Figure 11. All time slots are initiated by the master
driving the data line low . The falling edge of the data line
synchronizes the DS2404 to the master by triggering a
delay circuit in the DS2404. During write time slots, the
delay circuit determines when the DS2404 will sample
the data line. For a read data time slot, if a “0” is to be
transmitted, the delay circuit determines how long the
DS2404 will hold the data line low overriding the 1 gen-
erated by the master. If the data bit is a “1”, the device
will leave the read data time slot unchanged.
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 10
tRSTH
tRSTL tR
VPULLUP
VPULLUP MIN
VIH MIN
VIL MAX
0V
480 µs < tRSTL <  *
480 µs < tRSTH < (includes recovery time)
15 µs < tPDH < 60 µs
60 µs < tPDL < 240 µs
tPDH
tPDL
MASTER RX “PRESENCE PULSE”MASTER TX “RESET PULSE”
RESISTOR
MASTER
DS2404
*In order not to mask interrupt signaling by other devices on the 1–Wire bus, tRSTL + tR should always be less than 960 µs.
DS2404
020998 16/25
READ/WRITE TIMING DIAGRAM Figure 11
Write–one Time Slot
60 µs
tREC
tLOW1
VPULLUP
VPULLUP MIN
VIH MIN
VIL MAX
0V
60 µs < tSLOT < 120 µs
1 µs < tLOW1 < 15 µs
1 µs < tREC <
15 µs
DS2404
SAMPLING WINDOW
tSLOT
Write–zero Time Slot
VPULLUP
VPULLUP MIN
VIH MIN
VIL MAX
0V
tSLOT
tREC
tLOW0
60 µs < tLOW0 < tSLOT < 120 µs
1 µs < tREC <
DS2404
SAMPLING WINDOW
60 µs
15 µs
Read–data Time Slot
VPULLUP
VPULLUP MIN
VIH MIN
VIL MAX
0V
tSLOT tREC
tRDV
tLOWR
60 µs < tSLOT < 120 µs
1 µs < tLOWR < 15 µs
0 < tRELEASE < 45 µs
1 µs < tREC <
tRDV = 15 µs
tSU < 1 µs
tRELEASE
MASTER SAMPLING
WINDOW
RESISTOR
MASTER
DS2404
tSU
DS2404
020998 17/25
Interrupts
If the DS2404 detects an alarm condition, it will automat-
ically set the corresponding alarm flag (CCF, ITF or
RTF) in the Status Register. If the flag’s corresponding
interrupt bit (CCE, ITE or RTE) is enabled (logic 0) an
interrupt condition begins as the alarm goes off. The
DS2404 signals the interrupt condition by pulling the
open drain IRQ output low. The interrupt condition
ceases when the alarm flags are cleared (i.e., the inter-
rupt is acknowledged by reading the Status Register,
address 200H) or if the corresponding interrupt enable
bit is disabled (set to logic 1).
Interrupts can also be generated on the 1–Wire port.
Since communication and interrupt signaling share the
same pin, one has to distinguish between two types of
interrupts: spontaneous interrupts, called type 1, and
delayed interrupts, type 2. Spontaneous interrupts that
have not yet occurred need to be (re–)armed by a reset
pulse after all communication on the 1–Wire bus has fin-
ished. A single falling slope on the 1–Wire bus will dis-
arm this type of interrupt. If an alarm condition occurs
while the device is disarmed, at first a type 2 interrupt will
be produced.
Spontaneous interrupts are signaled by the DS2404 by
pulling the data line low for 960 to 3840 µs as the inter-
rupt condition begins (Figure 12). After this long low
pulse a presence pulse will follow . If the alarm condition
occurs just after the master has sent a reset pulse, i.e.,
during the high or low time of the presence pulse, the
DS2404 will not assert its Interrupt Pulse until the pres-
ence pulse is finished (Figure 13).
If the DS2404 cannot assert a spontaneous interrupt,
either because the data line was not pulled high, com-
munication was in progress, or the interrupt was not
armed, it will extend the next reset pulse to a total length
of 960 to 3840 µs (delayed interrupt). If the alarm condi-
tion occurs during the reset low time of the reset pulse,
the DS2404 will immediately assert its interrupt pulse;
thus the total low time of the pulse can be extended up to
4800 µs (Figure 14). If a DS2404 with a not previously
signaled alarm detects a power–on cycle on the 1–Wire
bus, it will send a presence pulse and wait for the reset
pulse sent by the master to extend it and to subse-
quently issue a presence pulse (Figure 15). As long as
an interrupt has not been acknowledged by the master ,
the DS2404 will continue sending interrupt pulses.
The interrupt signaling discussed so far is valid for the
first opportunity the device has to signal an interrupt. It is
not required for the master to acknowledge an interrupt
immediately. If an interrupt is not acknowledged, the
DS2404 will continue signaling the interrupt with every
reset pulse. To do so, DS2404 devices of Revision B4
(earlier production parts) will always use the waveform
of the T ype 2 Interrupt (Figure 14). Devices of Revision
B5 (current production) will either use the waveform of
the Type 2 Interrupt (Figure 14) or the waveform of the
Type 1A Interrupt (Figure 13). The waveform of the Type
2 Interrupt will be observed after a communication to a
device other than the interrupting one; after successful
communication to the interrupting device (without
acknowledging the interrupt) the waveform of the Type
1A Interrupt will be found. The revision code of the
DS2404 is appended to the manufacturing date code
which is printed on the top of the package right below the
part number.
TYPE 1 INTERRUPT Figure 12
RESET PULSE INTERRUPT PULSE
960 – 3840 µsPRESENCE
PULSE
Note: No communication following
presence pulse., i.e., no falling edge. Interrupt condition occurs here.
VPUP
1–WIRE
BUS
GND
PRESENCE
PULSE
LINE TYPE LEGEND: See next page.
DS2404
020998 18/25
TYPE 1A INTERRUPT (SPECIAL CASE) Figure 13
INTERRUPT PULSE
960 – 3840 µsPRESENCE
PULSE
RESET PULSE
Interrupt condition occurs during the presence pulse, but the interrupt is not generated until the
presence pulse is completed.
VPUP
GND
1–WIRE
BUS VIH OF DS1994
PRESENCE
PULSE
TYPE 2 INTERRUPT Figure 14
INTERRUPT PULSE
960 – 4800 µsPRESENCE
PULSE
Interrupt condition exists prior to master
releasing reset or occurs during low time
of reset pulse.
1–WIRE
BUS
VPUP
GND
TYPE 2 INTERRUPT (SPECIAL CASE) Figure 15
PRESENCE
PULSE
Interrupt condition occurs while the
bus is powered down.
1–Wire
BUS
V
GND
INTERRUPT PULSE
960 - 3840 µs
PRESENCE
PULSE
Bus powers up.
PUP
LINE TYPE LEGEND:
Bus master active low
Both bus master and
DS2404 active low
DS2404 active low
Resistor pull–up
DS2404
020998 19/25
3–WIRE I/O COMMUNICATIONS
The 3–wire bus is comprised of three signals. These are
the RST (reset) signal, the CLK (clock) signal, and the
DQ (data) signal. All data transfers are initiated by driv-
ing the RST input high. Driving the RST input low termi-
nates communication. (See Figures 19 and 20.)
A clock cycle is a sequence of a falling edge followed by
a rising edge. For data inputs, the data must be valid
during the rising edge of a clock cycle. Command bits
and data bits are input on the rising edge of the clock and
data bits are output on the falling edge of the clock.
When reading data from the DS2404, the DQ pin goes
to a high impedance state while the clock is high. T aking
RST low will terminate any communication and cause
the DQ pin to go to a high impedance state.
POWER CONTROL
There are two methods of supplying power to the
DS2404, VCC Operate mode with battery backup and
Battery Operate mode. If the DS2404 is used in an
application where battery backup is not desired, the part
must be wired for Battery Operate mode.
VCC Operate Mode (Battery Backed)
Figure 16 shows the necessary connections for operat-
ing the DS2404 in VCC Operate mode.
VCC OPERATE MODE Figure 16
GND
GND
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
VCC
VBATO
VBATB +3V TYPICAL
+5V TYPICAL+5V
UNCONNECTED
VCC CONNECT PIN 13
TO GUARD RING
(SEE FIGURE 18)
VCC Pin 1 & 16 2.8 to 5.5 volts
VBATB Pin 9 2.8 to 5.5 volts
VBATO Pin 10 must be unconnected
To always allow communication through the 1–Wire or
3–wire port, the voltage on VCC must be approximately
0.2V above the voltage on VBATB. Otherwise the
DS2404 will retain data, but will not allow any access.
The VBATB pin is normally connected to any standard 3V
lithium cell or other energy source. As VCC falls below
VBATB, the power switching circuit allows VBATB to pro-
vide energy for maintaining clock functionality and data
retention. No communication can take place while
VBATB is greater than VCC. During power–up, when VCC
reaches a value of approximately 0.2V above VBATB, the
power switching circuit connects VCC and disconnects
VBATB. If the oscillator is on, no communication can take
place until VCC has stayed approximately 0.2V above
VBATB for 123 ± 2 ms. During power–down, the falling
VCC must pass the range from VBATB to 0V in no less
than 100 ns for the power switching circuit to function
properly.
Battery Operate Mode
Figure 17 shows the necessary connections for operat-
ing the DS2404 in Battery Operate mode.
BATTERY OPERATE MODE Figure 17
GND
GND
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
VCC VCC
VBATO + 2.8 TO 5.5V
VBATB
CONNECT PIN 13
TO GUARD RING
(SEE FIGURE 18)
VCC Pin 1 & 16 Ground
VBATB Pin 9 Ground
VBATO Pin 10 2.8 to 5.5 volts
The VBATO pin is normally connected to any standard 3 V
lithium cell or other energy source. The Battery Operate
mode also minimizes the power–consumption in
applications where battery backup is not required and
the VBATO lead is directly connected to the system’s 5V
supply.
Note: In Battery Operate mode, the voltage on DQ must
never exceed the voltage on VBATO if the 3–wire inter-
face is used. This restriction does not apply to the
1–Wire interface.
DS2404
020998 20/25
DEVICE OPERATION MODES
With its two ports and two power modes the DS2404 can
be operated in several ways. While the maximum volt-
age on the 1–Wire port (I/O) is always 6V , the maximum
voltage on the 3–wire port (DQ) depends on the power
mode and actual operating voltage. A particular port is
selected by setting the control lines to a state that makes
the other port inactive. See Table 1 for details.
When using the 3–wire port only and the DS2404 is
wired for VCC Operate Mode (Battery Backed) the
1–Wire I/O pin can be used as counter input. This mode
requires that the I/O lead is connected to VCC through a
5k (typical) resistor. T o enable communication through
the 3–wire port a reset/presence sequence has to be
performed on the 1–Wire port after the system has pow-
ered up.
OPERATION MODES AND CONDITIONS (Table 1)
PORT USAGE BATTERY OPERATE MODE VCC OPERATE MODE (BATTERY BACKED)
1–Wire only Float RST, DQ, CLK or tie to GND
3–wire only DQ Voltage (3–wire) VBATO DQ Voltage (3–wire) VCC +0.3V
If unused: float I/O (1–Wire) or tie to GND; if used as counter input: see text
1–Wire and 3–wire
Dual Port Operation
DQ Voltage (3–wire) VBATO DQ Voltage (3–wire) VCC +0.3V
Dual Port Operation 1–Wire Port: finish each communication with a reset/presence sequence: when
idle: either keep I/O pulled high through a resistor or pull it low;
3–wire Port: when idle: keep RST and CLK low, keep DQ high or low or floating
DUAL PORT OPERATION
The on–chip arbitration logic works on a first–come, first
serve principle. Assuming that at one time both ports are
idle, the one port that becomes active prior to the other
one is granted access. Activity on the 3–wire port begins
as the voltage level on the RST input changes from low
to high. The 1–Wire port is considered active with the
first falling edge detected after the presence pulse.
Attempting to communicate with the device through the
port that temporarily has no access does not affect com-
munication through the other port. If communication on
the 1–Wire port is initiated while the 3–wire port is
active, the device will still respond to the reset pulse, but
any subsequently transmitted 1–Wire command will be
ignored. When reading the ROM or memory, for exam-
ple, the response will always be 1’s, indicating that
access was denied. While the 1–Wire port is active, the
3–wire data line DQ is in tristate mode. The always pres-
ent resistor of approximately 60 k pulls DQ low. The
micro connected to the 3–wire port will fight against this
weak pull–down and, depending on its port characteris-
tics, possibly dominate the logical value on DQ.
Since writing to the memory of the DS2404 requires
multiple steps with short periods where both ports are
inactive, additional measures are required. T o avoid one
port overwriting actions initiated by the other port one
should do the following:
Allow the microcontroller operating the 3–wire port to
monitor the activity on the 1–Wire port. This could be
done by means of a retriggerable one–shot, for exam-
ple. The microcontroller should wait for a break of sev-
eral milliseconds on the 1–Wire port before attempting
communication through the 3–wire port.
In addition, data should be organized as data packets
with a length byte at the beginning and a CRC check at
the end. Whenever one side has finished communica-
tion with the DS2404 it should write a token such as a
“null–packet” into the scratchpad. A null–packet con-
sists of three bytes that represent a zero length followed
by a valid 16–bit CRC. As one port tries to communicate
with the device, the first memory function command
should be a Read Scratchpad. Communication should
only proceed if the null–packet is found. Otherwise com-
munication through the other port is not yet finished and
one is likely to interfere if one does not immediately
release the port for the communication on the other port
to resume. For details on recommended data structures
please refer to chapters 7 or 10 of the “Book of DS19xx
iButton Standards”.
DS2404
020998 21/25
CRYSTAL PLACEMENT ON PCB Figure 18
LOCAL GROUND
PLANE BENEATH
SIGNAL PLANE
OR ON OTHER
SIDE OF PCB
GUARD RING
ON SIGNAL
PLANE
CRYSTAL
PADS
X1
X2
GND
3–WIRE WRITE DATA TIMING DIAGRAM Figure 19
t
t
t
t
t
t
ttt
CWH
CCH
F
R
CL
CC
DC CDH CH
WW
W
CLK
DQ
RST
WW
3–WIRE READ DATA TIMING DIAGRAM Figure 20
t
t
CWH
CC
t
tt
DC
CDD CDZ
W
CLK
RST
DQ
tCDH
W READ READ
tCDZ
W
TRI–
STATE DS2404
DRIVES DQ TRI–
STATE DS2404
DRIVES DQ T.
S.
DS2404
020998 22/25
ABSOLUTE MAXIMUM RATINGS*
Voltage on DATA to Ground –0.5V to +7.0V
Operating Temperature –40°C to +85°C
Storage Temperature –55°C to +125°C
Soldering Temperature 260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED OPERATING CONDITIONS (–40°C to +85°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Logic 1 VIH3 2.2 VCC +0.3 V 1
Logic 0 VIL3 –0.3 +0.8 V 1
RST Logic 1 2.8 5.5 V 1
Supply VCC 2.8 5.5 V 1
Battery VBATB,
VBATO 2.8 3.0 5.5 V 1, 6
DC ELECTRICAL CHARACTERISTICS (1–WIRE PORT) (–40°C to +85°C; VCC = 5V+ 10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Logic 1 VIH1 2.2 6.0 V 1, 9
Logic 0 VIL1 –0.3 +0.8 V 1, 16
Output Logic Low @ 4 mA VOL 0.4 V 1
Output Logic High VOH VPUP V 1, 12
Input Load Current IL5µA 13
DC ELECTRICAL CHARACTERISTICS (VCC OP. MODE) (–40°C to +85°C; VCC = 5V+ 10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Output Leakage ILO 1µA17
Output Current @ 2.4V on DQ IOH 3mA 18
Output Current @ 0.4V on DQ IOL –3 mA 19
Active Current ICC1 2mA 5
Standby Current ICC2 500 µA11
DS2404
020998 23/25
DC ELECTRICAL CHARACTERISTICS (BATT. OP. MODE) (–40°C to +85°C; VBATO = 3.0V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Output Leakage ILO 1µA17
Output Current @ 2.4V on DQ IOH 1mA 18
Output Current @ 0.4V on DQ IOL –1 mA 19
I/O Operate Charge QBATO 200 nC 10
Battery Current (OSC On) IBAT1 350 nA 7
Battery Current (OSC Off) IBAT2 200 nA 7, 21
CAPACITANCE (tA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance CIN 10 pF
Output Capacitance COUT 15 pF
I/O (1–Wire) CIN/OUT 100 800 pF 8
RESISTANCES (–40°C to +85°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
RST Resistance to Ground ZRST 65 k
DQ Resistance to Ground ZDQ 65 k
CLK Resistance to Ground ZCLK 65 k
AC ELECTRICAL CHARACTERISTICS: 3–WIRE PORT (–40°C to +85°C; VCC = 5V+ 10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Data to CLK Setup tDC 35 ns 2
CLK to Data Hold tCDH 40 ns 2
CLK to Data Delay tCDD 100 ns 2, 3, 4
CLK Low T ime t CL 250 ns 2
CLK High T ime tCH 250 ns 2
CLK Frequency tCLK DC 2.0 MHz 2
CLK Rise and Fall tR,tF500 ns 2
RST to CLK Setup tCC 1µs 2
CLK to RST Hold tCCH 40 ns 2
RST Inactive T ime tCWH 250 ns 2
CLK or RST to DQ High Z tCDZ 50 ns 2
DS2404
020998 24/25
AC ELECTRICAL CHARACTERISTICS: 1–WIRE PORT (–40°C to +85°C; VCC=2.8 to 5.5V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
T ime Slot tSLOT 60 120 µs
Write 1 Low Time tLOW1 115 µs
Write 0 Low Time tLOW0 60 120 µs
Read Low T ime tLOWR 115 µs
Read Data Valid tRDV exactly 15 µs
Release T ime tRELEASE 015 45 µs
Read Data Setup tSU 1µs15
Recovery Time tREC 1µs
Interrupt tINT 960 4800 µs
Reset T ime High tRSTH 480 µs 14
Reset T ime Low tRSTL 480 960 µs 20
Presence Detect High tPDH 15 60 µs
Presence Detect Low tPDL 60 240 µs
NOTES:
1. All voltages are referenced to ground.
2. VIH = 2.0V or VIL = 0.8V with 10 ns maximum rise and fall time.
3. VDQH = 2.4V and VDQL = 0.4V, respectively.
4. Load capacitance = 50 pF.
5. Measured with outputs open.
6. When battery is applied to VBATO input, VCC and VBATB must be 0V.
7. VBATB, or VBATO = 3.0V; all inputs inactive state.
8. Capacitance on the I/O pin could be 800 pF when power is first applied. If a 5k resistor is used to pull–up the
I/O line to VPUP, 5 µs after power has been applied, the parasite capacitance will not affect normal communica-
tions.
9. For auto–mode operation of the interval timer, the high level on the I/O pin must be greater than or equal to 70%
of VCC or VBATO.
10.Read and write scratchpad (all 32 bytes) at 3.0V.
11. All other inputs at CMOS levels.
12.VPUP = external pull–up voltage.
13.Input load is to ground.
14.An additional reset or communication sequence cannot begin until the reset high time has expired.
DS2404
020998 25/25
15.Read data setup time refers to the time the host must pull the I/O line low to read a bit. Data is guaranteed to be
valid within 1 µs of this falling edge.
16.Under certain low voltage conditions VIL1MAX may have to be reduced to as much as 0.5V to always guarantee
a presence pulse.
17.Applies to 1Hz and IRQ pins only.
18.Applies to DQ pin only.
19.Applies to DQ, 1Hz and IRQ pins only.
20.The reset low time (tRSTL) should be restricted to a maximum of 960 µs, to allow interrupt signaling, otherwise,
it could mask or conceal interrupt pulses.
21.When the battery is attached, the oscillator powers up in the off state.