IRDC3822A Rev 0.0 02/22/2008 1 IRDC3822A SupIRBuck TM USER GUIDE FOR IR3822A EVALUATION BOARD DESCRIPTION The IR3822A is a synchronous buck converter, providing a compact, high performance and flexible solution in a small 5mmx6mm Power QFN package. An output over-current protection function is implemented by sensing the voltage developed across the on-resistance of the synchronous rectifier MOSFET for optimum cost and performance. Key features offered by the IR3822A include programmable soft-start ramp, precision 0.6V reference voltage, programmable Power Good, thermal protection, fixed 300kHz switching frequency requiring no external component, input under-voltage lockout for proper start-up, and pre-bias start-up. This user guide contains the schematic and bill of materials for the IR3822A evaluation board. The guide describes operation and use of the evaluation board itself. Detailed application information for IR3822A is available in the IR3822A data sheet. BOARD FEATURES * Vin = +12V (13.2V Max) * Vout = +1.8V @ 0- 6A * L= 2.2uH * Cin= 3x10uF (ceramic 1206) + 330uF (electrolytic) * Cout= 6x22uF (ceramic 0805) Rev 0.0 02/22/2008 2 IRDC3822A CONNECTIONS and OPERATING INSTRUCTIONS A well regulated +12V input supply should be connected to VIN+ and VIN-. A maximum 6A load should be connected to VOUT+ and VOUT-. The connection diagram is shown in Fig. 1 and inputs and outputs of the board are listed in Table I. IR3822A has two input supplies, one for biasing (Vcc) and the other as input voltage (Vin). These inputs are connected on the board with a zero ohm resistor (R15). Separate supplies can be applied to these inputs. Vcc input cannot be connected unless R15 is removed. Vcc input should be a well regulated 5V-12V supply and it would be connected to Vcc+ and Vcc-. Table I. Connections Connection Signal Name VIN+ Vin (+12V) VIN- Ground of Vin Vcc+ Optional Vcc input Vcc- Ground for Optional Vcc input VOUT- Ground of Vout VOUT+ Vout (+1.8V) P_Good Power Good Signal LAYOUT The PCB is a 4-layer board. All of layers are 2 Oz. copper. The IR3822A SupIRBuck and all of the passive components are mounted on the top side of the board. Power supply decoupling capacitors, the charge-pump capacitor and feedback components are located close to IR3822A. The feedback resistors are connected to the output voltage at the point of regulation and are located close to the SupIRBuck. To improve efficiency, the circuit board is designed to minimize the length of the on-board power ground current path. Rev 0.0 02/22/2008 3 IRDC3822A Connection Diagram Vin = +12v GROUND GROUND VCC+ GROUND VOUT = +1.8v PGood Fig. 1: Connection diagram of IR3822A evaluation board Rev 0.0 02/22/2008 4 IRDC3822A Fig. 2: Board layout, top overlay Fig. 3: Board layout, bottom overlay (rear view) Rev 0.0 02/22/2008 5 IRDC3822A Fig. 4: Board layout, mid-layer I. AGND Plain PGND Plain Single point connection between AGND and PGND. Fig. 5: Board layout, mid-layer II. Rev 0.0 02/22/2008 6 PGood 1 R17 10K VCC R10 N/S R9 0 J1 SS C10 0.22uF C23 N/S 1000pF 34.8k Agnd C26 C11 22pF R1 3.09k R16 1 D1 BAT54S 1 U1 C13 1uF VCC OCset SS AGnd2 AGnd1 COMP FB Vsns IR3822A R3 40.2K C8 A PGND 10 11 180pF 80.6k R2 2.61K R4 PGnd SW 12 C24 1000pF Vin R18 N/S D2 N/S 20 R6 VCC C9 N/S R12 12.4K B 0 R15 C12 0.1uF 2.2uH L1 C21 N/S C6 N/S + C15 22uF C5 N/S C17 22uF + C22 N/S C16 22uF C4 10uF C18 22uF C3 10uF C20 22uF C7 0.1uF C19 22uF C2 10uF + 1 1 1 1 C14 0.1uF 1 1 1 1 C1 330uF Vout Vin Vout- Vout- Vout+ Vout+ Vin- Vin- Vin+ Vin+ Ground and Signal ( "analog" ) Ground Single point of connection between Power Fig. 6: Schematic of the IR3822A evaluation board 7 6 5 4 3 2 1 1 1 C25 0.1uF 3 13 Hg 2 14 Vc Vcc 8 PGood 9 1 2 AGnd3 15 R14 10k 1 1 Vcc+ 1 Rev 0.0 02/22/2008 Vcc- IRDC3822A 7 IRDC3822A Bill of Materials Item Quantity Designator Value Description 1 1 2 3 3 4 Size Manufacturer Mfr. Part Number C1 330uF 10uF SMD Electrolytic, 25V, 20% SMD Ceramic, 16V, X7R, 10% 1206 Panasonic Panasonic EEV-FK1E331P ECJ-3YX1C106K 0.1uF Ceramic, 50V, X7R, 10% 0603 Panasonic ECJ-1VB1H104K 4 1 C2 C3 C4 C7 C12 C14 C25 C10 0.22uF Ceramic, 10V, X5R, 10% 0603 Panasonic ECJ-1VB1A224K 5 1 C8 180pF Ceramic, 50V, NPO, 5% 0603 Murata GRM1885C1H181JA01 6 1 C11 22pF Ceramic, 50V, NPO, 5% 0603 Murata GRM1885C1H220JA01 7 1 Ceramic, 16V, X5R, 10% 0603 Panasonic ECJ-1VB1C105K 8 6 Ceramic, 6.3V, X5R, 20% 0805 Panasonic ECJ-2FB0J226M 9 2 C13 1uF C15 C16 C17 22uF C18 C19 C20 C24, C26 1000pF Ceramic, 50V, NPO, 5% 0603 Murata GRM1885C1H102JA01 10 1 D1 BAT54S Diode Schottky ,40V, 200mA SOT-23 Fairchild 11 1 L1 2.2uH 12 1 R1 13 1 14 1 15 16 BAT54S 34.8K SMT Inductor, 4.2mOhm, 20% Thick film, 1/10W, 1% 11.8x ACT 10.5mm 0603 Vishey/Dale R3 40.2K Thick film, 1/10W, 1% 0603 Vishey/Dale CRCW060340K2FKEA R2 80.6K Thick film, 1/10W, 1% 0603 Vishey/Dale CRCW060380K6FKEA 1 R4 2.61K Thick film, 1/10W, 1% 0603 Vishey/Dale 1 R6 20 Thick film, 1/10W, 1% 0603 Vishey/Dale CRCW06032K61FKEA CRCW060320R0FKEA STS1205-2R2 CRCW060334K8FKEA 17 2 R9 R15 0 Thick film, 1/10W, 1% 0603 Vishey/Dale CRCW06030000Z0EA 18 1 R12 12.4K Thick film, 1/10W, 1% 0603 Vishey/Dale CRCW060312K4FKEA 19 2 R14, R17 10K Thick film, 1/10W, 1% 0603 Vishey/Dale CRCW060310K0FKEA 20 1 R16 3.09K 0603 1 U1 IR3822A 22 2 - - 23 1 - - 24 1 - - Vishey/Dale International 5x6mm Rectifier Johnson Components Johnson Components Johnson Components CRCW06033K09FKEA 21 Thick film, 1/10W, 1% 300kHz, 6A, SupIRBuck Module Banana Jack, Insulated Solder Terminal, Black Banana Jack- Insulated Solder Terminal, Red Banana Jack- Insulated Solder Terminal, Green Rev 0.0 02/22/2008 IR3822A 105-0853-001 105-0852-001 105-0854-001 8 IRDC3822A TYPICAL OPERATING WAVEFORMS Vin=Vcc=12.0V, Vo=1.8V, Io=0- 6A, Room Temperature, No Air Flow Fig. 7: Start up at 6A Load Ch1:Vin, Ch2:VSS, Ch3:Vout, Ch4:Iout Fig. 8: Start up at 6A Load, Ch1:Vin, Ch2:VSS, Ch3:Vout, Ch4:VPGood Fig. 9: Start up with 0.5V Pre Bias, 0A Load, Ch1:Vin, Ch2:VSS, Ch3:Vout Fig. 10: Output Voltage Ripple, 6A load Ch1: Vout ,Ch4: Iout Fig. 11: Inductor node at 6A load Ch1:LX, Ch4:Iout Fig. 12: Short (Hiccup) Recovery Ch1:VSS , Ch2:Vout Rev 0.0 02/22/2008 9 IRDC3822A TYPICAL OPERATING WAVEFORMS Vin=Vcc=12V, Vo=1.8V, Io=3A- 6A, Room Temperature, No Air Flow Fig. 13: Transient Response, 3A to 6A step Ch1:Vout, Ch4:Iout Rev 0.0 02/22/2008 10 IRDC3822A TYPICAL OPERATING WAVEFORMS Vin=Vcc=12V, Vo=1.8V, Io=6A, Room Temperature, No Air Flow Fig. 14: Bode Plot at 6A load shows a bandwidth of 52.7kHz and phase margin of 52 degrees Rev 0.0 02/22/2008 11 IRDC3822A TYPICAL OPERATING WAVEFORMS Vin=12V, Vo=1.8V, Io=0- 6A, Room Temperature, No Air Flow Efficiency (%) 85 80 75 70 65 60 55 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Load Current (A) Efficiency Vin=Vcc=12V Efficiency Vin=12V Vcc=5V Fig.15: Efficiency versus load current Power Loss (W) 2.2 1.8 1.4 1.0 0.6 0.2 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Load Current (A) Power Loss Vin=Vcc=12V Power Loss Vin=12V Vcc=5V Fig.16: Power loss versus load current Rev 0.0 02/22/2008 12 IRDC3822A THERMAL IMAGES Vin=12V, Vo=1.8V, Io=6A, Room Temperature, No Air Flow Fig. 17: Thermal Image at 6A load Test point 3 is IR3822A Rev 0.0 02/22/2008 13 IRDC3822A PCB Metal and Components Placement The lead lands (the 11 IC pins) width should be equal to the nominal part lead width. The minimum lead to lead spacing should be 0.2mm to minimize shorting. Lead land length should be equal to the maximum part lead length + 0.3 mm outboard extension. The outboard extension ensures a large and inspectable toe fillet. The pad lands (the 4 big pads other than the 11 IC pins) length and width should be equal to maximum part pad length and width. However, the minimum metal to metal spacing should be no less than 0.17mm for 2 oz. Copper; no less than 0.1mm for 1 oz. Copper and no less than 0.23mm for 3 oz. Copper. Rev 0.0 02/22/2008 IRDC3822A Solder Resist It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads. The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.05mm to accommodate solder resist mis-alignment. Ensure that the solder resist in between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. Rev 0.0 02/22/2008 IRDC3822A Stencil Design * * The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much solder is deposited on the center pad the part will float and the lead lands will be open. The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. Rev 0.0 02/22/2008 IRDC3822A IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 This product has been designed and qualified for the Consumer market. Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 11/07 Rev 0.0 02/22/2008