MC21206A6W-SPTLY - MIDAS - Product.Network

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)1493602602

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)1493665111

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tsLtd, Electra H

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nents.co.uk

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onents.co.uk

ouse, 32 Southt

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wn Road, Great

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Yarmouth,Norf

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lk, England, NR31ODU

PAGE 2 OF 22

DOCUMENT REVISION HISTORY:

DATE

PAGE

DESCRIPTION

1999.8.

2005.3.

.12

-

4

First release

Modify the full specification

Update the part number system

PAGE 3 OF 22

Contents

1. Module Classification Information

2. Precautions in use of LCD Modules

3. General Specification

4. Absolute Maximum Ratings

5. Electrical Characteristics

6. Optical Characteristics

7. Interface Pin Function

8. Power Supply

9. Contour Drawing & Block Diagram

10. Function Description

11. Character Generator ROM Pattern

12. Instruction Table

13. Timing Characteristics

14. Initializing of LCM

15. Quality Assurance

16. Reliability

PAGE 5 OF 22

2. Precautions in use of LCD Modules

(1)Avoid applying excessive shocks to the module or making any alterations or modifications to

it.

(2)Don’t make extra holes on the printed circuit board, modify its shape or change the

components of LCD module.

(3)Don’t disassemble the LCM.

(4)Don’t operate it above the absolute maximum rating.

(5)Don’t drop, bend or twist LCM.

(6)Soldering: only to the I/O terminals.

(7)Storage: please storage in anti-static electricity container and clean environment.

3. General Specification

Item Dimension Unit

Number of Characters 16 characters x 2 Lines Ё

Module dimension(No Backlight ) 55.7 x 32.0 x 10.0˄MAX˅ mm

Module dimension(With LED Backlight ) 55.7 x 32.0 x 15.0˄MAX˅ mm

View area 45.0 x 15.5 mm

Active area 37.85 x 11.70 mm

Dot size 0.45x 0.60 mm

Dot pitch 0.55 x 0.70 mm

Character size 2.65 x 5.50 mm

Character pitch 3.20 x 6.20 mm

LCD type STN

Duty 1/16

View direction 6 o’clock or 12 o’clock

Backlight Type None, YELLOW-GREEN

PAGE 6 OF 22

4. Absolute Maximum Ratings

Item Symbol Min Max Unit

Input Voltage VI -0.3 VDD+0.3 V

Supply Voltage For Logic VDD-VSS -0.3 7.0 V

Supply Voltage For LCD VDD-V0 Vdd-13.5 0 V

Operating Temp. Top 0 50 ć Standard

Temperature LCM Storage Temp. Tstr -10 60 ć

Operating Temp. Top -20 70 ć Wide Temperature

LCM Storage Temp. Tstr -30 80 ć

5. Electrical Characteristics

Item Symbol Condition Min Typ Max Unit

Supply Voltage For Logic VDD-VSS Ё 4.5 5.0 5.5 V

Supply Voltage For LCD VDD-V0 Ta=25ć 4.5 5.0 5.5 V

Input High Volt. VIH Ё 0.7 VDD Ё VDD V

Input Low Volt. VIL Ё VSS Ё 0.3 VDD V

Supply Current IDD V

DD=5V 0.5 0.7 2.0 mA

Supply Voltage of

Yellow-green backlight VLED

Forward

current

=70 mA

Number of

LED die

2x7= 14

3.8 4.1 4.4 V

PAGE 7 OF 22

6. Optical Characteristics

Item Symbol Condition Min Typ Max Unit

(V) CR 2 -20

Ё 35 deg

View Angle

(H) CR 2

 -30

Ё 30 deg

Contrast Ratio CR Ё Ё 3 Ё Ё

T rise Ё Ё Ё 250 ms

Response Time

T fall Ё Ё Ё 250 ms

Definition of Operation Voltage (Vop) Definition of Response Time ( Tr , Tf )

Driving Voltage(V)

Intensity

Cr Max

100ˁ

Vop

Selected Wave

Non-selected Wave

[positive type]

Cr = Lon / Loff

Intensity

90ˁ

100ˁ

Tr

10ˁ

Tf

Non-selected

Conition

Non-selected

Conition

Selected Conition

[positive type]

Conditions :

Operating Voltage : Vop Viewing Angle(Δ) : 0°Δ 0°

Frame Frequency : 64 HZ Driving Waveform : 1/N duty , 1/a bias

Definition of viewing angle(CR 2)



f= 180°

= 90°

= 0°

= 270°

b

r

l

PAGE 8 OF 22

7. Interface Pin Function

Pin No. Symbol Level Description

1 VSS 0V Ground

2 VDD 5.0V Supply Voltage for logic

3 VO (Variable) Operating voltage for LCD

4 RS H/L H: DATA, L: Instruction code

5 R/W H/L H: Read(MPUModule) L: Write(MPUModule)

6 E H,HL Chip enable signal

7 DB0 H/L Data bit 0

8 DB1 H/L Data bit 1

9 DB2 H/L Data bit 2

10 DB3 H/L Data bit 3

11 DB4 H/L Data bit 4

12 DB5 H/L Data bit 5

13 DB6 H/L Data bit 6

14 DB7 H/L Data bit 7

15 LED(+) Anode of LED Backlight

16 LED(-) Cathode of LED Backlight

PAGE 9 OF 22

8. POWER SUPPLY

SINGLE SUPPLY VOLTAGE TYPE

DUAL SUPPLY VOLTAGE TYPE

PAGE 10 OF 22

9. Contour Drawing &Block Diagram

0.10

6.20

5.50

0.60

3.20

2.65

0.45

4-R1.25

15.0(MAX.)

8.8± 0.5

11.70(A.A.)

15.5(V.A.)

24.7± 0.3

30.0

37.85(A.A.)

31.2

45.0(V.A.)

51.0± 0.3

P1.27X15=19.0519.0

32.0± 0.5

55.7± 0.3

LED B/L

20

DRIVER

16

4

40

CONTROLLER

8

RS

E

DB0

R/W

Vss

V0

Vdd

DB7

CHARACTERS

LCD PANEL 12X2

10.0(MAX.)

4.4± 0.5

NO/B/L

116

16-Ø0.4 1.6± 0.1 1.6± 0.1

PAGE 11 OF 22

10. Function Description

The LCD display Module is built in a LSI controller, the controller has two 8-bit registers, an

instruction register (IR) and a data register (DR).

The IR stores instruction codes, such as display clear and cursor shift, and address information

for display data RAM (DDRAM) and character generator (CGRAM). The IR can only be written

from the MPU. The DR temporarily stores data to be written or read from DDRAM or

CGRAM. When address information is written into the IR, then data is stored into the DR from

DDRAM or CGRAM. By the register selector (RS) signal, these two registers can be selected.

RS R/W Operation

0 0 IR write as an internal operation (display clear, etc.)

0 1 Read busy flag (DB7) and address counter (DB0 to DB7)

1 0 Write data to DDRAM or CGRAM (DR to DDRAM or CGRAM)

1 1 Read data from DDRAM or CGRAM (DDRAM or CGRAM to DR)

Busy Flag (BF)

When the busy flag is 1, the controller LSI is in the internal operation mode, and the next

instruction will not be accepted. When RS=0 and R/W=1, the busy flag is output to DB7. The

next instruction must be written after ensuring that the busy flag is 0.

Address Counter (AC)

The address counter (AC) assigns addresses to both DDRAM and CGRAM

Display Data RAM (DDRAM)

This DDRAM is used to store the display data represented in 8-bit character codes. Its extended

capacity is 80×8 bits or 80 characters. Below figure is the relationships between DDRAM

addresses and positions on the liquid crystal display.

AC

(hexadecimal)

High bits Low bits

AC6 AC5 AC4 AC3 AC2 AC1 AC0 1 0 0 1 1 1 0

Example: DDRAM addresses 4E

PAGE 12 OF 22

Character Generator ROM (CGROM)

The CGROM generate 5×8 dot or 5×10 dot character patterns from 8-bit character codes. See

Table 2.

Character Generator RAM (CGRAM)

In CGRAM, the user can rewrite character by program. For 5×8 dots, eight character patterns

can be written, and for 5×10 dots, four character patterns can be written.

Write into DDRAM the character code at the addresses shown as the left column of table 1. To

show the character patterns stored in CGRAM.

Display position DDRAM address

00 01 02 03 04 05 06 07 08 09 0A 0B

40 41 42 43 44 45 46 47 48 49 4A 4B

-Line by 12-Character Display

1 2 3 4 5 6 7 8 9 10 11 12

PAGE 13 OF 22

Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character

patterns

Table 1.

For 5 * 8 dot character patterns

Character Codes

( D D R A M data ) CGRAM Address C haracter P atterns

( C G R A M data )

543210675432 0176543210

000

001

100

101

010

011

110

111

000

001

100

101

010

011

110

111

000

001

010

011

110

111

***

***00000

***

***00000

00 00

000

00 0

000

0

000

0

000

001

***

1110000 *111

0000 *000

0000 *001

H ig h L ow H igh L ow H ig h L ow

For 5 * 10 dot character patterns

Character Codes

( D D R A M data ) CGRAM Address C haracter P atterns

( C G R A M data )

7

H ig h L ow

4563210

H ig h L ow

543210

H igh L ow

7654 1230

***00000

00000***

***

********

0000

0001

0010

0011

0100

0101

0110

0111

1000

100 1

10 10

1111

00000

0000 *000 00

00

000

0

0000

Character

pattern( 1 )

Cursor pattern

Character

pattern( 2 )

Cursor pattern

Character

pattern

Cursor pattern

: " H igh "

PAGE 14 OF 22

11. Character Generator ROM Pattern

Table.2

PAGE 15 OF 22

12. Instruction Table

Instruction Code

Instruction

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Description Execution time

(fosc=270Khz)

Clear Display 0 0 0 0 0 0 0 0 0 1

Write “00H” to DDRAM and set

DDRAM address to “00H” from AC 1.53ms

Return Home 0 0 0 0 0 0 0 0 1

Ё

Set DDRAM address to “00H” from AC

and return cursor to its original position

if shifted. The contents of DDRAM are

not changed.

1.53ms

Entry Mode

Set 0 0 0 0 0 0 0 1 I/D SH

Assign cursor moving direction and

enable the shift of entire display. 39μs

Display

ON/OFF

Control

0 0 0 0 0 0 1 D C B

Set display (D), cursor (C), and blinking

of cursor (B) on/off control bit. 39μs

Cursor or

Display Shift 0 0 0 0 0 1 S/C R/L Ё Ё

Set cursor moving and display shift

control bit, and the direction, without

changing of DDRAM data.

39μs

Function Set 0 0 0 0 1 DL N F

Ё Ё

Set interface data length

(DL:8-bit/4-bit), numbers of display line

(N:2-line/1-line)and, display font type

(F:5×11 dots/5×8 dots)

39μs

Set CGRAM

Address 0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter. 39μs

Set DDRAM

Address 0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address counter. 39μs

Read Busy

Flag and

Address

0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0

Whether during internal operation or not

can be known by reading BF. The

contents of address counter can also be

read.

0μs

Write Data to

RAM 1 0 D7 D6 D5 D4 D3 D2 D1 D0

Write data into internal RAM

(DDRAM/CGRAM). 43μs

Read Data

from RAM 1 1 D7 D6 D5 D4 D3 D2 D1 D0

Read data from internal RAM

(DDRAM/CGRAM). 43μs

Ϡ ”Ё”Κdon’t care

PAGE 16 OF 22

13. Timing Characteristics

13.1

ʳ

Write Operation

Ta=25 , VDD=5.0± 0.5Vć

Item Symbol Min Typ Max Unit

Enable cycle time tcycE 1200 Ё Ё ns

Enable pulse width (high level) PWEH 140 Ё Ё ns

Enable rise/fall time tEr,tEf Ё Ё 25 ns

Address set-up time (RS, R/W to E) tAS 0

Ё Ё ns

Address hold time tAH 10

Ё Ё ns

Data set-up time tDSW 40 Ё Ё ns

Data hold time tH 10

Ё Ё ns

VIH1

VIL1

VIH1

VIL1

tcycE

VIH1

VIL1

VIH1

VIL1

tAS tAH

tAH

tEf

tH

tDSW

PWEH

tEr

VIL1

VIH1

VIL1

VIH1

VIL1

RS

R/W

E

DB0 to DB7 Valid data

PAGE 17 OF 22

13.2

ʳ

Read Operation

Ta=25, VDD=5.0± 0.5Vć

Item Symbol Min Typ Max Unit

Enable cycle time tcycE 1200 Ё Ё ns

Enable pulse width (high level) PWEH 140 Ё Ё ns

Enable rise/fall time tEr,tEf Ё Ё 25 ns

Address set-up time (RS, R/W to E) tAS 0

Ё Ё ns

Address hold time tAH 10

Ё Ё ns

Data delay time tDDR Ё Ё 100 ns

Data hold time tDHR 10 Ё Ё ns

VIH1

VIL1

VIH1

VIL1

tcycE

VOH1

VOL1*

tAS tAH

tAH

tEf

tDHR

PWEH

tEr

VIL1

VIH1

VIL1

VIH1

VIL1

RS

R/W

E

DB0 to DB7

VIH1 VIH1

VOH1

*VOL1

Valid data

tDDR

NOTE: *VOL1 is assumed to be 0.8V at 2 MHZ operation.

PAGE 18 OF 22

13.3 Timing Diagram of VDD Against V0.

Power on sequence shall meet the requirement of Figure 4, the timing diagram of VDD against

V0.

VDD

0V

V0

95%

50ms(typical)

LOGIC SUPPLY

VOLTAGE

LCD SUPPLY

VOLTAGE

PAGE 19 OF 22

14.Initializing of LCM

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

Wait for more than 40 ms after VDD rises to 4.5 V

R/W

0

RS

0

RS

0

RS

0

RS

0

Display Clear

Entry Mode Set

Display ON/OFF control

4-Bit Ineterface

Initialization ends

01 SH

I/D ****

Wait for more than 37 Ps

DB3

Wait for more than 1ms

DB3

DB4DB6DB7 DB5

DB5DB7

0

DB6

0

DB4

0

0*

0

10

0

*

DB5DB7

0

1

0

D

DB6

B

0

DB4

0

C

*

DB2 DB1 DB0

*

DB0

*

DB1DB2

**

*

DB0DB1

*

DB2

*

BF can not be checked before this instruction.

Function set

BF can not be checked before this instruction.

Wait for more than 37us

DB3

Wait for more than 39 Ps

DB3

Wait for more than 39us

DB5

FN

DB7

0

DB6

0

***

0

DB4

1 *

DB5

00

NF

DB7 DB6

*10

*

**

DB4

*

DB0

**

DB1DB2

** Function set

*

DB0

***

**

DB1DB2

DB3

DB5DB7

00

DB6

1

DB4

1*

Power on

*

DB0DB1

*

DB2

*

PAGE 20 OF 22

Power on

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Wait for more than 40 ms after VDD rises to 4.5 V

Wait for more than 39us

1

DB4DB6

0

DB5

1

DB1DB2DB3

F**

DB0

DB4DB7RS R/W DB6 DB5 DB1DB2DB3 DB0

0000001BC D

Initialization ends

BF can not be checked before this instruction.

Function set

BF can not be checked before this instruction.

8-Bit Ineterface

Wait for more than 37us

Display ON/ OFF control

000011*F*

000

R/W

0

R/W

0

RS

0

Entry Mode Set

DB3

Wait for more than 1ms

00000

DB5DB7 DB6 DB4

I/D

1S

DB0DB1DB2

Display Clear

DB3

Wait for more than 37 Ps

DB5DB7

00

DB6 DB4

0

00

DB0

1

DB1

0

DB2

0

RS R/W DB7

N

PAGE 21 OF 22

15.Quality Assurance

Screen Cosmetic Criteria

Item Defect Judgment Criterion Partition

1 Spots

A)Clear

Size: d mm Acceptable Qty in active area

d 0.1 Disregard

0.1<d 0.2 6

0.2<d 0.3 2

0.3<d 0

Note: Including pin holes and defective dots which must

be within one pixel size.

B)Unclear

Size: d mm Acceptable Qty in active area

d 0.2 Disregard

0.2<d 0.5 6

0.5<d 0.7 2

0.7<d 0

Minor

2 Bubbles in Polarizer

Size: d mm Acceptable Qty in active area

d 0.3 Disregard

0.3<d 1.0 3

1.0<d 1.5 1

1.5<d 0

Minor

3 Scratch

In accordance with spots cosmetic criteria. When the light

reflects on the panel surface, the scratches are not to be

remarkable.

Minor

4 Allowable Density Above defects should be separated more than 30mm each

other. Minor

5 Coloration

Not to be noticeable coloration in the viewing area of the

LCD panels.

Back-light type should be judged with back-light on state

only.

Minor

PAGE 22 OF 22

16.Reliability

Content of Reliability Test

Environmental Test

Test Item Content of Test Test Condition Applicable

Standard

High

Temperature

storage

Endurance test applying the high storage

temperature for a long time.

60ć

96hrs ——

Low

Temperature

storage

Endurance test applying the high storage

temperature for a long time.

-10ć

96hrs ——

High

Temperature

Operation

Endurance test applying the electric stress

(Voltage & Current) and the thermal stress

to the element for a long time.

50ć

96hrs ——

Low

Temperature

Operation

Endurance test applying the electric stress

under low temperature for a long time.

0ć

96hrs ——

High

Temperature/

Humidity

Storage

Endurance test applying the high

temperature and high humidity storage for a

long time.

60 ,90%RHć

96hrs ——

High

Temperature/

Humidity

Operation

Endurance test applying the electric stress

(Voltage & Current) and temperature /

humidity stress to the element for a long

time.

50 ,90%RHć

96hrs ——

Temperature

Cycle

Endurance test applying the low and high

temperature cycle.

-10 25 60ćć ć

30min 5min 30min

1 cycle

-10 /60ćć

10 cycles ——

Mechanical Test

Vibration test Endurance test applying the vibration

during transportation and using.

10~22Hz1.5mmp-p

22~500Hz1.5G

Total 0.5hrs

——

Shock test

Constructional and mechanical endurance

test applying the shock during

transportation.

50G Half sign

wave 11 msedc

3 times of each

direction

——

***Supply voltage for logic system=5V. Supply voltage for LCD system =Operating voltage at 25ć

Address:

Email:sal

e

Website:

w

Tel:+44(0

Fax:+44(

0

MidasCompone

n

e

s@midascomp

o

w

ww.midascom

p

)1493602602

0

)1493665111

n

tsLtd, Electra H

o

nents.co.uk

p

onents.co.uk

ouse, 32 Southt

o

wn Road, Great

Y

Yarmouth,Norf

o

lk, England, NR31ODU