Address: Midas Componennts Ltd, Electra House, 32 Southto own Road, Great Y armouth, Norfo olk, England, NR31 ODU Email:sale es@midascompoonents.co.uk Website:w www.midascompponents.co.uk Tel:+44(0)1493 602602 0)1493 665111 Fax:+44(0 DOCUMENT REVISION DATE PAGE 1999.8. 2005.3. .12 4 HISTORY: DESCRIPTION First release Modify the full specification Update the part number system PAGE 2 OF 22 Contents 1. Module Classification Information 2. Precautions in use of LCD Modules 3. General Specification 4. Absolute Maximum Ratings 5. Electrical Characteristics 6. Optical Characteristics 7. Interface Pin Function 8. Power Supply 9. Contour Drawing & Block Diagram 10. Function Description 11. Character Generator ROM Pattern 12. Instruction Table 13. Timing Characteristics 14. Initializing of LCM 15. Quality Assurance 16. Reliability PAGE 3 OF 22 2. Precautions in use of LCD Modules (1)Avoid applying excessive shocks to the module or making any alterations or modifications to it. (2)Don't make extra holes on the printed circuit board, modify its shape or change the components of LCD module. (3)Don't disassemble the LCM. (4)Don't operate it above the absolute maximum rating. (5)Don't drop, bend or twist LCM. (6)Soldering: only to the I/O terminals. (7)Storage: please storage in anti-static electricity container and clean environment. 3. General Specification Item Dimension Unit 16 characters x 2 Lines Module dimension(No Backlight ) 55.7 x 32.0 x 10.0MAX mm Module dimension(With LED Backlight ) 55.7 x 32.0 x 15.0MAX mm View area 45.0 x 15.5 mm Active area 37.85 x 11.70 mm Dot size 0.45x 0.60 mm Dot pitch 0.55 x 0.70 mm Character size 2.65 x 5.50 mm Character pitch 3.20 x 6.20 mm Number of Characters LCD type STN Duty 1/16 View direction 6 o'clock or 12 o'clock Backlight Type None, YELLOW-GREEN PAGE 5 OF 22 4. Absolute Maximum Ratings Item Symbol Min Max Unit VI -0.3 VDD+0.3 V Supply Voltage For Logic VDD-VSS -0.3 7.0 V Supply Voltage For LCD VDD-V0 Vdd-13.5 0 V Input Voltage Standard Operating Temp. Top 0 50 Temperature LCM Storage Temp. Tstr -10 60 Wide Temperature Operating Temp. Top -20 70 LCM Storage Temp. Tstr -30 80 5. Electrical Characteristics Item Symbol Condition Min Typ Max Unit Supply Voltage For Logic VDD-VSS 4.5 5.0 5.5 V Supply Voltage For LCD VDD-V0 Ta=25 4.5 5.0 5.5 V Input High Volt. VIH 0.7 VDD VDD V Input Low Volt. VIL VSS 0.3 VDD V Supply Current IDD VDD=5V 0.5 0.7 2.0 mA 3.8 4.1 4.4 V Supply Voltage of Yellow-green backlight Forward current =70 mA VLED Number of LED die 2x7= 14 PAGE 6 OF 22 6. Optical Characteristics Item Symbol Condition Min Typ Max Unit (V) CR2 -20 35 deg (H) CR2 -30 30 deg CR 3 T rise 250 ms T fall 250 ms View Angle Contrast Ratio Response Time Definition of Operation Voltage (Vop) Intensity 100 Definition of Response Time ( Tr , Tf ) Non-selected Conition Selected Wave Non-selected Wave Selected Conition Non-selected Conition Intensity 10 Cr Max Cr = Lon / Loff 90 100 Vop Tr Driving Voltage(V) [positive type] Tf [positive type] Conditions : Operating Voltage : Vop Viewing Angle() : 0 0 Frame Frequency : 64 HZ Driving Waveform : 1/N duty , 1/a bias Definition of viewing angle(CR2) f b l = 180 r = 90 = 270 = 0 PAGE 7 OF 22 7. Interface Pin Function Pin No. Symbol Level Description 1 VSS 0V Ground 2 VDD 5.0V 3 VO 4 RS H/L H: DATA, L: Instruction code 5 R/W H/L H: Read(MPUModule) L: Write(MPUModule) 6 E H,HL 7 DB0 H/L Data bit 0 8 DB1 H/L Data bit 1 9 DB2 H/L Data bit 2 10 DB3 H/L Data bit 3 11 DB4 H/L Data bit 4 12 DB5 H/L Data bit 5 13 DB6 H/L Data bit 6 14 DB7 H/L Data bit 7 15 LED(+) Anode of LED Backlight 16 LED(-) Cathode of LED Backlight Supply Voltage for logic (Variable) Operating voltage for LCD Chip enable signal PAGE 8 OF 22 8. POWER SUPPLY SINGLE SUPPLY VOLTAGE TYPE DUAL SUPPLY VOLTAGE TYPE PAGE 9 OF 22 9. Contour Drawing &Block Diagram 55.7 0.3 51.0 0.3 45.0(V.A.) LED B/L 11.70(A.A.) 15.5(V.A.) NO/B/L 37.85(A.A.) 10.0(MAX.) 15.0(MAX.) 4.4 0.5 8.8 0.5 24.7 0.3 30.0 32.0 0.5 31.2 16 1 16-O 0.4 19.0 1.6 0.1 4-R1.25 P1.27X15=19.05 1.6 0.1 3.20 2.65 Vdd V0 Vss 8 20 0.10 DB0 DB7 LCD PANEL 12X2 CHARACTERS 16 6.20 5.50 0.60 E R/W RS CONTROLLER 0.45 40 DRIVER 4 0.10 PAGE 10 OF 22 10. Function Description The LCD display Module is built in a LSI controller, the controller has two 8-bit registers, an instruction register (IR) and a data register (DR). The IR stores instruction codes, such as display clear and cursor shift, and address information for display data RAM (DDRAM) and character generator (CGRAM). The IR can only be written from the MPU. The DR temporarily stores data to be written or read from DDRAM or CGRAM. When address information is written into the IR, then data is stored into the DR from DDRAM or CGRAM. By the register selector (RS) signal, these two registers can be selected. RS R/W Operation 0 0 IR write as an internal operation (display clear, etc.) 0 1 Read busy flag (DB7) and address counter (DB0 to DB7) 1 0 Write data to DDRAM or CGRAM (DR to DDRAM or CGRAM) 1 1 Read data from DDRAM or CGRAM (DDRAM or CGRAM to DR) Busy Flag (BF) When the busy flag is 1, the controller LSI is in the internal operation mode, and the next instruction will not be accepted. When RS=0 and R/W=1, the busy flag is output to DB7. The next instruction must be written after ensuring that the busy flag is 0. Address Counter (AC) The address counter (AC) assigns addresses to both DDRAM and CGRAM Display Data RAM (DDRAM) This DDRAM is used to store the display data represented in 8-bit character codes. Its extended capacity is 80x8 bits or 80 characters. Below figure is the relationships between DDRAM addresses and positions on the liquid crystal display. High bits Low bits Example: DDRAM addresses 4E AC (hexadecimal) AC6 AC5 AC4 AC3 AC2 AC1 AC0 PAGE 11 OF 22 1 0 0 1 1 1 0 Display position DDRAM address 1 2 3 4 5 6 00 01 02 03 04 05 40 41 42 43 44 45 7 8 9 10 11 12 06 07 08 09 0A 0B 46 47 48 49 4A 4B -Line by 12-Character Display Character Generator ROM (CGROM) The CGROM generate 5x8 dot or 5x10 dot character patterns from 8-bit character codes. See Table 2. Character Generator RAM (CGRAM) In CGRAM, the user can rewrite character by program. For 5x8 dots, eight character patterns can be written, and for 5x10 dots, four character patterns can be written. Write into DDRAM the character code at the addresses shown as the left column of table 1. To show the character patterns stored in CGRAM. PAGE 12 OF 22 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character patterns Table 1. F o r 5 * 8 d o t c h a ra c te r p a tte rn s C h a ra c te r C o d e s ( D D R A M d a ta ) 7 6 5 4 3 H ig h 0 0 0 0 0 0 0 0 0 2 1 0 Low 0 0 0 * 0 * 0 * 1 0 0 1 C h a ra c te r P a tte rn s ( C G R A M d a ta ) C G R A M A d d re ss 5 4 3 2 1 0 0 1 1 Low 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 0 0 1 1 0 1 1 1 1 0 0 0 0 7 H ig h 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 * * * * * * * * * * * * * * * * * * 6 5 H ig h * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 4 3 2 1 0 Low 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C h a ra c te r p a tte rn ( 1 ) 0 0 0 0 C u rs o r p a tte r n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C h a ra c te r p a tte rn ( 2 ) C u rs o r p a tte r n * F o r 5 * 1 0 d o t c h a ra c te r p a tte rn s C h a ra c te r C o d e s ( D D R A M d a ta ) 7 6 5 4 H ig h 0 0 0 3 2 1 0 Low 0 * 0 0 C h a ra c te r P a tte rn s ( C G R A M d a ta ) C G R A M A d d re ss 5 4 3 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 H ig h 0 0 2 1 0 7 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 * * * * * * * * * * * 1 1 * Low 6 5 4 3 1 0 * * * * * * * * * * * * 0 * 0 * * * * * * * * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * * * * * * H ig h : " H ig h " PAGE 13 OF 22 2 Low * C h a ra c te r p a tte rn C u rs o r p a tte r n 11. Character Generator ROM Pattern Table.2 PAGE 14 OF 22 12. Instruction Table Instruction Code Instruction Description Execution time (fosc=270Khz) RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Clear Display 0 0 0 0 0 0 0 0 Write "00H" to DDRAM and set 0 1 Set DDRAM address to "00H" from AC and return cursor to its original position if shifted. The contents of DDRAM are not changed. Assign cursor moving direction and enable the shift of entire display. 39s Set display (D), cursor (C), and blinking of cursor (B) on/off control bit. 39s DDRAM address to "00H" from AC Return Home 0 0 0 0 0 0 0 0 1 Entry Mode Set 0 0 0 0 0 0 0 1 I/D SH Display ON/OFF Control 0 0 0 0 0 0 1 D C B Cursor or Display Shift 0 0 0 0 0 1 control bit, and the direction, without Function Set 1.53ms 1.53ms Set cursor moving and display shift S/C R/L 39s changing of DDRAM data. 0 0 0 0 1 DL N F Set interface data length (DL:8-bit/4-bit), numbers of display line (N:2-line/1-line)and, display font type 39s (F:5x11 dots/5x8 dots) Set CGRAM Address Set DDRAM Address 0 0 0 0 0 1 1 AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter. 39s AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address counter. 39s Whether during internal operation or not can be known by reading BF. The Read Busy Flag and Address 0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 Write Data to RAM 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Write data into internal RAM (DDRAM/CGRAM). 43s Read Data from RAM 1 1 D7 D6 D5 D4 D3 D2 D1 D0 Read data from internal RAM (DDRAM/CGRAM). 43s contents of address counter can also be read. 0s ""don't care PAGE 15 OF 22 13. Timing Characteristics 13.1 Write Operation VIH1 RS VIH1 VIL1 VIL1 tAS R/W tAH VIL1 VIL1 PWEH VIH1 E tAH tEf VIH1 VIL1 VIL1 tEr VIL1 tDSW tH VIH1 DB0 to DB7 VIH1 Valid data VIL1 VIL1 tcycE Ta=25, VDD=5.0 0.5V Item Symbol Min Typ Max Unit tcycE 1200 ns Enable pulse width (high level) PWEH 140 ns Enable rise/fall time tEr,tEf 25 ns Address set-up time (RS, R/W to E) tAS 0 ns Address hold time tAH 10 ns Data set-up time tDSW 40 ns tH 10 ns Enable cycle time Data hold time PAGE 16 OF 22 13.2 Read Operation VIH1 RS VIH1 VIL1 VIL1 tAS tAH VIH1 R/W VIH1 PWEH VIH1 E VIH1 VIL1 tEr tAH tEf VIL1 VOH1 DB0 to DB7 VIL1 tDHR t DDR VOL1* VOH1 Valid data *VOL1 tcycE NOTE: *VOL1 is assumed to be 0.8V at 2 MHZ operation. Ta=25, VDD=5.0 0.5V Item Symbol Min Typ Max Unit tcycE 1200 ns Enable pulse width (high level) PWEH 140 ns Enable rise/fall time tEr,tEf 25 ns Address set-up time (RS, R/W to E) tAS 0 ns Address hold time tAH 10 ns Data delay time tDDR 100 ns Data hold time tDHR 10 ns Enable cycle time PAGE 17 OF 22 13.3 Timing Diagram of VDD Against V0. Power on sequence shall meet the requirement of Figure 4, the timing diagram of VDD against V0. VDD 95% LOGIC SUPPLY VOLTAGE V0 0V 50ms(typical) 0V LCD SUPPLY VOLTAGE PAGE 18 OF 22 14.Initializing of LCM Power on Wait for more than 40 ms after VDD rises to 4.5 V BF can not be checked before this instruction. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 * * * * 0 0 0 0 Function set Wait for more than 39us BF can not be checked before this instruction. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 * * * 1 0 * 0 0 0 0 N F * * * * * * 0 0 Function set Wait for more than 39 Ps BF can not be checked before this instruction. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 * * * * Function set 0 0 0 0 N F * * * * * * 0 0 Wait for more than 37us RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display ON/OFF control * * * * 0 0 0 0 0 0 1 D C B * * * * 0 0 Wait for more than 37 Ps RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display Clear * * * * 0 0 0 0 0 0 * * * * 1 0 0 0 0 0 Wait for more than 1ms RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Entry Mode Set * * * * 0 0 0 0 0 0 1 I/D SH * * * * 0 0 0 Initialization ends 4-Bit Ineterface PAGE 19 OF 22 Power on Wait for more than 40 ms after VDDrises to 4.5 V BF can not be checked before this instruction. RS R/WDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function set 0 0 0 0 1 1 N F * * Wait for more than 39us BF can not be checked before this instruction. RS R/WDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function set 0 0 0 0 1 1 N F * * Wait for more than 37us RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display ON/OFF control 0 0 0 0 0 0 1 B C D Wait for more than 37 Ps RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display Clear 0 0 0 0 0 0 0 0 0 1 Wait for more than 1ms RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Entry Mode Set 0 0 0 0 0 0 0 1 I/D S Initialization ends 8-Bit Ineterface PAGE 20 OF 22 15.Quality Assurance Screen Cosmetic Criteria Item Defect 1 Spots 2 Bubbles in Polarizer 3 Scratch 4 Allowable Density 5 Coloration Judgment Criterion A)Clear Size: d mm Acceptable Qty in active area d 0.1 Disregard 0.1<d0.2 6 0.2<d0.3 2 0.3<d 0 Note: Including pin holes and defective dots which must be within one pixel size. B)Unclear Size: d mm Acceptable Qty in active area d 0.2 Disregard 0.2<d0.5 6 0.5<d0.7 2 0.7<d 0 Acceptable Qty in active area Size: d mm d0.3 Disregard 0.3<d1.0 3 1.0<d1.5 1 1.5<d 0 In accordance with spots cosmetic criteria. When the light reflects on the panel surface, the scratches are not to be remarkable. Above defects should be separated more than 30mm each other. Not to be noticeable coloration in the viewing area of the LCD panels. Back-light type should be judged with back-light on state only. PAGE 21 OF 22 Partition Minor Minor Minor Minor Minor 16.Reliability Content of Reliability Test Environmental Test Test Item High Temperature storage Low Temperature storage High Temperature Operation Low Temperature Operation High Temperature/ Humidity Storage High Temperature/ Humidity Operation Temperature Cycle Content of Test Test Condition Applicable Standard Endurance test applying the high storage temperature for a long time. 60 96hrs ---- Endurance test applying the high storage temperature for a long time. -10 96hrs ---- Endurance test applying the electric stress (Voltage & Current) and the thermal stress to the element for a long time. 50 96hrs ---- Endurance test applying the electric stress under low temperature for a long time. 0 96hrs ---- Endurance test applying the high 60,90%RH temperature and high humidity storage for a 96hrs long time. Endurance test applying the electric stress (Voltage & Current) and temperature / humidity stress to the element for a long time. Endurance test applying the low and high temperature cycle. -10 25 60 30min 5min 1 cycle ---- 50,90%RH 96hrs ---- -10/60 10 cycles ---- 30min Mechanical Test Vibration test Endurance test applying the vibration during transportation and using. Shock test Constructional and mechanical endurance test applying the shock during transportation. 10~22Hz1.5mmp-p 22~500Hz1.5G Total 0.5hrs 50G Half sign wave 11 msedc 3 times of each direction ---- ---- ***Supply voltage for logic system=5V. Supply voltage for LCD system =Operating voltage at 25 Address: Midas Componennts Ltd, Electra House, 32 Southto own Road, Great Y armouth, Norfo olk, England, NR31 ODU Email:sale es@midascompoonents.co.uk Website:w www.midascompponents.co.uk Tel:+44(0)1493 602602 0)1493 665111 Fax:+44(0 PAGE 22 OF 22