CS4340A 24-Bit, 192 kHz Stereo DAC for Audio Features Description ! 101 The CS4340A is a complete stereo digital-to-analog system including digital interpolation, fourth-order deltasigma digital-to-analog conversion, digital de-emphasis and switched capacitor analog filtering. The advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature, and a high tolerance to clock jitter. dB Dynamic Range ! -91 dB THD+N ! +3.3 V or +5 V Power Supply ! 50 mW with 3.3 V supply ! Low Clock Jitter Sensitivity ! Filtered Line Level Outputs ! On-Chip Digital De-emphasis for 44.1 kHz ! Popguard(R) Technology for Control of Clicks and Pops ! Up to 200 kHz Sample Rates ! Automatic Mode Detection for Sample Rates between 4 and 200 kHz ! Pin Compatible with the CS4340 SCLK The CS4340A accepts data at all standard audio sample rates up to 192 kHz, consumes very little power, operates over a wide power supply range and is pin compatible with the CS4340, as described in section 3.1. These features are ideal for DVD audio players. ORDERING INFORMATION CS4340A-KS 16-pin SOIC, -10 to 70 C CS4340A-KSZ, Lead Free, 16-pin SOIC, -10 to 70 C CDB4340A Evaluation Board DEM M UTEC De-emphasis External Mute Control RST LRCK Serial Audio Interface SDIN DIF0 DIF1 http://www.cirrus.com Interpolation Filter DAC Analog Filter AOUTL Interpolation Filter DAC Analog Filter AOUTR MCLK Copyright (c) Cirrus Logic, Inc. 2005 (All Rights Reserved) JULY '05 DS590F2 1 CS4340A TABLE OF CONTENTS 1. PIN DESCRIPTION ....................................................................................................................4 2. TYPICAL CONNECTION DIAGRAM......................................................................................5 3. APPLICATIONS .........................................................................................................................6 3.1 Upgrading from the CS4340 to the CS4340A .....................................................................6 3.2 Sample Rate Range/Operational Mode Detect ....................................................................6 3.3 System Clocking ..................................................................................................................6 3.4 Digital Interface Format.......................................................................................................7 3.5 De-Emphasis ........................................................................................................................8 3.6 Power-up Sequence..............................................................................................................9 3.7 Popguard(R) Transient Control...............................................................................................9 3.7.1 Power-up .....................................................................................................................9 3.7.2 Power-down ................................................................................................................9 3.7.3 Discharge Time ...........................................................................................................9 3.8 Mute Control ......................................................................................................................10 3.9 Grounding and Power Supply Arrangements ....................................................................10 4. CHARACTERISTICS AND SPECIFICATIONS.....................................................................11 RECOMMENDED OPERATING SPECIFICATION .................................................................11 ABSOLUTE MAXIMUM RATINGS...........................................................................................11 ANALOG CHARACTERISTICS (CS4340A-KS/KSZ)...............................................................12 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE.......................14 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE ..........................................17 DC ELECTRICAL CHARACTERISTICS ...................................................................................18 DIGITAL INTERFACE SPECIFICATIONS................................................................................18 DIGITAL INPUT CHARACTERISTICS .....................................................................................18 5. PARAMETER DEFINITIONS..................................................................................................19 6. REFERENCES...........................................................................................................................19 7. PACKAGE DIMENSIONS .......................................................................................................20 THERMAL CHARACTERISTICS AND SPECIFICATIONS ....................................................20 8. REVISION HISTORY...............................................................................................................21 2 DS590F2 CS4340A LIST OF FIGURES Figure 1. Typical Connection Diagram..........................................................................................................5 Figure 2. CS4340A Format 0 - I2S up to 24-Bit Data ....................................................................................7 Figure 3. CS4340A Format 1 - Left Justified up to 24-Bit Data.....................................................................8 Figure 4. CS4340A Format 2 - Right Justified, 24-Bit Data ..........................................................................8 Figure 5. CS4340A Format 3 - Right Justified, 16-Bit Data ..........................................................................8 Figure 6. De-Emphasis Curve.......................................................................................................................8 Figure 7. Output Test Load .........................................................................................................................13 Figure 8. Maximum Loading........................................................................................................................13 Figure 9. Single-Speed Stopband Rejection ...............................................................................................14 Figure 10. Single-Speed Transition Band ...................................................................................................14 Figure 11. Single-Speed Transition Band (Detail).......................................................................................15 Figure 12. Single-Speed Passband Ripple .................................................................................................15 Figure 13. Double-Speed Stopband Rejection............................................................................................15 Figure 14. Double-Speed Transition Band..................................................................................................15 Figure 15. Double-Speed Transition Band (Detail) .....................................................................................16 Figure 16. Double-Speed Passband Ripple................................................................................................16 Figure 17. Serial Input Timing .....................................................................................................................17 LIST OF TABLES Table 1. CS4340A Auto-Detect.....................................................................................................................6 Table 2. Single-Speed Mode Standard Frequencies ....................................................................................7 Table 3. Double-Speed Mode Standard Frequencies...................................................................................7 Table 4. Quad-Speed Mode Standard Frequencies .....................................................................................7 Table 5. Digital Interface Format - DIF1 and DIF0 ........................................................................................7 Table 6. De-Emphasis Control ......................................................................................................................8 DS590F2 3 CS4340A 1. PIN DESCRIPTION RST 1 16 MUTEC SDIN 2 15 AOUTL SCLK 3 14 VA LRCK 4 13 AGND MCLK 5 12 AOUTR DIF1 6 11 REF_GND DIF0 7 10 VQ DEM 8 9 FILT+ Pin Name # Pin Description RST 1 Reset (Input) - Powers down device. SDIN 2 Serial Audio Data (Input) - Input for two's complement serial audio data. SCLK 3 Serial Clock (Input) -Serial clock for the serial audio interface. LRCK 4 Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. MCLK 5 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. DIF1 DIF0 6 7 Digital Interface Format (Input) - Defines the required relationship between the Left Right Clock, Serial Clock and Serial Audio Data. DEM 8 De-emphasis Control (Input) - Selects the standard 15s/50s digital de-emphasis filter response for the 44.1 kHz sample rate. FILT+ 9 Positive Voltage Reference (Output) - Positive voltage reference for the internal sampling circuits. VQ 10 Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage. REF_GND 11 Reference Ground (Input) - Ground reference for the internal sampling circuits. AOUTR AOUTL 12 15 Analog Outputs (Output) - The full scale analog output level is specified in the Analog Characteristics table. AGND 13 Analog Ground (Input) VA 14 Power (Input) - Positive power for the analog, digital and serial audio interface sections. MUTEC 16 Mute Control (Output) - Control signal for an optional mute circuit. 4 DS590F2 CS4340A 2. TYPICAL CONNECTION DIAGRAM +3.3V or +5.0V + 0.1 F 14 1 F VA 2 Serial Audio Data Processor 3 4 SDIN 3.3 F SCLK AOUT L 560 Left Audio O utput 15 + LR CK C 10 k RL CS4340A M UTEC 16 External Clock 5 M CLK FILT+ VQ 6 7 Mode Configuration OPTIONAL MUTE CIRCUIT 9 + 10 .1 F + 1 F 0.1 F 1 F 11 REF_GND DIF1 3.3 F DIF0 560 Right Audio O utput 12 8 AOUTR DEM 1 + 10 k RST C RL AGND 13 C= R L + 560 4 F S R L 560 Figure 1. Typical Connection Diagram DS590F2 5 CS4340A 3. APPLICATIONS 3.1 Upgrading from the CS4340 to the CS4340A The CS4340A is pin and functionally compatible with all CS4340 designs, operating at the standard audio sample rates, that use pin 3 as a serial clock input. In addition to the features of the CS4340, the CS4340A supports standard sample rates up to 192 kHz, as well as automatic mode detection for sample rates between 4 and 200 kHz. The automatic mode detection feature allows sample rate changes between single, double and quad-speed modes without external intervention. The CS4340A does not support an internal serial clock mode, sample rates between 50 kHz and 84 kHz, de-emphasis for 32 and 48 kHz, or 2.7 V operation as does the CS4340. 3.2 Sample Rate Range/Operational Mode Detect The device operates in one of three operational modes. It will auto-detect the correct mode when the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges illustrated in Table 1. Sample rates outside the specified range for each mode are not supported. Input Sample Rate (FS) 4 kHz - 50 kHz 84 kHz - 100 kHz 170 kHz - 200 kHz MODE Single-Speed Mode Double-Speed Mode Quad-Speed Mode Table 1. CS4340A Auto-Detect 3.3 System Clocking The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks. The LRCK, defined also as the input sample rate (Fs), must be synchronously derived from the MCLK according to specified ratios. The specified ratios of MCLK to LRCK, along with several standard audio sample rates and the required MCLK frequency, are illustrated in Tables 2-4. 6 DS590F2 CS4340A Sample Rate (kHz) MCLK (MHz) 256x 8.1920 11.2896 12.2880 32 44.1 48 384x 12.2880 16.9344 18.4320 512x 16.3840 22.5792 24.5760 768x 24.5760 33.8688 36.8640 Table 2. Single-Speed Mode Standard Frequencies Sample Rate (kHz) 128x 11.2896 12.2880 88.2 96 MCLK (MHz) 192x 256x 16.9344 22.5792 18.4320 24.5760 384x 33.8688 36.8640 Table 3. Double-Speed Mode Standard Frequencies Sample Rate (kHz) MCLK (MHz) 128x 22.5792 24.5760 176.4 192 192x 33.8688 36.8640 Table 4. Quad-Speed Mode Standard Frequencies 3.4 Digital Interface Format The device will accept audio samples in several digital interface formats as illustrated in Table 5. The desired format is selected via the DIF1 and DIF0 pins. For an illustration of the required relationship between LRCK, SCLK and SDIN, see Figures 2-5. DIF1 0 0 1 1 DIF0 0 1 0 1 DESCRIPTION I2S, up to 24-bit data Left Justified, up to 24-bit data Right Justified, 24-bit Data Right Justified, 16-bit Data FORMAT 0 1 2 3 FIGURE 2 3 4 5 Table 5. Digital Interface Format - DIF1 and DIF0 Left C ha nnel LR C K R ig ht C ha n nel SCLK SDIN M SB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB M SB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 2. CS4340A Format 0 - I2S up to 24-Bit Data DS590F2 7 CS4340A Left C ha nnel LR C K R ig ht C ha n nel SCLK SDIN M SB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 M SB -1 LSB -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 3. CS4340A Format 1 - Left Justified up to 24-Bit Data LRCK R ig ht C ha nne l Le ft C ha nne l SCLK SDIN 0 7 23 22 21 20 19 18 6 5 4 3 2 1 0 7 23 22 21 20 19 18 6 5 4 3 2 1 0 Figure 4. CS4340A Format 2 - Right Justified, 24-Bit Data 3 2 clo cks LRCK R ig ht C ha nne l Le ft C ha nne l SCLK SDIN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 5. CS4340A Format 3 - Right Justified, 16-Bit Data 3 2 clo cks 3.5 De-Emphasis The device includes on-chip digital de-emphasis. Figure 6 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. Please see Table 6 for the desired de-emphasis control. Gain dB T1=50 s 0dB T2 = 15 s -10dB DEM DESCRIPTION 0 1 Disabled 44.1 kHz Table 6. De-Emphasis Control F1 3.183 kHz F2 Frequency 10.61 kHz Figure 6. De-Emphasis Curve 8 DS590F2 CS4340A 3.6 Power-up Sequence Reliable power-up can be accomplished by keeping the device in reset until the power supply and configuration pins are stable, and the clocks are locked to the appropriate frequencies discussed in section 3.3. It is also recommended that reset be enabled if the analog supply drops below the minimum specified operating voltage to prevent power glitch related issues. 3.7 Popguard(R) Transient Control The CS4340A uses Popguard(R) technology to minimize the effects of output transients during power-up and power-down. This technology, when used with external DC-blocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by single-ended single-supply converters. It is activated inside the DAC when RST is enabled/disabled and requires no other external control, aside from choosing the appropriate DC-blocking capacitors. 3.7.1 Power-up When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to AGND. Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach VQ and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quiescent voltage, minimizing the power-up transient. 3.7.2 Power-down To prevent transients at power-down, the device must first enter its power-down state by enabling RST. When this occurs, audio output ceases and the internal output buffers are disconnected from AOUTL and AOUTR. In their place, a soft-start current sink is substituted which allows the DCblocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off and the system is ready for the next power-on. 3.7.3 Discharge Time To prevent an audio transient at the next power-on, it is necessary to ensure that the DC-blocking capacitors have fully discharged before turning on the power or exiting the power-down state. If not, a transient will occur when the audio outputs are initially clamped to AGND. The time that the device must remain in the power-down state is related to the value of the DC-blocking capacitance. For example, with a 3.3 F capacitor, the minimum power-down time will be approximately 0.4 seconds. DS590F2 9 CS4340A 3.8 Mute Control The Mute Control pin goes high during power-up initialization, reset, or if the MCLK to LRCK ratio is incorrect. The pin will also go high following the reception of 8192 consecutive audio samples of static 0 or -1 on both the left and right channels. A single sample of non-zero data on either channel will cause the Mute Control pin to go low. This pin is intended to be used as a control for an external mute circuit to prevent the clicks and pops that can occur in any single-ended single supply system. Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. See the CDB4340A data sheet for a suggested mute circuit. 3.9 Grounding and Power Supply Arrangements As with any high resolution converter, the CS4340A requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 shows the recommended power arrangements, with VA connected to a clean supply. If the ground planes are split between digital ground and analog ground, REF_GND & AGND should be connected to the analog ground plane. Decoupling capacitors should be as close to the DAC as possible, with the low value ceramic capacitor being the closest. To further minimize impedance, these capacitors should be located on the same layer as the DAC. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path from FILT+ and REF_GND (as well as VQ and REF_GND), and should also be located on the same layer as the DAC. The CDB4340A evaluation board demonstrates the optimum layout and power supply arrangements. 10 DS590F2 CS4340A 4. CHARACTERISTICS AND SPECIFICATIONS (Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics are derived from measurements taken at TA = 25C.) RECOMMENDED OPERATING SPECIFICATION Parameters Symbol Min Typ Max Units 3.3 V Nominal 5.0 V Nominal VA 3.0 4.5 3.3 5 3.6 5.5 V V (Power Applied) TA -10 - +70 C DC Power Supply Ambient Operating Temperature ABSOLUTE MAXIMUM RATINGS (AGND = 0 V; all voltages with respect to AGND. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.) Parameters DC Power Supply Input Current Symbol Min Max Units VA -0.3 6.0 V Iin - 10 mA VIND -0.3 VA+0.4 V Ambient Operating Temperature (power applied) TA -55 125 C Storage Temperature Tstg -65 150 C Digital Input Voltage (Note 1) 1.Any pin except supplies. DS590F2 11 CS4340A ANALOG CHARACTERISTICS (CS4340A-KS/KSZ) (Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; test load RL = 10 k, CL = 10 pF (see Figure 7).) VA = 5.0 V Parameter Single-Speed Mode Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit 16-Bit Double-Speed Mode Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit 16-Bit Quad-Speed Mode Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit 16-Bit 12 VA = 3.3 V Min Typ Max Min Typ Max Unit 92 95 - 98 101 92 95 - 88 91 - 94 97 92 95 - dB dB dB dB - -91 -78 -38 -90 -72 -32 -85 - - -94 -74 -34 -91 -72 -32 -88 - dB dB dB dB dB dB 92 95 - 98 101 92 95 - 88 91 - 94 97 92 95 - dB dB dB dB - -91 -78 -38 -90 -72 -32 -85 - - -94 -74 -34 -91 -72 -32 -88 - dB dB dB dB dB dB 92 95 - 98 101 92 95 - 88 91 - 94 97 92 95 - dB dB dB dB - -91 -78 -38 -90 -72 -32 -85 - - -94 -74 -34 -91 -72 -32 -88 - dB dB dB dB dB dB Fs = 48 kHz (Note 2) unweighted A-Weighted unweighted A-Weighted (Note 2) 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB Fs = 96 kHz (Note 2) unweighted A-Weighted unweighted A-Weighted (Note 2) 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB Fs = 192 kHz (Note 2) unweighted A-Weighted unweighted A-Weighted (Note 2) 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB DS590F2 CS4340A ANALOG CHARACTERISTICS (CS4340A-KS/KSZ) (Continued) Parameters Symbol Min Typ Max Units - 102 - dB Interchannel Gain Mismatch - 0.1 - dB Gain Drift - 100 - ppm/C 0.6*VA 0.7*VA 0.8*VA Vpp - 100 - Dynamic Performance for All Modes Interchannel Isolation (1 kHz) DC Accuracy Analog Output Characteristics and Specifications Full Scale Output Voltage Output Impedance Minimum AC-Load Resistance (Note 3) RL - 3 - k Maximum Load Capacitance (Note 3) CL - 100 - pF Notes: 2. One-half LSB of triangular PDF dither is added to data. 3. Refer to Figure 8. . 3.3 F AOUTx + V out R L AGND C L Capacitive Load -- C L (pF) 125 100 75 25 2.5 3 Figure 7. Output Test Load DS590F2 Safe Operating Region 50 5 10 15 20 Resistive Load -- RL (k ) Figure 8. Maximum Loading 13 CS4340A COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (The filter characteristics and the X-axis of the response plots have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs.) Parameter Min Typ Max Unit 0 0 - 0.4535 0.4998 Fs Fs -0.02 - +0.08 dB 0.5465 - - Fs 50 - - dB - 9/Fs - s - - +0.05/-0.14 dB 0 0 - 0.4621 0.4982 Fs Fs -0.06 - +0.2 dB 0.577 - - Fs 55 - - dB - 4/Fs - s Single-Speed Mode - (4 kHz to 50 kHz sample rates) Passband to -0.05 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 4) Group Delay De-emphasis Error (Relative to 1 kHz) Fs = 44.1 kHz (Note 5) Double-Speed Mode - (84 kHz to 100 kHz sample rates) Passband to -0.1 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 4) Group Delay Quad-Speed Mode - (170 kHz to 200 kHz sample rates) Frequency Response 10 Hz to 20 kHz -1 - 0 dB Group Delay - 3/Fs - s Notes: 4. For Single-Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs. For Double-Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs. 5. De-emphasis is only available in Single-Speed Mode. Figure 9. Single-Speed Stopband Rejection 14 Figure 10. Single-Speed Transition Band DS590F2 CS4340A Figure 11. Single-Speed Transition Band (Detail) Figure 13. Double-Speed Stopband Rejection DS590F2 Figure 12. Single-Speed Passband Ripple Figure 14. Double-Speed Transition Band 15 CS4340A Figure 15. Double-Speed Transition Band (Detail) 16 Figure 16. Double-Speed Passband Ripple DS590F2 CS4340A SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE Parameters Symbol Min Max Units MCLK Frequency 1.024 38.4 MHz MCLK Duty Cycle 45 55 % 4 84 170 50 100 200 kHz kHz kHz 40 60 % Single-Speed Mode Double-Speed Mode - 128xFs 64xFs Hz Hz Quad-Speed Mode - MCLK -----------------2 Hz Input Sample Rate Single-Speed Mode Double-Speed Mode Quad-Speed Mode (Note 6) Fs Fs Fs LRCK Duty Cycle SCLK Frequency SCLK Pulse Width Low tsclkl 20 - ns SCLK Pulse Width High tsclkh 20 - ns SCLK rising to LRCK edge delay tslrd 20 - ns SCLK rising to LRCK edge setup time tslrs 20 - ns SDIN valid to SCLK rising setup time tsdlrs 20 - ns SCLK rising to SDIN hold time tsdh 20 - ns SCLK rising to MCLK edge delay (Note 7) tsmd 8 - ns Notes: 6. Speed mode is detected automatically, based on the input sample rate. 7. Only required for Quad-Speed Mode. MCLK t smd LRCK t t slrd t slrs t sclkh sclkl SCLK t t sdlrs sdh SDATA Figure 17. Serial Input Timing DS590F2 17 CS4340A DC ELECTRICAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to AGND.) Parameters Symbol Min Typ Max Units IA - 18 15 25 20 mA mA - 90 50 125 100 mW mW - 60 35 - A A - 0.3 0.1 - mW mW - 60 40 - dB dB VQ Nominal Voltage Output Impedance Maximum allowable DC current source/sink - 0.5*VA 250 0.01 - k Filt+ Nominal Voltage Output Impedance Maximum allowable DC current source/sink - VA 250 0.01 - mA MUTEC Low-Level Output Voltage - 0 - V MUTEC High-Level Output Voltage - VA - V Maximum MUTEC Drive Current - 3 - mA Normal Operation (Note 8) Power Supply Current VA = 5.0 V VA = 3.3 V Power Dissipation VA = 5.0 V VA = 3.3 V Power-down Mode (Note 9) Power Supply Current VA = 5.0 V VA = 3.3 V Power Dissipation VA = 5.0 V VA = 3.3 V IA All Modes of Operation Power Supply Rejection Ratio (Note 10) DIGITAL INTERFACE SPECIFICATIONS Parameters 1 kHz 60 Hz PSRR V mA V k (GND = 0 V; all voltages with respect to GND.) Symbol Min Max Units High-Level Input Voltage VIH 2.0 - V Low-Level Input Voltage VIL - 0.8 V High-Level Input Voltage VIH 2.0 - V Low-Level Input Voltage VIL - 0.8 V 3.3 V Logic (2.7 V to 3.6 V DC Supply) 5.0 V Logic (4.5 V to 5.5 V DC Supply) DIGITAL INPUT CHARACTERISTICS (AGND = 0 V; all voltages with respect to AGND.) Parameters Input Leakage Current Input Capacitance Symbol Min Typ Max Units Iin - - 10 A - 8 - pF Notes: 8. Normal operation is defined as RST = HI with a 997 Hz, 0 dBFS input sampled at the highest Fs for each speed mode, and open outputs, unless otherwise specified. 9. Power Down Mode is defined as RST = LO with all clocks and data lines held static. 10. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 1. Increasing the capacitance will also increase the PSRR. 18 DS590F2 CS4340A 5. PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Drift The change in gain value with temperature. Units in ppm/C. 6. REFERENCES 1) CDB4340A Evaluation Board Datasheet DS590F2 19 CS4340A 7. PACKAGE DIMENSIONS 16L SOIC (150 MIL BODY) PACKAGE DRAWING E H 1 b c D SEATING PLANE A L e DIM A A1 b C D E e H L MIN 0.053 0.004 0.013 0.0075 0.386 0.150 0.040 0.228 0.016 0 A1 INCHES NOM 0.064 0.006 0.016 0.008 0.390 0.154 0.050 0.236 0.025 4 MAX 0.069 0.010 0.020 0.010 0.394 0.157 0.060 0.244 0.050 8 MILLIMETERS NOM 1.63 0.15 0.41 0.20 9.91 3.90 1.27 6.0 0.64 4 MIN 1.35 0.10 0.33 0.19 9.80 3.80 1.02 5.80 0.40 0 MAX 1.75 0.25 0.51 0.25 10.00 4.00 1.52 6.20 1.27 8 JEDEC #: MS-012 Controling Dimension is Millimeters THERMAL CHARACTERISTICS AND SPECIFICATIONS Parameters Package Thermal Resistance (multi-layer boards) 20 Symbol Min Typ Max Units JA - 74 - C/Watt DS590F2 CS4340A 8. REVISION HISTORY Release F2 Date Changes July 2005 Added Revision History table and updated ordering information. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. 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Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. DS590F2 21 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Cirrus Logic: CS4340A-KSZ CS4340A-KSZR