General Description
The MAX1220/MAX1257/MAX1258 integrate a 12-bit,
multichannel, analog-to-digital converter (ADC), and a 12-
bit, octal, digital-to-analog converter (DAC) in a single IC.
These devices also include a temperature sensor and
configurable general-purpose I/O ports (GPIOs) with a
25MHz SPI-/QSPI™-/MICROWIRE®-compatible serial
interface. The ADC is available in 8 and 16 input-channel
versions. The octal DAC outputs settle within 2.0µs and
the ADC has a 225ksps conversion rate.
All devices include an internal reference (2.5V or
4.096V) for both the ADC and DAC. Programmable ref-
erence modes allow the use of an internal reference, an
external reference, or a combination of both. Features
such as an internal ±1°C accurate temperature sensor,
FIFO, scan modes, programmable internal or external
clock modes, data averaging, and AutoShutdown™
allow users to minimize power consumption and proces-
sor requirements. The low glitch energy (4nV•s) and low
digital feedthrough (0.5nV•s) of the integrated octal
DACs make these devices ideal for digital control of
fast-response closed-loop systems.
The devices are guaranteed to operate with a supply volt-
age from +2.7V to +3.6V (MAX1257) and from +4.75V to
+5.25V (MAX1220/MAX1258). These devices consume
2.5mA at 225ksps throughput, only 22µA at 1ksps
throughput, and under 0.2µA in the shutdown mode. The
MAX1257/MAX1258 feature 12 GPIOs, while the
MAX1220 offers four GPIOs that can be configured as
inputs or outputs.
The MAX1220 is available in a 36-pin TQFN package.
The MAX1257/MAX1258 are available in 48-pin TQFN
package. All devices are specified over the
-40°C to +85°C temperature range.
Applications
Controls for Optical Components
Base-Station Control Loops
System Supervision and Control
Data-Acquisition Systems
Features
o12-Bit, 225ksps ADC
Analog Multiplexer with True-Differential
Track/Hold (T/H)
16 Single-Ended Channels or 8 Differential
Channels (Unipolar or Bipolar)
(MAX1257/MAX1258)
Eight Single-Ended Channels or Four Differential
Channels (Unipolar or Bipolar) (MAX1220)
Excellent Accuracy: ±0.5 LSB INL, ±0.5 LSB DNL
o12-Bit, Octal, 2µs Settling DAC
Ultra-Low Glitch Energy (4nV•s)
Power-Up Options from Zero Scale or Full Scale
Excellent Accuracy: ±0.5 LSB INL
oInternal Reference or External Single-Ended/
Differential Reference
Internal Reference Voltage 2.5V or 4.096V
oInternal ±1°C Accurate Temperature Sensor
oOn-Chip FIFO Capable of Storing 16 ADC
Conversion Results and One Temperature Result
oOn-Chip Channel-Scan Mode and Internal
Data-Averaging Features
oAnalog Single-Supply Operation
+2.7V to +3.6V or +4.75V to +5.25V
oDigital Supply: +2.7V to AVDD
o25MHz, SPI/QSPI/MICROWIRE Serial Interface
oAutoShutdown Between Conversions
oLow-Power ADC
2.5mA at 225ksps
22µA at 1ksps
0.2µA at Shutdown
oLow-Power DAC: 1.5mA
oEvaluation Kit Available (Order MAX1258EVKIT)
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
________________________________________________________________
Maxim Integrated Products
1
19-3295; Rev 7; 2/12
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Note: All devices are specified over the -40°C to +85°C operating range.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
EP = Exposed pad.
**
Number of resolution bits refers to both DAC and ADC.
EVALUATION KIT
AVAILABLE
Pin Configurations appear at end of data sheet.
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corp.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
Ordering Information/Selector Guide
PART PIN-PACKAGE
REF
VOLTAGE
(V)
ANALOG
SUPPLY
VOLTAGE (V)
RESOLUTION
BITS**
ADC
CHANNELS
DAC
CHANNELS GPIOs
MAX1220BETX+ 36 Thin QFN-EP* 4.096 4.75 to 5.25 12 8 8 4
MAX1257BETM+ 48 Thin QFN-EP* 2.5 2.7 to 3.6 12 16 8 12
MAX1258BETM+ 48 Thin QFN-EP* 4.096 4.75 to 5.25 12 16 8 12
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VAVDD = VDVDD = 2.7V to 3.6V (MAX1257), external reference VREF = 2.5V (MAX1257), VAVDD = 4.75V to 5.25V, VDVDD = 2.7V to VAVDD
(MAX1220/MAX1258), external reference VREF = 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C,
unless otherwise noted. Typical values are at VAVDD = VDVDD = 3V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), TA= +25°C.
Outputs are unloaded, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD to AGND ........................................................-0.3V to +6V
DGND to AGND.....................................................-0.3V to +0.3V
DVDD to AVDD......................................................-3.0V to +0.3V
Digital Inputs to DGND.............................................-0.3V to +6V
Digital Outputs to DGND ........................-0.3V to (VDVDD + 0.3V)
Analog Inputs, Analog Outputs and REF_
to AGND .............................................-0.3V to (VAVDD + 0.3V)
Maximum Current into Any Pin (except AGND, DGND, AVDD,
DVDD, and OUT_)...........................................................50mA
Maximum Current into OUT_.............................................100mA
Continuous Power Dissipation (multilayer board, TA= +70°C)
36-Pin TQFN (6mm x 6mm)
(derate 35.7mW/°C above +70°C)......................2857.1mW
48-Pin TQFN (7mm x 7mm)
(derate 40mW/°C above +70°C)............................3200mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-60°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature ...................................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ADC
DC ACCURACY (Note 1)
Resolution 12 Bits
Integral Nonlinearity INL ±0.5 ±1.0 LSB
Differential Nonlinearity DNL ±0.5 ±1.0 LSB
Offset Error ±1 ±4.0 LSB
Gain Error (Note 2) ±0.1 ±4.0 LSB
Gain Temperature Coefficient ±0.8 ppm/°C
Channel-to-Channel Offset ±0.1 LSB
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, VIN = 2.5VP-P (MAX1257), VIN = 4.096VP-P (MAX1220/MAX1258),
225ksps, fCLK = 3.6MHz)
Signal-to-Noise Plus Distortion SINAD 70 dB
Total Harmonic Distortion
(Up to the Fifth Harmonic) THD -76 dBc
Spurious-Free Dynamic Range SFDR 72 dBc
Intermodulation Distortion IMD fIN1 = 9.9kHz, fIN2 = 10.2kHz 76 dBc
Full-Linear Bandwidth SINAD > 70dB 100 kHz
Full-Power Bandwidth -3dB point 1 MHz
CONVERSION RATE (Note 3)
External reference 0.8 µs
Power-Up Time tPU Internal reference (Note 4) 218
C onver si on
cl ock
cycl es
Note: If the package power dissipation is not exceeded, one output at a time may be shorted to AVDD, DVDD, AGND, or DGND
indefinitely.
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 2.7V to 3.6V (MAX1257), external reference VREF = 2.5V (MAX1257), VAVDD = 4.75V to 5.25V, VDVDD = 2.7V to VAVDD
(MAX1220/MAX1258), external reference VREF = 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C,
unless otherwise noted. Typical values are at VAVDD = VDVDD = 3V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), TA= +25°C.
Outputs are unloaded, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Acquisition Time tACQ (Note 5) 0.6 µs
Internally clocked 5.5
Conversion Time tCONV Externally clocked 3.6 µs
External Clock Frequency fCLK Externally clocked conversion (Note 5) 0.1 3.6 MHz
Duty Cycle 40 60 %
Aperture Delay 30 ns
Aperture Jitter < 50 ps
ANALOG INPUTS
Unipolar 0 VREF
Input Voltage Range (Note 6) Bipolar -VREF/2 +VREF/2 V
Input Leakage Current ±0.01 ±1 µA
Input Capacitance 24 pF
INTERNAL TEMPERATURE SENSOR
TA = +25°C ±0.7
Measurement Error (Notes 5, 7) TA = TMIN to TMAX ±1.0 ±3.0
°C
Temperature Resolution 1/8 °C/LSB
INTERNAL REFERENCE
MAX1257 2.482 2.50 2.518
REF1 Output Voltage (Note 8) MAX1220/MAX1258 4.066 4.096 4.126
V
REF1 Voltage Temperature
Coefficient TCREF ±30 ppm/°C
REF1 Output Impedance 6.5 k
VREF = 2.5V 0.39
REF1 Short-Circuit Current VREF = 4.096V 0.63 mA
EXTERNAL REFERENCE
REF1 Input Voltage Range VREF1 REF mode 11 (Note 4) 1 VAVDD
+ 0.05 V
REF mode 01 1 VAVDD
+ 0.05
REF2 Input Voltage Range
(Note 4) VREF2
REF mode 11 0 1
V
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 2.7V to 3.6V (MAX1257), external reference VREF = 2.5V (MAX1257), VAVDD = 4.75V to 5.25V, VDVDD = 2.7V to VAVDD
(MAX1220/MAX1258), external reference VREF = 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C,
unless otherwise noted. Typical values are at VAVDD = VDVDD = 3V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), TA= +25°C.
Outputs are unloaded, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VREF = 2.5V (MAX1257), fSAMPLE = 25 80
VREF = 4.096V (MAX1220/MAX1258),
fSAMPLE = 225ksps 40 80
REF1 Input Current (Note 9) IREF1
Acquisition between conversions ±0.01 ±1
µA
VREF = 2.5V (MAX1257), fSAMPLE = 25 80
VREF = 4.096V (MAX1220/MAX1258),
fSAMPLE = 225ksps 40 80
REF2 Input Current IREF2
Acquisition between conversions ±0.01 ±1
µA
DAC
DC ACCURACY (Note 10)
Resolution 12 Bits
Integral Nonlinearity INL ±0.5 ±4 LSB
Differential Nonlinearity DNL Guaranteed monotonic ±1.0 LSB
Offset Error VOS (Note 8) ±3 ±10 mV
Offset-Error Drift ±10 ppm of
FS/°C
Gain Error GE (Note 8) ±5 ±10 LSB
Gain Temperature Coefficient ±8 ppm of
FS/°C
DAC OUTPUT
No load 0.02 VAVDD -
0.02
Output-Voltage Range
10k load to either rail 0.1 VAVDD -
0.1
V
DC Output Impedance 0.5
Capacitive Load (Note 11) 1 nF
VAVDD = 2.7V, VREF = 2.5V (MAX1257),
gain error < 1% 2000
Resistive Load to AGND RLVAVDD = 4.75V, VREF = 4.096V
(MAX1220/MAX1258), gain error < 2% 500
From power-down mode, VAVDD = 5V 25
Wake-Up Time (Note 12) From power-down mode, VAVDD = 2.7V 21 µs
1k Output Termination Programmed in from power-down mode 1 k
100k Output Termination At wake-up or programmed in
power-down mode 100 k
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 2.7V to 3.6V (MAX1257), external reference VREF = 2.5V (MAX1257), VAVDD = 4.75V to 5.25V, VDVDD = 2.7V to VAVDD
(MAX1220/MAX1258), external reference VREF = 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C,
unless otherwise noted. Typical values are at VAVDD = VDVDD = 3V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), TA= +25°C.
Outputs are unloaded, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC PERFORMANCE (Notes 5, 13)
Output-Voltage Slew Rate SR Positive and negative 3 V/µs
Output-Voltage Settling Time tS To 1 LSB, 400 - C00 hex (Note 7) 2 5 µs
Digital Feedthrough Code 0, all digital inputs from 0 to
VDVDD 0.5 nV•s
Major Code Transition Glitch
Impulse Between codes 2047 and 2048 4 nV•s
From VREF 660
Output Noise (0.1Hz to 50MHz) Using internal reference 720 µVP-P
From VREF 260
Output Noise (0.1Hz to
500kHz) Using internal reference 320 µVP-P
DAC-to-DAC Transition
Crosstalk 0.5 nV•s
INTERNAL REFERENCE
MAX1257 2.482 2.5 2.518
REF1 Output Voltage (Note 8) MAX1220/MAX1258 4.066 4.096 4.126
V
REF1 Temperature Coefficient TCREF ±30 ppm/°C
VREF = 2.5V 0.39
REF1 Short-Circuit Current VREF = 4.096V 0.63 mA
EXTERNAL-REFERENCE INPUT
REF1 Input Voltage Range VREF1 REF modes 01, 10, and 11 (Note 4) 0.7 VAVDD V
REF1 Input Impedance RREF1 70 100 130 k
DIGITAL INTERFACE
DIGITAL INPUTS (SCLK, DIN, CS,CNVST,LDAC)
Input-Voltage High VIH V
DVDD = 2.7V to 5.25V 2.4 V
VDVDD = 3.6V to 5.25V 0.8
Input-Voltage Low VIL VDVDD = 2.7V to 3.6V 0.6 V
Input Leakage Current IL ±0.01 ±10 µA
Input Capacitance CIN 15 pF
DIGITAL OUTPUT (DOUT) (Note 14)
Output-Voltage Low VOL I
SINK = 2mA 0.4 V
Output-Voltage High VOH I
SOURCE = 2mA VDVDD -
0.5 V
Three-State Leakage Current ±10 µA
Three-State Output
Capacitance COUT 15 pF
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 2.7V to 3.6V (MAX1257), external reference VREF = 2.5V (MAX1257), VAVDD = 4.75V to 5.25V, VDVDD = 2.7V to VAVDD
(MAX1220/MAX1258), external reference VREF = 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C,
unless otherwise noted. Typical values are at VAVDD = VDVDD = 3V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), TA= +25°C.
Outputs are unloaded, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL OUTPUT (EOC) (Note 14)
Output-Voltage Low VOL I
SINK = 2mA 0.4 V
Output-Voltage High VOH I
SOURCE = 2mA VDVDD -
0.5 V
Three-State Leakage Current ±10 µA
Three-State Output
Capacitance COUT 15 pF
DIGITAL OUTPUTS (GPIO_) (Note 14)
ISINK = 2mA 0.4
GPIOB_, GPIOC_ Output-
Voltage Low ISINK = 4mA 0.8 V
GPIOB_, GPIOC_ Output-
Voltage High I
SOURCE = 2mA VDVDD -
0.5 V
GPIOA_ Output-Voltage Low ISINK = 15mA 0.8 V
GPIOA_ Output-Voltage High ISOURCE = 15mA VDVDD -
0.8 V
Three-State Leakage Current ±10 µA
Three-State Output
Capacitance COUT 15 pF
POWER REQUIREMENTS (Note 15)
Digital Positive-Supply Voltage DVDD 2.7 VAVDD V
Idle, all blocks shut down 0.2 4 µA
Digital Positive-Supply Current DIDD Only ADC on, external reference 1 mA
MAX1257 2.7 3.6
Analog Positive-Supply Voltage AVDD MAX1220/MAX1258 4.75 5.25
V
Idle, all blocks shut down 0.2 2 µA
fSAMPLE = 225ksps 2.8 4.2
Only ADC on,
external reference fSAMPLE = 100ksps 2.6
Analog Positive-Supply Current AIDD
All DACs on, no load, internal reference 1.5 4
mA
MAX1257, VAVDD = 2.7V -77
REF1 Positive-Supply
Rejection PSRR MAX1220/MAX1258, VAVDD = 4.75V -80 dB
MAX1257, VAVDD = 2.7V to ±0.1 ±0.5
DAC Positive-Supply Rejection PSRD
Output
code =
FFFhex
MAX1220/MAX1258,
VAVDD = 4.75V to 5.25V ±0.1 ±0.5
mV
MAX1257, VAVDD = 2.7V to ±0.06 ±0.5
ADC Positive-Supply Rejection PSRA
Full-
scale
input
MAX1220/MAX1258,
VAVDD = 4.75V to 5.25V ±0.06 ±0.5
mV
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
_______________________________________________________________________________________ 7
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 2.7V to 3.6V (MAX1257), external reference VREF = 2.5V (MAX1257), VAVDD = 4.75V to 5.25V, VDVDD = 2.7V to VAVDD
(MAX1220/MAX1258), external reference VREF = 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C,
unless otherwise noted. Typical values are at VAVDD = VDVDD = 3V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), TA= +25°C.
Outputs are unloaded, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS (Figures 6–13)
SCLK Clock Period tCP 40 ns
SCLK Pulse-Width High tCH 40/60 duty cycle 16 ns
SCLK Pulse-Width Low tCL 60/40 duty cycle 16 ns
GPIO Output R ise/Fall After
CS Rise tGOD C
LOAD = 20pF 100 ns
GPIO Input Setup Before CS
Fall tGSU 0 ns
LDAC Pulse Width tLDACPWL 20 ns
CLOAD = 20pF, SLOW = 0 1.8 12.0
SCLK Fall to DOUT Transition
(Note 16) tDOT CLOAD = 20pF, SLOW = 1 10 40 ns
CLOAD = 20pF, SLOW = 0 1.8 12.0
SCLK Rise to DOUT Transition
(Notes 16, 17) tDOT CLOAD = 20pF, SLOW = 1 10 40 ns
CS Fall to SCLK Fall Setup Time tCSS 10 ns
SCLK Fall to CS Rise Hold Time tCSH 0 2000 ns
DIN to SCLK Fall Setup Time tDS 10 ns
DIN to SCLK Fall Hold Time tDH 0 ns
CS Pulse-Width High tCSPWH 50 ns
CS Rise to DOUT Disable tDOD C
LOAD = 20pF 25 ns
CS Fall to DOUT Enable tDOE C
LOAD = 20pF 1.5 25.0 ns
EOC Fall to CS Fall tRDS 30 ns
CKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference on
(Note 18)
65
CKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference
initially off
140
CKSEL = 01 (voltage conversion) 9
CKSEL = 10 (voltage conversion),
internal reference on (Note 18) 9
CS or CNVST Rise to EOC
Fall—Internally Clocked
Conversion Time
tDOV
CKSEL = 10 (voltage conversion),
internal reference initially off 80
µs
CKSEL = 00, CKSEL = 01 (temp sense) 40 ns
CNVST Pulse Width tCSW CKSEL = 01 (voltage conversion) 1.4 µs
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
8 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 2.7V to 3.6V (MAX1257), external reference VREF = 2.5V (MAX1257), VAVDD = 4.75V to 5.25V, VDVDD = 2.7V to VAVDD
(MAX1220/MAX1258), external reference VREF = 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C,
unless otherwise noted. Typical values are at VAVDD = VDVDD = 3V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), TA= +25°C.
Outputs are unloaded, unless otherwise noted.)
Note 1: Tested at VDVDD = VAVDD = +2.7V (MAX1257), VDVDD = +2.7V, VAVDD = +5.25V (MAX1220/MAX1258).
Note 2: Offset nulled.
Note 3: No bus activity during conversion. Conversion time is defined as the number of conversion clock cycles multiplied by the
clock period.
Note 4: See Table 5 for reference-mode details.
Note 5: Not production tested. Guaranteed by design.
Note 6: See the
ADC/DAC References
section.
Note 7: Fast automated test, excludes self-heating effects.
Note 8: Specified over the -40°C to +85°C temperature range.
Note 9: REFSEL[1:0] = 00 and when DACs are not powered up.
Note 10: DAC linearity, gain, and offset measurements are made between codes 115 and 3981.
Note 11: The DAC buffers are guaranteed by design to be stable with a 1nF load.
Note 12: Time required by the DAC output to power up and settle within 1 LSB in the external reference mode.
Note 13: All DAC dynamic specifications are valid for a load of 100pF and 10kΩ.
Note 14: Only one digital output (either DOUT, EOC, or the GPIOs) can be indefinitely shorted to either supply at one time.
Note 15: All digital inputs at either VDVDD or DGND. VDVDD should not exceed VAVDD.
Note 16: See the
Reset Register
section and Table 9 for details on programming the SLOW bit.
Note 17: Clock mode 11 only.
Note 18: First conversion after reference power-up is always timed as if the internal reference was initially off to ensure the internal
reference has settled. Subsequent conversions are timed as shown.
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
_______________________________________________________________________________________ 9
Typical Operating Characteristics
(VAVDD = VDVDD = 3V (MAX1257), external VREF = 2.5V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), external VREF =
4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF,
TA= +25°C, unless otherwise noted.)
0
0.1
0.3
0.2
0.4
0.5
ANALOG SHUTDOWN CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1220 toc01
SUPPLY VOLTAGE (V)
ANALOG SHUTDOWN CURRENT (µA)
4.750 5.0004.875 5.125 5.250
MAX1220/MAX1258
0
0.1
0.3
0.2
0.4
0.5
ANALOG SHUTDOWN CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1220 toc02
SUPPLY VOLTAGE (V)
MAX1257
ANALOG SHUTDOWN CURRENT (µA)
2.7 3.33.0 3.6
0.4
0.3
0.2
0.1
0
-40 10-15 35 60 85
ANALOG SHUTDOWN CURRENT
vs. TEMPERATURE
MAX1220 toc03
TEMPERATURE (°C)
ANALOG SHUTDOWN CURRENT (µA)
MAX1220/MAX1258
MAX1257
ADC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
MAX1220 toc04
OUTPUT CODE
INTEGRAL NONLINEARITY (LSB)
307220481024
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
-1.00
0 4096
MAX1220/MAX1258
ADC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
MAX1220 toc05
OUTPUT CODE
INTEGRAL NONLINEARITY (LSB)
307220481024
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
-1.00
0 4096
MAX1257
ADC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
MAX1220 toc06
OUTPUT CODE
DIFFERENTIAL NONLINEARITY (LSB)
307220481024
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
-1.00
0 4096
MAX1220/MAX1258
ADC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
MAX1220 toc07
OUTPUT CODE
DIFFERENTIAL NONLINEARITY (LSB)
307220481024
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
-1.00
0 4096
MAX1257
0
0.2
0.6
0.4
0.8
1.0
ADC OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX1220 toc08
SUPPLY VOLTAGE (V)
OFFSET ERROR (LSB)
4.750 5.0004.875 5.125 5.250
MAX1220/MAX1258
0
0.2
0.6
0.4
0.8
1.0
ADC OFFSET ERROR
vs. ANALOG SUPPLY VOLATGE
MAX1220 toc09
SUPPLY VOLTAGE (V)
MAX1257
OFFSET ERROR (LSB)
2.7 3.33.0 3.6
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
10 ______________________________________________________________________________________
2
1
0
-1
-2
-40 10-15 356085
ADC GAIN ERROR
vs. TEMPERATURE
MAX1220 toc13
TEMPERATURE (°C)
GAIN ERROR (LSB)
MAX1257
MAX1220/MAX1258
ADC EXTERNAL REFERENCE
INPUT CURRENT vs. SAMPLING RATE
MAX1220 toc14
SAMPLING RATE (ksps)
ADC EXTERNAL REFERENCE INPUT CURRENT (µA)
25020015010050
10
20
30
40
50
60
0
0 300
MAX1220/MAX1258
MAX1257
ANALOG SUPPLY CURRENT
vs. SAMPLING RATE
MAX1220 toc15
SAMPLING RATE (ksps)
ANALOG SUPPLY CURRENT (mA)
25020015010050
0.5
1.0
1.5
2.0
2.5
3.0
0
0300
MAX1220/MAX1258
MAX1257
1.90
1.94
1.92
1.98
1.96
2.02
2.00
2.04
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1220 toc16
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
4.750 4.875 5.000 5.125 5.250
MAX1220/MAX1258
1.90
1.94
1.92
1.98
1.96
2.02
2.00
2.04
2.7 3.0 3.3 3.6
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1220 toc17
SUPPLY VOLTAGE (V)
MAX1257
SUPPLY CURRENT (mA)
1.88
1.92
1.90
1.96
1.94
2.00
1.98
2.02
-40 10-15 35 60 85
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
MAX1220 toc18
TEMPERATURE (°C)
ANALOG SUPPLY CURRENT (mA)
MAX1257
MAX1220/MAX1258
2
1
0
-1
-2
-40 10-15 356085
ADC OFFSET ERROR
vs. TEMPERATURE
MAX1220 toc10
TEMPERATURE (°C)
OFFSET ERROR (LSB)
MAX1257
MAX1220/MAX1258
1.0
0.5
0
-0.5
-1.0
4.750 5.0004.875 5.125 5.250
ADC GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX1220 toc11
SUPPLY VOLTAGE (V)
GAIN ERROR (LSB)
MAX1220/MAX1258
1.0
0.5
0
-0.5
-1.0
2.7 3.33.0 3.6
ADC GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX1220 toc12
SUPPLY VOLTAGE (V)
MAX1257
GAIN ERROR (LSB)
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = 3V (MAX1257), external VREF = 2.5V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), external VREF =
4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF,
TA= +25°C, unless otherwise noted.)
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
______________________________________________________________________________________ 11
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = 3V (MAX1257), external VREF = 2.5V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), external VREF =
4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF,
TA= +25°C, unless otherwise noted.)
DAC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
MAX1220 toc19
OUTPUT CODE
INTEGRAL NONLINEARITY (LSB)
307220481024
-1.0
-0.5
0
0.5
1.0
1.5
-1.5
0 4096
MAX1220/MAX1258
DAC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
MAX1220 toc20
OUTPUT CODE
INTEGRAL NONLINEARITY (LSB)
307220481024
-1.0
-0.5
0
0.5
1.0
1.5
-1.5
0 4096
MAX1257
DAC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
MAX1220 toc21
OUTPUT CODE
DIFFERENTIAL NONLINEARITY (LSB)
2059205620532050
-0.2
0
0.2
0.4
-0.4
2047 2062
MAX1220/MAX1258
DAC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
MAX1220 toc22
OUTPUT CODE
DIFFERENTIAL NONLINEARITY (LSB)
2059205620532050
-0.2
0
0.2
0.4
-0.4
2047 2062
MAX1257
0.2
0.4
0.8
0.6
1.0
1.2
DAC FULL-SCALE ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX1220 toc23
SUPPLY VOLTAGE (V)
DAC FULL-SCALE ERROR (LSB)
4.750 5.0004.875 5.125 5.250
MAX1220/MAX1258
EXTERNAL REFERENCE = 4.096V
0.2
0.4
0.8
0.6
1.0
1.2
DAC FULL-SCALE ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX1220 toc24
SUPPLY VOLTAGE (V)
DAC FULL-SCALE ERROR (LSB)
2.7 3.33.0 3.6
MAX1257
EXTERNAL REFERENCE = 2.5V
-6
-4
-2
0
2
4
6
8
10
-40 -15 10 35 60 85
DAC FULL-SCALE ERROR
vs. TEMPERATURE
MAX1220 toc25
TEMPERATURE (°C)
DAC FULL-SCALE ERROR (LSB)
MAX1220/MAX1258
EXTERNAL
REFERENCE = 4.096V
INTERNAL
REFERENCE
-6
-4
-2
0
2
4
6
8
10
-40 -15 10 35 60 85
DAC FULL-SCALE ERROR
vs. TEMPERATURE
MAX1220 toc26
TEMPERATURE (°C)
DAC FULL-SCALE ERROR (LSB)
MAX1257
EXTERNAL
REFERENCE = 2.5V
INTERNAL
REFERENCE
DAC FULL-SCALE ERROR
vs. REFERENCE VOLTAGE
MAX1220 toc27
REFERENCE VOLTAGE (V)
DAC FULL-SCALE ERROR (LSB)
431 2
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
-1.00
05
MAX1220/MAX1258
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
12 ______________________________________________________________________________________
DAC FULL-SCALE ERROR
vs. REFERENCE VOLTAGE
MAX1220 toc28
REFERENCE VOLTAGE (V)
DAC FULL-SCALE ERROR (LSB)
2.0 2.51.50.5 1.0
-6
-5
-4
-3
-2
-1
0
-7
03.0
MAX1257
DAC FULL-SCALE ERROR
vs. LOAD CURRENT
MAX1220 toc29
LOAD CURRENT (mA)
DAC FULL-SCALE ERROR (LSB)
252015105
-10
-5
0
5
-15
030
MAX1220/MAX1258
DAC FULL-SCALE ERROR
vs. LOAD CURRENT
MAX1220 toc30
LOAD CURRENT (mA)
DAC FULL-SCALE ERROR (LSB)
2.52.01.51.00.5
-10
-5
0
5
-15
0 3.0
MAX1257
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = 3V (MAX1257), external VREF = 2.5V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), external VREF =
4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF,
TA= +25°C, unless otherwise noted.)
4.12
4.11
4.10
4.09
4.08
-40 10-15 356085
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1220 toc31
TEMPERATURE (°C)
INETRNAL REFERENCE VOLTAGE (V)
MAX1220/MAX1258
2.52
2.51
2.50
2.49
2.48
-40 10-15 356085
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1220 toc32
TEMPERATURE (°C)
INTERNAL REFERENCE VOLTAGE (V)
MAX1257
24.84
24.88
24.86
24.92
24.90
24.94
24.96
4.750 5.0004.875 5.125 5.250
ADC REFERENCE SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1220 toc33
SUPPLY VOLTAGE (V)
ADC REFERENCE SUPPLY CURRENT (µA)
MAX1220/MAX1258
25.1
25.0
24.9
24.8
24.7
2.7 3.33.0 3.6
ADC REFERENCE SUPPLY CURRENT
vs. ANALOG SUPPLY VOLATAGE
MAX1220 toc34
SUPPLY VOLTAGE (V)
MAX1257
ADC REFERENCE SUPPLY CURRENT (µA)
40.5
40.6
40.8
40.7
40.9
41.0
-40 10-15 35 60 85
MAX1220 toc35
TEMPERATURE (°C)
ADC REFERENCE SUPPLY CURRENT (µA)
ADC REFERENCE SUPPLY CURRENT
vs. TEMPERATURE
MAX1220/MAX1258
EXTERNAL REFERENCE = 4.096V
25.1
25.0
24.9
24.8
24.7
-40 10-15 356085
ADC REFERENCE SUPPLY CURRENT
vs. TEMPERATURE
MAX1220 toc36
TEMPERATURE (°C)
ADC REFERENCE SUPPLY CURRENT (µA)
MAX1257, EXTERNAL REFERENCE = 2.5V
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
______________________________________________________________________________________ 13
ADC FFT PLOT
MAX1220 toc37
ANALOG INPUT FREQUENCY (kHz)
AMPLITUDE (dB)
15010050
-140
-120
-100
-80
-60
-40
-20
0
-160
0 200
fSAMPLE = 32.768kHz
fANALOG_N = 10.080kHz
fCLK = 5.24288MHz
SINAD = 71.27dBc
SNR = 71.45dBc
THD = 85.32dBc
SFDR = 87.25dBc
ADC IMD PLOT
MAX1220 toc38
ANALOG INPUT FREQUENCY (kHz)
AMPLITUDE (dB)
15010050
-140
-120
-100
-80
-60
-40
-20
0
-160
0 200
fCLK = 5.24288MHz
fIN1 = 9.0kHz
fIN2 = 11.0kHz
AIN = -6dBFS
IMD = 82.99dBc
ADC CROSSTALK PLOT
MAX1220 toc39
ANALOG INPUT FREQUENCY (kHz)
AMPLITUDE (dB)
15010050
-140
-120
-100
-80
-60
-40
-20
0
-160
0200
fCLK = 5.24288MHz
fIN1 = 10.080kHz
fIN2 = 8.0801kHz
SNR = 72.00dBc
THD = 85.24dBc
ENOB = 11.65 BITS
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENT
MAX1220 toc40
OUTPUT CURRENT (mA)
DAC OUTPUT VOLTAGE (V)
60300
2.01
2.02
2.03
2.04
2.05
2.06
2.07
2.08
2.00
-30 90
DAC OUTPUT = MIDSCALE
MAX1220/MAX1258
SINKING
SOURCING
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENT
MAX1220 toc41
OUTPUT CURRENT (mA)
DAC OUTPUT VOLTAGE (V)
20100-20 -10
1.22
1.23
1.24
1.25
1.26
1.27
1.28
1.29
1.21
-30 30
DAC OUTPUT = MIDSCALE
MAX1257
SINKING
SOURCING
GPIO OUTPUT VOLTAGE
vs. SOURCE CURRENT
MAX1220 toc42
SOURCE CURRENT (mA)
GPIO OUTPUT VOLTAGE (V)
80604020
1
2
3
4
5
0
0100
MAX1220/MAX1258
GPIOA0–A3 OUTPUTS
GPIOB0–B3,
C0–C3 OUTPUTS
GPIO OUTPUT VOLTAGE
vs. SOURCE CURRENT
MAX1220 toc43
SOURCE CURRENT (mA)
GPIO OUTPUT VOLTAGE (V)
80604020
0.5
1.0
1.5
2.0
2.5
3.0
0
0 100
MAX1257
GPIOA0–A3 OUTPUTS
GPIOB0–B3, C0–C3
OUTPUTS
GPIO OUTPUT VOLTAGE
vs. SINK CURRENT
MAX1220 toc44
SINK CURRENT (mA)
GPIO OUTPUT VOLTAGE (mV)
80604020
300
600
900
1200
1500
0
0 100
MAX1220/MAX1258
GPIOA0–A3 OUTPUTS
GPIOB0–B3, C0–C3
OUTPUTS
GPIO OUTPUT VOLTAGE
vs. SINK CURRENT
MAX1220 toc45
SINK CURRENT (mA)
GPIO OUTPUT VOLTAGE (mV)
40 50302010
300
600
900
1200
1500
0
060
MAX1257
GPIOA0–A3 OUTPUTS
GPIOB0–B3, C0–C3
OUTPUTS
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = 3V (MAX1257), external VREF = 2.5V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), external VREF =
4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF,
TA= +25°C, unless otherwise noted.)
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
14 ______________________________________________________________________________________
TEMPERATURE SENSOR ERROR
vs. TEMPERATURE
MAX1220 toc46
TEMPERATURE (°C)
TEMPERATURE SENSOR ERROR (°C)
6035-15 10
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
-1.00
-40 85
DAC-TO-DAC CROSSTALK
RLOAD = 10kΩ, CLOAD = 100pF
MAX1220 toc47
100µs/div
VOUTA
1V/div
VOUTB
10mV/div
AC-COUPLED
MAX1257
DAC-TO-DAC CROSSTALK
RLOAD = 10kΩ, CLOAD = 100pF
MAX1220 toc48
100µs/div
VOUTA
2V/div
VOUTB
10mV/div
AC-COUPLED
MAX1220/MAX1258
DYNAMIC RESPONSE RISE TIME
RLOAD = 10kΩ, CLOAD = 100pF
MAX1220 toc49
1µs/div
VOUT_
1V/div
CS
1V/div
MAX1257
DYNAMIC RESPONSE RISE TIME
RLOAD = 10kΩ, CLOAD = 100pF
MAX1220 toc50
1µs/div
VOUT_
2V/div
CS
2V/div
MAX1220/MAX1258
DYNAMIC RESPONSE FALL TIME
RLOAD = 10kΩ, CLOAD = 100pF
MAX1220 toc51
1µs/div
VOUT_
1V/div
CS
1V/div
MAX1257
DYNAMIC RESPONSE FALL TIME
RLOAD = 10kΩ, CLOAD = 100pF
MAX1220 toc52
1µs/div
VOUT_
2V/div
CS
2V/div
MAX1220/MAX1258
MAJOR CARRY TRANSITION
RLOAD = 10kΩ, CLOAD = 100pF
MAX1220 toc53
1µs/div
VOUT_
10mV/div
AC-COUPLED
CS
1V/div
MAX1257
MAJOR CARRY TRANSITION
RLOAD = 10kΩ, CLOAD = 100pF
MAX1220 toc54
1µs/div
VOUT_
20mV/div
AC-COUPLED
CS
2V/div
MAX1220/MAX1258
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = 3V (MAX1257), external VREF = 2.5V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), external VREF =
4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF,
TA= +25°C, unless otherwise noted.)
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
______________________________________________________________________________________ 15
DAC DIGITAL FEEDTHROUGH RLOAD = 10kΩ,
CLOAD = 100pF, CS = HIGH, DIN = LOW
MAX1220 toc55
200ns/div
VOUT_
100mV/div
AC-COUPLED
SCLK
1V/div
MAX1257
DAC DIGITAL FEEDTHROUGH RLOAD = 10kΩ,
CLOAD = 100pF, CS = HIGH, DIN = LOW
MAX1220 toc56
200ns/div
VOUT_
100mV/div
AC-COUPLED
SCLK
2V/div
MAX1220/MAX1258
NEGATIVE FULL-SCALE SETTLING TIME
RLOAD = 10kΩ, CLOAD = 100pF
MAX1220 toc57
1µs/div
VOUT_
1V/div
MAX1257
VLDAC
1V/div
NEGATIVE FULL-SCALE SETTLING TIME
RLOAD = 10kΩ, CLOAD = 100pF
MAX1220 toc58
2µs/div
VOUT_
2V/div
MAX1220/MAX1258
VLDAC
2V/div
POSITIVE FULL-SCALE SETTLING TIME
RLOAD = 10kΩ, CLOAD = 100pF
MAX1220 toc59
1µs/div
VOUT_
1V/div
MAX1257
VLDAC
1V/div
POSITIVE FULL-SCALE SETTLING TIME
RLOAD = 10kΩ, CLOAD = 100pF
MAX1220 toc60
1µs/div
VOUT_
2V/div
MAX1220/MAX1258
VLDAC
2V/div
ADC REFERENCE FEEDTHROUGH
RLOAD = 10kΩ, CLOAD = 100pF
MAX1220 toc61
200µs/div
VDAC-OUT
10mV/div
AC-COUPLED
MAX1257
VREF2
1V/div
ADC REFERENCE SWITCHING
ADC REFERENCE FEEDTHROUGH
RLOAD = 10kΩ, CLOAD = 100pF
MAX1220 toc62
200µs/div
VDAC-OUT
2mV/div
AC-COUPLED
MAX1220/MAX1258
VREF2
2V/div
ADC REFERENCE SWITCHING
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = 3V (MAX1257), external VREF = 2.5V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), external VREF =
4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF,
TA= +25°C, unless otherwise noted.)
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
16 ______________________________________________________________________________________
Pin Description
PIN
MAX1220 MAX1257
MAX1258
NAME FUNCTION
1, 2 — GPIOA0, GPIOA1 General-Purpose I/O A0, A1. GPIOA0, A1 can sink and source 15mA.
3 4 EOC Active-Low End-of-Conversion Output. Data is valid after the falling edge
of EOC.
4 7 DVDD
Digital Positive-Power Input. Bypass DVDD to DGND with a 0.1µF
capacitor.
5 8 DGND Digital Ground. Connect DGND to AGND.
6 9 DOUT
Serial-Data Output. Data is clocked out on the falling edge of the SCLK
clock in modes 00, 01, and 10. Data is clocked out on the rising edge of
the SCLK clock in mode 11. It is high impedance when CS is high.
7 10 SCLK
Serial-Clock Input. Clocks data in and out of the serial interface. (Duty
cycle must be 40% to 60%.) See Table 5 for details on programming the
clock mode.
8 11 DIN
Serial-Data Input. DIN data is latched into the serial interface on the
falling edge of SCLK.
9–12, 16–19 12–15,
22–25 OUT0–OUT7 DAC Outputs
13 18 AVDD
Positive Analog Power Input. Bypass AVDD to AGND with a 0.1µF
capacitor.
14 19 AGND Analog Ground
15, 23, 32, 33 — N.C. No Connection. Not internally connected.
20 26 LDAC
Active-Low Load DAC. LDAC is an asynchronous active-low input that
updates the DAC outputs. Drive LDAC low to make the DAC registers
transparent.
21 27 CS Active-Low Chip-Select Input. When CS is low, the serial interface is
enabled. When CS is high, DOUT is high impedance.
22 28 RES_SEL
Reset Select. Select DAC wake-up mode. Set RES_SEL low to wake up
the DAC outputs with a 100k resistor to AGND or set RES_SEL high to
wake up the DAC outputs with a 100k resistor to VREF. Set RES_SEL
high to power up the DAC input register to FFFh. Set RES_SEL low to
power up the DAC input register to 000h.
24, 25 — GPIOC0, GPIOC1 General-Purpose I/O C0, C1. GPIOC0, C1 can sink 4mA and source 2mA.
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
______________________________________________________________________________________ 17
Pin Description (continued)
PIN
MAX1220 MAX1257
MAX1258
NAME FUNCTION
26 35 REF1
Reference 1 Input. Reference voltage; leave unconnected to use the
internal reference (2.5V for the MAX1257 or 4.096V for the
MAX1220/MAX1258). REF1 is the positive reference in ADC external
differential reference mode. Bypass REF1 to AGND with a 0.1µF
capacitor in external reference mode only. See the ADC/DAC
References section.
27–31, 34 — AIN0–AIN5 Analog Inputs
35 — REF2/AIN6
Reference 2 Input/Analog Input 6. See Table 5 for details on
programming the setup register. REF2 is the negative reference in the
ADC external differential reference mode.
36 — CNVST/AIN7 Active-Low Conversion-Start Input/Analog Input 7. See Table 5 for details
on programming the setup register.
— 1 CNVST/AIN15 Active-Low Conversion-Start Input/Analog Input 15. See Table 5 for
details on programming the setup register.
— 2, 3, 5, 6 GPIOA0–GPIOA3 General-Purpose I/O A0–A3. GPIOA0–GPIOA3 can sink and source 15mA.
—16, 17,
20, 21 GPIOB0–GPIOB3 General-Purpose I/O B0–B3. GPIOB0–GPIOB3 can sink 4mA and
source 2mA.
— 29–32 GPIOC0–GPIOC3
General-Purpose I/O C0–C3. GPIOC0–GPIOC3 can sink 4mA and
source 2mA.
— 33, 34, 36–47 AIN0–AIN13 Analog Inputs
— 48 REF2/AIN14
Reference 2 Input/Analog Input 14. See Table 5 for details on
programming the setup register. REF2 is the negative reference in the
ADC external differential reference mode.
— — EP
Exposed Pad. Must be externally connected to AGND. Do not use as a
ground connect.
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
18 ______________________________________________________________________________________
Detailed Description
The MAX1220/MAX1257/MAX1258 integrate a 12-bit,
multichannel, analog-to-digital converter (ADC), and a
12-bit, octal, digital-to-analog converter (DAC) in a sin-
gle IC. These devices also include a temperature sen-
sor and configurable GPIOs with a 25MHz
SPI-/QSPI-/MICROWIRE-compatible serial interface.
The ADC is available in 8 and 16 input-channel
versions. The octal DAC outputs settle within 2.0µs, and
the ADC has a 225ksps conversion rate.
All devices include an internal reference (2.5V or
4.096V) providing a well-regulated, low-noise reference
for both the ADC and DAC. Programmable reference
modes for the ADC and DAC allow the use of an inter-
nal reference, an external reference, or a combination
of both. Features such as an internal ±1°C accurate
temperature sensor, FIFO, scan modes, programmable
internal or external clock modes, data averaging, and
AutoShutdown allow users to minimize both power con-
sumption and processor requirements. The low glitch
energy (4nV•s) and low digital feedthrough (0.5nV•s) of
the integrated octal DACs make these devices ideal for
digital control of fast-response closed-loop systems.
These devices are guaranteed to operate with a supply
voltage from +2.7V to +3.6V (MAX1257) and from
+4.75V to +5.25V (MAX1220/MAX1258). These devices
consume 2.5mA at 225ksps throughput, only 22µA at
1ksps throughput, and under 0.2µA in the shutdown
mode. The MAX1257/MAX1258 feature 12 GPIOs while
the MAX1220 offers four GPIOs that can be configured
as inputs or outputs.
Figure 1 shows the MAX1257/MAX1258 functional dia-
gram. The MAX1220 only includes the GPIOA0,
GPIOA1 and GPIOC0, GPIOC1 block. The output-con-
ditioning circuitry takes the internal parallel data bus
and converts it to a serial data format at DOUT, with the
appropriate wake-up timing. The arithmetic logic unit
(ALU) performs the averaging function.
SPI-Compatible Serial Interface
The MAX1220/MAX1257/MAX1258 feature a serial inter-
face that is compatible with SPI and MICROWIRE
devices. For SPI, ensure the SPI bus master (typically a
microcontroller (µC)) runs in master mode so that it
generates the serial clock signal. Select the SCLK fre-
quency of 25MHz or less, and set the clock polarity
(CPOL) and phase (CPHA) in the µC control registers to
the same value. The MAX1220/MAX1257/MAX1258
operate with SCLK idling high or low, and thus operate
with CPOL = CPHA = 0 or CPOL = CPHA = 1. Set CS
low to latch any input data at DIN on the falling edge of
SCLK. Output data at DOUT is updated on the falling
edge of SCLK in clock modes 00, 01, and 10. Output
data at DOUT is updated on the rising edge of SCLK in
clock mode 11. See Figures 6–11. Bipolar true-differen-
tial results and temperature-sensor results are available
in two’s complement format, while all other results are in
binary.
A high-to-low transition on CS initiates the data-input
operation. Serial communications to the ADC always
begin with an 8-bit command byte (MSB first) loaded
from DIN. The command byte and the subsequent data
bytes are clocked from DIN into the serial interface on
the falling edge of SCLK. The serial-interface and fast-
interface circuitry is common to the ADC, DAC, and
GPIO sections. The content of the command byte
determines whether the SPI port should expect 8, 16, or
24 bits and whether the data is intended for the ADC,
DAC, or GPIOs (if applicable). See Table 1. Driving CS
high resets the serial interface.
The conversion register controls ADC channel selec-
tion, ADC scan mode, and temperature-measurement
requests. See Table 4 for information on writing to the
conversion register. The setup register controls the
clock mode, reference, and unipolar/bipolar ADC con-
figuration. Use a second byte, following the first, to
write to the unipolar-mode or bipolar-mode registers.
See Table 5 for details of the setup register and see
Tables 6, 7, and 8 for setting the unipolar- and bipolar-
mode registers. Hold CS low between the command
byte and the second and third byte. The ADC averag-
ing register is specific to the ADC. See Table 9 to
address that register. Table 11 shows the details of the
reset register.
Begin a write to the DAC by writing 0001XXXX as a
command byte. The last 4 bits of this command byte
are don’t-care bits. Write another 2 bytes (holding CS
low) to the DAC interface register following the com-
mand byte to select the appropriate DAC and the data
to be written to it. See the
DAC Serial Interface
section
and Tables 10, 20, and 21.
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
______________________________________________________________________________________ 19
DOUT
EOC
ADDRESS
AIN0
AIN13
REF2/
AIN14
CNVST/
AIN15
REF1
DIN
SCLK
CS
GPIOA0–
GPIOA3
GPIOB0–
GPIOB3
GPIOC0–
GPIOC3
AVDD
SPI
PORT
GPIO
CONTROL
INPUT
REGISTER
DAC
REGISTER
OUTPUT
CONDITIONING
12-BIT
DAC BUFFER
USER-PROGRAMMABLE
I/O
OSCILLATOR
OUT0
OUT1
OUT2
OUT4
OUT5
OUT6
MAX1257
MAX1258
12-BIT
SAR
ADC
LOGIC
CONTROL
TEMPERATURE
SENSOR
FIFO AND
ALU
LDAC RES_SEL
AGND
T/H
REF2
INPUT
REGISTER
DAC
REGISTER
OUTPUT
CONDITIONING
12-BIT
DAC BUFFER
INPUT
REGISTER
DAC
REGISTER
OUTPUT
CONDITIONING
12-BIT
DAC BUFFER
INPUT
REGISTER
DAC
REGISTER
OUTPUT
CONDITIONING
12-BIT
DAC BUFFER
INPUT
REGISTER
INTERNAL
REFERENCE
DAC
REGISTER
OUTPUT
CONDITIONING
12-BIT
DAC BUFFER
INPUT
REGISTER
DAC
REGISTER
OUTPUT
CONDITIONING
12-BIT
DAC BUFFER
INPUT
REGISTER
DAC
REGISTER
OUTPUT
CONDITIONING
12-BIT
DAC BUFFER
INPUT
REGISTER
DAC
REGISTER
OUTPUT
CONDITIONING
12-BIT
DAC BUFFER
OUT3
OUT7
DGND
DVDD
CNVST
Figure 1. MAX1257/MAX1258 Functional Diagram
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
20 ______________________________________________________________________________________
Table 1. Command Byte (MSB First)
REGISTER
NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
ADDITIONAL
NO. OF
BYTES
Conversion 1 CHSEL3 CHSEL2 CHSEL1 CHSEL0 SCAN1 SCAN0 TEMP 0
Setup 0 1 CKSEL1 CKSEL0 REFSEL1 REFSEL0 DIFFSEL1 DIFFSEL0 1
ADC 0 0 1 AVGON NAVG1 NAVG0 NSCAN1 NSCAN0 0
DAC Select 0 0 0 1 X X X X 2
Reset 0 0 0 0 1 RESET SLOW FBGON 0
GPIO Configure 0 0 0 0 0 0 1 1 1 or 2
GPIO Write 0 0 0 0 0 0 1 0 1 or 2
GPIO Read 0 0 0 0 0 0 0 1 1 or 2
No Operation 0 0 0 0 0 0 0 0 0
X = Don’t care.
Write to the GPIOs by issuing a command byte to the
appropriate register. Writing to the MAX1220 GPIOs
requires 1 additional byte following the command byte.
Writing to the MAX1257/MAX1258 requires 2 additional
bytes following the command byte. See Tables 12–19
for details on GPIO configuration, writes, and reads.
See the
GPIO Command
section. Command bytes writ-
ten to the GPIOs on devices without GPIOs are ignored.
Power-Up Default State
The MAX1220/MAX1257/MAX1258 power up with all
blocks in shutdown (including the reference). All regis-
ters power up in state 00000000, except for the setup
register and the DAC input register. The setup register
powers up at 0010 1000 with CKSEL1 = 1 and
REFSEL1 = 1. The DAC input register powers up to
FFFh when RES_SEL is high and powers up to 000h
when RES_SEL is low.
12-Bit ADC
The MAX1220/MAX1257/MAX1258 ADCs use a fully
differential successive-approximation register (SAR)
conversion technique and on-chip track-and-hold (T/H)
circuitry to convert temperature and voltage signals into
12-bit digital results. The analog inputs accept both sin-
gle-ended and differential input signals. Single-ended
signals are converted using a unipolar transfer function,
and differential signals are converted using a selec-
table bipolar or unipolar transfer function. See the
ADC
Transfer Functions
section for more data.
ADC Clock Modes
When addressing the setup, register bits 5 and 4 of the
command byte (CKSEL1 and CKSEL0, respectively)
control the ADC clock modes. See Table 5. Choose
between four different clock modes for various ways to
start a conversion and determine whether the acquisi-
tions are internally or externally timed. Select clock
mode 00 to configure CNVST/AIN_ to act as a conver-
sion start and use it to request internally timed conver-
sions, without tying up the serial bus. In clock mode 01,
use CNVST to request conversions one channel at a
time, thereby controlling the sampling speed without
tying up the serial bus. Request and start internally
timed conversions through the serial interface by writ-
ing to the conversion register in the default clock mode,
10. Use clock mode 11 with SCLK up to 3.6MHz for
externally timed acquisitions to achieve sampling rates
up to 225ksps. Clock mode 11 disables scanning and
averaging. See Figures 6–9 for timing specifications on
how to begin a conversion.
These devices feature an active-low, end-of-conversion
output. EOC goes low when the ADC completes the last
requested operation and is waiting for the next com-
mand byte. EOC goes high when CS or CNVST go low.
EOC is always high in clock mode 11.
Single-Ended or Differential Conversions
The MAX1220/MAX1257/MAX1258 use a fully differen-
tial ADC for all conversions. When a pair of inputs are
connected as a differential pair, each input is connect-
ed to the ADC. When configured in single-ended mode,
the positive input is the single-ended channel and the
negative input is referred to AGND. See Figure 2.
In differential mode, the T/H samples the difference
between two analog inputs, eliminating common-mode
DC offsets and noise. IN+ and IN- are selected from the
following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5,
AIN6/AIN7, AIN8/AIN9, AIN10/AIN11, AIN12/AIN13,
AIN14/AIN15. AIN0–AIN7 are available on all devices.
AIN0–AIN15 are available on the MAX1257/MAX1258.
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
______________________________________________________________________________________ 21
See Tables 5–8 for more details on configuring the
inputs. For the inputs that are configurable as CNVST,
REF2, and an analog input, only one function can be
used at a time.
Unipolar or Bipolar Conversions
Address the unipolar- and bipolar-mode registers
through the setup register (bits 1 and 0). See Table 5 for
the setup register. See Figures 3 and 4 for the transfer-
function graphs. Program a pair of analog inputs for dif-
ferential operation by writing a one to the appropriate bit
of the bipolar- or unipolar-mode register. Unipolar mode
sets the differential input range from 0 to VREF1. A nega-
tive differential analog input in unipolar mode causes the
digital output code to be zero. Selecting bipolar mode
sets the differential input range to ±VREF1 / 2. The digital
output code is binary in unipolar mode and two’s com-
plement in bipolar mode.
In single-ended mode, the MAX1220/MAX1257/
MAX1258 always operate in unipolar mode. The analog
inputs are internally referenced to AGND with a full-scale
input range from 0 to the selected reference voltage.
Analog Input (T/H)
The equivalent circuit of Figure 2 shows the ADC input
architecture of the MAX1220/MAX1257/MAX1258. In
track mode, a positive input capacitor is connected to
AIN0–AIN15 in single-ended mode and AIN0, AIN2,
and AIN4–AIN14 (only positive inputs) in differential
mode. A negative input capacitor is connected to
AGND in single-ended mode or AIN1, AIN3, and
AIN5–AIN15 (only negative inputs) in differential mode.
For external T/H timing, use clock mode 01. After the
T/H enters hold mode, the difference between the sam-
pled positive and negative input voltages is converted.
The input capacitance charging rate determines the
time required for the T/H to acquire an input signal. If
the input signal’s source impedance is high, the
required acquisition time lengthens.
Any source impedance below 300Ωdoes not signifi-
cantly affect the ADC’s AC performance. A high-imped-
ance source can be accommodated either by
lengthening tACQ (only in clock mode 01) or by placing
a 1µF capacitor between the positive and negative ana-
log inputs. The combination of the analog-input source
impedance and the capacitance at the analog input cre-
ates an RC filter that limits the analog input bandwidth.
Input Bandwidth
The ADC’s input-tracking circuitry has a 1MHz small-
signal bandwidth, making it possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Anti-alias prefiltering
of the input signals is necessary to avoid high-frequen-
cy signals aliasing into the frequency band
of interest.
Analog Input Protection
Internal electrostatic-discharge (ESD) protection diodes
clamp all analog inputs to AVDD and AGND, allowing
the inputs to swing from (AGND - 0.3V) to (AVDD +
0.3V) without damage. However, for accurate conver-
sions near full scale, the inputs must not exceed AVDD
by more than 50mV or be lower than AGND by 50mV. If
an analog input voltage exceeds the supplies, limit the
input current to 2mA.
Internal FIFO
The MAX1220/MAX1257/MAX1258 contain a first-
in/first-out (FIFO) buffer that holds up to 16 ADC results
plus one temperature result. The internal FIFO allows
the ADC to process and store multiple internally
clocked conversions and a temperature measurement
without being serviced by the serial bus.
If the FIFO is filled and further conversions are request-
ed without reading from the FIFO, the oldest ADC
results are overwritten by the new ADC results. Each
result contains 2 bytes, with the MSB preceded by four
leading zeros. After each falling edge of CS, the oldest
available pair of bytes of data is available at DOUT,
MSB first. When the FIFO is empty, DOUT is zero.
AIN0–AIN15
(SINGLE-ENDED),
AIN0, AIN2,
AIN4–AIN14
(DIFFERENTIAL)
COMPARATOR
HOLD
ACQ
ACQ
HOLD
ACQ
HOLD
AVDD / 2
REF1
AGND
CIN+
CIN-
DAC
AGND
(SINGLE-ENDED),
AIN1, AIN3,
AIN5–AIN15
(DIFFERENTIAL)
Figure 2. Equivalent Input Circuit
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
22 ______________________________________________________________________________________
The first 2 bytes of data read out after a temperature
measurement always contain the 12-bit temperature
result, preceded by four leading zeros, MSB first. If
another temperature measurement is performed before
the first temperature result is read out, the old measure-
ment is overwritten by the new result. Temperature
results are in degrees Celsius (two’s complement), at a
resolution of 8 LSB per degree. See the
Temperature
Measurements
section for details on converting the dig-
ital code to a temperature.
12-Bit DAC
In addition to the 12-bit ADC, the MAX1220/
MAX1257/MAX1258 also include eight voltage-output,
12-bit, monotonic DACs with less than 4 LSB integral
nonlinearity error and less than 1 LSB differential nonlin-
earity error. Each DAC has a 2µs settling time and ultra-
low glitch energy (4nV•s). The 12-bit DAC code is
unipolar binary with 1 LSB = VREF/4096.
DAC Digital Interface
Figure 1 shows the functional diagram of the MAX1257/
MAX1258. The shift register converts a serial 16-bit word
to parallel data for each input register operating with a
clock rate up to 25MHz. The SPI-compatible digital inter-
face to the shift register consists of CS, SCLK, DIN, and
DOUT. Serial data at DIN is loaded on the falling edge
of SCLK. Pull CS low to begin a write sequence. Begin a
write to the DAC by writing 0001XXXX as a command
byte. The last 4 bits of the DAC select register are don’t-
care bits. See Table 10. Write another 2 bytes to the
DAC interface register following the command byte to
select the appropriate DAC and the data to be written to
it. See Tables 20 and 21.
The eight double-buffered DACs include an input and a
DAC register. The input registers are directly connect-
ed to the shift register and hold the result of the most
recent write operation. The eight 12-bit DAC registers
hold the current output code for the respective DAC.
Data can be transferred from the input registers to the
DAC registers by pulling LDAC low or by writing the
appropriate DAC command sequence at DIN. See
Table 20. The outputs of the DACs are buffered through
eight rail-to-rail op amps.
The MAX1220/MAX1257/MAX1258 DAC output voltage
range is based on the internal reference or an external
reference. Write to the setup register (see Table 5) to
program the reference. If using an external voltage ref-
erence, bypass REF1 with a 0.1µF capacitor to AGND.
The MAX1257 internal reference is 2.5V. The
MAX1220/MAX1258 internal reference is 4.096V. When
using an external reference on any of these devices,
the voltage range is 0.7V to VAVDD.
DAC Transfer Function
See Table 2 for various analog outputs from the DAC.
DAC Power-On Wake-Up Modes
The state of the RES_SEL input determines the wake-up
state of the DAC outputs. Connect RES_SEL to AVDD
or AGND upon power-up to be sure the DAC outputs
wake up to a known state. Connect RES_SEL to AGND
to wake up all DAC outputs at 000h. While RES_SEL is
low, the 100kΩinternal resistor pulls the DAC outputs to
AGND and the output buffers are powered down.
Connect RES_SEL to AVDD to wake up all DAC outputs
at FFFh. While RES_SEL is high, the 100kΩpullup
resistor pulls the DAC outputs to VREF1 and the output
buffers are powered down.
DAC Power-Up Modes
See Table 21 for a description of the DAC power-up
and power-down modes.
GPIOs
In addition to the internal ADC and DAC, the
MAX1257/MAX1258 also provide 12 general-purpose
input/output channels, GPIOA0–GPIOA3, GPIOB0–
DAC CONTENTS
MSB LSB ANALOG OUTPUT
1111 1111 1111
1000 0000 0001
1000 0000 0000
0111 0111 0111
0000 0000 0001
0000 0000 0000 0
+⎛
⎝
⎜⎞
⎠
⎟
VREF 4095
4096
+⎛
⎝
⎜⎞
⎠
⎟=+
⎛
⎝
⎜⎞
⎠
⎟
VV
REF REF
2048
4096 2
+⎛
⎝
⎜⎞
⎠
⎟
VREF 2047
4096
+⎛
⎝
⎜⎞
⎠
⎟
VREF 1
4096
+⎛
⎝
⎜⎞
⎠
⎟
VREF 2049
4096
Table 2. DAC Output Code Table
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
______________________________________________________________________________________ 23
GPIOB3, and GPIOC0–GPIOC3. The MAX1220 includes
four GPIO channels (GPIOA0, GPIOA1, GPIOC0,
GPIOC1). Read and write to the GPIOs as detailed in
Table 1 and Tables 12–19. Also, see the
GPIO Command
section. See Figures 11 and 12 for GPIO timing.
Write to the GPIOs by writing a command byte to the
GPIO command register. Write a single data byte to the
MAX1220 following the command byte. Write 2 bytes to
the MAX1257/MAX1258 following the command byte.
The GPIOs can sink and source current. The
MAX1257/MAX1258 GPIOA0–GPIOA3 can sink and
source up to 15mA. GPIOB0–GPIOB3 and GPIOC0–
GPIOC3 can sink 4mA and source 2mA. The MAX1220
GPIOA0 and GPIOA1 can sink and source up to 15mA.
The MAX1220 GPIOC0 and GPIOC1 can sink 4mA and
source 2mA. See Table 3.
Clock Modes
Internal Clock
The MAX1220/MAX1257/MAX1258 can operate from an
internal oscillator. The internal oscillator is active in
clock modes 00, 01, and 10. Figures 6, 7, and 8 show
how to start an ADC conversion in the three internally
timed conversion modes.
Read out the data at clock speeds up to 25MHz
through the SPI interface.
External Clock
Set CKSEL1 and CKSEL0 in the setup register to 11 to
set up the interface for external clock mode 11. See
Table 5. Pulse SCLK at speeds from 0.1MHz to
3.6MHz. Write to SCLK with a 40% to 60% duty cycle.
The SCLK frequency controls the conversion timing.
See Figures 9a and 9b for clock mode 11 timing. See
the
ADC Conversions in Clock Mode 11
section.
ADC/DAC References
Address the reference through the setup register, bits 3
and 2. See Table 5. Following a wake-up delay, set
REFSEL[1:0] = 00 to program both the ADC and DAC
for internal reference use. Set REFSEL[1:0] = 10 to pro-
gram the ADC for internal reference. Set REFSEL[1:0] =
10 to program the DAC for external reference, REF1.
When using REF1 or REF2/AIN_ in external-reference
mode, connect a 0.1µF capacitor to AGND. Set
REFSEL[1:0] = 01 to program the ADC and DAC for
external-reference mode. The DAC uses REF1 as its
external reference, while the ADC uses REF2 as its
external reference. Set REFSEL[1:0] = 11 to program
the ADC for external differential reference mode. REF1
is the positive reference and REF2 is the negative refer-
ence in the ADC external differential mode.
When REFSEL[1:0] = 00 or 10, REF2/AIN_ functions as
an analog input channel. When REFSEL[1:0] = 01 or 11,
REF2/AIN_ functions as the device’s negative reference.
Temperature Measurements
Issue a command byte setting bit 0 of the conversion
register to one to take a temperature measurement.
See Table 4. The MAX1220/MAX1257/MAX1258 perform
temperature measurements with an internal diode-con-
nected transistor. The diode bias current changes from
68µA to 4µA to produce a temperature-dependent bias
voltage difference. The second conversion result at 4µA
is subtracted from the first at 68µA to calculate a digital
value that is proportional to absolute temperature. The
output data appearing at DOUT is the digital code
above, minus an offset to adjust from Kelvin to Celsius.
The reference voltage used for the temperature mea-
surements is always derived from the internal reference
source to ensure that 1 LSB corresponds to 1/8 of a
degree Celsius. On every scan where a temperature
measurement is requested, the temperature conversion
is carried out first. The first 2 bytes of data read from
the FIFO contain the result of the temperature measure-
ment. If another temperature measurement is per-
formed before the first temperature result is read out,
the old measurement is overwritten by the new result.
Temperature results are in degrees Celsius (two’s com-
plement). See the
Applications Information
section for
information on how to perform temperature measure-
ments in each clock mode.
Register Descriptions
The MAX1220/MAX1257/MAX1258 communicate
between the internal registers and the external circuitry
through the SPI-compatible serial interface. Table 1
details the command byte, the registers, and the bit
Table 3. GPIO Maximum Sink/Source Current
MAX1257/MAX1258 (mA) MAX1220 (mA)
CURRENT GPIOA0–GPIOA3 GPIOB0–GPIOB3 GPIOC0–GPIOC3 GPIOA0, GPIOA1 GPIOC0, GPIOC1
Sink 15 4 4 15 4
Source 15 2 2 15 2
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
24 ______________________________________________________________________________________
names. Tables 4–12 show the various functions within
the conversion register, setup register, unipolar-mode
register, bipolar-mode register, ADC averaging regis-
ter, DAC select register, reset register, and GPIO com-
mand register, respectively.
Conversion Register
Select active analog input channels, scan modes, and
a single temperature measurement per scan by issuing
a command byte to the conversion register. Table 4
details channel selection, the four scan modes, and
how to request a temperature measurement. Start a
scan by writing to the conversion register when in clock
mode 10 or 11, or by applying a low pulse to the
CNVST pin when in clock mode 00 or 01. See Figures 6
and 7 for timing specifications for starting a scan with
CNVST.
A conversion is not performed if it is requested on a
channel or one of the channel pairs that has been con-
figured as CNVST or REF2. For channels configured as
differential pairs, the CHSEL0 bit is ignored and the two
pins are treated as a single differential channel.
Select scan mode 00 or 01 to return one result per sin-
gle-ended channel and one result per differential pair
within the selected scanning range (set by bits 2 and 1,
SCAN1 and SCAN0), plus one temperature result, if
selected. Select scan mode 10 to scan a single input
channel numerous times, depending on NSCAN1 and
NSCAN0 in the ADC averaging register (Table 9).
Select scan mode 11 to return only one result from a
single channel.
Setup Register
Issue a command byte to the setup register to config-
ure the clock, reference, power-down modes, and ADC
single-ended/differential modes. Table 5 details the bits
in the setup-register command byte. Bits 5 and 4
(CKSEL1 and CKSEL0) control the clock mode, acqui-
sition and sampling, and the conversion start. Bits 3
and 2 (REFSEL1 and REFSEL0) set the device for either
internal or external reference. Bits 1 and 0 (DIFFSEL1
and DIFFSEL0) address the ADC unipolar-mode and
bipolar-mode registers and configure the analog input
channels for differential operation.
Table 4. Conversion Register*
BIT
NAME BIT FUNCTION
— 7 (MSB) S et to one to sel ect conver si on r eg i ster .
CHSEL3 6 Analog-input channel select.
CHSEL2 5 Analog-input channel select.
CHSEL1 4 Analog-input channel select.
CHSEL0 3 Analog-input channel select.
SCAN1 2 Scan-mode select.
SCAN0 1 Scan-mode select.
TEMP 0 (LSB)
Set to one to take a single temp-
erature measurement. The first
conversion result of a scan contains
temperature information.
CHSEL3 CHSEL2 CHSEL1 CHSEL0
SELEC T ED
C H AN N EL
( N )
0 0 0 0 AIN0
0 0 0 1 AIN1
0 0 1 0 AIN2
0 0 1 1 AIN3
0 1 0 0 AIN4
0 1 0 1 AIN5
0 1 1 0 AIN6
0 1 1 1 AIN7
1 0 0 0 AIN8
1 0 0 1 AIN9
1 0 1 0 AIN10
1 0 1 1 AIN11
1 1 0 0 AIN12
1 1 0 1 AIN13
1 1 1 0 AIN14
1 1 1 1 AIN15
SCAN1 SCAN0
SCAN MODE
(CHANNEL N IS SELECTED BY
BITS CHSEL3–CHSEL0)
0 0 Scans channels 0 through N.
01
Scans channels N through the highest
numbered channel.
10
S cans channel N r epeated l y. The AD C
aver ag ing reg i ster sets the numb er of
r esul ts.
11N o scan. C onver ts channel N once onl y.
*
See below for bit details.
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
______________________________________________________________________________________ 25
Table 5. Setup Register*
BIT NAME BIT FUNCTION
— 7 (MSB) Set to zero to select setup register.
— 6 Set to one to select setup register.
CKSEL1 5 Clock mode and CNVST configuration; resets to one at power-up.
CKSEL0 4 Clock mode and CNVST configuration.
REFSEL1 3 Reference-mode configuration.
REFSEL0 2 Reference-mode configuration.
DIFFSEL1 1 Unipolar-/bipolar-mode register configuration for differential mode.
DIFFSEL0 0 (LSB) Unipolar-/bipolar-mode register configuration for differential mode.
Table 5a. Clock Modes*
CKSEL1 CKSEL0 CONVERSION CLOCK ACQUISITION/SAMPLING CNVST CONFIGURATION
0 0 Internal Internally timed. CNVST
0 1 Internal Externally timed by CNVST.CNVST
1 0 Internal Internally timed. AIN15/AIN7
1 1 External (3.6MHz max) Externally timed by SCLK. AIN15/AIN7
Table 5b. Clock Modes 00, 01, and 10
REFSEL1 REFSEL0 VOLTAGE
REFERENCE
OVERRIDE
CONDITIONS AUTOSHUTDOWN REF2
CONFIGURATION
AIN
Inter nal r efer ence tur ns off after scan i s com p l ete. If
i nter nal r efer ence i s tur ned off, ther e i s a p r og r am m ed
d el ay of 218 i nter nal - conver si on cl ock cycl es.
00
Internal (DAC
and ADC)
Temperature
Internal reference required. There is a programmed
delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
AIN14/AIN6
AIN Internal reference not used.
01
External single-
ended (REF1
for DAC and
REF2 for ADC)
Temperature
Internal reference required. There is a programmed
delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
REF2
AIN
Default reference mode. Internal reference turns off
after scan is complete. If internal reference is turned
off, there is a programmed delay of 218 internal-
conversion clock cycles.
10
Internal (ADC)
and external
REF1 (DAC)
Temperature
Internal reference required. There is a programmed
delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
AIN14/AIN6
AIN Internal reference not used.
11
External
differential
(ADC), external
REF1 (DAC)
Temperature
Internal reference required. There is a programmed
delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
REF2
*
See below for bit details.
*
See the Clock Modes section.
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
26 ______________________________________________________________________________________
Table 5c. Clock Mode 11
REFSEL1 REFSEL0 VOLTAGE
REFERENCE
OVERRIDE
CONDITIONS AUTOSHUTDOWN REF2
CONFIGURATION
AIN
Inter nal r efer ence tur ns off after scan i s com p l ete. If
i nter nal r efer ence i s tur ned off, ther e i s a p r og r am m ed
d el ay of 218 exter nal conver si on cl ock cycl es.
00
Internal (DAC
and ADC)
Temperature
Inter nal r efer ence r eq ui r ed . Ther e i s a p r og r am m ed
d el ay of 244 exter nal conver si on cl ock cycl es for the
i nter nal r efer ence. Tem p er atur e- sensor outp ut ap p ear s
at D OU T after 188 fur ther exter nal cl ock cycl es.
AIN14/AIN6
AIN Internal reference not used.
01
External single-
ended (REF1
for DAC and
REF2 for ADC)
Tem p er atur e
Inter nal r efer ence r eq ui r ed . Ther e i s a p r og r am m ed
d el ay of 244 exter nal conver si on cl ock cycl es for the
i nter nal r efer ence. Tem p er atur e- sensor outp ut ap p ear s
at D OU T after 188 fur ther exter nal cl ock cycl es.
REF2
AIN
Default reference mode. Internal reference turns off
after scan is complete. If internal reference is turned
off, there is a programmed delay of 218 external
conversion clock cycles.
10
Internal (ADC)
and external
REF1 (DAC)
Temperature
Inter nal r efer ence r eq ui r ed . Ther e i s a p r og r am m ed
d el ay of 244 exter nal conver si on cl ock cycl es for the
i nter nal r efer ence. Tem p er atur e- sensor outp ut ap p ear s
at D OU T after 188 fur ther exter nal cl ock cycl es.
AIN14/AIN6
AIN Internal reference not used.
11
External
differential
(ADC), external
REF1 (DAC)
Temperature
Inter nal r efer ence r eq ui r ed . Ther e i s a p r og r am m ed
d el ay of 244 exter nal conver si on cl ock cycl es for the
i nter nal r efer ence. Tem p er atur e- sensor outp ut ap p ear s
at D OU T after 188 fur ther exter nal cl ock cycl es.
REF2
Table 5d. Differential Select Modes
DIFFSEL1 DIFFSEL0 FUNCTION
0 0 No data follows the command setup byte. Unipolar-mode and bipolar-mode registers remain unchanged.
0 1 No data follows the command setup byte. Unipolar-mode and bipolar-mode registers remain unchanged.
1 0 1 byte of data follows the command setup byte and is written to the unipolar-mode register.
1 1 1 byte of data follows the command setup byte and is written to the bipolar-mode register.
The ADC reference is always on if any of the following
conditions are true:
1) The FBGON bit is set to one in the reset register.
2) At least one DAC output is powered up and
REFSEL[1:0] (in the setup register) = 00.
3) At least one DAC is powered down through the
100kΩto VREF and REFSEL[1:0] = 00.
If any of the above conditions exist, the ADC reference
is always on, but there is a 188 clock-cycle delay
before temperature-sensor measurements begin, if
requested.
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
______________________________________________________________________________________ 27
Table 6. Unipolar-Mode Register (Addressed Through the Setup Register)
BIT NAME BIT FUNCTION
UCH0/1 7 (MSB) Configure AIN0 and AIN1 for unipolar differential conversion.
UCH2/3 6 Configure AIN2 and AIN3 for unipolar differential conversion.
UCH4/5 5 Configure AIN4 and AIN5 for unipolar differential conversion.
UCH6/7 4 Configure AIN6 and AIN7 for unipolar differential conversion.
UCH8/9 3 Configure AIN8 and AIN9 for unipolar differential conversion.
UCH10/11 2 Configure AIN10 and AIN11 for unipolar differential conversion.
UCH12/13 1 Configure AIN12 and AIN13 for unipolar differential conversion.
UCH14/15 0 (LSB) Configure AIN14 and AIN15 for unipolar differential conversion.
Table 7. Bipolar-Mode Register (Addressed Through the Setup Register)
BIT NAME BIT FUNCTION
BCH0/1 7 (MSB)
Set to one to configure AIN0 and AIN1 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN0 and AIN1 for unipolar
single-ended conversion.
BCH2/3 6
Set to one to configure AIN2 and AIN3 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN2 and AIN3 for unipolar
single-ended conversion.
BCH4/5 5
Set to one to configure AIN4 and AIN5 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN4 and AIN5 for unipolar
single-ended conversion.
BCH6/7 4
Set to one to configure AIN6 and AIN7 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN6 and AIN7 for unipolar
single-ended conversion.
BCH8/9 3
Set to one to configure AIN8 and AIN9 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN8 and AIN9 for unipolar
single-ended conversion.
BCH10/11 2
Set to one to configure AIN10 and AIN11 for bipolar differential conversion. Set the corresponding
bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN10 and AIN11 for
unipolar single-ended conversion.
BCH12/13 1
Set to one to configure AIN12 and AIN13 for bipolar differential conversion. Set the corresponding
bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN12 and AIN13 for
unipolar single-ended conversion.
BCH14/15 0 (LSB)
Set to one to configure AIN14 and AIN15 for bipolar differential conversion. Set the corresponding
bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN14 and AIN15 for
unipolar single-ended conversion.
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
28 ______________________________________________________________________________________
Unipolar/Bipolar Registers
The final 2 bits (LSBs) of the setup register control the
unipolar-/bipolar-mode address registers. Set
DIFFSEL[1:0] = 10 to write to the unipolar-mode regis-
ter. Set bits DIFFSEL[1:0] = 11 to write to the bipolar-
mode register. In both cases, the setup command byte
must be followed by 1 byte of data that is written to the
unipolar-mode register or bipolar-mode register. Hold
CS low and run 16 SCLK cycles before pulling CS high.
If the last 2 bits of the setup register are 00 or 01, nei-
ther the unipolar-mode register nor the bipolar-mode
register is written. Any subsequent byte is recognized
as a new command byte. See Tables 6, 7, and 8 to pro-
gram the unipolar- and bipolar-mode registers.
Both registers power up at all zeros to set the inputs as
16 unipolar single-ended channels. To configure a
channel pair as single-ended unipolar, bipolar differen-
tial, or unipolar differential, see Table 8.
In unipolar mode, AIN+ can exceed AIN- by up to
VREF. The output format in unipolar mode is binary. In
bipolar mode, either input can exceed the other by up
to VREF / 2. The output format in bipolar mode is two’s
complement (see the
ADC Transfer Functions
section).
ADC Averaging Register
Write a command byte to the ADC averaging register to
configure the ADC to average up to 32 samples for
each requested result, and to independently control the
number of results requested for single-channel scans.
Table 8. Unipolar/Bipolar Channel Function
UNIPOLAR-
MODE
REGISTER BIT
BIPOLAR-MODE
REGISTER BIT
CHANNEL PAIR
FUNCTION
0 0 Unipolar single-ended
0 1 Bipolar differential
1 0 Unipolar differential
1 1 Unipolar differential
Table 9. ADC Averaging Register*
BIT NAME BIT FUNCTION
— 7 (MSB) Set to zero to select ADC averaging register.
— 6 Set to zero to select ADC averaging register.
— 5 Set to one to select ADC averaging register.
AVGON 4 Set to one to turn averaging on. Set to zero to turn averaging off.
NAVG1 3 Configures the number of conversions for single-channel scans.
NAVG0 2 Configures the number of conversions for single-channel scans.
NSCAN1 1 Single-channel scan count. (Scan mode 10 only.)
NSCAN0 0 (LSB) Single-channel scan count. (Scan mode 10 only.)
AVGON NAVG1 NAVG0 FUNCTION
0 X X Performs one conversion for each requested result.
1 0 0 Performs four conversions and returns the average for each requested result.
1 0 1 Performs eight conversions and returns the average for each requested result.
1 1 0 Performs 16 conversions and returns the average for each requested result.
1 1 1 Performs 32 conversions and returns the average for each requested result.
NSCAN1 NSCAN0 FUNCTION (APPLIES ONLY IF SCAN MODE 10 IS SELECTED)
0 0 Scans channel N and returns four results.
0 1 Scans channel N and returns eight results.
1 0 Scans channel N and returns 12 results.
1 1 Scans channel N and returns 16 results.
*
See below for bit details.
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
______________________________________________________________________________________ 29
Table 9 details the four scan modes available in the
ADC conversion register. All four scan modes allow
averaging as long as the AVGON bit, bit 4 in the
averaging register, is set to 1. Select scan mode 10 to
scan the same channel multiple times. Clock mode 11
disables averaging. For example, if AVGON = 1,
NAVG[1:0] = 00, NSCAN[1:0] = 11, and SCAN[1:0] =
10, 16 results are written to the FIFO, with each result
being the average of four conversions of channel N.
DAC Select Register
Write a command byte 0001XXXX to the DAC select
register (as shown in Table 10) to set up the DAC inter-
face and indicate that another word will follow. The last
4 bits of the DAC select register are don’t-care bits. The
word that follows the DAC select-register command
byte controls the DAC serial interface. See Table 20
and the
DAC Serial Interface
section.
Reset Register
Write to the reset register (as shown in Table 11) to
clear the FIFO or reset all registers (excluding the DAC
and GPIO registers) to their default states. When the
RESET bit in the reset register is set to 0, the FIFO is
cleared. Set the RESET bit to one to return all the
device registers to their default power-up state. All reg-
isters power up in state 00000000, except for the setup
register that powers up in clock mode 10 (CKSEL1 = 1
and REFSEL1 = 1). The DAC and GPIO registers are
not reset by writing to the reset register. Set the SLOW
bit to one to add a 15ns delay in the DOUT signal path
to provide a longer hold time. Writing a one to the
SLOW bit also clears the contents of the FIFO. Set the
FBGON bit to one to force the bias block and bandgap
reference to power up regardless of the state of the
DAC and activity of the ADC block. Setting the FBGON
bit high also removes the programmed wake-up delay
between conversions in clock modes 01 and 11.
Setting the FBGON bit high also clears the FIFO.
Table 10. DAC Select Register
BIT
NAME BIT FUNCTION
— 7 (MSB) Set to zero to select DAC select register.
— 6 Set to zero to select DAC select register.
— 5 Set to zero to select DAC select register.
— 4 Set to one to select DAC select register.
X 3 Don’t care.
X 2 Don’t care.
X 1 Don’t care.
X 0 Don’t care.
Table 11. Reset Register
BIT
NAME BIT FUNCTION
— 7 (MSB) Set to zero to select ADC reset register.
— 6 Set to zero to select ADC reset register.
— 5 Set to zero to select ADC reset register.
— 4 Set to zero to select ADC reset register.
— 3 Set to one to select ADC reset register.
RESET 2
Set to zero to clear the FIFO only. Set to
one to set the device in its power-on
condition.
SLOW 1 Set to one to turn on slow mode.
FBGON 0 (LSB)
Set to one to force internal bias block and
bandgap reference to be always powered
up.
Table 12. GPIO Command Register
BIT NAME BIT FUNCTION
— 7 (MSB) Set to zero to select GPIO register.
— 6 Set to zero to select GPIO register.
— 5 Set to zero to select GPIO register.
— 4 Set to zero to select GPIO register.
— 3 Set to zero to select GPIO register.
— 2 Set to zero to select GPIO register.
GPIOSEL1 1 GPIO configuration bit.
GPIOSEL2 0 (LSB) GPIO write bit.
GPIOSEL1 GPIOSEL2 FUNCTION
11
GPIO configuration; written data is
entered in the GPIO configuration
register.
10
GPIO write; written data is entered
in the GPIO write register.
01
GPIO read; the next 8/16 SCLK
cycles transfer the state of all GPIO
drivers into DOUT.
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
30 ______________________________________________________________________________________
Table 13. MAX1220 GPIO Configuration
DATA PIN GPIO COMMAND BYTE DATA BYTE
DIN 0 0 0 0 0 0 1 1 GPIOC1 GPIOC0 GPIOA1 GPIOA0 X X X X
DOUT 00000000 0 0 0 0 0 0 0 0
Table 14. MAX1257/MAX1258 GPIO Configuration
DATA PIN GPIO COMMAND BYTE DATA BYTE 1 DATA BYTE 2
DIN 00000011
GPIOC3
GPIOC2
GPIOC1
GPIOC0
GPIOB3
GPIOB2
GPIOB1
GPIOB0
GPIOA3
GPIOA2
GPIOA1
GPIOA0
XXXX
DOUT 000000000 0 0 0 00 0 0 0 00 0 0 0 00
Table 15. MAX1220 GPIO Write
DATA PIN GPIO COMMAND BYTE DATA BYTE
DIN 0 0 0 0 0 0 1 0 GPIOC1 GPIOC0 GPIOA1 GPIOA0 X X X X
DOUT 00000000 0 0 0 0 0 00 0
Table 16. MAX1257/MAX1258 GPIO Write
DATA PIN GPIO COMMAND BYTE DATA BYTE 1 DATA BYTE 2
DIN 00000010
GPIOC3
GPIOC2
GPIOC1
GPIOC0
GPIOB3
GPIOB2
GPIOB1
GPIOB0
GPIOA3
GPIOA2
GPIOA1
GPIOA0
XXXX
DOUT 000000000 0 0 0 00 0 0 0 00 0 0 0 00
GPIO Command
Write a command byte to the GPIO command register
to configure, write, or read the GPIOs, as detailed in
Table 12.
Write the command byte 00000011 to configure the
GPIOs. The eight SCLK cycles following the command
byte load data from DIN to the GPIO configuration reg-
ister in the MAX1220. The 16 SCLK cycles following the
command byte load data from DIN to the GPIO configu-
ration register in the MAX1257/MAX1258. See Tables
13 and 14. The register bits are updated after the last
CS rising edge. All GPIOs default to inputs upon power-
up.
The data in the register controls the function of each
GPIO, as shown in Tables 13–19.
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
______________________________________________________________________________________ 31
GPIO Write
Write the command byte 00000010 to indicate a GPIO
write operation. The eight SCLK cycles following the
command byte load data from DIN into the GPIO write
register in the MAX1220. The 16 SCLK cycles following
the command byte load data from DIN into the GPIO
write register in the MAX1257/MAX1258. See Tables 15
and 16. The register bits are updated after the last CS
rising edge.
GPIO Read
Write the command byte 00000001 to indicate a GPIO
read operation. The eight SCLK cycles following the
command byte transfer the state of the GPIOs to DOUT
in the MAX1220. The 16 SCLK cycles following the com-
mand byte transfer the state of the GPIOs to DOUT in the
MAX1257/MAX1258. See Tables 18 and 19.
DAC Serial Interface
Write a command byte 0001XXXX to the DAC select
register to indicate the word to follow is written to the
DAC serial interface, as detailed in Tables 1, 10, 20, and
21. Write the next 16 bits to the DAC interface register,
as shown in Tables 20 and 21. Following the high-to-low
transition of CS, the data is shifted synchronously and
latched into the input register on each falling edge of
SCLK. Each word is 16 bits. The first 4 bits are the con-
trol bits followed by 12 data bits (MSB first) and 2 don’t-
care sub-bits. See Figures 10–12 for DAC timing
specifications.
Table 18. MAX1220 GPIO Read
DATA PIN GPIO COMMAND BYTE DATA BYTE
DIN 00000001 X X X X X X X X
DOUT 00000000 0 0 0 0 GPIOC1 GPIOC0 GPIOA1 GPIOA0
Table 19. MAX1257/MAX1258 GPIO Read
DATA PIN GPIO COMMAND BYTE DATA BYTE 1 DATA BYTE 2
DIN 00000001XXXXXXXXXXXXXXXX
DOUT 000000000 0 00
GPIOC3
GPIOC2
GPIOC1
GPIOC0
GPIOB3
GPIOB2
GPIOB1
GPIOB0
GPIOA3
GPIOA2
GPIOA1
GPIOA0
Table 17. GPIO-Mode Control
CONFIGURATION
BIT
WRITE
BIT
OUTPUT
STATE
GPIO
FUNCTION
1 1 1 Output
1 0 0 Output
0 1 Three-state Input
0 0 0
Pulldown
(open drain)
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
32 ______________________________________________________________________________________
Table 20. DAC Serial-Interface Configuration
16-BIT SERIAL WORD
MSB LSB
CONTROL
BITS DATA BITS
C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DESCRIPTION FUNCTION
0 0 0 0 X X X X X X X X X X X X NOP No operation.
0 0 0 1 0 X 0 X X X X X X X X X RESET Reset all internal registers to 000h and
leave output buffers in their present state.
0 0 0 1 1 X 1 X X X X X X X X X Pull-High Preset all internal registers to FFFh and
leave output buffers in their present state.
0 0 1 0 ———————————— DAC0 D11–D0 to input register 0,
DAC output unchanged.
0 0 1 1 ———————————— DAC1 D11–D0 to input register 1,
DAC output unchanged.
0 1 0 0 ———————————— DAC2 D11–D0 to input register 2,
DAC output unchanged.
0 1 0 1 ———————————— DAC3 D11–D0 to input register 3,
DAC output unchanged.
0 1 1 0 ———————————— DAC4 D11–D0 to input register 4,
DAC output unchanged.
0 1 1 1 ———————————— DAC5 D11–D0 to input register 5,
DAC output unchanged.
1 0 0 0 ———————————— DAC6 D11–D0 to input register 6,
DAC output unchanged.
1 0 0 1 ———————————— DAC7 D11–D0 to input register 7,
DAC output unchanged.
1 0 1 0 ———————————— DAC0–DAC3
D11–D0 to input registers 0–3 and DAC
registers 0–3. DAC outputs updated
(write-through).
1 0 1 1 ———————————— DAC4–DAC7
D11–D0 to input registers 4–7 and DAC
registers 4–7. DAC outputs updated
(write-through).
1 1 0 0 ———————————— DAC0–DAC7
D11–D0 to input registers 0–7 and DAC
registers 0–7. DAC outputs updated
(write-through).
1 1 0 1 ———————————— DAC0–DAC7 D11–D0 to input registers 0–7.
DAC outputs unchanged.
1110
DAC7
DAC6
DAC5
DAC4
DAC3
DAC2
DAC1
DAC0
X X X X DAC0–DAC7
Input registers to DAC registers indicated
by ones, DAC outputs updated,
equivalent to software LDAC.
(No effect on DACs indicated by zeros.)
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
______________________________________________________________________________________ 33
If CS goes high prior to completing 16 SCLK cycles, the
command is discarded. To initiate a new transfer, drive
CS low again.
For example, writing the DAC serial interface word 1111
0000 and 1111 0100 disconnects DAC outputs 4
through 7 and forces them to a high-impedance state.
DAC outputs 0 through 3 remain in their previous state.
Output-Data Format
Figures 6–9 illustrate the conversion timing for the
MAX1220/MAX1257/MAX1258. All 12-bit conversion
results are output in 2-byte format, MSB first, with four
leading zeros. Data appears on DOUT on the falling
edges of SCLK. Data is binary for unipolar mode and
two’s complement for bipolar mode and temperature
results. See Figures 3, 4, and 5 for input/output and
temperature-transfer functions.
ADC Transfer Functions
Figure 3 shows the unipolar transfer function for single-
ended or differential inputs. Figure 4 shows the bipolar
transfer function for differential inputs. Code transitions
occur halfway between successive-integer LSB values.
Output coding is binary, with 1 LSB = VREF1/4096
(MAX1257) and 1 LSB = VREF1/4096 (MAX1220/
MAX1258) for unipolar and bipolar operation, and 1
LSB = +0.125°C for temperature measurements.
Bipolar true-differential results and temperature-sensor
Table 21. DAC Power-Up and Power-Down Commands
CONTROL
BITS DATA BITS
C3 C2 C1 C0
DAC7
DAC6
DAC5
DAC4
DAC3
DAC2
DAC1
DAC0
D3 D2 D1 D0
DESCRIPTION FUNCTION
1 1 1 1 ———————— 0 0 1 X Power-Up
Power up individual DAC buffers indicated by data
in DAC0 through DAC7. A one indicates the DAC
output is connected and active. A zero does not
affect the DAC’s present state.
1 1 1 1 ———————— 0 1 0 X Power-Down 1
Power down individual DAC buffers indicated by
data in DAC0 through DAC7. A one indicates the
DAC output is disconnected and high impedance.
A zero does not affect the DAC’s present state.
1 1 1 1 ———————— 1 0 0 X Power-Down 2
Power down individual DAC buffers indicated by
data in DAC0 through DAC7. A one indicates the
DAC output is disconnected and pulled to AGND
with a 1kΩ resistor. A zero does not affect the DAC’s
present state.
1 1 1 1 ———————— 0 0 0 X Power-Down 3
Power down individual DAC buffers indicated by
data in DAC0 through DAC7. A one indicates the
DAC output is disconnected and pulled to AGND
with a 100kΩ resistor. A zero does not affect the
DAC’s present state.
1 1 1 1 ———————— 1 1 1 X Power-Down 4
Power down individual DAC buffers indicated by
data in DAC0 through DAC7. A one indicates the
DAC output is disconnected and pulled to REF1 with
a 100kΩ resistor. A zero does not affect the DAC’s
present state.
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
34 ______________________________________________________________________________________
results are available in two’s complement format, while
all others are in binary. See Tables 6, 7, and 8 for
details on which setting (unipolar or bipolar) takes
precedence.
In unipolar mode, AIN+ can exceed AIN- by up to
VREF1. In bipolar mode, either input can exceed the
other by up to VREF1/2.
Partial Reads and Partial Writes
If the 1st byte of an entry in the FIFO is partially read
(CS is pulled high after fewer than eight SCLK cycles),
the remaining bits are lost for that byte. The next byte of
data that is read out contains the next 8 bits. If the first
byte of an entry in the FIFO is read out fully, but the
second byte is read out partially, the rest of that byte is
lost. The remaining data in the FIFO is unaffected and
can be read out normally after taking CS low again, as
long as the 4 leading bits (normally zeros) are ignored.
If CS is pulled low before EOC goes low, a conversion
may not be completed and the FIFO data may not be
correct. Incorrect writes (pulling CS high before com-
pleting eight SCLK cycles) are ignored and the register
remains unchanged.
Applications Information
Internally Timed Acquisitions and
Conversions Using
CNVST
ADC Conversions in Clock Mode 00
In clock mode 00, the wake-up, acquisition, conversion,
and shutdown sequence is initiated through CNVST
and performed automatically using the internal oscilla-
tor. Results are added to the internal FIFO to be read
out later. See Figure 6 for clock mode 00 timing after a
command byte is issued. See Table 5 for details on
programming the clock mode in the setup register.
Initiate a scan by setting CNVST low for at least 40ns
before pulling it high again. The MAX1220/MAX1257/
MAX1258 then wake up, scan all requested channels,
store the results in the FIFO, and shut down. After the
FULL-SCALE
TRANSITION
111....111
0
INPUT VOLTAGE (LSB)
FS = VREF
111....110
111....101
OFFSET BINARY OUTPUT CODE (LSB)
000....011
000....010
000....001
000....000
213 FS
1 LSB = VREF/4096
FS - 3/2 LSB
Figure 3. Unipolar Transfer Function—Full Scale (FS) = VREF
OUTPUT CODE
011....111
TEMPERATURE (°C)
011....110
000....001
111....101
100....001
100....000
111....111
111....110
000....000
0
000....010
-256 +255.5
Figure 5. Temperature Transfer Function
011....111
-FS
INPUT VOLTAGE (LSB)
FS = VREF/2 + VCOM
VREF = VREF+ - VREF-
-FS = -VREF/2
011....110
011....101
000....001
000....000
111....111
OFFSET BINARY OUTPUT CODE (LSB)
100....011
100....010
100....001
100....000
0
(COM)
-1 +1 +FS - 1 LSB
1 LSB = VREF/4096
ZS = COM
VREF VREF
VREF
(COM)
VREF
Figure 4. Bipolar Transfer Function—Full Scale (±FS) = ±VREF/2
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
______________________________________________________________________________________ 35
scan is complete, EOC is pulled low and the results are
available in the FIFO. Wait until EOC goes low before
pulling CS low to communicate with the serial interface.
EOC stays low until CS or CNVST is pulled low again. A
temperature-conversion result, if requested, precedes
all other FIFO results.
Do not issue a second CNVST signal before EOC goes
low; otherwise, the FIFO can be corrupted. Wait until all
conversions are complete before reading the FIFO. SPI
communications to the DAC and GPIO registers are per-
mitted during conversion. However, coupled noise may
result in degraded ADC signal-to-noise ratio (SNR).
Externally Timed Acquisitions and
Internally Timed Conversions with
CNVST
ADC Conversions in Clock Mode 01
In clock mode 01, conversions are requested one at a
time using CNVST and performed automatically using
the internal oscillator. See Figure 7 for clock mode 01
timing after a command byte is issued.
Setting CNVST low begins an acquisition, wakes up the
ADC, and places it in track mode. Hold CNVST low for
at least 1.4µs to complete the acquisition. If reference
mode 00 or 10 is selected, an additional 45µs is
required for the internal reference to power up. If a tem-
perature measurement is being requested, reference
power-up and temperature measurement is internally
timed. In this case, hold CNVST low for at least 40ns.
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
CS
DOUT
MSB1
tRDS
LSB1 MSB2
SCLK
CNVST
EOC
Figure 6. Clock Mode 00—After writing a command byte, set CNVST low for at least 40ns to begin a conversion.
(CONVERSION 2)
tCSW
tDOV
(ACQUISITION 2)
(ACQUISITION 1)
(CONVERSION 1)
CS
DOUT
MSB1 LSB1 MSB2
SCLK
CNVST
EOC
Figure 7. Clock Mode 01—After writing a command byte, request multiple conversions by setting CNVST low for each conversion.
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
36 ______________________________________________________________________________________
DIN
CONVERSION BYTE
MSB1 MSB2
LSB1
tDOV
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
EOC
DOUT
SCLK
CS
Figure 8. Clock Mode 10—The command byte to the conversion register begins the acquisition (CNVST is not required).
Set CNVST high to begin a conversion. Sampling is
completed approximately 500ns after CNVST goes
high. After the conversion is complete, the ADC shuts
down and pulls EOC low. EOC stays low until CS or
CNVST is pulled low again. Wait until EOC goes low
before pulling CS or CNVST low. The number of CNVST
signals must equal the number of conversions request-
ed by the scan and averaging registers to correctly
update the FIFO. Wait until all conversions are com-
plete before reading the FIFO. SPI communications to
the DAC and GPIO registers are permitted during
conversion. However, coupled noise may result in
degraded ADC SNR.
If averaging is turned on, multiple CNVST pulses need to
be performed before a result is written to the FIFO. Once
the proper number of conversions has been performed
to generate an averaged FIFO result (as specified to the
averaging register), the scan logic automatically switch-
es the analog input multiplexer to the next requested
channel. If a temperature measurement is programmed,
it is performed after the first rising edge of CNVST follow-
ing the command byte written to the conversion register.
The temperature-conversion result is available on DOUT
once EOC has been pulled low.
Internally Timed Acquisitions and
Conversions Using the Serial Interface
ADC Conversions in Clock Mode 10
In clock mode 10, the wake-up, acquisition, conversion,
and shutdown sequence is initiated by writing a com-
mand byte to the conversion register, and is performed
automatically using the internal oscillator. This is the
default clock mode upon power-up. See Figure 8 for
clock mode 10 timing.
Initiate a scan by writing a command byte to the conver-
sion register. The MAX1220/MAX1257/MAX1258 then
power up, scan all requested channels, store the results
in the FIFO, and shut down. After the scan is complete,
EOC is pulled low and the results are available in the
FIFO. If a temperature measurement is requested, the
temperature result precedes all other FIFO results. EOC
stays low until CS is pulled low again. Wait until all con-
versions are complete before reading the FIFO. SPI
communications to the DAC and GPIO registers are per-
mitted during conversion. However, coupled noise may
result in degraded ADC SNR.
Externally Clocked Acquisitions and
Conversions Using the Serial Interface
ADC Conversions in Clock Mode 11
In clock mode 11, acquisitions and conversions are ini-
tiated by writing a command byte to the conversion
register and are performed one at a time using SCLK
as the conversion clock. Scanning, averaging and the
FIFO are disabled, and the conversion result is avail-
able at DOUT during the conversion. Output data is
updated on the rising edge of SCLK in clock mode 11.
See Figures 9a and 9b for clock mode 11 timing.
Initiate a conversion by writing a command byte to the
conversion register followed by 16 SCLK cycles. If CS
is pulsed high between the eighth and ninth cycles, the
pulse width must be less than 100µs. To continuously
convert at 16 cycles per conversion, alternate 1 byte of
zeros (NOP byte) between each conversion byte. If 2
NOP bytes follow a conversion byte, the analog cells
power down at the end of the second NOP. Set the
FBGON bit to one in the reset register to keep the inter-
nal bias block powered.
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
______________________________________________________________________________________ 37
If reference mode 00 is requested, or if an external ref-
erence is selected but a temperature measurement is
being requested, wait 45µs with CS high after writing
the conversion byte to extend the acquisition and allow
the internal reference to power up. To perform a tem-
perature measurement, write 24 bytes (192 cycles) of
zeros after the conversion byte using 8-bit NOP com-
mands each framed by CS (to match production test
method; other length NOP sequences are not produc-
tion tested). The temperature result appears on DOUT
during the last 2 bytes of the 192 cycles. For tempera-
ture conversion in clock mode 11 with the TEMP bit set
in the conversion register, no scanning of AIN0 to
AIN15 is performed. Therefore, the CHSEL[3:0] bits are
don’t cares. These bits can be set to 0000b. When the
conversion is complete, only the temperature data is
available.
Conversion-Time Calculations
The conversion time for each scan is based on a num-
ber of different factors: conversion time per sample,
samples per result, results per scan, if a temperature
measurement is requested, and if the external refer-
ence is in use. Use the following formula to calculate
the total conversion time for an internally timed conver-
sion in clock mode 00 and 10 (see the
Electrical
Characteristics
, as applicable):
Total conversion time =
tCONV x nAVG x nSCAN + tTS + tINT-REF,SU
where:
tCONV = tDOV, where tDOV is dependent on the clock
mode and the reference mode selected
nAVG = samples per result (amount of averaging)
nSCAN = number of times each channel is scanned; set
to one unless [SCAN1, SCAN0] = 10
tTS = time required for temperature measurement
(53.1µs); set to zero if temperature measurement is not
requested
tINT-REF,SU = tWU (external-reference wake-up); if a
conversion using the external reference is requested
In clock mode 01, the total conversion time depends on
how long CNVST is held low or high. Conversion time in
externally clocked mode (CKSEL1, CKSEL0 = 11)
depends on the SCLK period and how long CS is held
high between each set of eight SCLK cycles. In clock
mode 01, the total conversion time does not include the
time required to turn on the internal reference.
DIN
CONVERSION BYTE #1
CONVERSION #1 CONVERSION #2
ACQUISITION #1
MSB1 LSB1 MSB2
ACQUISITION #2
NOP CONVERSION BYTE #2 CONVERSIONNOP
EOC
DOUT
SCLK
CS
Figure 9a. Clock Mode 11—Externally Timed Acquisition, Sampling and Conversion without CNVST for Maximum ADC Throughput
DIN
ACQUISITION CONVERSION
MSB1 LSB1
EOC
DOUT
SCLK
CS
CONVERSION BYTE NOP NOP
Figure 9b. Clock Mode 11—Externally Timed Acquisition, Sampling and Conversion without CNVST to Reduce Analog Power
Dissipation
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
38 ______________________________________________________________________________________
tCSH
SCLK
NOTE: FOR THE MAX1220 GPIO WRITES, n = 16; FOR ALL DAC WRITES AND GPIO WRITES ON THE MAX1257/MAX1258, n = 24.
DIN
DOUT
CS
1234 32
16
8
Dn-1 Dn-2 Dn-3 Dn-4 Dn-5
5
D15
D7
D14
D6
D13
D5
D12
D4
D0
D1 D0
tDOD
tDOT
tCSS
tCSPWH
D1
tDOE
tDS
tDH
tCH
tCL
Figure 10. DAC/GPIO Serial-Interface Timing (Clock Modes 00, 01, and 10)
DAC/GPIO Timing
Figures 10–13 detail the timing diagrams for writing to
the DAC and GPIOs. Figure 10 shows the timing speci-
fications for clock modes 00, 01, and 10. Figure 11
shows the timing specifications for clock mode 11.
Figure 12 details the timing specifications for the DAC
input select register and 2 bytes to follow. Output data
is updated on the rising edge of SCLK in clock mode
11. Figure 13 shows the GPIO timing. Figure 14 shows
the timing details of a hardware LDAC command DAC-
register update. For a software-command DAC-register
update, tSis valid from the rising edge of CS, which fol-
lows the last data bit in the software command word.
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
______________________________________________________________________________________ 39
SCLK
DIN
DOUT
1234
tCSPWH
tCSS
tDOE
tDS
tDH
tDOT
tCL
tCH
tCSH
tDOD
32
16
8
Dn-1 Dn-2 Dn-3 Dn-4 Dn-5
5
D15
D7
D14
D6
D13
D5
D12
D4
D0
D1 D0
D1
CS
NOTE: FOR THE MAX1220 GPIO WRITES, n = 16; FOR ALL DAC WRITES AND GPIO WRITES ON THE MAX1257/MAX1258, n = 24.
Figure 11. DAC/GPIO Serial-Interface Timing (Clock Mode 11)
SCLK
DIN
DOUT
CS
1289 24
BIT 7 (MSB) BIT 6 BIT 0 (LSB)
THE COMMAND BYTE
INITIALIZES THE DAC SELECT
REGISTER
THE NEXT 16 BITS SELECT THE DAC
AND THE DATA WRITTEN TO IT
BIT 15 BIT 14
10
BIT 0BIT 1
Figure 12. DAC-Select Register Byte and DAC Serial-Interface Word
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
40 ______________________________________________________________________________________
GPIO INPUT/OUTPUT
CS
tGSU
tGOD
Figure 13. GPIO Timing
LDAC
tLDACPWL
tS
OUT_
±1 LSB
Figure 14. LDAC Functionality
LDAC Functionality
Drive LDAC low to transfer the content of the input reg-
isters to the DAC registers. Drive LDAC permanently
low to make the DAC register transparent. The DAC
output typically settles from zero to full scale within ±1
LSB after 2µs. See Figure 14.
Layout, Grounding, and Bypassing
For best performance, use PC boards. Ensure that digi-
tal and analog signal lines are separated from each
other. Do not run analog and digital signals parallel to
one another (especially clock signals) or do not run digi-
tal lines underneath the MAX1220/MAX1257/
MAX1258 package. High-frequency noise in the AVDD
power supply may affect performance. Bypass the
AVDD supply with a 0.1µF capacitor to AGND, close to
the AVDD pin. Bypass the DVDD supply with a 0.1µF
capacitor to DGND, close to the DVDD pin. Minimize
capacitor lead lengths for best supply-noise rejection. If
the power supply is very noisy, connect a 10Ωresistor in
series with the supply to improve power-supply filtering.
The MAX1220/MAX1257/MAX1258 thin QFN packages
contain an exposed pad on the underside of the device.
Connect this exposed pad to AGND. Refer to the
MAX1258EVKIT for an example of proper layout.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. INL for
the MAX1220/MAX1257/MAX1258 is measured using
the end-point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
______________________________________________________________________________________ 41
Unipolar ADC Offset Error
For an ideal converter, the first transition occurs at 0.5
LSB, above zero. Offset error is the amount of deviation
between the measured first transition point and the
ideal first transition point.
Bipolar ADC Offset Error
While in bipolar mode, the ADC’s ideal midscale transi-
tion occurs at AGND -0.5 LSB. Bipolar offset error is the
measured deviation from this ideal value.
ADC Gain Error
Gain error is defined as the amount of deviation
between the ideal transfer function and the measured
transfer function, with the offset error removed and with
a full-scale analog input voltage applied to the ADC,
resulting in all ones at DOUT.
DAC Offset Error
DAC offset error is determined by loading a code of all
zeros into the DAC and measuring the analog output
voltage.
DAC Gain Error
DAC gain error is defined as the amount of deviation
between the ideal transfer function and the measured
transfer function, with the offset error removed, when
loading a code of all ones into the DAC.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples.
Aperture Delay
Aperture delay (tAD) is the time between the rising
edge of the sampling clock and the instant when an
actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital sam-
ples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The ideal, theoretical minimum analog-
to-digital noise is caused by quantization error only and
results directly from the ADC’s resolution (N bits):
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is calculated by taking
the ratio of the RMS signal to the RMS noise. RMS noise
includes all spectral components to the Nyquist fre-
quency excluding the fundamental, the first five har-
monics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
SINAD(dB) = 20 x log (SignalRMS / NoiseRMS)
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the ENOB as follows:
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
where V1is the fundamental amplitude, and V2through
V6are the amplitudes of the first five harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest distortion
component.
ADC Channel-to-Channel Crosstalk
Bias the ON channel to midscale. Apply a full-scale sine
wave test tone to all OFF channels. Perform an FFT on
the ON channel. ADC channel-to-channel crosstalk is
expressed in dB as the amplitude of the FFT spur at the
frequency associated with the OFF channel test tone.
Intermodulation Distortion (IMD)
IMD is the total power of the intermodulation products
relative to the total input power when two tones, f1 and
f2, are present at the inputs. The intermodulation prod-
ucts are (f1 ± f2), (2 x f1), (2 x f2), (2 x f1 ± f2), (2 x f2 ±
f1). The individual input tone levels are at -7dBFS.
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an
ADC so the signal’s slew rate does not limit the ADC’s
performance. The input frequency is then swept up to
the point where the amplitude of the digitized conver-
sion result has decreased by -3dB. Note that the T/H
performance is usually the limiting factor for the small-
signal input bandwidth.
THD x VVVVVV= ++++
()
⎡
⎣
⎢⎤
⎦
⎥
20 22324252621
log /
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
42 ______________________________________________________________________________________
AIN0
REF1
GPIOC0
N.C.
LDAC
OUT7
RES_SEL
CS
GPIOC1
EOC
DVDD
DGND
SCLK
DIN
OUT0
GPIOA0
+
+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
AGND
N.C.
OUT4
OUT6
AVDD
OUT3
OUT2
OUT1
REF2/AIN6
AIN5
N.C.
N.C.
AIN4
AIN3
AIN2
AIN1
CNVST/AIN7
TQFN
MAX1220
TOP VIEW
DOUT
OUT5
GPIOA1
AIN2
REF1
AIN0
GPIOC3
GPIOC0
RES_SEL
CS
OUT7
LDAC
GPIOC2
GPIOC1
AIN1
GPIOA1
EOC
GPIOA2
GPIOA3
DVDD
DGND
DOUT
OUT0
SCLK
DIN
GPIOA0
CNVST/AIN15 1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
GPIOB1
AVDD
AGND
GPIOB3
OUT6
OUT5
OUT4
GPIOB0
OUT3
OUT2
OUT1
AIN13
AIN12
AIN11
AIN10
AIN9
AIN8
AIN7
AIN6
AIN5
AIN3
AIN4
REF2/AIN14
TQFN
MAX1257
MAX1258
GPIOB2
48
47
46
45
44
43
42
41
40
39
38
37
13
14
15
16
17
18
19
20
21
22
23
24
Pin Configurations
Full-Power Bandwidth
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as full-
power input bandwidth frequency.
DAC Digital Feedthrough
DAC digital feedthrough is the amount of noise that
appears on the DAC output when the DAC digital con-
trol lines are toggled.
ADC Power-Supply Rejection
ADC power-supply rejection (PSR) is defined as the
shift in offset error when the power supply is moved
from the minimum operating voltage to the maximum
operating voltage.
DAC Power-Supply Rejection
DAC PSR is the amount of change in the converter’s
value at full-scale as the power-supply voltage changes
from its nominal value. PSR assumes the converter’s lin-
earity is unaffected by changes in the power-supply
voltage.
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE OUTLINE NO. LAND
PATTERN NO.
36 TQFN-EP T3666+3 21-0141 90-0050
48 TQFN-EP T4877+6 21-0144 90-0132
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
43
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
5 12/07 Changed timing characteristic specification. 7
Changed the Ordering Information table to show lead(Pb)-free packages. 1
Added Note 18 to the Electrical Characteristics table (tDOV spec). 7, 8
Added the ADDITIONAL NO. OF BYTES column to Table 1. 20
Corrected Figure 8, replaced Figure 9 with Figures 9a and 9b, and modified Figures
10 and 11. 36–39
6 1/10
Updated the ADC Conversions in Clock Mode 11 section. 36
7 2/12 Clarified Note 9. 8
