Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
1
Rev. B
11/21/02
IS61NP12832 IS61NP12836 IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
ISSI®
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
FEATURES
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single R/W (Read/Write) control pin
• Clock controlled, registered address,
data and control
• Interleaved or linear burst sequence control
using MODE input
• Three chip enables for simple depth expansion
and address pipelining for TQFP
• Power Down mode
• Common data inputs and data outputs
•CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP and 119 PBGA packages
• Single +3.3V power supply (± 5%)
• NP Version: 3.3V I/O Supply Voltage
• NLP Version: 2.5V I/O Supply Voltage
• Industrial temperature available
DESCRIPTION
The 4 Meg 'NP' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
network and communications customers. They are
organized as 131,072 words by 32 bits, 131,072 words
by 36 bits and 262,144 words by 18 bits, fabricated with
ISSI's advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the
ADV input. When the ADV is HIGH the internal burst
counter is incremented. New external addresses can be
loaded when ADV is LOW.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when WE is LOW.
Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
128K x 32, 128K x 36 and 256K x 18
PIPELINE 'NO WAIT' STATE BUS SRAM NOVEMBER 2002
FAST ACCESS TIME
Symbol Parameter -150 -133 -100 Units
tKQ Clock Access Time 3.8 4.2 5 ns
tKC Cycle Time 6.7 7.5 10 ns
Frequency 150 133 100 MHz
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. B
11/21/02
IS61NP12832 IS61NP12836 IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618 ISSI
®
BLOCK DIAGRAM
ADV
WE }
BW
Ÿ
X
(X=a,b,c,d or a,b)
CE
CE2
CE2
CONTROL
LOGIC
128Kx32; 128Kx36;
256Kx18
MEMORY ARRAY
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
CONTROL
LOGIC
OUTPUT
REGISTER
BUFFER
ADDRESS
REGISTER
A [0:16] or
A [0:17]
CLK
CKE
A2-A16 or A2-A17
A0-A1 A'0-A'1
BURST
ADDRESS
COUNTER
MODE
DATA-IN
REGISTER
DATA-IN
REGISTER
CONTROL
REGISTER
OE
ZZ 32, 36 or 18
K
K
DQa0-DQd7 or DQa0-DQb8
DQPa-DQPd
K
K
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Rev. B
11/21/02
IS61NP12832 IS61NP12836 IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618 ISSI
®
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCCQ
NC
NC
DQc1
DQc2
VCCQ
DQc5
DQc7
VCCQ
DQd1
DQd4
VCCQ
DQd6
DQd8
NC
NC
VCCQ
A6
CE2
A7
NC
DQc3
DQc4
DQc6
DQc8
VCC
DQd2
DQd3
DQd5
DQd7
NC
A5
NC
NC
A4
A3
A2
GND
GND
GND
BWc
GND
NC
GND
BWd
GND
GND
GND
MODE
A10
NC
NC
ADV
VCC
NC
CE
OE
NC
WE
VCC
CLK
NC
CKE
A1
A0
VCC
A11
NC
A8
A9
A12
GND
GND
GND
BWb
GND
NC
GND
BWa
GND
GND
GND
VCC
A14
NC
A16
CE2
A15
NC
DQb6
DQb5
DQb4
DQb2
VCC
DQa7
DQa5
DQa4
DQa3
NC
A13
NC
NC
VCCQ
NC
NC
DQb8
DQb7
VCCQ
DQb3
DQb1
VCCQ
DQa8
DQa6
VCCQ
DQa2
DQa1
NC
ZZ
VCCQ
1 2 3 4 5 6 7
128K x 32
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2
-
A16 Synchronous Address Inputs
CLK Synchronous Clock
ADV Synchronous Burst Address Advance
BWa-BWd Synchronous Byte Write Enable
WE Write Enable
CKE Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VCC +3.3V Power Supply
GND Ground
VCCQ
I
solated Output Buffer Supply: +3.3V/2.5V
ZZ Snooze Enable
PIN CONFIGURATION
119-pin PBGA (Top View) 100-Pin TQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
VCC
VCC
VCC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
VCC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
A6
A7
CE
CE2
BWd
BWc
BWb
BWa
CE2
VCC
GND
CLK
WE
CKE
OE
ADV
NC
NC
A8
A9
4
Integrated Silicon Solution, Inc. — www.issi.com —
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Rev. B
11/21/02
IS61NP12832 IS61NP12836 IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618 ISSI
®
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCCQ
NC
NC
DQc1
DQc2
VCCQ
DQc5
DQc7
VCCQ
DQd1
DQd4
VCCQ
DQd6
DQd8
NC
NC
VCCQ
A6
CE2
A7
DQPc
DQc3
DQc4
DQc6
DQc8
VCC
DQd2
DQd3
DQd5
DQd7
DQPd
A5
NC
NC
A4
A3
A2
GND
GND
GND
BWc
GND
NC
GND
BWd
GND
GND
GND
MODE
A10
NC
NC
ADV
VCC
NC
CE
OE
NC
WE
VCC
CLK
NC
CKE
A1
A0
VCC
A11
NC
A8
A9
A12
GND
GND
GND
BWb
GND
NC
GND
BWa
GND
GND
GND
VCC
A14
NC
A16
CE2
A15
DQPb
DQb6
DQb5
DQb4
DQb2
VCC
DQa7
DQa5
DQa4
DQa3
DQPa
A13
NC
NC
VCCQ
NC
NC
DQb8
DQb7
VCCQ
DQb3
DQb1
VCCQ
DQa8
DQa6
VCCQ
DQa2
DQa1
NC
ZZ
VCCQ
1 2 3 4 5 6 7
PIN CONFIGURATION
119-pin PBGA (Top View) 100-Pin TQFP
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2
-
A16 Synchronous Address Inputs
CLK Synchronous Clock
ADV Synchronous Burst Address Advance
BWa-BWd Synchronous Byte Write Enable
WE Write Enable
CKE Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VCC +3.3V Power Supply
GND Ground
VCCQ
Isolated Output Buffer Supply: +3.3V/2.5V
ZZ Snooze Enable
DQPa-DQPd Parity Data I/O
128K x 36
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPc
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
VCC
VCC
VCC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
DQPd
DQPb
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
VCC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
DQPa
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
A6
A7
CE
CE2
BWd
BWc
BWb
BWa
CE2
VCC
GND
CLK
WE
CKE
OE
ADV
NC
NC
A8
A9
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Rev. B
11/21/02
IS61NP12832 IS61NP12836 IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618 ISSI
®
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCCQ
NC
NC
DQ9
NC
VCCQ
NC
DQ12
VCCQ
NC
DQ14
VCCQ
DQ16
NC
NC
NC
VCCQ
A6
CE2
A7
NC
DQ10
NC
DQ11
NC
VCC
DQ13
NC
DQ15
NC
DQP2
A5
A10
NC
A4
A3
A2
GND
GND
GND
BWb
GND
NC
GND
NC
GND
GND
GND
MODE
A11
NC
NC
ADV
VCC
NC
CE
OE
A17
WE
VCC
CLK
NC
CKE
A1
A0
VCC
NC
NC
A8
A9
A12
GND
GND
GND
NC
GND
NC
GND
BWa
GND
GND
GND
VCC
A14
NC
A16
CE2
A15
DQP1
NC
DQ7
NC
DQ5
VCC
NC
DQ3
NC
DQ2
NC
A13
NC
NC
VCCQ
NC
NC
NC
DQ8
VCCQ
DQ6
NC
VCCQ
DQ4
NC
VCCQ
NC
DQ1
NC
ZZ
VCCQ
1 2 3 4 5 6 7
PIN CONFIGURATION
119-pin PBGA (Top View) (B) 100-Pin TQFP
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2
-
A17 Synchronous Address Inputs
CLK Synchronous Clock
ADV Synchronous Burst Address Advance
BWa-BWb Synchronous Byte Write Enable
WE Write Enable
CKE Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQ1-DQ16 Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VCC +3.3V Power Supply
GND Ground
VCCQ
Isolated Output Buffer Supply: +3.3V/2.5V
ZZ Snooze Enable
DQP1-DQP2 Parity Data I/O DQP1 is parity for
DQ1-8; DQP2 is parity for DQ9-16
256K x 18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
NC
VCCQ
GND
NC
NC
DQ9
DQ10
GND
VCCQ
DQ11
DQ12
VCC
VCC
VCC
GND
DQ13
DQ14
VCCQ
GND
DQ15
DQ16
DQP2
NC
GND
VCCQ
NC
NC
NC
A10
NC
NC
VCCQ
GND
NC
DQP1
DQ8
DQ7
GND
VCCQ
DQ6
DQ5
GND
VCC
VCC
ZZ
DQ4
DQ3
VCCQ
GND
DQ2
DQ1
NC
NC
GND
VCCQ
NC
NC
NC
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A11
A12
A13
A14
A15
A16
A17
A6
A7
CE
CE2
NC
NC
BWb
BWa
CE2
VCC
GND
CLK
WE
CKE
OE
ADV
NC
NC
A8
A9
6
Integrated Silicon Solution, Inc. — www.issi.com —
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Rev. B
11/21/02
IS61NP12832 IS61NP12836 IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618 ISSI
®
PIN CONFIGURATION
119-pin PBGA (Top View) (B2)
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2
-
A17 Synchronous Address Inputs
CLK Synchronous Clock
ADV Synchronous Burst Address Advance
BWa-BWb Synchronous Byte Write Enable
WE Write Enable
CKE Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQ1-DQ16 Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VCC +3.3V Power Supply
GND Ground
VCCQ
Isolated Output Buffer Supply: +3.3V/2.5V
ZZ Snooze Enable
DQP1-DQP2 Parity Data I/O DQP1 is parity for
DQ1-8; DQP2 is parity for DQ9-16
256K x 18
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCCQ
NC
NC
DQ9
NC
VCCQ
NC
DQ12
VCCQ
NC
DQ14
VCCQ
DQ16
NC
NC
NC
VCCQ
A
CE2
A
NC
DQ10
NC
DQ11
NC
VCC
DQ13
NC
DQ15
NC
DQP2
A
A
NC
A
A
A
GND
GND
GND
BWb
GND
NC
GND
GND
GND
GND
GND
MODE
A
NC
NC
ADV
VCC
NC
CE
OE
NC
WE
VCC
CLK
NC
CKE
A1
A0
VCC
NC
NC
A
A
A
GND
GND
GND
GND
GND
NC
GND
BWa
GND
GND
GND
VCC
A
NC
A
CE2
A
DQP1
NC
DQ7
NC
DQ5
VCC
NC
DQ3
NC
DQ2
NC
A
A
NC
VCCQ
NC
NC
NC
DQ8
VCCQ
DQ6
NC
VCCQ
DQ4
NC
VCCQ
NC
DQ1
NC
ZZ
VCCQ
1 2 3 4 5 6 7
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Rev. B
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IS61NP12832 IS61NP12836 IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618 ISSI
®
SYNCHRONOUS TRUTH TABLE(1)
Address
Operation Used CSCS
CSCS
CS1 CS2 CSCS
CSCS
CS2 ADV WEWE
WEWE
WE BWBW
BWBW
BWxOEOE
OEOE
OE CKECKE
CKECKE
CKE CLK
Not Selected Continue N/A X X X H X X X L ↑
Begin Burst Read External Address L H L L H X L L ↑
Continue Burst Read Next Address X X X H X X L L ↑
NOP/Dummy Read External Address L H L L H X H L ↑
Dummy Read Next Address X X X H X X H L ↑
Begin Burst Write External Address L H L L L L X L ↑
Continue Burst Write Next Address X X X H X L X L ↑
NOP/Write Abort N/A L H L L L H X L ↑
Write Abort Next Address X X X H X H X L ↑
Ignore Clock Current Address X X X X X X X H ↑
Notes:
1. "X" means don't care.
2 . The rising edge of clock is symbolized by ↑
3 . A continue deselect cycle can only be entered if a deselect cycle is executed first.
4. WE = L means Write operation in Write Truth Table.
WE = H means Read operation in Write Truth Table.
5. Operation finally depends on status of asynchronous pins (ZZ and OE).
BURST
READ
DESELECT
BURST
WRITE
BEGIN
READ BEGIN
WRITE
READ
WRITE
READ WRITE
BURST
BURST
BURST
DS
DS
DS
READ
DSDS
READ WRITE
WRITE
BURST BURST
WRITE
READ
STATE DIAGRAM
8
Integrated Silicon Solution, Inc. — www.issi.com —
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Rev. B
11/21/02
IS61NP12832 IS61NP12836 IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618 ISSI
®
ASYNCHRONOUS TRUTH TABLE(1)
Operation ZZ OEOE
OEOE
OE I/O STATUS
Sleep Mode H X High-Z
Read LL DQ
L H High-Z
Write L X Din, High-Z
Deselected L X High-Z
Notes:
1. X means "Don't Care".
2 . For write cycles following read cycles, the output buffers must be disabled with OE,
otherwise data bus contention will occur.
3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle
time.
4. Deselected means power Sleep Mode where stand-by current depends on cycle time.
WRITE TRUTH TABLE (x18)
Operation WEWE
WEWE
WE BWBW
BWBW
BWaBWBW
BWBW
BWb
READ H X X
WRITE BYTE a L L H
WRITE BYTE b L H L
WRITE ALL BYTEs L L L
WRITE ABORT/NOP L H H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
WRITE TRUTH TABLE (x32/x36)
Operation WEWE
WEWE
WE BWBW
BWBW
BWaBWBW
BWBW
BWbBWBW
BWBW
BWcBWBW
BWBW
BWd
READ H X X X X
WRITE BYTE a L L H H H
WRITE BYTE b L H L H H
WRITE BYTE c L H H L H
WRITE BYTE d L H H H L
WRITE ALL BYTEs L L L L L
WRITE ABORT/NOP L H H H H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
Integrated Silicon Solution, Inc. — www.issi.com —
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9
Rev. B
11/21/02
IS61NP12832 IS61NP12836 IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618 ISSI
®
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address
A1 A0 A1 A0 A1 A0 A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
LINEAR BURST ADDRESS TABLE (MODE = GND)
ABSOLUTE MAXIMUM RATINGS(1) (MODE = GND)
Symbol Parameter Value Unit
TSTG Storage Temperature –65 to +150 ° C
PDPower Dissipation 1.6 W
IOUT Output Current (per I/O) 100 mA
VIN, VOUT Voltage Relative to GND for I/O Pins –0.5 to VCCQ + 0.3 V
VIN Voltage Relative to GND for –0.3 to 4.6 V
for Address and Control Inputs
Notes:
1 . Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-
nent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specifi-
cation is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or
electric fields; however, precautions may be taken to avoid application of any voltage higher
than maximum rated voltages to this high-impedance circuit.
3.
This device contains circuitry that will ensure the output devices are in High-Z at power up.
0,0
1,0
0,1A1', A0' = 1,1
10
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. B
11/21/02
IS61NP12832 IS61NP12836 IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618 ISSI
®
OPERATING RANGE
Range Ambient Temperature DEVICE VCC VCCQ
Commercial 0°C to +70°C 61NPXXXXX 3.3V ± 5% 3.3V ± 5%
61NLPXXXXX 3.3V ± 5% 2.5V ± 5%
Industrial -40°C to +85°C 61NPXXXXX 3.3V ± 5% 3.3V ± 5%
61NLPXXXXX 3.3V ± 5% 2.5V ± 5%
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-150 -133 -100
MAX MAX MAX
Symbol Parameter Test Conditions
x18 x32/36 x18 x32/36 x18 x32/36 Uni
t
ICC AC Operating Device Selected, Com. 305 305 290 290 275 275 mA
Supply Current OE = VIH, ZZ ≤ VIL,IND. — — 305 305 290 290
All Inputs ≤ 0.2V OR ≥ VCC – 0.2V,
Cycle Time ≥ tKC min.
ISB Standby Current Device Deselected, COM.9090 8080 7070 mA
TTL Input VCC = Max., Ind. — — 90 90 80 80
All Inputs ≤ 0.2V OR ≥ VCC – 0.2V,
ZZ ≤ VIL, f = Max.
ISBI Standby Current Device Deselected, Com. 10 10 10 10 10 10 mA
CMOS Input VCC = Max., Ind. — — 15 15 15 15
VIN
≤
GND + 0.2V or ≥ VCC – 0.2V
f = 0
Note:
1. MODE pin has an internal pullup and should be tied to Vcc or GND. It exhibits ±30 µA maximum leakage current when
tied to ≤ GND + 0.2V or ≥ Vcc – 0.2V.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
2.5V 3.3V
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
VOH Output HIGH Voltage IOH = –4.0 mA (3.3V VCCQ) 2.0 — 2.4 — V
IOH = 1.0 mA (2.5V VCCQ)
VOL Output LOW Voltage IOL = 8.0 mA (3.3V VCCQ) — 0.4 — 0.4 V
IOL = 1.0 mA (2.5V VCCQ)
VIH Input HIGH Voltage 1.7 VCC + 0.3 2.0 VCC + 0.3 V
VIL Input LOW Voltage –0.3 0.7 –0.3 0.8 V
ILI Input Leakage Current GND ≤ VIN ≤ VCC
(1)
–5 5 –5 5 µA
ILO Output Leakage Current GND ≤ VOUT ≤ VCCQ, OE = VI–5 5 –5 5 µA
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IS61NP12832 IS61NP12836 IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618 ISSI
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3.3V I/O AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 1.5 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1 and 2
3.3V I/O OUTPUT LOAD EQUIVALENT
Z
O = 50Ω
1.5V
50Ω
OUTPUT
317 Ω
5 pF
Including
jig and
scope
351 Ω
OUTPUT
+3.3V
Figure 1 Figure 2
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
12
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2.5V I/O AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 2.5V
Input Rise and Fall Times 1.5 ns
Input and Output Timing 1.25V
and Reference Level
Output Load See Figures 3 and 4
2.5V I/O OUTPUT LOAD EQUIVALENT
ZO = 50Ω
1.25V
50Ω
OUTPUT
1,667 Ω
5 pF
Including
jig and
scope
1,538 Ω
OUTPUT
+2.5V
Figure 3 Figure 4
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Rev. B
11/21/02
IS61NP12832 IS61NP12836 IS61NP25618
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®
READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-150 -133 -100
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
fmax Clock Frequency — 150 — 133 — 100 MHz
tKC Cycle Time 6. 7 — 7. 5 — 1 0 — ns
tKH Clock High Time 2. 5 — 3 — 3 — ns
tKL Clock Low Time 2. 5 — 3 — 3 — ns
tKQ Clock Access Time — 3.8 — 4.2 — 5 ns
tKQX(2) Clock High to Output Invalid 1 .5 — 1. 5 — 1. 5 — ns
tKQLZ(2,3) Clock High to Output Low-Z 0 — 0 — 0 — ns
tKQHZ(2,3) Clock High to Output High-Z — 3 — 3.5 — 3.5 ns
tOEQ Output Enable to Output Valid — 3.8 — 4.2 — 5 ns
tOELZ(2,3) Output Enable to Output Low-Z 0 — 0 — 0 — ns
tOEHZ(2,3) Output Disable to Output High-Z — 3.5 — 3.5 — 3.5 ns
tAS Address Setup Time 1.5 — 1.5 — 1.5 — ns
tWS Read/Write Setup Time 1.5 — 1.5 — 1.5 — ns
tCES Chip Enable Setup Time 1.5 — 1.5 — 1.5 — ns
tSE Clock Enable Setup Time 1. 5 — 1.5 — 1 .5 — ns
tAVS Address Advance Setup Time 1. 5 — 1.5 — 1 .5 — ns
tDS Data Setup Time 2.0 — 2.0 — 2.0 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — ns
tHE Clock EnableHold Time 0.5 — 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — ns
tADVH Address Advance Hold Time 0.5 — 0.5 — 0.5 — ns
tDH Data Hold Time 0.5 — 0.5 — 0.5 — ns
tPDS ZZ High to Power Down — 2 — 2 — 2 cyc
tPUS ZZ Low to Power Down — 2 — 2 — 2 cyc
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
14
Integrated Silicon Solution, Inc. — www.issi.com —
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Rev. B
11/21/02
IS61NP12832 IS61NP12836 IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618 ISSI
®
SLEEP MODE TIMING
Don't Care
Deselect or Read Only Deselect or Read Only
t
RZZI
K
ZZ
Isupply
All Inputs
(except ZZ)
Outputs
(Q)
I
SB2
ZZ setup cycle ZZ recovery cycle
Normal
operation
cycle
t
PDS
t
PUS
t
ZZI
High-Z
SLEEP MODE ELECTRICAL CHARACTERISTICS
Symbol Parameter Conditions Min. Max. Unit
ISB2Current during SLEEP MODE ZZ ≥ Vih 10 mA
tPDS ZZ active to input ignored 2 cycle
tPUS ZZ inactive to input sampled 2 cycle
tZZI ZZ active to SLEEP current 2 cycle
tRZZI ZZ inactive to exit SLEEP current 0 ns
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IS61NP12832 IS61NP12836 IS61NP25618
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®
READ CYCLE TIMING
tDS
Clock
ADV
A16 - A0 or
A17 - A0
WE
CKE
CE
OE
Data Out
A1 A2 A3
tKH tKL
tKC
Q3-3 Q3-4Q3-2Q3-1Q2-4Q2-3Q2-2Q2-1
Don't Care
Undefined
NOTES: WE = L and BWX = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
tOEHZ
tSE tHE
tAS tAH
tWS tWH
tCES tCEH
tADVS tADVH
tKQHZ
tKQ
tOEQ tOEHZ
Q1-1
16
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IS61NP12832 IS61NP12836 IS61NP25618
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®
WRITE CYCLE TIMING
t
DS
t
DH
Clock
ADV
A16 - A0 or
A17 - A0
WE
CKE
CE
OE
Data In
Data Out
A1 A2 A3
t
KH
t
KL
t
KC
t
SE
t
HE
D3-3 D3-4D3-2D3-1D2-4D2-3D2-2D2-1D1-1
Don't Care
Undefined
NOTES: WE = L and BWX = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
t
OEHZ
Q0-3 Q0-4
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IS61NP12832 IS61NP12836 IS61NP25618
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SINGLE READ/WRITE CYCLE TIMING
Clock
CKE
Address
WRITE
CS
ADV
OE
Data Out
Data In D5
t
SE
t
HE
t
KH
t
KL
t
KC
Don't Care
Undefined
NOTES: WRITE = L means WE = L and BWx = L
CS = L means CS
1
= L, CS
2
= H and CS
2
= L
CS = H means CS
1
= H, or CS
1
= L and CS
2
= H, or CS
1
= L and CS
2
= L
D2
t
OELZ
t
OEQ
A1 A2 A3 A4 A5 A6 A7 A8 A9
Q1 Q3 Q4 Q6 Q7
t
DS
t
DH
18
Integrated Silicon Solution, Inc. — www.issi.com —
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11/21/02
IS61NP12832 IS61NP12836 IS61NP25618
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®
CKE CKE
CKE CKE
CKE OPERATION TIMING
A1 A2 A3 A4 A5 A6
Q1 Q3 Q4
Clock
CKE
Address
WRITE
CS
ADV
OE
Data Out
Data In D2
t
SE
t
HE
tKH tKL
tKC
tKQLZ
tKQHZ
tKQ
tDH
tDS
Don't Care
Undefined
NOTES: WRITE = L means WE = L and BWx = L
CS = L means CS
1
= L, CS
2
= H and CS
2
= L
CS = H means CS
1
= H, or CS
1
= L and CS
2
= H, or CS
1
= L and CS
2
= L
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Rev. B
11/21/02
IS61NP12832 IS61NP12836 IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618 ISSI
®
CS CS
CS CS
CS OPERATION TIMING
Don't Care
Undefined
Clock
CKE
Address
WRITE
CS
ADV
OE
Data Out
Data In
t
SE
t
HE
t
KH
t
KL
t
KC
NOTES: WRITE = L means WE = L and BWx = L
CS = L means CS
1
= L, CS
2
= H and CS
2
= L
CS = H means CS
1
= H, or CS
1
= L and CS
2
= H, or CS
1
= L and CS
2
= L
D5
D2
t
DH
t
DS
t
OELZ
t
OEQ
Q1 Q2 Q4
t
KQHZ
t
KQLZ
t
KQ
A1 A2 A3 A4 A5
20
Integrated Silicon Solution, Inc. — www.issi.com —
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Rev. B
11/21/02
IS61NP12832 IS61NP12836 IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618 ISSI
®
ORDERING INFORMATION
(61NPXXXXX)
Commercial Range: 0°C to +70°C
Frequency Order Part Number Package
128Kx32
150 IS61NP12832-150TQ TQFP
133 IS61NP12832-133TQ TQFP
100 IS61NP12832-100TQ TQFP
128Kx36
150 IS61NP12836-150TQ TQFP
IS61NP12836-150B PBGA
133 IS61NP12836-133TQ TQFP
IS61NP12836-133B PBGA
100 IS61NP12836-100TQ TQFP
256Kx18
150 IS61NP25618-150TQ TQFP
IS61NP25618-150B2 PBGA
133 IS61NP25618-133TQ TQFP
IS61NP25618-133B2 PBGA
100 IS61NP25618-100TQ TQFP
Industrial Range: -40°C to +85°C
Frequency Order Part Number Package
128Kx32
133 IS61NP12832-133TQI TQFP
133 IS61NP12832-133BI PBGA
128Kx36
133 IS61NP12836-133TQI TQFP
133 IS61NP12836-133BI PBGA
256Kx18
133 IS61NP25618-133TQI TQFP
133 IS61NP25618-133B2I PBGA
Integrated Silicon Solution, Inc. — www.issi.com —
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Rev. B
11/21/02
IS61NP12832 IS61NP12836 IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618 ISSI
®
ORDERING INFORMATION (61NL
PXXXXX)
Commercial Range: 0°C to +70°C
Frequency Order Part Number Package
128Kx32
133 IS61NLP12832-133TQ TQFP
IS61NLP12832-133B PBGA
128Kx36
133 IS61NLP12836-133TQ TQFP
IS61NLP12836-133B PBGA
150 IS61NLP12836-150TQ TQFP
IS61NLP12836-150B PBGA
256Kx18
133 IS61NLP25618-133TQ TQFP
IS61NLP25618-133B PBGA
IS61NLP25618-133B2 PBGA
150 IS61NLP25618-150TQ TQFP
IS61NLP25618-150B2 PBGA
Industrial Range: -40°C to +85°C
Frequency Order Part Number Package
128Kx32
133 IS61NLP12832-133TQI TQFP
128Kx36
133 IS61NLP12836-133TQI TQFP
133 IS61NLP12836-133BI PBGA
256Kx18
133 IS61NLP25618-133TQI TQFP
133 IS61NLP25618-133B2I PBGA
