SPT9693 WIDE INPUT VOLTAGE, JFET COMPARATOR TECHNICAL DATA MARCH 1, 2001 FEATURES APPLICATIONS * * * * * * * * * * * * * * Common mode range -3.0 to +8.0 V Low input bias current <100 pA Propagation delay 1.5 ns (max) Low offset 25 mV Low feedthrough and crosstalk Differential latch control Automated test equipment High-speed instrumentation Window comparators High-speed timing Line receivers High-speed triggers Threshold detection Peak detection GENERAL DESCRIPTION The SPT9693 is a high-speed, wide common mode voltage, JFET input, dual comparator. It is designed for applications that measure critical timing parameters in which wide common mode input voltages of -3.0 to +8.0 V are required. Propagation delays are constant for overdrives greater than 50 mV. JFET inputs reduce the input bias currents to the nanoamp level, eliminating the need for input drivers and BLOCK DIAGRAM QA QA buffers in most applications. The device has differential analog inputs and complementary logic outputs compatible with ECL systems. Each comparator has a complementary latch enable control that can be driven by standard ECL logic. The SPT9693 is available in 20-contact LCC and 20-lead PLCC packages over the commercial temperature range. It is also available in die form. QB QB GNDB GNDA LEB LEA LEB LEA N/C N/C AVEE(B) AVEE(A) AVCC(B) AVCC(A) INA +INA +INB INB ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 C Supply Voltages (Measured to GND) Positive Supply Voltage (AVCC) ............ -0.5 to +11.0 V Negative Supply Voltage (AVEE) ........... -11.0 to +0.5 V Output Output Current ................................................... 30 mA Temperature Operating Temperature, ambient ................ 0 to +70 C junction......................+150 C Lead Temperature, (soldering 60 seconds) ..... +300 C Storage Temperature ............................ -65 to +150 C Input Voltages Input Common Mode Voltage ................ -6 to +AVCC+1 Differential Input Voltage .................... -12.0 to +12.0 V Input Voltage, Latch Controls ...................... -6 to 0.5 V VIN to AVCC Differential Voltage ............... -16 to +1.0 V VIN to AVEE Differential Voltage ............... +4 to +21.0 V Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. Application of multiple maximum rating conditions at the same time may damage the device. ELECTRICAL SPECIFICATIONS TA = +25 C, AVCC = +10 V, AVEE = -10.0 V, RL = 50 Ohm to -2 V, unless otherwise specified. PARAMETERS DC CHARACTERISTICS Input Offset Voltage Offset Voltage Tempco Input Bias Current Input Bias Current TEST CONDITIONS TEST LEVEL VIN (Common Mode) = 0 TMIN<TA<TMAX TMIN<TA<TMAX VIN (Common Mode) = -3 to +7 V TMIN<TA<TMAX VIN (Common Mode) = +7 to +8 V Input Offset Current Positive Supply Current (Dual) Negative Supply Current (Dual) Positive Supply Voltage, AVCC Negative Supply Voltage, AVEE Input Common Mode Range Latch Enable Common Mode Range Differential Voltage Range Open Loop Gain Differential Input Resistance Input Capacitance Power Supply Sensitivity Common Mode Rejection Ratio Power Dissipation Output High Level Output Low Level I IV V I IV I V V V V I IV I I I TMIN<TA<TMAX Dual ECL 50 Ohms to -2 V ECL 50 Ohms to -2 V TYP MAX UNITS -25 -25 0.0 0.0 50 10 +25 +25 100 mV mV V/C nA 50 150 nA 6 55 10.25 -10.25 +8.0 nA nA mA mA V V V I V V I I IV IV I TMIN<TA<TMAX AVCC=10 V AVEE=-10.0 V MIN 9.75 -9.75 -3.0 1.0 10 3 40 10.0 -10.0 -2.0 50 45 -.98 -1.95 0 10 52 2 1.0 60 60 55 430 610 -.70 -1.65 V V dB G pF dB dB dB mW V V SPT9693 2 3/1/01 ELECTRICAL SPECIFICATIONS TA = +25 C, AVCC = +10 V, AVEE = -10.0 V, RL = 50 Ohm to -2 V, unless otherwise specified. PARAMETERS AC ELECTRICAL PARAMETERS Propagation Delay1 Propagation Delay Tempco Propagation Delay Skew (A vs B) Delay Dispersion from Input Direction Delay Dispersion from Input Common Mode Latch Set-up Time Latch to Output Delay Latch Pulse Width Latch Hold Time Rise Time Fall Time Slew Rate TEST CONDITIONS TEST LEVEL 50 mV O.D., Slew 10 V/ns IV V V V 50 mV O.D. 20% to 80% 20% to 80% MIN TYP MAX UNITS .75 1.25 2 100 50 1.50 ns ps/ C ps ps V 60 V V V V V V V 500 500 500 0 0.45 0.45 5 ps ps ps ps ps ns ns V/ns 1Valid for both high-to-low and low-to-high transitions TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. LEVEL I II III IV V VI TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25 C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 C. Parameter is guaranteed over specified temperature range. SPT9693 3 3/1/01 TYPICAL PERFORMANCE CHARACTERISTICS INPUT OFFSET VOLTAGE vs COMMON MODE VOLTAGE (T=+25 C) 100 +10.0 10 INPUT BIAS CURRENT (nA) INPUT OFFSET VOLTAGE (mV) +6.0 +2.0 2.0 6.0 1.0 0.1 0.01 10.0 3.0 1.6 +0.8 +3.2 +5.6 0.001 +8.0 3.0 COMMON MODE VOLTAGE (V) +0.8 +3.2 +5.6 +8.0 DELAY DISPERSION vs INPUT PULSE WIDTH 50 1500 40 DELAY DISPERSION (ps) 1600 Slope 2 ps/ C 1400 1300 1200 0 1.6 COMMON MODE VOLTAGE (V) PROPAGATION DELAY TIME vs TEMPERATURE PROPAGATION DELAY TIME (ps) INPUT BIAS CURRENT vs COMMON MODE VOLTAGE (+25 C) 30 20 10 +25 +50 +75 +100 +125 +150 0 TEMPERATURE (C) 500 1000 1500 2000 2500 3000 INPUT PULSE WIDTH (ps) SPT9693 4 3/1/01 TYPICAL PERFORMANCE CHARACTERISTICS RISE AND FALL OF OUTPUTS vs TIME CROSSOVER HYSTERESIS vs DLATCH VOLTAGE .90 V Hysteresis (mV) 1.10 40 OUTPUT RISE & FALL (V) HYSTERESIS (mV) 50 30 20 10 30 1.30 1.50 1.70 20 10 0 10 20 VLEVLE (mV) 30 1.90 1.1 1.5 1.9 2.3 2.7 3.5 TIME (ns) PROPAGATION DELAY vs INPUT OVERDRIVE VOLTAGE 1600 Input Slew Rates = 1 V/ns PROPAGATION DELAY TIME (ps) PROPAGATION DELAY TIME (ps) 1500 PROPAGATION DELAY vs COMMON MODE INPUT VOLTAGE = 2 V/ns 1400 = 5 V/ns 1300 1200 1100 1500 1400 1300 1200 50 100 150 200 250 300 350 400 4 VOD (mV) 2 0 +2 +4 +6 +8 VIN, cm (V) SPT9693 5 3/1/01 GENERAL INFORMATION Single-channel operation can be accomplished by floating all pins (including the ground and supply pins) of the unused comparator. Power dissipation during single-channel operation is 50% of the dissipation during dual-channel operation. The SPT9693 is an ultrahigh-speed dual voltage comparator. It offers tight absolute characteristics. The device has differential analog inputs and complementary logic outputs compatible with ECL systems. The output stage is adequate for driving terminated 50 ohm transmission lines. This comparator offers the following improvements over existing devices: The SPT9693 has a complementary latch enable control for each comparator. Both should be driven by standard ECL logic levels. * * * * Ultra low input bias current and input current offset Common mode voltage of -3 to +8 V Short propagation delays Excellent input and output rejection between comparator channels * Improved input protection reliability due to JFET input stage design A common mode voltage range of -3 V to +8 V is achieved by a proprietary JFET input design, which requires a separate negative power supply (AVEE). The dual comparators have separate AVCC, AVEE, and grounds for each comparator to achieve high crosstalk rejection. All of these combined features produce high-performance products with timing stability and repeatability for large system precision. Figure 1 - Internal Function Diagram Q + +IN IN PRE AMP ECL OUT LATCH Q REF 1 AVEE VCC REF 2 CLK BUF GND LE LE SPT9693 6 3/1/01 TYPICAL INTERFACE CIRCUIT techniques must be employed to prevent ringing on the output waveform. Also, the microstriplines must be terminated at the far end with the characteristic impedance of the line to prevent reflections. All supply voltages should be decoupled with high-frequency capacitors as close to the device as possible. If using the SPT9693 as a single comparator, the outputs of the inactive comparator can be grounded, left open or terminated with 50 ohms to -2 V. All outputs on the active comparator, whether used or unused, should have identical terminations to minimize ground current switching transients. The typical interface circuit using the comparator is shown in figure 2. Although it needs few external components and is easy to apply, there are several conditions that should be noted to achieve optimal performance. The very high operating speeds of the comparator require careful layout, decoupling of supplies, and proper design of transmission lines. Since the SPT9693 comparator is a very high-frequency and high-gain device, certain layout rules must be followed to avoid oscillations. The comparator should be soldered to the board with component lead lengths kept as short as possible. A ground plane should be used, while the input impedance to the part is kept as low as possible, to decrease parasitic feedback. If the output board traces are longer than approximately half an inch, microstripline All ground pins should be connected to the same ground plane to further improve noise immunity and shielding. Unused outputs must be terminated with 50 ohms to ground. VRef D2 LE D2 D1 LE 550 W .1 F Q Output RL 50 W RL 50 W VC 5 V .1 F 550 W 2 V Notes: 1) D1 = 1N5231B or 1N751 or equivalent. 2) D2 = 1N914 or equivalent. 3) At no time should both inputs be allowed to float with power applied to the device. At least one of the inputs should be tied to a voltage within the common mode range (3.0 to +8.0 V) to prevent possible damage to the device. Additional protection diodes D2 should be used on the inputs if there is the possibility of exceeding the absolute maximum ratings. VC 5 V Q Output LE LE D2 D1 VRef .1 F AVCC Q Output + D2 VIN D2 D2 Q Output GND AVEE AVEE + VIN Figure 3 - SPT9693 Typical Interface Circuit with Hysteresis .1 F AVCC .1 F D2 D2 GND Figure 2 - SPT9693 Typical Interface Circuit RL 50 W RL 50 W 1.3 V 0.1 F 0.1 F 100 W 2 V 0 to 200 W 2 V Notes: 1) D1 = 1N5231B or 1N751 or equivalent. 2) D2 = 1N914 or equivalent. 3) At no time should both inputs be allowed to float with power applied to the device. At least one of the inputs should be tied to a voltage within the common mode range (3.0 to +8.0 V) to prevent possible damage to the device. Additional protection diodes D2 should be used on the inputs if there is the possibility of exceeding the absolute maximum ratings. SPT9693 7 3/1/01 TIMING INFORMATION after the falling edge for the comparator to accept data. After tH, the output ignores the input status until the latch is strobed again. A minimum latch pulse width of tpL is needed for strobe operation, and the output transitions occur after a time of tpLOH or tpLOL. The timing diagram for the comparator is shown in figure 4. If LE is high and LE low in the SPT9693, the comparator tracks the input difference voltage. When LE is driven low and LE high, the comparator outputs are latched into their existing logic states. The set-up and hold times are a measure of the time required for an input signal to propagate through the first stage of the comparator to reach the latching circuitry. Input signals occurring before tS will be detected and held; those occurring after tH will not be detected. Changes between tS and tH may not be detected. The leading edge of the input signal (which consists of a 150 mV overdrive voltage) changes the comparator output after a time of tpdL or tpdH (Q or Q). The input signal must be maintained for a time tS (set-up time) before the LE falling edge and LE rising edge and held for time tH Figure 4 - Timing Diagram Latch Enable 50% Latch Enable tH tpL tS Differential Input Voltage VRef VOS VOD VIN t pLOH t pdL Output Q 50% 50% Output Q t pdH t pLOL VIN+ = 300 mV, VOD = 150 mV SWITCHING TERMS (Refer to figure 4) tpdH INPUT TO OUTPUT HIGH DELAY - The propagation delay measured from the time the input signal reaches the reference voltage ( the input offset voltage) to the 50% point of an output LOW to HIGH transition. tpdL INPUT TO OUTPUT LOW DELAY - The propagation delay measured from the time the input signal reaches the reference voltage ( the input offset voltage) to the 50% point of an output HIGH to LOW transition. tpLOH LATCH ENABLE TO OUTPUT HIGH DELAY - The propagation delay measured from the 50% point of the Latch Enable signal LOW to HIGH transition to 50% point of an output LOW to HIGH transition. tH MINIMUM HOLD TIME - The minimum time after the negative transition of the Latch Enable signal that the input signal must remain unchanged in order to be acquired and held at the outputs. tpL MINIMUM LATCH ENABLE PULSE WIDTH - The minimum time that the Latch Enable signal must be HIGH in order to acquire an input signal change. tS MINIMUM SET-UP TIME - The minimum time before the negative transition of the Latch Enable signal that an input signal change must be present in order to be acquired and held at the outputs. VOD VOLTAGE OVERDRIVE - The difference between the differential input and reference input voltages. tpLOL LATCH ENABLE TO OUTPUT LOW DELAY - The propagation delay measured from the 50% point of the Latch Enable signal LOW to HIGH transition to the 50% point of an output HIGH to LOW transition. SPT9693 8 3/1/01 PACKAGE OUTLINES 20-Contact Leadless Chip Carrier (LCC) H A INCHES SYMBOL A B C D E F G H G B Bottom View Pin 1 C F MIN MAX .040 typ .050 typ 0.045 0.345 0.054 0.055 0.360 0.066 .020 typ 0.022 0.028 0.075 MILLIMETERS MIN MAX 1.02 typ 1.27 typ 1.14 1.40 8.76 9.14 1.37 1.68 0.51 typ 0.56 0.71 1.91 D E 20-Lead Plastic Leadless Chip Carrier (PLCC) A G INCHES SYMBOL A B C D E F G H I J K L M N O B Pin 1 N TOP VIEW M O E F L C D H I J K Pin 1 MIN MAX .045 typ .045 typ 0.350 0.385 0.350 0.385 0.042 0.165 0.085 0.025 0.015 0.026 0.013 0.290 0.356 0.395 0.356 0.395 0.056 0.180 0.110 0.040 0.025 0.032 0.021 0.050 0.330 MILLIMETERS MIN MAX 1.14 typ 1.14 typ 8.89 9.04 9.78 10.03 8.89 9.04 9.78 10.03 1.07 1.42 4.19 4.57 2.16 2.79 0.64 1.02 0.38 0.64 0.66 0.81 0.33 0.53 1.27 7.37 8.38 BOTTOM VIEW SPT9693 9 3/1/01 PIN ASSIGNMENTS QA 3 GNDA LEA LEA QA 2 PIN FUNCTIONS QB 1 QB GNDB 20 19 18 LEB 4 17 LEB 5 16 N/C TOP VIEW LCC/PLCC 6 N/C 7 15 AVEE(B) AVEE(A) 8 14 AVCC(B) 9 10 11 12 13 AVCC(A) INA +INA +INB INB NAME FUNCTION QA Output A QA Inverted Output A GNDA Ground A LEA Inverted Latch Enable A LEA Latch Enable A AVCC(A) Positive Supply Voltage (+10 V) AVEE(A) Negative Supply Voltage (-10 V) AVCC(B) Positive Supply Voltage (+10 V) AVEE(B) Negative Supply Voltage (-10 V) -INA Inverting Input A +INA Noninverting Input A +INB Noninverting Input B -INB Inverting Input B LEB Inverted Latch Enabled B LEB Latch Enable B GNDB Ground B QB Inverted Output B QB Output B N/C Not Connected ORDERING INFORMATION PART NUMBER SPT9693SCC SPT9693SCP SPT9693SCU TEMPERATURE RANGE 0 to +70 C 0 to +70 C +25 C PACKAGE TYPE LCC PLCC Die* *Please see the die specification for guaranteed electrical performance. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com (c) Copyright 2002 Fairchild Semiconductor Corporation SPT9693 10 3/1/01