Wireless Components
ASK/FSK 915MHz Single Conversion Receiver
TDA 5212 Version 1.3
Specif ication December 2006
Edition 12.06
Published by Infineon Technologies AG,
Am Campeon 1-12,
85579 N eubib er g
© Infineon Technologies AG December 2006.
All Rights Reserved.
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Revision History
Current Version: 1 .3 as of 12.12.06
Previous Version: 1.2
Page
(in previo us
Version)
Page
(in current
Version)
Subjects (ma jor changes si nce last rev is ion )
3-4, 5-12 3-4, 5-12 Correction of some typing mistakes
Product
Info, 2-3 Product
Inf o, 2-3 Change of package name to PG-TSSOP-28
Product Info
Produ ct Info
Wireless Components
Specific ati on, D ece mb er 2006
Package
TDA 5212
Product Info
General Description The IC is a very lo w power consump-
tion single chip FSK/ASK Superhet-
erodyne Receiver (SHR) for the re-
ceive frequency range between 902
and 92 8 MHz that is pin co mpatib le to
the ASK Receiver TDA5202. The IC
offers a high level of integration and
needs only a few external compo-
nents. The device contains a low noise
amplifier (LNA), a double balanced
mixer, a fully integrated VCO, a PLL
synthesiser, a crystal oscillator, a lim-
iter with RSSI generator, a PLL FSK
demodulator, a data filter, a data com-
parator (slicer) and a peak detector.
Additionally there is a power down fea-
ture to save battery life.
Features ■Low supply current (Is = 5.4 mA typ.
in FSK mode, Is = 4.8 mA typ. in
ASK mode)
■Supply voltage range 5 V ±10%
■Power down mode with very low
supply current (90 nA typ.)
■FSK and ASK demodulation capa-
bility
■Fully integrated VCO and PLL
Synthesiser
■ASK sensitivity better than
-109 dBm over specified tempera-
ture range (- 40 to +85°C)
■Receive frequency range 902 to
928 MHz
■Limiter with RSSI generation,
operating at 10.7 MHz
■Selectab le reference frequency
■2nd order low pass data filter with
external capacitors
■Data slicer with self-adjusting
threshold
■FSK sensitivity better than
-102 dBm over specified tempera-
ture range (- 40 to +85°C)
Application ■Keyless Entry Systems
■Remote Control Systems
■Low Bitrate ISM-band Communica-
tion Systems
Ordering Information
Type Ordering Code Package
TDA 5212 SP000013430 PG-TSSOP-28
samples available
1Table of Co ntents
1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-i
2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.4 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.4.1 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.4.2 Mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.4.3 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.4.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.4.5 Limiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.4.6 FSK Demodulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.4.7 Data Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.4.8 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.4.9 Peak Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.4.10 Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
4.1 Choice of LNA Threshold Voltage and Time Constant. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2 Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.3 Crystal Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.4 Crystal Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.5 Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.6 ASK/FSK Switch Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.6.1 FSK Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.6.2 ASK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4.7 Principle of the Precharge Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
5 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 -4
5.2 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.3 Test Board Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-10
5.4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
6 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-i
7 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-i
2Product Description
2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Contents of this Chapter
Product Description
2 - 2
TDA 5212
Wireless Components
Specific ati on, D ece mb er 2006
2.1 Overview
The IC is a very low power consumption single chip FSK/ASK Superheterodyne
Receiv er (SHR) fo r receiv e frequenci es between 902 and 928 MHz that is pin
compatible to the ASK Receiver TDA5202. The IC offers a high level of integra-
tion and needs only a few external components. The device contains a low
noise amp lifier (L NA), a double balanc ed mixer, a full y integrated VC O, a PLL
synthesiser, a crystal oscillator, a limiter with RSSI generator, a PLL FSK
demodulator, a data filter, a data comparator (slicer) and a peak detector. Addi-
tionally there is a power down feature to save battery life.
2.2 Application
■Keyless Entry Systems
■Remote Control Systems
■Low Bitrate ISM-band Communication Systems
2.3 Features
■Low supply current (Is = 5.4 mA typ.FSK mode, 4.8 mA typ. ASK mode)
■Supply voltage range 5V ±10%
■Power down mode with very low supply current (90nA typ.)
■FSK and ASK demodulation capability
■Fully integrated VCO and PLL Synthesiser
■RF input sensitivity ASK -112dBm typ. at 25°C, better than -109dBm over
complete specified operating temperature range (-40 to +85°C)
■RF input sensitivity FSK -105dBm typ. at 25°C, better than -102dBm over
complete specified operating temperature range (-40 to +85°C)
■Receive frequency range between 902 and 928 MHz
■Selectable reference frequency
■Limiter with RSSI generation, operating at 10.7MHz
■2nd order low pass data filter with external capacitors
■Data slicer with self-adjusting threshold
Product Description
2 - 3
TDA 5212
Wireless Components
Specific ati on, D ece mb er 2006
2.4 Package Outlines
P_TSSOP_28.EPS
Figure 2-1 PG-TSSOP-28 pac kage outl in es
3Functional Description
3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.4 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Contents of this Chapter
Functional Description
3 - 2
TDA 5212
Wireless Components
Specific ati on, D ece mb er 2006
3.1 Pin Configuration
Pin_Configuration_5212_V1.0.wmf
Figure 3-1 IC Pin Co nfi gur atio n
CRST2
PDWN
PDO
DATA
3VOUT
THRES
FFB
OPP
SLN
SLP
LIMX
LIM
CSEL
MSEL
CRST1
VCC
LNI
TAGC
AGND
LNO
VCC
MI
MIX
AGND
FSEL
IFO
DGND
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TDA 5212
Functional Description
3 - 3
TDA 5212
Wireless Components
Specific ati on, D ece mb er 2006
3.2 Pin Definition and Function
Table 3-1 Pin Definition and Function
Pin No. Symbol Equivalent I/O-Schematic Function
1CRST1 External Crystal Connector 1
2VCC 5V Supply
3LNI LNA Input
4.15V
50uA
1
57uA
4k
1k
3
500uA
Functional Description
3 - 4
TDA 5212
Wireless Components
Specific ati on, D ece mb er 2006
6
1k
5V
4TAGC AGC Time Constant Control
5AGND Analogue Gro und Retu rn
6LNO LNA Output
7VCC 5V Supply
8
9
MI
MIX
Mixer Input
Complementar y Mixe r Input
10 AGND Analogue Gro und Retu rn
11 BUF Mixer Buffer Ground
1k
4.2uA
1.5uA
1.7V
4.3V
4
6
1k
5V
8
1.7V
9
400uA
2k 2k
Functional Description
3 - 5
TDA 5212
Wireless Components
Specific ati on, D ece mb er 2006
2.2V
4.5k
60
12
300uA
12 IFO 10.7 MHz IF Mixer Output
13 DGND Digital Ground Return
14 VDD 5V Supply (PLL Counter Cir-
cuitry)
15 MSEL ASK/FSK Modulati on Format
Selector
16 CSEL 7.xx or 14.xx MHz Quartz
Selector
2.2V
4.5k
60
12
300uA
15
1.2V
3.6k
1.2V
80k
16
Functional Description
3 - 6
TDA 5212
Wireless Components
Specific ati on, D ece mb er 2006
17
18
LIM
LIMX
Limiter Input
Complementary Limi ter Input
19 SLP Data Slicer Positive Input
20 SLN Data Slicer Negative Input
330
15k
15k
18
17
2.4V
75uA
19
80µA
15uA
3k
100
5uA
20 10k
Functional Description
3 - 7
TDA 5212
Wireless Components
Specific ati on, D ece mb er 2006
21 OPP OpAmp Noninverting Input
22 FFB Data Filter Feedback Pin
23 THRES AGC Threshold Input
24 3VOUT 3V Reference Output
21 200
5uA
100k
5uA
22
10k
5uA
23
3.1V
24 20k
Ω
Functional Description
3 - 8
TDA 5212
Wireless Components
Specific ati on, D ece mb er 2006
25 DATA Data Output
26 PDO Peak Detector Output
27 PDWN Power Down Input
28 CRST2 External Crystal Connector 2
25 500
40k
26 200
27
220k
220k
4.15V
50uA
28
Functional Description
3 - 9
TDA 5212
Wireless Components
Specific ati on, D ece mb er 2006
3.3 Functional Block Diagram
Functional_diagram_5212.wmf
Figure 3-2 Main Block Diagram
PDO
BUF VCO : 128 / 64 Φ
DET CRYSTAL
OSC
DATA
Crystal
PDWN
CSELBUF
Loop
Filter Bandgap
Reference
UREF
LNA
RF
-
+
SLICER
TAGC
TDA 5212
TDA 5212
TDA 5212
VCC
VCC AGND
AGC
Reference
THRES
3VOUT
FSK
PLL Demod
OTA
PEAK
DETECTOR
LNI
DGND
-
+
MIXLNO MI OPPFFB SLP
VCC
LIM LIMX
IF
Filter
IFO SLN
MSEL
LIMITER
68912 1718 22 21 19 20
25
26
23
24
3
4
14
13 2,7 5,10 11
15
16 1 28 27
-
+ASK
FSK
OP
+
-
Functional Description
3 - 10
TDA 5212
Wireless Components
Specific ati on, D ece mb er 2006
3.4 Functional Blocks
3.4.1 Low Noise Amplifier (LNA)
The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB. The
gain fig ure i s determi ned by the exter nal matc hing ne tworks s ituated ah ead of
LNA and between the LNA output LNO (Pin 6) and the Mixer Inputs MI and MIX
(Pins 8 and 9). The noise figure of the LNA is approximately 2dB, the current
consum ption is 500 µA. The g ain can b e reduce d by approx imately 18 dB. The
swit ching point o f this AG C action can be determ ined exte rnally by applyin g a
threshold voltage at the THRES pin (Pin 23). This voltage is compared internally
with the re ceived sign al (RSSI) le vel gener ated by the li miter circui try. In case
that the RSSI level is higher than the threshold voltage the LNA gain is reduced
and vice versa. The threshold voltage can be generated by attaching a voltage
divider between the 3VOUT pin (Pi n 24) which provides a t emperature s table
3V outpu t gen er ate d from the int er nal ban dgap voltage and the THRES pi n a s
described in Section 4.1. The time constant of the AGC action can be deter-
mined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen
along with the appr opriate thre shold volta ge according to the intended operat-
ing cas e and interference s cenario to be expe cted during oper ation. The opti-
mum choice of AGC time constant and the threshold voltage is described in
Section 4.1.
3.4.2 Mixer
The Double Balanced Mixer downconverts the input frequency (RF) in the
range of 90 2 to 928 MHz to the inter mediat e freque ncy (IF ) at 10.7MH z with a
voltage gain of a pproximate ly 18 dB . A low pas s filter w ith a corne r frequenc y
of 20MHz is built on chip in order to suppress RF signals to appear at the IF out-
put ( IFO pin). The IF output is internally cons isting of an emitte r follower that
has a so ur ce i mpe dan ce o f a ppr oximately 33 0Ω to fa cili tate i nterfa cing the pi n
directly to a standard 10.7MHz ceramic filter without additional matching cir-
cuitry.
3.4.3 PLL Synthesizer
The Phase Locked Loop synthesiser consists of a VCO, an asynchronous
divide r chain, a ph ase detector wi th charge pump and a l oop filter and is fully
implemented on-chip. The VCO is including spiral inductors and varactor
diodes . The osc ill ator sig nal is fe d both to the sy nthes iser di vide r chain and to
the downconverting mixer via a buffer amplifier. The BUF pin (P in 11) h as to be
tied to gro und . No add iti on al c omp one nts ar e nec essa r y. The loop fil ter is als o
realised fully on-chip.
Using high side injection of the local oscillator (L0) for receiving frequencies
below 921MHz and low side injection for frequencies above 921MHz, the
receivi ng frequen cy band of 902 to 928MH z can be cov ered du e to the L0 fre-
Functional Description
3 - 11
TDA 5212
Wireless Components
Specific ati on, D ece mb er 2006
quency band of 910 to 932MHz. But please note that using high side injetion of
the L0 yields a sign inversion of the demodulated data signal in case of FSK.
See also Section 4.4.
3.4.4 Cry stal Osci llator
The on-chip crystal oscillator circuitry allows for utilisation of quartzes both in
the 7 and 14MHz range as the overall division ratio of the PLL can be switched
between 64 and 128 via the CSEL (Pin 16 ) pin according to the following table.
The c al cu l at i on of t he v al u e of t h e nece ss ary qu ar tz lo a d ca pa ci t a nc e i s s h ow n
in Section 4.3, the quartz frequency calculation is expained in Section 4.4.
3.4.5 Limiter
The Limiter is an AC coupled multistage amplifier with a cumulative gain of
approximately 80dB that has a bandpass-characteristic centred around
10.7M Hz. It has an inpu t impedanc e of 330Ω to allo w for easy interfac ing to a
10.7M Hz ce ram ic IF fil ter . The li mi ter ci r cuit ac ts as a R eceiv e S ign al Streng th
Indicator (RSSI) generator which produces a DC voltage that is directly propor-
tional to the inpu t si gna l leve l as c an be seen in Figu re 4.2. Thi s si gn al is us ed
to demodulate the ASK receive signal in the subsequent baseband circuitry and
to turn down the LNA gain by approximately 18dB in case the input signal
strength is too strong as described in Section 3.4.1 and Section 4.1.
3.4.6 FSK Demodulator
To demodulate frequency shift keyed (FSK) signals a PLL circuit is used that is
contain ed fully on c hi p. T he Li mit er outp u t d iffere nti al signal is f ed to the li near
phase detector as is the output of the 10.7MHz center frequency VCO. The
demodul ator gain is typically 200µV/kHz. Th e passive loop filter output that is
comprised fully on chip is fed to both the VCO and the modulation format
swit ch.This si gnal is repr esenting the d emodul ated signal. T his switch i s actu-
ally a switchable amplifier with an AC gain of 11 that is controlled by the MSEL
Table 3-2 CSEL Pin Operating States
CSEL Crystal Frequency
Open 7.xx MHz
Shorted to ground 14.xx MHz
Functional Description
3 - 12
TDA 5212
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pin (Pin 15) as shown in the fol lowing table. This gain was chosen to fac ilitate
detection in the subsequent circuits.
The DC gain is 1 in order not to saturate the subsequent Data Filter wih the DC
offset produced by the demodulator in case of large frequency offsets of the IF
signal. The resulting frequency characteristic and details on the principle of
operation of the switch are described in Section 4.6. The demodulator circuit is
switched off in case of reception of ASK signals.
3.4.7 Data Filter
The data filter comprises an OP-Amp with a bandwidth of 100kHz used as a
voltage follower and two 100kΩ on-chip resistors. Along with two external
capacitors a 2nd order Sallen-Key low pass filter is formed. The selection of the
capacitor values is described in Section 4.2.
3.4.8 Data Slicer
The da ta slicer is a fast compa rator with a b andwidth of 100 kHz. Thi s allows
for a maximum receive data rate of approximately 120kBaud. The maximum
achievable data rate also depends on the IF Filter bandwidth and the local oscil-
lator toler an ce values . B oth inpu ts a re acces s ible. T he outp ut del iver s a dig ital
data signal (CMOS-like levels) for the detector. The self-adjusting threshold on
pin 20 its generate d by RC-ter m or peak detecto r dependi ng on the baseband
coding scheme. The data slicer threshold generation alternatives are described
in more detail in Section 4.5.
3.4. 9 Peak Det ect or
The peak detector generates a DC voltage which is proportional to the peak
value of the receive data signal. An external RC network is necessary. The input
is co nnecte d to the output of the RSSI- output of the Limite r, the output is con-
nec ted to t he PDO pin (Pin 26 ). This output can be used as an indicator for the
received signal strength to use in wake-up circuits and as a reference for the
data slicer in ASK mode. Note that the RSSI level is also output in case of FSK
mode.
Table 3-3 MSEL Pin Operating States
MSEL Modulation Format
Open ASK
Shorted to ground FSK
Functional Description
3 - 13
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3.4.10 Bandgap Reference Circuitry
A Band gap Re fer enc e Circ ui t p rovi des a tempe ra ture stable reference vo ltage
for the device. A power down mode is available to switch off all subcircuits which
is controlled by the PWDN pin (Pin 27) as shown in the following table. The sup-
ply current drawn in this case is typically 90nA.
Table 3-4 PDWN Pin Operating States
PDWN Operating State
Open or tied to groun d Powerdown Mode
Tied to Vs Receiver On
4Applications
4.1 Choice of LNA Threshold Voltage and Time Constant. . . . . . . . . . . . 4-2
4.2 Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.3 Crystal Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.4 Crystal Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.5 Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.6 ASK/FSK Switch Functional Description . . . . . . . . . . . . . . . . . . . . . . 4-8
4.7 Principle of the Precharge Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Contents of this Chapter
Applications
4 - 2
TDA 5212
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4.1 Choice of LNA Threshold Voltage and Time Constant
In the fol lowi ng fig ure th e interna l circ uit ry of the L N A a uto mati c gai n c ontro l i s
shown.
LNA_autom.wmf
Figure 4-1 LNA Automatic Gain Control Circuitry
The LNA autom atic gain con trol circuitr y consis ts of an operational transimpe-
dance amplifier that is used to compare the received signal strength signal
(RSSI) gen erated by the Limiter with an externally provided threshold voltage
Uthres. As shown in the following figure the threshold voltage can have any
value b etween approxi mately 0.8 and 2. 8V to provide a switching poi nt within
the receive signal dynamic range.
This v olt age U thres is appl ied to the THRES pin (Pin 23) The threshol d volta ge
can be generated by attachin g a voltage divider between the 3VOUT pin (i.e.
Pin 24) which provides a temperature stable 3V output generated from the inter-
nal bandgap voltage and the THRES pin. If the RSSI level generated by the
Limiter is hig her than Uthres, the OTA ge nerates a positiv e current Iload. This
yields a voltage rise on the TAGC pin (Pin 4). Otherwise, the OTA generates a
negative current. These currents do not have the same values in order to
achieve a fast-attack and slow-release action of the AGC and are used to
charg e an ex te rnal c apa ci tor whi ch finally g ene ra tes the LN A ga in c ont ro l v olt-
age.
4
LNA
RSSI (0.8 - 2.8V)
VCC
Gain control
voltage
OTA
+3 . 1 V
I
load
RSSI > U
threshold
: I
load
=4.2µA
RSSI < U
threshold
: I
load
= -1 .5µA
U
C
C
U
c
:< 2.6V : Gain high
U
c
:> 2.6V : Gain low
U
cmax
= V
CC
- 0.7V
U
cmin
= 1.67V
R1 R2
Pins: 24 23
U
threshold
20k
Ω
Applications
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RSSI-AGC.wmf
Figure 4-2 RSSI Level and Permissive AGC Threshold Levels
The switching point should be chosen according to the intended operating sce-
nario. The determination of the optimum point is described in the accompanying
Application Note, a threshold voltage level of 1.8V is apparently a viable choice.
It sh ould be note d that the out put of the 3VOUT pin is capable o f driv ing up to
50µA, but that the THRES pin input current is only in the region of 40nA. As the
current drawn out of the 3VOUT pin is directly related to the receiver power con-
sumption, the power divider resistors should have high impedance values. The
sum of R1 and R2 has to b e 600k Ω in or der to y ield 3V at the 3VOUT pin. R1
can thus be chos en as 240kΩ, R2 as 360k Ω to yield an ov erall 3VOUT output
current of 5µA1 and a threshold voltage of 1.8V
Note: If the LNA gain sha ll b e ke pt in eith er hig h or low gain mode this has to
be accomplished by tying the THRES pin to a fixed voltage. In order to achieve
high gain mode operation, a voltage higher than 2.8V shall be applied to the
THRES pin, such as a short to the 3VOLT pin. In order to achieve low gain
mode operation a voltage lower than 0.7V shall be applied to the THRES, such
as a short to ground.
As stated above the capacitor connected to the TAGC pin is generating the gain
contro l volt age of the LNA due to the c hargi ng and di scharg ing cu rrents o f the
OTA and thus is al so responsi ble for the AG C time constan t. As the ch arging
and dischar ging currents are not equ al two different time cons tants will result.
The time constant corresponding to the charging process of the capacitor shall
be cho sen accordi ng to the data rate. Ac cording to m easurements performed
at Infineon the capacitor value should be greater than 47nF.
1. note the 20kΩ resistor in series with the 3.1V internal voltage source
LNA alw ays
in high gain mode
0
0.5
1
1.5
2
2.5
3
-120 -110 -100 -90 -80 -70 -60 -50 -40 -30
Input Level at LNA Input [dB m]
UTHRES Voltage Range
RSSI Level Range LNA always
in low ga in mode
RSSI Level
Applications
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4.2 D ata Filter Design
Utilising the on-board voltage follower and the two 100kΩ on-chip resistors a
2nd order Sallen-Key low pass data filter can be constructed by adding 2 exter-
nal capacitors between pins 19 (SLP) and 22 (FFB) and to pin 21 (OPP) as
depicted in the following figure and described in the following formulas1.
Filter_Design.wmf
Figure 4-3 Data Filter D esign
with
the quality factor of the poles
where
in case of a Bessel filter a = 1.3617, b = 0.618
and thus Q = 0.577
and in case of a Butterworth filter a = 1.141, b = 1
and thus Q = 0.71
Example: Butterworth fil ter with f3dB = 5kHz and R = 100kΩ:
C1 = 450pF, C2 = 225pF
1. taken from Tietze/Schenk: Halbleiterschaltungstechnik, Springer Berlin, 1999
Pins: 22 21 19
RR
100k 100k
C
1
C
2
dB
fR bQ
C3
2
2
1Π
=dB
fQR b
C3
4
2Π
=
a
b
Q=
Applications
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4.3 Crystal Load Capacitance Calculation
The value of the capacitor necessary to achieve that the crystal oscillator is
operating at the intended frequency is determined by the reactive part of the
negative resistance of the oscillator circuit as shown in Section 5.1.3 and by the
crystal specifications given by the crystal manufacturer.
Quartz_load_5212.wmf
Figure 4-4 Determination of Series Capacitance Value for the Crystal Oscillator
Crystal specified with load capacitance
with CL the l oad capacitance (refer to the crystal specification).
Examples:
7.2 MHz: CL = 12 pF XL=500 ΩCS = 9.5 pF
14.5 MHz: CL = 12 pF XL=1050 ΩCS = 5.6 pF
These values may be obtained in high accuracy by putting two capacitors in
series to the quartz, such as 18pF and 20pF in the 7.2MHz case and 18pF and
8.2pF in the 14.5MHz case. But please note that the calculated value for CS
includes also all parasitic capacitors.
C
S
Crystal Input
impedance
Z
1-28
TDA5212
Pin 28
Pin 1
L
L
SXf
C
C
π
2
11
+
=
Applications
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4.4 Crystal Frequency Calculation
As mentioned in Section 3.4.3 the local oscillator (UHF PLL) signal has to be
high-side injected for a RF below 921MHz and low-side injected for a RF above
921MHz into the downconverting mixer. Thus the crystal frequency is calcu-
lated by using the following formula:
with ƒRF .... receive frequency
ƒLO .... local oscillator (PLL) frequency (ƒRF ± 10.7)
ƒQU .... crystal oscillator frequency
r .... ratio of local oscillator (PLL) frequency and crystal
frequency as shown in the subsequent table.
This yields the following calculation for a RF of 915MHz for instance:
CSEL tied to GND1:
Table 4-1 PLL Division Ratio Dependence on States of CSEL
CSEL Ratio r = (fLO/fQU)
open 128
GND 64
1.In the Infineon Evalboard the L0 is used in low side injection mode and therefore
crystal with 14.1296875MHz is used. But to guarantee the function over the whole
temperature range the L0 has to be used in high side injection mode for a RF of
915MHz (see also VDO frequency range).
r
f
fRF
QU 7.10±
=
MHz
MHzMHz
fQU 4641.14
64 7.10915 =
+
=
Applications
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4.5 D ata Slicer Threshold Generation
The threshold of the data slicer can be generated in two ways, depending on
the signa l c odi ng sch eme use d. In c ase of a si gna l c odi ng s cheme w ithout DC
content such as Manchester coding the threshold can be generated using an
external R-C integrator as shown in Figure 4-5. The time constant TA of the R-
C integrator has to be significantly larger than the longest period of no signal
change TL within the data sequence. For the calculation of the time constant TA
please see Application Note „TDA521X_ANV1.1.“ chapter „4.11. Data Slicer“.
In order to keep distortion low, the minimum value for R is 20kΩ.
Data_slice1.wmf
Figure 4-5 Data Slicer Threshold Generation with External R-C Integrator
Another possibili ty for thresh old gene ration is to use the peak de tector in con-
nection with two resistors and one capacitor as shown in the following figure.
The c ompone nt va lues are dep ending on th e cod ing s cheme a nd the proto col
used.
Data_slice2.wmf
Figure 4-6 Data Slicer Threshold Generation Utilising the Peak Detector
Pins: 2019
R
C
25
data out
U
threshold
data slicer
data
filter
Pins: 20
19 25
data out
U
threshold
data slicer
data
filter
26
peak detector
CR
R
Applications
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4.6 A SK/FSK Switch Functional Description
The TDA5211 is containing an ASK/FSK switch which can be controlled via Pin
15 (MSEL). This switch is actually consisting of 2 operational amplifiers that are
having a g ain of 1 in ca se o f the A SK am plifie r and a g ain of 11 in ca se of t he
FSK amp lifier in or der to achieve an app ropr iate demo dulation gai n characte r-
istic . In order to c ompensa te for the DC -offset gener ated espe cially in case of
the FS K P LL dem odu la tor the re is a fee dba ck c onn ec tion be twee n th e thr e sh-
old voltage of the bit slicer comparator (Pin 20) to the negative input of the FSK
switch amplifier. This is shown in the figure below:
ask_fsk_datapath.WMF
Figure 4-7 ASK/FSK mode datapath
4.6.1 FSK Mode
The FSK datapath has a bandpass characterisitc due to the feedback shown
above (highpass) and the data filter (lowpass). The lower cutoff frequency f2 is
determined by the external RC-combination. The upper cutoff frequency f3 is
determined by the data filter bandwidth.
The demodulation gain of the FSK PLL demodulator is 200µV/kHz. This gain is
increased by the gain v of the FSK switch, which is 11. Therefore the resulting
dynamic gain of this circuit is 2.2mV/kHz round about within the bandpass. The
R
1
=100k R
2
=100k
v = 1
19
R
4
=30k
R
3
=300k
DATA Out
AC DC
typ. 2 V
1.5 V......2.5 V
0.18 mV/kHz
FSK PLL De modulator
RSSI (ASK sign al)
C
1
R
ASK/FSK Switch
ASK
FSK
+
-
+
-
22
25
C
C
2
20
ASK mode : v=1
FSK mode : v=11
21
15 MSEL
FFB OPP SLP SLN
Comp
-
+
Data Filter
Applications
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gain for the DC content of FSK signal remains at 200µV/kHz. The cutoff fre-
quencies of the bandpass have to be chosen such that the spectrum of the data
signal is influenced in an acceptable amount.
In case that the user data is containing long sequences of logical zeros the
effect of the drift-off of the bit slicer threshold voltage can be lowered if the offset
voltage inher ent at the negativ e inpu t of the slic er comp arator (Pin2 0) is use d.
The comparator has no hysteresis built in.
This offs et v oltage is gen er ate d by the bias cur rent o f the neg ative i np ut of t he
comparator (i.e. 20nA) running over the external resistor R. This voltage raises
the volt age appearing at pin 20 (e.g. 1mV wi th R = 100kΩ). In order to obtain
benefit of this asymmetrical offset for the demodulation of long zeros the lower
of the two FSK frequencies should be chosen in the transmitter as the zero-
symbol frequency.
In the following figure the shape of the above mentioned bandpass is shown.
frequenzgang.WMF
Figure 4-8 Frequency characterstic in case of FSK mode
The cutoff frequencies are calculated with the following formulas:
v
0dB
3dB
v-3dB
f
20dB/dec -40dB/dec
f1 f2 f3
gain (pin19)
DC
0.18mV/kHz 2mV/kHz
C
kR kR
f
×
Ω+
Ω⋅
=
330
330
2
1
1
π
Applications
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f3 is the 3dB cutoff frequency of the data filter - see Section 4.2.
Example:
R = 100kΩ
C = 47nF
This leads to f1 = 44Hz
and f2 = 485Hz
4.6.2 ASK Mode
In ca se the rece iver is operated in ASK m ode the data path frequ ency char ac-
tersitic is dominated by the data filter alone, thus it is lowpass shaped.The cutoff
frequency is determined by the external capacitors C12 and C14 and the inter-
nal 100k resistors as described in Section 4.2
freq_ask.WMF
Figure 4-9 Frequency charcteristic in case of ASK mode
112 11 ffvf ⋅=⋅=
dB
ff 33 =
0dB
-3dB
f
-40dB/dec
f3dB
Applications
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4.7 Principle of the Precharge Circuit
In case the data slicer threshold shall be generated with an external RC network
as described in Section 4.5 it is necessary to use large values for the capacitor
C attached to the SLN pin (pin 20) in order to achieve long time constants. This
results also fro m the fact that the choic e of the val ue for R connec ted betwe en
the SLP and SLN pins (pins 19 and 20) is limited by the 330kΩ resistor appear-
ing in parallel to R as can be seen in Figure 4-6. Apart from this a resistor value
of 100 k Ω leads to a voltage offset of 1mv at the comparator input as described
in Section 4.6.1. The resulting startup time constant τ1 can be calculated with:
In case R is chosen to be 100kΩ and C is chosen as 47nF this leads to
When the device is turned on this time constant dominates the time necessary
for the device to be able to demodulate data properly. In the powerdown mode
the capacitor is only discharged by leakage currents.
In order to r educe the turn-on time in the presen ce of larg e values of C a pr e-
charge circuit was included in the TDA5210 as shown in the following figure.
precharge.WMF
Figure 4-10 Principle of the precharge circuit
(
)
CkR ×Ω= 330||
1
τ
(
)
msnFknFkk 6.3477747330||100
1=×Ω=×ΩΩ=
τ
I
load
+3.1V
20k
+
-
OTA
+2.4V
R1 R2
24 23 U
threshold
C
0 / 240uA +
-
20 19
R
Da ta Filter ASK/FSK Sw itch
C2
U2
Us
Uc
Uc<UsUc>Us
U2<2.4V : I=240uA
U2 >2 .4 V : I=0
R1+R2=600k
Applications
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This circuit charges the capacitor C with an inrush current Iload of 240µA for a
duration of T2 until the voltage Uc appearing on the capacitor is equal to the volt-
age Us at the in put of the data fil ter. T his vo lta ge is lim ited to 2.5V . As soon as
these voltages are equal or the duration T2 is exceeded the precharge circuit is
disabled.
τ2 is the time constant of the charging process of C which can be calculated as
as the sum of R1 and R2 is sufficiently large and thus can be neglected. T2 can
then be calculated according to the following formula:
The voltage transient during the charging of C2 is shown in the following figure:
e-fkt1.WMF
Figure 4-11 Voltage appearing on C2 during precharging process
The v oltage appear ing on t he capacito r C c onnected to pin 20 is sho wn in t he
followi ng figure. It can b e seen that due to the fact that it is charged by a con-
stant current source it exhibits is a linear increase in voltage which is limited to
220
2Ck ×Ω≈
τ
6.1
34.2
1
1
ln 222 ⋅≈
−
=
ττ
VV
T
U2
2
3V
2.4V
T2
Applications
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USmax = 2.5V which is also the approximate operating point of the data filter
input. The time constant appearing in this case can be denoted as T3, which
can be calcula ted with
e-Fkt2.WMF
Figure 4-12 Voltage transient on capacitor C attached to pin 20
As an example the choice of C2 = 20nF and C = 47nF yields
τ2 = 0.4ms
T2 = 0.64ms
T3 = 0.49ms
This means that in this case the inrush current could flow for a duration of
0.64ms but stops already after 0.49ms when the USmax limit has been reached.
T3 should always be chosen to be shorter than T2.
It has t o be noted finally that during the turn-o n duratio n T2 the overall device
power consumption is increased by the 240µA needed to charge C.
The prec harge circui t may be dis abled if C2 is not equippe d. This yie lds a T2
close to zero. Note that the sum of R4 and R5 has to be 600kΩ in order to pro-
duce 3V at the THRES p in as this vol tage is inter nally used als o as the refer-
ence for the FSK demodulator.
C
A
V
ACU
TS×=
×
=
µµ
240
5.2
240
3max
Us
T3
Uc
5Reference
5.1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.2 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.3 Test Board Layouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Contents of this Chapter
Reference
5 - 2
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5.1 Electrical Data
5.1.1 Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even
momentarily and individually, as permanent damage to the IC may result.
Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB=-40°C ... + 85°C
#Parameter Symbol Limit Va lues Unit Remarks
min max
1Supply Voltage Vs-0.3 5.5 V
2Junction Temperature Tj-40 +125 °C
3Storage Temperature Ts-40 +150 °C
4Thermal Re si st anc e RthJA 114 K/W
5ESD integrity, all pins VESD -1 +1 kV HBM
accordin g to
MIL STD
883D,
method
3015.7
Reference
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5.1.2 Operating Range
Within the operating range the IC operates as explained in the circuit descrip-
tion. The AC/DC characteristic limits are not guaranteed.
Supply voltage: VCC = 4.5V .. 5.5V
Table 5- 2 Operating Range, Am bient temperature TAMB= -40°C ... + 85°C
#Parameter Symbol Limit Values Unit Test Conditions/Notes L Item
min max
1Supply Current ISF
ISA
6
5.4 mA
mA fRF = 915MHz, FSK Mode
fRF = 915MHz, ASK Mode
2Receiver Input Level
ASK
FSK, frequ. dev. ± 50kHz RFin -109
-102 -13
-13 dBm
dBm
@ source impedance 50Ω,
BER 2E-3, average power
level, Manchester encoded
datarate 4kBit, 280kHz IF
Bandwidth
■
3LNI Input Frequency fRF 902 928 MHz
4MI/X Input Frequency fMI 902 928 MHz
6UHF Local Oscillator Fre-
quency Range fLO 910 932 MHz
73dB IF Frequency Range fIF -3dB 523 MHz
8Powerdown Mo de On PWDNON 00.8 V
9Powerdown Mo de Off PWDNOFF 2 VSV
10 Gain Contr ol Volta ge,
LNA high gain state VTHRES 2.8 VSV
11 Gain Contr ol Volta ge,
LNA low gain state VTHRES 00.7V V
■ Not part of the production test - either verified by design or measured in an Infineon Evalboard as described in
Section 5.2.
Reference
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5.1.3 AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the spec-
ified voltage and ambient temperature range. Typical characteristics are the
median of the production. The device performance parameters marked with ■
are not part of the production test, but verified by design or measured in an Infi-
neon Evalboard as described in Section 5.2.
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V
#Parameter Symbol Limit Values Unit Test Conditi ons/
Notes LItem
min typ max
Supply
Supply Current
1Supply current,
standby mode IS PDWN 90 120 nA Pin 27 (PDWN)
open or tied to 0 V
2Supply current, device
operating in FSK mode ISF 5.4 5.7 mA Pin 11 (FSEL)
open, Pin 15
(MSEL) tied to
GND
3Supply current, device
operating in ASK mode ISA 4.8 5.1 mA Pin 11 (FSEL)
open, Pin 15
(MSEL) open
LNA
Signal Input LNI (PIN 3), VTHRES > 2.8V, high gain mode
1Average Power Lev el
at BER = 2E-3
(Sensitivity) ASK
RFin -112 dBm Manchester
encoded da tarate
4kBit, 280kHz IF
Bandwidth
■
2Average Power Lev el
at BER = 2E-3
(Sensitivity) FSK
RFin -105 dBm Manc heste r enc.
datarate 4kBit,
280kHz IF Bandw.,
± 50kHz pk. dev.
■
3Input impedance,
fRF = 915 MHz S11 LNA 0.717 / -78.4 deg ■
4Input level @ 1dB C.P.
fRF=915 MHz P1dBLNA -15 dBm ■
5Input 3rd order intercept
point fRF = 915 MHz IIP3LNA -14 dBm fin = 914 & 916MHz ■
6LO signa l feedt hrou gh at
antenna port LOLNI 73 dBm ■
Signal Output LNO (PIN 6), VTHRES > 2.8V, high gain mode
1Gain fRF = 915 MHz S21 LNA 1.401 / 98.4 deg ■
2Output im ped anc e,
fRF = 915 MHz S22 LNA 0.869 / -25.7 deg ■
Reference
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Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
#Parameter Symbol Limit Values Unit Test Conditions/
Notes LItem
min typ max
3Voltage Gain Antenna to
IFO fRF = 915 MHz GAntMI 40 dB
Signal Input LNI, VTHRES = GND, low gain mode
1Input impedance,
fRF = 915 MHz S11 LNA 0.753 / -86.26 deg ■
2Input level @ 1dB C. P.
fRF = 915 MHz P1dBLNA -6 dBm ■
Signal Input LNI, VTHRES = GND, low gain mode
3Input 3rd order intercept
point fRF = 915 MHz IIP3LNA -5 dBm fin = 914 & 916MHz ■
Signal Output LNO, VTHRES = GND, low gain mode
1Gain fRF = 915 MHz S21 LNA 0.174 / 107.4 deg ■
2Output im ped anc e,
fRF = 915 MHz S22 LNA 0.868 / -28.1 deg ■
3Voltage Gain Antenna to
IFO fRF = 915 MHz GAntMI 19 dB
Signal 3VOUT (PIN 24)
1Output vo ltage V3VOUT 2.9 3 3.1 V I3Vout = 5µA
2Current out I3VOUT 50 µA
Signal THRES (PIN 23)
1Input Voltage range VTHRES 0 VS-1 V see Se cti on 4.1
2LNA low gain mode VTHRES 0 V
3LNA high gain mode VTHRES 3 VS-1 V or shorted to Pin 24
4Current in ITHRES_in 5nA ■
Signal TAGC (PIN 4)
1Current out,
LNA low gain state ITAGC_out 3.8 4.2 4.8 µA RSSI > VTHRES
2Current in,
LNA high gain state ITAGC_in 11.5 2µARSSI < VTHRES
MIXER
Signal Input MI/MIX (PINS 8/9)
1Input impedance,
fRF = 915 MHz S11 MIX 0.912 / -30.13 deg ■
2Input 3rd order intercept
point IIP3MIX -25 dBm ■
Reference
5 - 6
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Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter Symbol Limit Values Unit Test Conditions/
Notes LItem
min typ max
Signal Output IFO (PIN 12)
1Output im ped anc e ZIFO 330 Ω■
2Conversion Voltage Gain
fRF=915 MHz GMIX 18 dB
LIMITER
Signal Input LIM/X (PINS 17/18)
1 Input Impedance ZLIM 264 330 396 Ω■
2RSSI dynamic range DRRSSI 60 80 dB
3RSSI linear ity LINRSSI ±1dB ■
4Operati ng frequenc y (3dB
points) fLIM 510.723 MHz ■
DATA FILTER
1Useable bandwidth BWBB
FILT 100 kHz ■
SLICER
Signal Output DATA (PIN 25)
1Useable bandwith BWBB
SLIC 100 kHz ■
2Capacitive loading of out-
put Cmax SLIC 20 pF
3LOW output voltage VSLIC_L 00.1 V
4HIGH output volta ge VSLIC_H VS-
1.3 VS-1 VS-0.7 V Output current=
200µA
Slicer, SLN (PIN 20)
1Precharge Current Out IPCH_SLN -100 -220 -300 µA see Secti on 4.7
PEAK DETECTOR
Signal Output PDO (PIN 26)
1LOW output voltage VSLIC_L 00.1 V
2HIGH output volta ge VSLIC_H 2.9 3 3.1 V
3Load current Iload -500 µA Static ou tput cur-
rent must not
exceed -50 0µA
4Leakage current Ileakage 580 700 820 nA
Reference
5 - 7
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Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter Symbol Limit Values Unit Test Conditi ons/
Notes LItem
min typ max
CRYSTAL OSCILLATOR
Signals CRSTL1, CRISTL 2, (PINS 1/28)
1Operati ng frequency fCRSTL 615 MHz f undam ental mod e,
series resonance
2Input Impedance
@ ~7.2MHz Z1-28 - 860 +
j500 Ω■
3Input Impedance
@ ~14.5MHz Z1-28 - 550 +
j1050 Ω■
4Serial Capacity
@ ~7.2MHz CS7=C1 9.5 pF
5Serial Capacity
@ ~14.5MHz CS14=C1 5.6 pF
ASK/FSK Signal Switch
Signal MSEL (PIN 15)
1ASK Mode VMSEL 1.4 4Vor open
2FSK Mode VMSEL 00.2 V
FSK DEMODULATOR
1Demodulation Gain GFMDEM 200 µV/
kHz
2Useable IF Bandwidth BWIFPLL 10.2 10.7 11.2 MHz
POWER DOWN MODE
Signal PDWN (PIN 27)
1Power down Mode On PWDNON 00.8 V
2Power down Mode Off PWDNOff 2.8 VSV
3Input bias current PDWN IPDWN 19 µA
4Start-up Time until vali d IF
signal is detected TSU <1 ms note: startup - tim e
is al so dep ends on
the used cryst al
PLL DIVIDER
Signal CSEL (PIN 16)
1fCRSTL range 7.xxMHz VCSEL 1.4 4Vor ope n
Reference
5 - 8
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Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter Symbol Limit Values Unit Test Conditi ons/
Notes LItem
min typ max
2 fCRSTL range 14.xxMHz VCSEL 00.2 V
3Input bias current CSEL ICSEL 5µA CSEL tied to GND
■ Not part of the production test - either verified by design or measured in an Infineon Evalboard as described in
Section 5.2.
Reference
5 - 9
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5.2 Test Circuit
The device performance parameters marked with ■ in Section 5.1.3 were either
verified by design or measured on an Infineon evaluation board.
Test_circuit.wmf
Figure 5-1 Schematic of the Evaluation Board
Infineon Technologies
TITLE:
TDA52xx Evaluation Board
FILE: -10 V 2.0
DATE: Jul.19, 1999
Reference
5 - 10
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5.3 Test Board Layouts
Figure 5-2 Top Side of the Evaluation Board
Figure 5-3 Bottom Side of the Evaluation Board
Reference
5 - 11
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Figure 5-4 Component Placement on the Evaluation Board
Reference
5 - 12
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5.4 Bill o f Mat e rials
The following components are necessary for evaluation of the TDA5212 at
915 MHz without use of a Microchip HCS515 decoder.
Table 5-4 Bill of Materials
Ref Value Specification
R1 100kΩ0805, ± 5%
R2 100kΩ08 05, ± 5%
R3 820kΩ08 05, ± 5%
R4 240kΩ08 05, ± 5%
R5 360kΩ08 05, ± 5%
R6 10kΩ0805, ± 5%
L1 3.3nH Toko, PTL2012 -F3N 3 C
L2 3.9nH Toko, PTL2012 -F3N 9 C
C1 1pF 0805, COG, ± 0.1pF
C2 3.3pF 0805, COG, ± 0.1pF
C3 4.7pF 0805, COG, ± 0.1pF
C4 100pF 0805, COG, ± 5%
C5 47nF 1206, X7R, ± 10%
C6 3.3pF 0805, COG, ± 0.1pF
C7 100pF 0805, COG, ± 5%
C8 22pF 0805, COG, ± 5%
C9 100pF 0805, COG, ± 5%
C10 10nF 0805, X7R, ± 10%
C11 10nF 0805, X7R, ± 10%
C12 220pF 0805, COG, ± 5%
C13 47nF 0805, X7R, ± 10%
C14 470pF 0805, COG, ± 5%
C15 47nF 0805, X7R, ± 10%
C16 8.2pF 0805, COG, ± 1%
C17 18pF 0805, COG, ± 0.25pF
Q1 14.129690MHz1 Jauch Q 14.129690-S1
Q2 SFE10.7MA5-A Murata
X2, X3 142-0701-801 Johnson
X1, X4, S1, S5 STL_2POL 2-pole pin connector
S4 STL_3POL 3-pole pin connector, or not equipped
IC1 TDA 5212 Infineon
1. 14.129690 MHz crystal s are used in the In fine on Evalb oard, whic h means that the L0 is in low sid e inject ion
mode (L0-fre quency=904 .3MHz). But t o guarantee the fu nction of the IC over the wh ole temperatu re range the
L0 has to be used in high side rejection mode (L0-frequency=925.7MHz), therefore 14.4640625MHz crystals
have to be used for a RF of 915MHz (see also VCO-frequency range).
Reference
5 - 13
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The following components are necessary in addition to the above mentioned
ones for evaluation of the TDA5212 in conjunction with a Microchip HCS512
decoder.
Table 5-5 Bill of Materials Addendum
Ref Value Specification
R21 22kΩ0805, ± 5%
R22 10kΩ0805, ± 5%
R23 22kΩ0805, ± 5%
R24 820kΩ08 05, ± 5%
R25 560kΩ08 05, ± 5%
C21 100nF 1206, X7R, ± 10%
C22 100nF 1206, X7R, ± 10%
IC2 HCS512 Microchip
T1 BC 847B Infineon
D1 LS T670-JL Infineon
List of Figures
List of Figures - i
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6List of Figures
Figure 2-1 PG-TSSOP-28 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Figure 3-1 IC Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Figure 3-2 Main Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Figure 4-1 LNA Automatic Gain Control Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Figure 4-2 RSSI Level and Permissive AGC Threshold Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Figure 4-3 Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Figure 4-4 Determination of Series Capacitance Value for the Crystal Oscillator . . . . . . . . . . . . . 4-5
Figure 4-5 Data Slicer Threshold Generation with External R-C Integrator . . . . . . . . . . . . . . . . . . 4-7
Figure 4-6 Data Slicer Threshold Generation Utilising the Peak Detector . . . . . . . . . . . . . . . . . . . 4-7
Figure 4-7 ASK/FSK mode datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Figure 4-8 Frequency characterstic in case of FSK mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Figure 4-9 Frequency charcteristic in case of ASK mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Figure 4-10 Principle of the precharge circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-11
Figure 4-11 Voltage appearing on C2 during precharging process . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Figure 4-12 Voltage transient on capacitor C attached to pin 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Figure 5-1 Schematic of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Figure 5-2 Top Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Figure 5-3 Bottom Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Figure 5-4 Component Placement on the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
List of Tables
List of Tables - i
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7List of Tables
Table 3-1 Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3
Table 3-2 CSEL Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Table 3-3 MSEL Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Table 3-4 PDWN Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB=-40°C ... + 85°C . . . . . . . . . 5-2
Table 5-2 Operating Range, Ambient temperature TAMB= -40°C ... + 85°C . . . . . . . . . . . . . . . . . 5-3
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V . . . . . . . . . . . . . . . . . . . . . 5-4
AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued) 5-5
AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued) 5-6
AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued) 5-7
AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued) 5-8
Table 5-4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Table 5-5 Bill of Materials Addendum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-13
