ANALOG DEVICES Dual Precision JFET-Input Operational Amplifier OP-215 FEATURES High Slew Rate ........................5- 10V/yus Min Fast Settling Time .................. 0.9us to 0.1% Typ Low Input Offset Voltage Drift ........... 10nV/C Max Wide Bandwidth .....................005. 3.5MHz Min Temperature-Compensated Input Bias Currents @ Guaranteed Input Bias Current ..... 18nA Max (125C) Bias Current Specified Warmed-Up Over Temperature Low Input Noise Current ........... 0.01pA/\/ Hz Typ @ High Common-Mode Rejection Ratio ........ 86dB Min Pin Compatible With Standard Dual Pinouts @ 125C Temperature Tested DICE Models With MIL-STD-883 Class B Processing Available Available in Die Form ORDERING INFORMATION t T,=25C PACKAGE OPERATING Vag MAX CERDIP = PLASTIC LCC TEMPERATURE (mV) TO-90 8-PIN SPIN 20-CONTACT RANGE 1.0 OP215AP = OP215AZ* - - Mi 1.0 OP215EJ OP215EZ OP215EP - COM 2.0 OP215BNe83 OP215B7/883 - OP215BRC883 MIL 2.0 OP215FJ OP215FZ OP215FP - COM 4.0 OP215C./883 OP215CZ/883 - ~ MIL 60 - OP215GZ OP215GP - XIND 6.0 - - OP215GS - XIND * For devices processed in total compliance to MIL-STD-883, add /883 after part number. Consult factory for 883 data sheet. t Burn-in is available on commercial and industrial temperature range parts in CerDIP, plastic DIP, and TO-can packages. GENERAL DESCRIPTION The OP-215 offers the proven JFET-input performance ad- vantages of high speed and low input bias current with the SIMPLIFIED SCHEMATIC (1/2 OP-215) tracking and convenience advantages of a dual op-amp configuration. Low input offset voltages, low input currents, and low drift are featured in these high-speed amplifiers. On-chip zener-zap trimming is used to achieve low Vos while a bias-current compensation scheme gives a low input bias current at elevated temperatures. Thus the OP-215 features an input bias current of 18nA at 125C ambient (not junction) temperature which greatly extends the application useful- ness of this device. Applications include high-speed amplifiers for current output DACs, active filters, sample-and-hold buffers, and photocell PIN CONNECTIONS Ve & OUT A1 7ouTe oNA2 64NB +INAZ S+INB 4 ye TO-99 LCC 20-CONTACT (J-Suffix) (RC-Suffix) *V+ A & V+ B INTERNALLY CONNECTED 8) INA [7] OUTA 8-PIN CERDIP $} v* (Z-Suttix) fs] ours 8-PIN PLASTIC DIP 8-PIN SO (P-Suffix) (S-Suffix) V+ T NOTE: R7, RB ARE ELECTRONICALLY ADJUSTED ON CHIP FOR MINIMUM OFFSET VOLTAGE. < OUTPUT SnOP-215 GENERAL DESCRIPTION Continued amplifiers. For additional precision JFET op amps, see the OP-15/16/17 data sheet. ABSOLUTE MAXIMUM RATINGS (Note 1) Supply Voltage OP-215A, OP-215B, OP-215E, OP-215F (All DICE Except GR) ...........-cscssssnesenseentereerreeeeeeneees +22V OP-215C, OP-215G (GR DICE Only) ........ seers +18V Operating Temperature Range OP-215A, OP-215B, OP-215C ........ eee 58C to +125C OP-215E, OP215F ........ceeeeseeecceseeeensereeeesenees 0C to + 70C OP~215G 0... ceccsecccceeesesesceeenessensacaseeneneserersneeees 40C to +85C Maximum Junction Temperature (T, ) sesesceaentnerasovesonntaes +150C Differential Input Voltage OP-215A, OP-215B, (All DICE Except GR) ................. +40V OP-215E, OP-215F, (All DICE Except GR) ................4 +40V OP-215C, OP-215G, (GR DICE Onlly).........0..cceeeeeees +30V input Voltage OP-215A, OP-215B, (All DICE Except GR) ................. +20V OP-215E, OP-215F, (All DICE Except GR).................. +20V OP-215C, OP-215G, (GR DICE Onlly)............ccceseseerees +16V (Unless otherwise specified, the absolute maximum nega- tive input voltage is equal to one volt more positive than the negative power supply voltage.) Output Short-Circuit Duration ...........eccceeseeeerenenees indefinite Storage Temperature Range ............cseserees -65C to +150C Lead Temperature (Soldering, 60 S@C) ..........sseceeees 300C Junction Temperature (T) saneenseessateessceeccereeaees -65C to +150C PACKAGE TYPE 6,, (NOTE 2) Sc UNITS TO-99 (J) 145 16 CW 8-Pin Hermetic DIP (2) 134 12 CW 8-Pin Plastic DIP (P) 96 37 Cw 20-Contact LCC (RC) 88 33 C/W 8-Pin SO (S) 150 41 CW NOTES: 1. Absolute maximum ratings apply to both DICE and packaged parts, unless other- wise noted. 2 @,is specified for worst case mounting conditions, i.e., @., is specified for device in socket for TO, CerDIP, P-DIP, and LCC packages; 8 A is specified for device soldered to printed circuit board for SO package. ELECTRICAL CHARACTERISTICS at Vs = + 15V, Ta = 25C, unless otherwise noted. OP-215A/E OP-215B/F OP-215C/G PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Rs = 500 - 02 10 08 20 20 40 ; Vv Input Offset Voltage Vos G Grade _ _ _ _ _ _ _ 25 60 m T, = 25C (Note 1) - ee) - 3 50 - 3 100 J A Input Offset Current log Device Operating _ 5 100 - 5 100 _ 5 200 p Input Bias Current T, = 25C (Note 1) +15 +100 +15 +200 +158 +300 A nput Bias Curren B Device Operating +18 +300 +18 +400 +18 +600 P Input Resistance Rin we ee gt n Large-Signal Voltage R,_ 2 2kn A 150 500 _ nr) - 50 200 _ vim Gain vo Vo = t10V m Output Voltage y Ry = 10kn +12 13 - +12 13 - +12 +13 - Vy Swing Ry, = 2k +11 $12.7 - +14 127 _ +11 +127 _ 60 85 60 85 70 100 f t A Supply Curren sy G' Grade - - = - - = 70 120 m Stew Rate SR Aver = +1 10 18 - 75 18 - 5 15 _ V/us i i Gain Bandwidth GBW (Note 3) 35 57 _ 35 57 - 30 5.4 - MHz Product Closed-Loop Le =+1 - 13 _ - 13 - - 12 - Bandwidth cLew Avot MHz to 0.01% ~ 23 _ 23 - 24 _ Settling Time ts to 0.05% (Note 2) - 44 _ 44 - 12 - ys to 0.10% - o98 og - - 10 _ , +102 +148 +10.2 +148 +101 +148 - Input Voltage Range = IVR -10.2 -11.5 _ -102 -11.5 - =10.1 0-115 _ V Common-Mode A, B, C Grades 86 100 - 86 100 _ 82 96 - A =+IV Rejection Ratio cMR Vom==IVR G Grades 82 10000 82 100 - 80 96 _ dB Power Supply Vg = + 10V to + 16V _ 10 51 _ 10 80 _ _ Rejection Ratio PSRR Vg = 10 to + 15V - - - - - - - 16 100 wv Input Noise Voltage fo = 100Hz - 20 - - 20 - - 20 - Density Sn fo = 1000Hz 15 - 15 - - 15 _ Whe Input Noise Current fg = 100Hz 0.01 _ 001 - 0.01 - i J Density " fo = 1000Hz 0.01 - 001 - 001 PAWHZ Input Capacitance Cin 7. 3 - To. 3 7 7 3 - pFELECTRICAL CHARACTERISTICS at Vs = + 15V, 55C < Ta < + 125C, unless otherwise noted. : OP-215A OP-215B OP-215C PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Input Offset Voltage Vo Rg = 502 _ 0.5 2.0 15 3.0 _ 3.0 6.0 mv Average Input Offset Voltage Drift Without External Trim = TCVos5 (Note 3) _ 3 10 _ 3 10 _ 6 - vec With External Trim TCVosn Rp = 100k 3 - _ 3 - 4 # Input Offset Current i T= + 125C _ 0.8 8 _ 0.8 8 _ 1.0 12 nA (Note 1) os Ta =+125C, Device Operating 1.2 14 1.2 14 - 15 22 Input Bias Current Tj = +125C _ #1.5 +10 _ +15 +10 _ +18 +15 nA (Note 14) B Tg = + 125C, Device Operating +2.2 +18 _ 42.2 +18 _ +27 +28 input Vottage ve; - +10.2 +146 - +10.2 +146 - +10.1 +146 _ V nput Voltage range -10.2 -11.3 - -10.2 -11.3 - 10.1 -113 _ Common-Mode CMRR Vom = LIVR 82 97 - 62 97 - 80 93 _ dB Rejection Ratio cM Power Suppl Vg = 10V to + 16V - 10 100 15 = 100 - wer SUpPIY PSRR 8 KV Rejection Ratio Vg = 10V to +15V - _ - _ - - _ 23 126 Large-Signal Avo Ay 2 2k 390 10 Cn 22 00 vim Voltage Gain Vo =+10V Output Voltage Vo Ry > 10k +2419 420-419 #120 49 = v Swing ELECTRICAL CHARACTERISTICS at Vg = #15V, 0C s T, = +70C for E/F Grades, 40Cs T, = +85C for G Grade, unless otherwise noted. OP-215E OP-215F OP-215G PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS input Offset Voitage Vos Rg = 500 _ 0.4 1,65 - 1.4 2.65 _ 3.6 8.0 mV Average Input Offset Voltage Drift . Without External Trim = TCVog (Note 3) -_ 3 15 _ 3 15 _- 6 _ vec With External Trim = TCVgg, Rp = 100kN - 3 - - 3 - - 4 Input Offset Current \ T= 470C _ 0.06 0.45 - 0.06 0.45 - 0.08 0.65 nA (Note 1) os Ta =+70C, Device Operating 0.08 0.80 008 0.80 010 1.2 Input Bias Current \ Tj=+70C +012 +0.70 +012 +0.70 +014 +09 nA (Note 1) 8 Ta = +70C, Device Operating +016 +140 +016 +140 +0.19 +1.8 a - $10.2 +147 _ +102 +147 _ $10.1 +147 - Input Voltage Range = IVA 102-140 102 -14 = 101-130 v Common-Mode Vou = LIVR 80 98 _ 80 98 _ 76 94 - Rejection Ratio CMRR cM a8 Po Ss Vg = 10V to + 16V _- 13 100 _ 13 100 - _ _ wer Supply PSAR s BV Rejection Ratio Vg = 10V to + 15V _- - ad _ _ _ _ 20 159 Larger Signal Avo RL > ko 50 1800S 50 18000 35 19000Cl vimv Voltage Gain Vo = 10V Output Vottage Vo R. > 10kn 120041800 #200 418 #1200413 v Swing NOTES: 1. Input bias current is specified for two different conditions. The T; = 25C 2. Settling time is defined here for a unity gain inverter connection using 2kN. resistors. It is the time required for the error voltage (the voltage at the specification is with the junction at ambient temperature; the Device Operating specification is with the device operating in a warmed-up condition at 25C ambient. The warmed-up bias current value is corre- lated to the junction temperature value via the curves of |, vs. Tj and Ig vs. Ta. PMI has a bias current compensation circuit which gives improved bias current and bias current over temperature vs. standard JFET input op amps. Ig and log are measured at Voy = 0. inverting input pin on the amplifier) to settle to within a specified percent of its final value from the time a 10V step input is applied to the inverter. See settling time test circuit. Sample tested.OP-215 DICE CHARACTERISTICS (125C TESTED DICE AVAILABLE) 1. INVERTING INPUT (A) 8. NULL (B) 2. NONINVERTING INPUT (A) 9. V+ 3. NULL (A) 10. Vo (B) 4. V- 11. V+ 5. NULL (B) 12. Vo (A) 6. NONINVERTING INPUT (B) 13. V+ 7. INVERTING INPUT (B) 14. NULL (A) ALL V+ PADS ARE INTERNALLY CONNECTED. DIE SIZE 0.110 x 0.075 inch, 8250 sq. mils (2.79 X 1.91 mm, 5.33 sq. mm) WAFER TEST LIMITS at Vs=+15V, Ta= 25C for OP-215N, OP-215G and OP-215GR devices; Ta= 125 C for OP-215NT and OP-215GT devices, unless otherwise noted. OP-215NT OP-215N OP-215GT OP-215G OP-215GR PARAMETER SYMBOL CONDITIONS LIMIT LIMIT LIMIT LIMIT LIMIT UNITS Input Offset Voltage Vos Rg= 500 2 1 3 2 6 mV MAX Input Bias Current Ip +18 - +18 - - nA MAX Input Offset Current = log 14 - 14 _ -AAMAX Large-Signal Vo = + 10V, 1 Voltage Gain Avo R= 2kn 30 50 30 75 50 WmVMIN Input Voltage Range IVR +10.2 +10.2 410.2 + 10.2 +10.1 VMIN Common-Mode =+ Rejection Ratio CMRR- Voy =+IVR 82 86 82 86 82 dB MIN Power Supply Vs = +10 to +16V 100 51 100 80 _ Rejection Ratio PSR Vg= +10 to +18V _ - 100 WV MAX. . R= 10k0 +12 +12 +12 +12 +12 Output Voltage Swing Vo R= 2kn _ +11 _ +11 + VMIN Supply Current Igy _ 85 _ 85 12.0 mA MAX NOTES: For 25C characteristics of NT & GT devices, see N & G characteristics respectively. Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing. TYPICAL ELECTRICAL CHARACTERISTICS at Vs = + 15V, Ta = + 25C, unless otherwise noted. OP-215NT OP-215N OP-215GT OP-215G OP-215GR PARAMETER SYMBOL CONDITIONS TYPICAL TYPICAL TYPICAL TYPICAL TYPICAL UNITS Average Input Unnulled 2 2 3 3 4 ViPS Offset Vottage Dritt, CVos Ry = 100kn # Average Input Nulled 0.5 0.5 1 1 2 ve Offset Voltage Drift TC%OS" R= 100K a Whe Input Offset Current log 3 3 3 3 3 pA Input Bias Current lpg +15 +15 15 +15 +15 pA Stew Rate SR Ave. =+1 7 17 16 16 15 Wus . to 0.01% 2.2 2.2 2.3 2.3 2.4 i Settling Time ts to 0.05% 11 11 11 11 12 BS to 0.10% 0.9 0.9 0.9 0.9 1.0 Gain Bandwidth GBW 6.0 6.0 5.7 5.7 5.4 MHz Product Closed-Loop _ Bandwidth CLBW Aver =+1 14 14 13 13 12 MHz Input Noise fg = 100Hz 20 20 20 20 20 Voltage Density &n fo = 1000Hz 15 15 15 15 15 Ot Input Noise . fo= 100Hz .01 0.01 0.01 0.01 .01 Vv Current Density fo = 1000Hz 06 O01 PAN H2 Input Capacitance = Cin 3 3 3 8 3 pFOP-215 TYPICAL PERFORMANCE CHARACTERISTICS SMALL-SIGNAL TRANSIENT RESPONSE LARGE-SIGNAL TRANSIENT RESPONSE CLOSED-LOOP BANDWIDTH AND PHASE SHIFT vs FREQUENCY BANDWIDTH vs TEMPERATURE 18 90 28 16 100 Vg = #15V ars 14 PHASE MARGIN = 66' 110 2 = BANDWIDTH VARIATION FROM 12 120 25V < Vg < +20V IS < 5% 10 130 4 _ 20 8 tao z = zr = = 6 150 4 = 16 CLOSED-LOOP = w z= BANDWIDTH Ay = +1 z4 160 2 a 6 2 170 = z 12 0 180 z GAIN BANDWIDTH ao 2 190 8 -4 200 6 4 -8 -10 0 1M 10M 100M -50 -25 0 25 50 75 100) 125 FREQUENCY (Hz) TEMPERATURE (C) MAXIMUM OUTPUT SWING vs FREQUENCY SLEW RATE vs TEMPERATURE 70 Vg = t15V Ay=+1 a Ta? 25C 60 Vg= 15V 5 Ay = +1 3 2 w _ 50 3 3 5 2 40 a wi = - < a = 30 ww w 3 a E 20 = is a 10 0 100k 1M 10M 50 -25 O 2 50 75 100 125 AMBIENT TEMPERATURE (C) FREQUENCY (Hz) OUTPUT VOLTAGE SWING FROM OV (VOLTS) OPEN-LOOP VOLTAGE GAIN (dB} COMMON-MODE REJECTION RATIO (dB) a 5 60 1 10 #100 tk 10k SETTLING TIME I Vg = #15V Y Tp = 25C Ay=-1 | 10mV 1 Imv 10mV 5mV imv 9 0.5 1.0 15 2.0 25 SETTLING TIME (us) OPEN-LOOP FREQUENCY RESPONSE Vg = +15V Ta = 25C 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M COMMON-MODE REJECTION RATIO vs FREQUENCY | l Vg = 15V Ta = 25C \ \ XV 100k 1M FREQUENCY {Hz) 10M 100MOP-215 TYPICAL PERFORMANCE CHARACTERISTICS POWER SUPPLY REJECTION OUTPUT IMPEDANCE VOLTAGE NOISE DENSITY vs FREQUENCY vs FREQUENCY vs FREQUENCY 100 Ty = 28C Vs 18V. Vg = 215V . Tp = 25C Le YY = Ta = 28C : g Ih a Yn ( | 2 2 10 u v l A = : sere eT MMIW iy : w us a : EL | eM : 3 All| 2 z 8 | y g 1/f CORNER $ ff _ WV 5 FREQUENCY Aire g VA 100 71000 tk 10K 100k IM 10M Ok 10k 100k m 10M 1 10 100 1k 10k FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz} BASIC CONNECTIONS SETTLING TIME TEST CIRCUIT 2k 0.1% +15V0 10V 2k22. 0.1% a Sa 2N4416 ) == 100pF 3k EVO SUMMING > Vout NODE Ay=-1 5k 0.1% WN Cy ] [ewes 0 +15V 2kQ (PINOUT FOR J, "2" AND "P" PACKAGES ONLY) SLEW RATE TEST CIRCUIT INPUT OFFSET VOLTAGE NULLING . *8V p$oVour OUT (A) ---+av v 3 sv " . 100pF ;+I NOTE: Vos CAN BE TRIMMED WITH POTENTIOMETERS RANGING FROM - 10k2 TO IMO. FOR MOST UNITS TCVgg WILL BE MINIMUM WHEN Vog |S ADJUSTED WITH A 100k POTENTIOMETER. Ni FOR J," Z" AND "P* PACKAGES ONL) (PINOUT (DICE ONLY)OP-215 BASIC CONNECTIONS BURN-IN CIRCUIT +15V NOTES: 1. Ta = 125C TO +150C ~15V 2. RESISTORS ARE TYPE RNSSD, +1% ("d," "2" AND "P" PACKAGES ONLY) 100k ~ +15 100 a 2 13, 19 OP-215 \ 18 0 10kN (A) 1 3 100k0 AAA vwvVv Joka. 10 -_NVY oP.215 4 4oKn Wy -o AAA ev 6 -BVv (*RC PACKAGE) APPLICATIONS INFORMATION DYNAMIC OPERATING CONSIDERATIONS As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize pick-up and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground sets the frequency of the pole. In many instances, the frequency of this pole is much greater than the expected 3dB frequency of the closed-loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately six times the expected 3dB frequency, a lead capacitor should be placed from the output to the negative input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than, or equal to, the original feedback-pole time constant.