SST34HF1621A-70-4E-L1PE - Silicon Storage Technology

S71217-05-EOL 3/05

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. Intel is a registered trademark of Intel Corporation.

CSF and ComboMemory are trademarks of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

EOL Product Data Sheet

FEATURES:

• Flash Organization: 1M x16

• Dual-Bank Architecture for Concurrent

Read/Write Operation

– 16 Mbit: 12 Mbit + 4 Mbit

• SRAM Organizatio n:

– 2 Mbit: 128K x1 6

– 4 Mbit: 256K x1 6

– 8 Mbit: 512K x1 6

• Single 2.7-3.3V Read and Write Operations

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 year s Data Ret ention

• Low Power Consumption:

– Active Current: 25 mA (typical)

– Standby Current: 20 µA (typical)

• Hardware Sector Protection (WP#)

– Protects 4 outer most sectors (4 KWord) in the

larger bank by holding WP# low and unprotects

by holding WP# high

• Hardware Reset Pin (RST#)

– Resets the internal state machine to reading

data array

• Sector-Erase Capability

– Uniform 1 KWord sectors

• Block-Erase Capability

– Uniform 32 KWord blocks

• Read Access Time

– Flash: 70 ns

–SRAM: 70 ns

• Latched Address and Data

• Fast Erase and Word-Program:

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 70 ms (typical)

– Word-Program Time: 14 µs (typical)

– Chip Rewrite Time: 8 seconds (typical)

• Automatic Write Timing

– Internal VPP Generation

• End-of-Write Detection

– Toggle Bit

– Data# Polling

– Ready/Busy# pin

• CMOS I/O Compatibility

• JEDEC Standard Command Set

• Conforms to Common Flash Memory Interface

(CFI)

• Packages Available

– 56-ball LFBGA (8mm x 10mm)

– 62-ball LFBGA (8mm x 10mm)

PRODUCT DESCRIPTION

The SST34HF16x1A and SST34HF1681 ComboMemory

devices integrate a 1M x16 CMOS flash memo ry bank with

either a 128K x16, 256K x16, or 512K x16 CMOS SRAM

memory bank in a multi-chip package (MCP). These devices

are fabricated using SST’s proprietary, high-performance

CMOS SuperFlash technology incorporating the split-gate

cell design and thick oxide tunneling injector to attain better

reliability and manufacturability compared with alternate

approaches. The SST34HF16x1A and SST34HF1681

devices are ideal for applications such as cellular phones,

GPS de vices, PD As, and other portable electronic de vices in

a low po wer and small f orm factor system.

The SST34HF16x1A and SST34HF1681 feature dual

flash memory bank architecture allowing for concurrent

operations between the two flash memory banks and the

SRAM. The devices can read data from either bank while

an Erase or Program operation is in progress in the oppo-

site bank. The two f lash memory banks are partitioned into

4 Mbit and 12 Mbit with botto m sector protection options f or

storing boot code, program code, configuration/parameter

data and user data.

The SuperFla sh technology provides fixed Erase and Pro-

gram times, independent of the number of Erase/Program

cycles that have occurred. Therefore, the system software

or hardware does not hav e to be modified or de-rated as is

necessary with alternativ e flash tech nologies , whose Erase

and Program times increase with accumulated Erase/Pro-

gram cycles. The SST34HF16x1A and SST34HF1681

devices offer a guaranteed endurance of 10,000 cycles.

Data retention is rated at greater than 100 years. With high

performance Word-Program, the flash memory banks pro-

vide a typical Word-Program time of 14 µsec. The entire

flash memory bank can be er ased and pr og r a mmed w or d-

by -word in t ypically 8 seconds for the SST34HF16x1A and

SST34HF1681, when using interface f eatures such as Tog-

gle Bit or Data# Polling to indicate the completion of Pro-

gram operation. To protect against inadvertent flash write,

the SST34HF16x1A and SST34HF1681 devices contain

on-chip hardware and software data protection schemes.

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

SST34HF1621A / 1641A / 168116Mb CSF (x16) + 2Mb / 4Mb / 8Mb SRAM

(x16) MCP ComboMemory

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

The flash a nd SRAM oper ate as two in dependent me mory

banks with respective bank enable signals. The memory

bank selection is done by two bank enable signals. The

SRAM bank enable signals, BES1# and BES2, select the

SRAM bank. The flash memory bank enab le signal, BEF#,

has to be used with Software Data Protection (SDP) com-

mand sequence when controlling the Erase and Program

operations in the flash memor y bank. The memor y banks

are superimposed in the same memory address space

where they share common address lines, data lines, WE#

and OE# which minimiz e po wer consumption and area.

Designed, man uf actured, and tested f or applications requir-

ing low power and small form factor, the SST34HF16x1A

and SST34HF1681 are offered in both commercial and

extended temperatures and a small footprint package to

meet board space constraint requirements.

Device Operation

The SST34HF16x1A and SST34HF1681 uses BES1#,

BES2 and BEF# to control operation of either the flash or

the SRAM memory bank. When BEF# is low, the flash

bank is activated for Read, Program or Erase operation.

When BES1# is low, and BES2 is high the SRAM is acti-

vated f or Read and Write operation. BEF# and BES1# can-

not be at lo w le v el, and BES2 cann ot be at high le v el at th e

same time. If all bank enable signals are asserted, bus

contention will result and the device may suffer perma-

nent damage. All address, data, and control lines are

shared by flash and SRAM memory banks which mini-

mizes power consumption and loading. The device goes

into standby when BEF# and BES1# bank enables are

raised to VIHC (Logic High) or when BEF# is high and

BES2 is low.

Concurrent Read/Write Operation

Dual bank architecture of SST34HF16x1A and

SST34HF1681 devices allows the Concurrent Read/Write

operation whereby the user can read from one bank while

program or erase in the other bank. This operation can be

used when the user needs to read system code in one

bank while updating data in the other bank. See Figure 1

f or Dual-Bank Memory Organization.

Note: For the purposes of this table, write means to Block-, Sector,

or Chip-Erase, or Word-Program as applicable to the appro-

priate bank.

Flash Read Operation

The Read operation of the SST34HF16x1A and

SST34HF1681 is controlled by BEF# and OE#, both have

to be low for the system to obtain data from the outputs.

BEF# is used f or device selection. When BEF# is high, the

chip is deselected and only standby power is consumed.

OE# is the output contr ol and is used to gate d ata from th e

output pins. The data bus is in high impe dance sta te whe n

either BEF# or OE# is high. Refer to the Read cycle timing

diagra m for fu rther details (Figure 7).

CONCURRENT READ/WRITE STATES

Flash

SRAMBank 1 Bank 2

Read Write No Operation

Write Read No Operation

Write No Operation Read

No Operation Write Read

Write No Operation Write

No Operation Write Write

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

Flash Word-Program Operation

The SST34HF16x1 A and SST34HF1681 are progr ammed

on a word-by-word basis. Before Program operations, the

memory must be er ased first. The Program operation con-

sists of three steps. The first step is the three-byte load

sequence f or Softw are Data Protection. The second step is

to load w ord address and w ord data . During the W ord-Pro-

gram operation, the addresses are latched on the falling

edge of either BEF# or WE#, whichever occurs last. The

data is latched on the rising edge of either BEF# or WE#,

whichever occurs first. The third step is the internal Pro-

gram operation which is in itiated after the rising edge of the

four th WE# or BEF#, whichever occurs first. The Program

operation, once initiated, will be completed typically within

10 µs. See Figures 8 and 9 for WE# and BEF# controlled

Progra m operation timing diag rams and Figure 22 for flow-

char ts. During the Program operation, the only valid reads

are Data# Polling and Toggle Bit. During the internal Pro-

gram o peration, the host is free to perform additional tasks.

Any commands issued during the internal Program opera-

tion are ignored.

Flash Sector/Block-Erase Operation

The Sector/Block-Erase operation allows the system to

erase the device on a sector-by-sector or block-by-block

basis. The SST34HF16x1A and SST34HF1681 offer both

Sector-Erase and Block-Erase mode. The sector architec-

ture is based on unif orm sector size of 1 KW ord. The Block-

Erase mode is based on uniform block size of 32 KWord.

The Sector-Erase operation is initiated by executing a six-

byte command sequence with Sector-Erase command

(30H) and sector address (SA) in the last bus cycle. The

Block-Erase operation is initiated by executing a six-byte

command sequence with Block-Erase command (50H)

and bl ock address (BA) in the last bus cycle. The sector or

block address is latched on the falling edge of the sixth

WE# pulse, while the command (30H o r 50H) is latched on

the rising edge of the sixth WE# pulse. The internal Erase

operatio n begins after the sixth WE# pulse. See F igures 13

and 14 f or timing wa vef orms. Any commands issued during

the Sector- or Bloc k-Erase ope ration are ignored.

Flash Chip-Erase Operation

The SST34HF16x1A and SST34HF1681 provide a Chip-

Erase operation, which allows the user to erase all unpro-

tected sectors/blocks to the “1” state. This is useful when

the de vice must be quic kly erased.

The Chip-Erase operation is initiated by executing a six-

byte command sequence with Chip-Er ase command (10H)

at address 5555H in the last byte sequence. The Erase

operation begins with the rising edge of the sixth WE# or

BEF#, whichever occurs first. During the Erase operation,

the only valid read is Toggle Bits or Data# Polling. See

Table 4 for the command sequence, Figure 12 for timing

diagram, and Figure 25 for the flowchart. Any commands

issued during the Chip-Er ase operat ion are ignored.

Flash Write Operation Status Detection

The SST34HF16x1A and SST34HF1681 provide one

hardware and two software means to detect the com ple-

tion of a Write (Program or Erase) cycle, in order to opti-

mize the system Write cycle time. The hardware

detection uses the Rea dy/Busy# (RY/BY#) pin. The soft-

ware detection includes two status bits: Data# Polling

(DQ7) and Toggle Bit (DQ6). The End-of-Wr ite detection

mode is enabled after the rising edge of WE#, which ini-

tiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchro-

nous with th e system; theref ore, either a Ready/ Busy# (R Y/

BY#), Data# P olling (DQ7) or Toggle Bit (DQ6) r ead ma y be

simultaneous with the completion of the Write cycle. If this

occurs, the system may possibly get an erroneous result,

i.e., valid data may appear to conflict with either DQ7 or

DQ6. In or der to p revent spurious rejection, if an e rroneous

result occurs, the software routine should include a loop to

read the accessed location an additional two (2) times. If

both reads are valid, then the device has completed the

Write cycle, otherwise the rejection is valid.

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

Ready/Busy# (RY/BY#)

The SST34HF16x1A and SST34HF1681 include a Ready/

Busy# (RY/BY#) output signal. During any SDP initiated

operatio n, e . g., Er ase , Prog r am, CFI or ID Read oper ation,

RY/BY# is actively pulled low, indicating a SDP controlled

operatio n is in Progress. The status of R Y/BY# is v alid after

the rising edge of fourth WE# (or BEF#) pulse fo r Progr am

operation. For Sector-, Block- or Bank-Erase, the RY/BY#

is valid after the rising edge of sixth WE# or (BEF#) pulse.

R Y/BY# is an open drain output that allows se v eral de vices

to be tied in parallel to VDD via an external pull up resistor.

Ready/Busy# is in high impedance whenever OE# or

BEF# is high or RST# is low. There is a 1 µs bus recover y

time (TBR) required before valid data can be read on the

data bus. New commands can be entered immediately

after R Y/ BY# goes high.

Flash Data# Polling (DQ7)

When the SST34HF16x1A and SST34HF1681 are in the

internal Program operation, any attempt to read DQ7 will

produce the complement of the true data. Once the Pro-

gram operation is completed, DQ7 will produce true data.

Note that even though DQ7 may have valid data immedi-

ately following the completion of an internal Write opera-

tion, the remaining data outputs may still be invalid: valid

data on the entire data bus will appear in subsequent suc-

cessive Read cycles. During internal Erase operation, any

attempt to read DQ7 will produce a ‘0’. Once the internal

Erase operation is completed, DQ7 will produce a ‘1’. The

Data# Polling (DQ7) is valid after the rising edge of fourth

WE# (or BEF#) pulse for Program operation. For Sector-,

Block- or Chip-Erase, the Data# Polling (DQ7) is valid after

the rising edge of sixth WE# (or BEF#) pulse. See Figure

10 f or Data# P olling (DQ7) timing diag ram and Figure 23 f or

a flowchart. There is a 1 µs bus recovery time (TBR)

required before valid data can be read on the data bus.

New commands can be entered immediately after DQ7

becomes true data.

Flash Toggle Bits (DQ6)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6 will produce alternating 1s

and 0s, i.e., toggling between 1 and 0. When the internal

Program or Er ase operation is completed, the DQ6 bit will

stop toggling. The device is then ready for the next oper-

ation. The Toggle Bit (DQ6) is valid after the rising edge

of fourth WE# (or BEF#) pulse for Program operation.

F or Sector-, Block- or Chip-Er ase, the Toggle Bit (DQ6) i s

valid after the rising edge of sixth WE# (or BEF#) pulse.

See Figure 11 for Toggle Bit timing diagram and Figure

23 for a flowchart. There is a 1 µs bus recov ery time (TBR)

required before valid data can be read on the data bus.

New commands can be entered immediat ely after DQ6 no

longer toggles .

Data Protection

The SST34HF16x1A and SST34HF1681 provide both

hardware and software features to protect nonvolatile data

from inadv ertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or BEF# pulse of less than

5 ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#

high will inhibit the Wr ite operation. This prevents inadvert-

ent writes during power-up or po wer-do wn.

Hardware Block Protection

The SST34HF16x1A and SST34HF1681 provide a hard-

ware block protection which protects the outermost 4

KW ord in Bank 1. The bloc k is protected when WP# is held

low. See Figure 1 f or Block-Protection location.

A user can disable block protection by driving WP# high

thus allowing erase or program of data into the protected

sectors. WP# must be held high prior to issuing the write

command and remain stable until after the entire Write

operatio n has completed.

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

Hardware Reset (RST#)

The RST# pin provides a hardw are method of resetting the

device to read array data. When the RST# pin is held low

f or at least TRP, any in-progress operation will terminate and

return to Read mode (see Figure 19). When no internal

Progra m/Er ase oper atio n is in prog ress, a minim um period

of TRHR is required aft er RST# is driven high before a valid

Read can tak e place (see Figur e 18).

The Erase oper ation that has been interrupted needs to be

reinitiated after the de vice resumes normal operation mod e

to ensure data integrity. See Figures 18 and 19 for timing

diagrams.

Software Data Protection (SDP)

The SST34HF16x1A and SST34HF1681 provide the

JEDEC standard Software Data Protection scheme for all

data alteration operations, i.e., Program and Erase. Any

Program operation requires the inclusion of the three-byte

sequence. The three- b yte loa d sequence is used t o initiate

the Program operation, providing optimal protection from

inadvertent Write operations, e.g., during the system

power-up or po wer-down. An y Erase operation requires the

inclusion of six-byte sequence. The SST34HF16x1A and

SST34HF1681 are shipped with the Software Data Protec-

tion permanently enabled. See Table 4 for the specific soft-

ware command codes. During SDP command sequence,

invalid commands will abort the device to Read mode

within TRC. The contents of DQ15-DQ8 are “Don’t Care”

during any SDP co mmand sequence .

Common Flash Memory Interface (CFI)

The SST34HF16x1A and SST34HF1681 also contain the

CFI inf ormation to describe the characteristics of the de vice.

In order to enter the CFI Query mode, the system must

write three-byte sequence, same as Softw are ID Entry com-

mand with 98H (CFI Query command) to address 555H in

the last byte sequence. Once the device enters the CFI

Query mode, the system can read CFI data at the

addresses given in Tables 5 through 7. The system must

write the CFI Exit command to return to Read mode from

the CFI Query mode.

Product Identification

The Product Ident ification mode identifies the de vice as the

SST34HF16x1A or SST34HF1681 and manufacturer as

SST. This mode may be accessed by software operations

only. The hardwar e de vice ID Read oper ation, which is typ-

ically used by programmers cannot be used on this device

because of the shared lines between flash and SRAM in

the multi-chip package. Therefore, application of high volt-

age to pin A9 may damage this device. Users may use the

software Prod uct Ident ification oper ation to iden tify the part

(i.e., using the device ID) when using multiple manufactur-

ers in the same socket. For details, see Tables 3 and 4 for

software o peration, Figure 15 for the Software ID Ent ry and

Read timing diagram and Figure 24 for the ID Entry com-

mand sequence flo wchart.

Product Identification Mode Exit/

CFI Mode Exit

In order to return to the standard Read mode , the Softw are

Product Identification mode must be exited. Exit is accom-

plished by issuing the Software ID Exit command

sequence, which returns the device to the Read mode.

This command ma y also be used to reset the de vice to the

Read mode after any inadvertent transient condition that

apparently causes the device to behave abnormally, e.g.,

not read correctly. Please note that the Software ID Exit/

CFI Exit command is ignored during an internal Program or

Erase operation. See Table 4 for software command

codes, Figure 17 for timing wavefor m and Figure 24 for a

flowchart.

SRAM Operation

With BES1# low, BES2 and BEF# high, the

SST34HF16x1A and SST34HF1681 operate as either

128K x16, 256K x16, or 512K x16 CMOS SRAM, with

fully static operation requiring no e xternal clocks or timing

st rob e s. Th e SST34HF16x1A and SST34HF1681 SRA M

is mapped into the first 512 KWord address space. When

BES1#, BEF# are high and BES2 is low, all memory

banks are deselected and the device enters standby.

Read and Write cycle times are equal. The control sig-

nals UBS# and LBS# provide access to the upper data

byte and lower data byte. See Table 3 for SRAM Read

and Write data byte control modes of operation.

TABLE 1: PRODUCT IDENTIFICATION

ADDRESS DATA

Manufacturer’s ID 0000H 00BFH

Device ID

SST34HF1621A/1641A/1681 0001H 2761H

T1.0 1217

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

SRAM Read

The SRAM Read operation of the SST34HF16x1A and

SST34HF1681 is controlled by OE# and BES1#, both have

to be low with WE# and BES2 high for the system to obtain

data from the outputs. BES1# and BES2 are used for

SRAM bank selection. OE# is the output control and is

used to gate data from the output pins. The data bus is in

high impedance state when OE# is high. Refer to the Read

cycle timing diagram, Figure 4, for further details.

SRAM Write

The SRAM Write operation of the SST34HF16x1A and

SST34HF1681 is controlled by WE# and BES1#, both

have to be low, BES2 must be high for the system to write

to the SRAM. During the Word-Write operation, the

addresses and data are referenced to the rising edge of

either BES1#, WE#, or the falling edge of BES2 whichever

occurs first. The write time is measured from the last falling

edge of BES#1 or WE# or the rising edge of BES2 to the

first rising edge of BES1#, or WE# or the falling edge of

BES2. Refer to the Write cycle timing diagrams, Figures 5

and 6, for further details.

1217 B1.1

SuperFlash Memory

(Bank 1)

I/O Buffers

SuperFlash Memory

(Bank 2)

2 / 4 / 8 Mbit

SRAM

MS1- A0

DQ15 - DQ

Notes: 1. AMS = Most significant address

2. For LS package only: WE# = WEF# and/or WES#

OE# = OEF# and/or OES#

Control

Logic

RST#

BEF#

WP#

LBS#

UBS#

WE#2

OE#2

BES1#

BES2

RY/BY#

Address

Buffers

Address

Buffers

FUNCTIONAL BLOCK DIAGRAM

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

FIGURE 1: SST34HF16X1A AND SST34HF1681,

1 MBIT X16 CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION

FFFFFH

F8000H Block 31

F7FFFH

F0000H Block 30

EFFFFH

E8000H Block 29

E7FFFH

E0000H Block 28

DFFFFH

D8000H Block 27

D7FFFH

D0000H Block 26

CFFFFH

C8000H Block 25

C7FFFH

C0000H Block 24

Bank 2

BFFFFH

B8000H Block 23

B7FFFH

B0000H Block 22

AFFFFH

A8000H Block 21

A7FFFH

A0000H Block 20

9FFFFH

98000H Block 19

97FFFH

90000H Block 18

8FFFFH

88000H Block 17

87FFFH

80000H Block 16

7FFFFH

78000H Block 15

77FFFH

70000H Block 14

6FFFFH

68000H Block 13

67FFFH

60000H Block 12

5FFFFH

58000H Block 11

57FFFH

50000H Block 10

4FFFFH

48000H Block 9

47FFFH

40000H Block 8

3FFFFH

38000H Block 7

37FFFH

30000H Block 6

2FFFFH

28000H Block 5

27FFFH

20000H Block 4

1FFFFH

18000H Block 3

17FFFH

10000H Block 2

00FFFFH

008000H Block 1

007FFFH

000FFFH

000000H

Block 0

Bank 1

ottom Sector Protection; 32 KWord Blocks; 1 KWord Sectors

4 KWord Sector Protection

(Four 1 KWord Sectors) 1217 F01.0

001000H

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

FIGURE 2: PIN ASSIGNMENTS FOR 56-BALL LFBGA (8MM X 10MM)

FIGURE 3: PIN ASSIGNMENTS FOR 62-BALL LFBGA (8MM X 10MM) INTEL COMPATIBLE PACKAGE

1217 56-lfbga P1.0

A11

WE#

WP#

LBS#

A15

A12

A19

BES2

RST#

UBS#

A13

RY/BY#

A18

A14

A10

A17

A16

DQ6

DQ1

VSS

DQ15

DQ13

DQ4

DQ3

DQ9

OE#

BEF#

VSS

DQ7

DQ12

VDDS

VDDF

DQ10

DQ0

BES1#

DQ14

DQ5

DQ11

DQ2

DQ8

A B C D E F G H

TOP VIEW (balls facing down)

1217 62-lfbga P2.0

A16

WEF#

VSSS

WP#

LBS#

A18

A11

RY/BY#

RST#

UBS#

A17

A15

A10

A19

OES#

A14

DQ11

A13

DQ15

DQ13

DQ12

DQ9

BEF#

A12

WES#

DQ6

BES2

DQ10

DQ8

VSSF

DQ14

DQ4

VDDS

DQ2

DQ0

OEF#

DQ7

DQ5

VDDF

DQ3

DQ1

BES1#

A B C D E F G H J K

TOP VIEW (balls facing down)

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions

AMS1 to A0Address Inputs To provide flash address, A19-A0.

To provide SRAM address, AMS-A0

DQ15-DQ0Data Inputs/Outputs To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a flash Erase/Program cycle. The outputs are in

tri-state when OE# is high or BES1# is high or BES2 is low and BEF# is high.

BEF# Flash Memory Bank Enable To activate the Flash memory bank when BEF# is low

BES1# SRAM Memory Bank Enable To activate the SRAM memory bank when BES1# is low

BES2 SRAM Memory Bank Enable To activate the SRAM memory bank when BES2 is high

OEF#2Output Enable To gate the data output buffers for Flash2 only

OES#2Output Enable To gate the data output buffers for SRAM2 only

WEF#2Write Enable To control the Wr ite operations for Flash2 only

WES#2Write Enable To control the Write operations for SRAM2 only

OE# Output Enable To gate the data output buffers

WE# Write Enable To control the Write operations

UBS# Upper Byte Control (SRAM) To enable DQ15-DQ8

LBS# Lower Byte Control (SRAM) To enable DQ7-DQ0

WP# Write Protect To protect and unprotect sectors from Erase or Program operation

RST# Reset To Reset and return the device to Read mode

RY/BY# Ready/Busy# To output the status of a Program or Erase Operation

RY /BY# is a open drain output, so a 10KΩ - 100KΩ pull-up resistor is requi red to

allow RY/BY# to transition high indicating the device is ready to read.

VSSF2Ground Flash2 only

VSSS2Ground SRAM2 only

VSS Ground

VDDFPower Supply (Flash) 2.7-3.3V Power Supp l y to Flash only

VDDSPower Supply (SRAM) 2.7-3.3V Power Supply to SRAM only

NC No Connection Unconnected pins

T2.1 1217

1. AMS = Most Significant Address

AMS = A16 for SST34HF1621A, A17 for SST34HF1641A, and A18 for SST34HF1681

2. LS package only

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

TABLE 3: OPERATIONAL MODES SELECTION1

Mode BEF# BES1# BES22OE#3WE#3LBS# UBS# DQ0-7 DQ8-15

Full Standby VIH VIH XXXXXHIGH-ZHIGH-Z

IL XXXX

Output Disable VIH VIL VIH VIH VIH XXHIGH-Z HIGH-Z

VIL VIH XXV

IH VIH

VIL VIH XV

IH VIH XXHIGH-ZHIGH-Z

Flash Rea d VIL VIH XV

IL VIH XXD

OUT DOUT

Flash Write VIL VIH X VIH VIL XXD

IN DIN

Flash Erase VIL VIH XV

IH VIL XX X X

SRAM Read VIH V

IL VIH VIL VIH VIL V

IL DOUT DOUT

VIH VIL HIGH-Z DOUT

VIL VIH DOUT HIGH-Z

SRAM Write VIH VIL VIH XV

IL VIL VIL DIN DIN

VIH VIL HIGH-Z DIN

VIL VIH DIN HIGH-Z

Product

Identification4VIL VIH X VIL VIH X X Manufacturer’s ID5

Device ID5

T3.2 1217

1. X can be VIL or VIH, but no other value.

2. Do not apply BEF# = VIL, BES1# = VIL and BES2 = VIH at the same time

3. OE# = OEF# and OES#

WE# = WEF# and WES# for LS package only

4. Software mode only

5. With A19-A1 = 0; SST Manufacturer’s ID = 00BFH, is read with A0=0,

SST34HF16x1A/1681 Device ID = 2761H, is read with A0=1

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command

Sequence 1st Bus

Write Cycle 2nd Bus

Write Cycle 3rd Bus

Write Cyc le 4th Bus

Write Cycle 5th Bus

Write Cycle 6th Bus

Write Cycle

Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2

Word-Program 5555H AAH 2AAAH 55H 5555H A0H WA3Data

Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX430H

Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BAX450H

Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Software ID Entry55555H AAH 2AAAH 55H 5555H 90H

CFI Query Entry55555H AAH 2AAAH 55H 5555H 98H

Software ID Exit/

CFI Exit65555H AAH 2AAAH 55H 5555H F0H

T4.1 1217

1. Address format A14-A0 (Hex),Address A19-A15 can be VIL or VIH, but no other value, for the Command sequence.

2. Data format DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence.

3. WA = Program Word address

4. SAX for Sector-Erase; uses A19-A11 address lines

BAX, for Block-Erase; uses A19-A15 address lines

5. The device does not remain in Software Product Identification Mode if powered down.

6. With A20-A1 = 0; SST Manufacturer’s ID = 00BFH, is read with A0=0

SST34HF16x1A/1681 Device ID = 2761H, is read with A0=1.

TABLE 5: CFI QUERY IDENTIFICATION STRING1

1. Refer to CFI publication 100 for more details.

Address Data Data

10H 0051H Que ry Unique ASCII string “QRY”

11H 0052H

12H 0059H

13H 0001H Primary OEM command set

14H 0007H

15H 0000H Ad dress for Primary Extended Table

16H 0000H

17H 0000H Alternate OEM command set (00H = none exists)

18H 0000H

19H 0000H Address for Alternate OEM extended Table (00H = none exits)

1AH 0000H

T5.0 1217

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

TABLE 6: SYSTEM INTERFACE INFORMATION

Address Data Data

1BH 0027H VDD Min (Program/Erase)

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1CH 0036H VDD Max (Program/Erase)

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1DH 0000H VPP Min (00H = no VPP pin)

1EH 0000H VPP Max (00H = no VPP pin)

1FH 0004H Typica l time out for Word-Program 2N µs (24 = 16 µs)

20H 0000H Typical time out for Min size buffer program 2N µs (00H = not supported)

21H 0004H Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)

22H 0006H Typica l time out for Chip-Erase 2N ms (26 = 64 ms)

23H 0001H Maximum time out for Word-Prog r am 2N times typical (21 x 24 = 32 µs)

24H 0000 H Maximum time out for buffer prog ram 2N times typical

25H 0001H Maximum time out for individual Sector/Block-Erase 2N times typical

(21 x 24 = 32 ms)

26H 0001H Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms)

T6.0 1217

TABLE 7: DEVICE GEOMETRY INFORMATION

Address Data Data

27H 0015H De vice size = 2N Byte (15H = 21; 221 = 2M Bytes)

28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface

29H 0000H

2AH 0000H Ma ximum number of byte in multi-byte write = 2N (00H = not supported)

2BH 0000H

2CH 0002H Number of Erase Sector/Block sizes supported by device

2DH 00FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size)

2EH 0003H y = 1023 + 1 = 1024 sectors (03FF = 1023)

2FH 0008H

30H 0000H z = 8 x 256 Bytes = 2 KByte/sector (0008H = 8)

31H 001FH Block Information (y + 1 = Number of blocks; z x 256B = block size)

32H 0000H y = 31 + 1 = 32 blocks (001F = 31)

33H 0000H

34H 0001H z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)

T7.0 1217

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD1+0.3V

Transient Voltage (<20 ns) on Any Pin to Ground Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD1+1.0V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Output Short Circuit Current2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. VDD = VDDF and VDDS

2. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE

Range Ambient Temp VDD

Commercial 0°C to +70°C 2.7-3.3V

Extended -20°C to +85°C 2.7-3.3V

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF

See Figures 20 and 21

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

TABLE 8: DC OPERATING CHARACTERISTICS (VDD = VDDF AND VDDS = 2.7-3.3V)

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Active VDD Current Address input = VILT/VIHT, at f=1/TRC Min,

VDD=VDD Max, all DQs open

Read OE#=VIL, WE#=VIH

Flash 35 mA BEF#=VIL, BES1#=VIH, or BES2=VIL

SRAM 30 mA BEF#=VIH, BES1#=VIL , BES2=VIH

Concurrent Operation 60 mA BEF#=VIH, BES1#=VIL , BES2=VIH

Write1WE#=VIL

Flash 40 mA BEF#=VIL, BES1#=VIH, or BES2=VIL, OE#=VIH

SRAM 30 mA BEF#=VIH, BES1#=VIL , BES2=VIH

ISB Standby VDD Current 3.0V

3.3V 40

75 µA

µA VDD = VDD Max, BEF#=BES1#=VIHC, BES2=VILC

IRT Reset VDD Current 30 µA Reset=VSS±0.3V

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max

VIH Input High Voltage 0.7 VDD VV

DD=VDD Max

VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max

VOLF Flash Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min

VOHF Flash Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

VOLS SRAM Output Low Voltage 0.4 V IOL =1 mA, VDD=VDD Min

VOHS SRAM Output High Voltage 2.2 V IOH =-500 µA, VDD=VDD Min

T8.1 1217

1. IDD active while Erase or Program is in progress.

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

TABLE 9: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

TPU-READ1Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Write Operation 100 µs

T9.0 1217

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 10: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance VI/O = 0V 20 pF

CIN1Input Capacitance VIN = 0V 16 pF

T10.0 1217

TABLE 11: FLASH RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

NEND1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T11.0 1217

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

AC CHARACTERISTICS

TABLE 12: SRAM READ CYCLE TIMING PARAMETERS

Min Max Units

TRCS Read Cycle Time 70 ns

TAAS Address Access Time 70 ns

TBES Bank Enable Access Time 70 ns

TOES Output Enable Access Time 35 ns

TBYES UBS#, LBS# Access Time 70 ns

TBLZS1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

BES# to Active Output 0 ns

TOLZS1Output Enable to Active Output 0 ns

TBYLZS1UBS#, LBS# to Active Output 0 ns

TBHZS1BES# to High-Z Output 25 ns

TOHZS1Output Disable to High-Z Output 25 ns

TBYHZS1UBS#, LBS# to High-Z Output 35 ns

TOHS Output Hold from Address Change 10 ns

T12.2 1217

TABLE 13: SRAM WRITE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

TWCS Write Cycle Time 70 ns

TBWS Bank Enable to End-of-Write 60 ns

TAWS Address Valid to End-of-Write 60 ns

TASTS Address Set-up Time 0 ns

TWPS Write Pulse Width 60 ns

TWRS Write Recovery Time 0 ns

TBYWS UBS#, LBS# to End-of-Write 60 ns

TODWS Output Disable from WE# Low 30 ns

TOEWS Output Enable from WE# High 0 ns

TDSS Data Set-up Time 30 ns

TDHS Data Hold from Write Time 0 n s

T13.2 1217

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

TABLE 14: FLASH READ CYCLE TIMING PARAMETERS VDD = 2.7-3.3V

Symbol Parameter Min Max Units

TRC Read Cycle Time 70 ns

TCE Chip Enable Access Time 70 ns

TAA Address Access Time 70 ns

TOE Output Enable Access Time 35 ns

TCLZ1BEF# Low to Active Output 0 ns

TOLZ1OE# Low to Active Output 0 ns

TCHZ1BEF# High to High-Z Output 20 ns

TOHZ1OE# High to High-Z Output 20 ns

TOH1Output Hold from Address Change 0 ns

TRP1RST# Pulse Width 500 ns

TRHR1RST# High Before Read 50 ns

TRY1,2 RST# Pin Low to Read 150 µs

T14.3 1217

1. This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.

2. This parameter applies to Sector-Erase, Block-Erase and Program operations. This parameter does not apply to Chip-Erase.

TABLE 15: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

TBP Word-Program Time 20 µs

TAS Address Setup Time 0 ns

TAH Address Hold Time 40 ns

TCS WE# and BEF# Setup Time 0 ns

TCH WE# and BEF# Hold Time 0 ns

TOES OE# High Setup Time 0 ns

TOEH OE# High Hold Time 10 ns

TCP BEF# Pulse Width 40 ns

TWP WE# Pulse Width 40 ns

TWPH1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

WE# Pulse Width High 30 ns

TCPH1 BEF# Pulse Width High 30 ns

TDS Data Setup Time 30 ns

TDH1Data Hold Time 0 ns

TIDA1Software ID Access and Exit Time 150 ns

TBY1RY/BY# Delay Time 90 ns

TBR1Bus# Recovery Time 1µs

TSE Sector-Erase 25 ms

TBE Block-Erase 25 ms

TSCE Chip-Erase 100 ms

T15.0 1217

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

FIGURE 4: SRAM READ CYCLE TIMING DIAGRAM

FIGURE 5: SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1

DDRESSES AMSS-0

DQ15-0

UBS#, LBS#

OE#

BES1#

BES2

TRCS

TAAS

TBES

TOES

TBLZS

TOLZS

TBYES

TBYLZS TBYHZS

D ATA V ALID

TOHZS

TBHZS

TOHS

1217 F04.0

TBES

Note: AMSS = Most Significant Address

AMSS = A16 for SST34HF1621A, A17 for SST34HF1641A, and A18 for SST34HF1681

TAWS

DDRESSES AMSS3-0

BES1#

BES2

WE#

UBS#, LBS#

TWPS TWRS

TWCS

TASTS

TBWS

TBYWS

TODWS TOEWS

TDSS TDHS

1217 F05.0

NOTE 2

DQ15-8, DQ7-0 VALID DATA IN

Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.

2. If BES1# goes Low or BES2 goes high coincident with or after WE# goes Low, the output will remain at high impedance.

If BES1# goes High or BES2 goes low coincident with or before WE# goes High, the output will remain at high impedance.

Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.

3. AMSS = Most Significant SRAM Address

AMSS = A16 for SST34HF1621A, A17 for SST34HF1641A, and A18 for SST34HF1681

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

FIGURE 6: SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1

DDRESSES AMSS3-0

WE#

BES1#

BES2

TBWS

TAWS

TWCS

TWPS TWRS

TASTS TBYWS

DQ15-8, DQ7-0 VALID DATA IN

NOTE 2 NOTE 2

TDSS TDHS

UBS#, LBS#

1217 F06.0

Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.

2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.

3. AMSS = Most Significant SRAM Address

AMSS = A16 for SST34HF1621A, A17 for SST34HF1641A, and A18 for SST34HF1681

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

FIGURE 7: FLASH READ CYCLE TIMING DIAGRAM

FIGURE 8: FLASH WE# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM

1217 F07.0

DDRESS A19-0

DQ15-0

WE#

OE#

BEF# TCE

TRC TAA

TOE

TOLZ

VIH

HIGH-Z TCLZ TOH TCHZ

HIGH-Z

D ATA V ALIDD ATA V ALID

TOHZ

1217 F08.0

DDRESS A19-0

DQ15-0 TDH

TWPH

TDS

TWP

TAH

TAS

TCH

TCS TBY

BEF#

RY/BY#

5555 2AAA 5555 ADDR

XXAA XX55 XXA0 DATA

WORD

(ADDR/DATA)

OE#

WE#

TBR

TBP

Note: X can be VIL or VIH, but no other value.

VALID

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

FIGURE 9: FLASH BEF# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM

FIGURE 10: FLASH DATA# POLLING TIMING DIAGRAM

VALID

1217 F09.0

DDRESS A19-0

DQ15-0 TDH

TCPH

TDS

TCP

TAH

TAS

TCH

TCS

WE#

5555 2AAA 5555 ADDR

XXAA XX55 XXA0 DATA

WORD

(ADDR/DATA)

OE#

BEF#

TBP

TBY

RY/BY# TBR

Note: X can be VIL or VIH, but no other value.

1217 F10.0

DDRESS A19-0

DQ7DATA# DATA# VALID DATA

WE#

OE#

BEF#

TOEH

TOE

TCE

TOES

TBR

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

FIGURE 11: FLASH TOGGLE BIT TIMING DIAGRAM

FIGURE 12: FLASH WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM

1217 F11.0

DDRESS A19-0

DQ6

WE#

OE#

BEF#

TOE

TOEH

TCE

TWO READ CYCLES

WITH SAME OUTPUTS

VALID DATA

TBR

VALID

TBR

1217 F12.0

DDRESS A19-0

DQ15-0

WE#

5555 2AAA 2AAA5555 5555

XX55 XX10XX55XXAA XX80 XXAA

5555

OE#

BEF#

SIX-BYTE CODE FOR CHIP-ERASE

TSCE

TWP

TBY

RY/BY#

Note: This device also supports BEF# controlled Chip-Erase operation.

The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 15.)

X can be VIL or VIH, but no other value.

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

FIGURE 13: FLASH WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM

FIGURE 14: FLASH WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM

1217 F13.0

DDRESS A19-0

DQ15-0

WE#

5555 2AAA 2AAA5555 5555

XX55 XX50XX55XXAA XX80 XXAA

BAX

OE#

BEF#

SIX-BYTE CODE FOR BLOCK-ERASE

TWP

TBY

RY/BY#

VALID

TBR

TBE

Note: This device also supports BEF# controlled Block-Erase operation.

The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 15.)

BAX = Block Address

X can be VIL or VIH, but no other value.

1217 F14.0

DDRESS A

19-0

15-0

WE#

5555 2AAA 2AAA5555 5555

XX55 XX30XX55XXAA XX80 XXAA

OE#

BEF#

SIX-BYTE CODE FOR SECTOR-ERASE

RY/BY#

VALID

Note: This device also supports BEF# controlled Sector-Erase operation.

The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 15.)

SAX = Sector Address

X can be VIL or VIH, but no other value.

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

FIGURE 15: FLASH SOFTWARE ID ENTRY AND READ

FIGURE 16: FLASH CFI ENTRY AND READ

1217 F15.0

DDRESS A14-0

TIDA

DQ15-0

WE#

5555 2AAA 5555 0000 0001

OE#

BEF#

Three-Byte Sequence For Software ID Entry

TWP

TWPH TAA

00BF Device ID

XX55XXAA XX90

Note: X can be VIL or VIH, but no other value.

Device ID - 2761H for SST34HF1621A, SST34HF1641A, and SST34HF1681

1217 F16.0

DDRESS A14-0

TIDA

DQ15-0

WE#

5555 2AAA 5555

OE#

BEF#

Three-Byte Sequence For CFI Query Entry

TWP

TWPH TAA

XX55XXAA XX98

Note: X can be VIL or VIH, but no other value.

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

FIGURE 17: FLASH SOFTWARE ID EXIT/CFI EXIT

FIGURE 18: RST# TIMING (WHEN NO INTERNAL OPERATION IS IN PROGRESS)

FIGURE 19: RST# TIMING (DURING SECTOR- OR BLOCK-ERASE OPERATION)

1217 F17.0

DDRESS A14-0

DQ15-0

TIDA

TWP

TWHP

WE#

5555 2AAA 5555

Three-Byte Sequence for Software ID Exit and Reset

OE#

BEF#

XXAA XX55 XXF0

Note:X can be VIL or VIH, but no other value

1217 F18.0

RY/BY#

RST#

EF#/OE#

TRP

TRHR

1217 F19

Y/BY#

BEF#

OE#

TRP

TRY

TBR

RST#

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

FIGURE 20: AC INPUT/OUTPUT REFERENCE WAVEFORMS

FIGURE 21: A TEST LOAD EXAMPLE

1217 F20.0

REFERENCE POINTS OUTPUTINPUT VIT

IHT

ILT

VOT

A C test inputs are driv en at VIHT (0. 9 VDD) f or a logic “1” and VILT (0.1 VDD) f o r a logic “0”. Measurement r ef erence points

f or inputs and outputs are VIT (0.5 VDD) and V OT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

Note: VIT - VINPUT Test

VOT - VOUTPUT Test

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

1217 F21.0

T O TESTER

O DUT

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

FIGURE 22: WORD-PROGRAM ALGORITHM

1217 F22.0

Start

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XXA0H

Address: 5555H

Load W ord

Address/Word

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

ote: X can be VIL or VIH, but no other valu

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

FIGURE 23: WAIT OPTIONS

1217 F23.0

W ait TBP,

TSCE, TSE

or TBE

Program/Erase

Initiated

Internal Timer Toggle Bit

Yes

Program/Erase

Completed

Does DQ6

match?

Read same

word

Data# Polling

Program/Erase

Completed

Program/Erase

Completed

Read word

Is DQ7 =

true data?

Read DQ7

Program/Erase

Initiated

Program/Erase

Initiated

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

FIGURE 24: SOFTWARE PRODUCT ID/CFI COMMAND FLOWCHARTS

1217 F24.0

Load data: XXAAH

Address: 5555H

Software Product ID Entry

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX90H

Address: 5555H

W ait TIDA

Read Software ID

Load data: XXAAH

Address: 5555H

CFI Query Entry

ommand Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX98H

Address: 5555H

W ait TIDA

Read CFI data

Load data: XXAAH

Address: 5555H

Software ID Exit/CFI Ex

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XXF0H

Address: 5555H

W ait TIDA

Return to normal

operation

Note: X can be VIL or VIH, but no other value.

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

FIGURE 25: ERASE COMMAND SEQUENCE

1217 F25.0

Load data: XXAAH

Address: 5555H

Chip-Erase

ommand Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX10H

Address: 5555H

Load data: XXAAH

Address: 5555H

W ait TSCE

Chip erased

to FFFFH

Load data: XXAAH

Address: 5555H

Sector-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX30H

Address: SAX

Load data: XXAAH

Address: 5555H

W ait TSE

Sector erased

to FFFFH

Load data: XXAAH

Address: 5555H

Block-Erase

Command Sequenc

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX50H

Address: BAX

Load data: XXAAH

Address: 5555H

W ait TBE

Block erased

to FFFFH

Note: X can be VIL or VIH, but no other value.

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

PRODUCT ORDERING INFORMATION

Environmental Attribute

E = non-Pb

Package Modifier

P = 56 balls

S = 62 balls

Package Type

L1 = LFBGA (8mm x 10mm x 1.4mm, 0.45mm ba ll size )

L = LFBGA (8mm x 10mm x 1.4mm, 0.40mm ball siz e)

LF = LFBGA (8mm x 10mm x 1.4mm, 0.40mm ball size)

Temperature Ra nge

C = Commercial = 0°C to +70°C

E = Extended = -20°C to +85°C

Minimum Endurance

4 =10,000 cycles

Read Access Speed

70 = 70 ns

Bank Split

1 = 12Mbit + 4Mbit

SRAM Density

0 = No SRAM

2 = 2 Mbit

4 = 4 Mbit

8 = 8 Mbit

Flash Density

16 = 16 Mbit

Voltage

H = 2.7-3.3V

Product Series

34 = Concurrent Su perFlash + SRAM ComboMemor

Device Speed Suffix1 Suffix2

SST34HF16xxX- XXX -XX-XXXX

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

Valid combinations for SST34HF1621A

SST34HF1621A-70-4C-L1P SST34HF1621A-70-4C-LS SST34HF1621A-70-4C-LFP

SST34HF1621A-70-4C-L1PE SST34HF1621A-70-4C-LSE

SST34HF1621A-70-4E-L1P SST34HF1621A-70-4E-LS SST34HF1621A-70-4E-LFP

SST34HF1621A-70-4E-L1PE SST34HF1621A-70-4E-LSE

Valid combinations for SST34HF1641A

SST34HF1641A-70-4C-L1P SST34HF1641A-70-4C-LS SST34HF1641A-70-4C-LFP

SST34HF1641A-70-4C-L1PE SST34HF1641A-70-4C-LSE

SST34HF1641A-70-4E-L1P SST34HF1641A-70-4E-LS SST34HF1641A-70-4E-LFP

SST34HF1641A-70-4E-L1PE SST34HF1641A-70-4E-LSE

Valid combinations for SST34HF1681

SST34HF1681-70-4C-L1P SST34HF1681-70-4C-LS SST34HF1681-70-4C-LFP

SST34HF1681-70-4C-L1PE SST34HF1681-70-4C-LSE

SST34HF1681-70-4E-L1P SST34HF1681-70-4E-LS SST34HF1681-70-4E-LFP

SST34HF1681-70-4E-L1PE SST34HF1681-70-4E-LSE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

PACKAGING DIAGRAMS

56-BALL L OW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 8MM X 10MM

SST PACKAGE CODE: L1P

H G F E D C B A

A B C D E F G H

SIDE VIEW

SEATING PLANE 0.35 ± 0.05

1.30 ± 0.10

0.12

0.45 ± 0.0

(56X)

0.80

5.60

0.80

5.60

56-lfbga-L1P-8x10-450mic

-4

ote: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.38 mm (± 0.05 mm)

1mm

A1 CORNER

BOTTOM VIEWTOP VIEW

8.00 ± 0.20

A1 CORNER

10.00 ± 0.20

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

62-BALL L OW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 8MM X 10MM

SST PACKAGE CODE: LS

A1 CORNER

K J H G F E D C B A

A B C D E F G H J K

BOTTOM VIEWTOP VIEW

8.00 ± 0.20

0.40 ± 0.0

(62X)

A1 CORNER

10.00 ± 0.20

0.80

5.60

0.80

7.20

62-lfbga-LS-8x10-400mic-

ote: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.32 mm (± 0.05 mm)

1mm

SIDE VIEW

SEATING PLANE 0.32 ± 0.05

1.30 ± 0.10

0.12

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EOL Product Data Sheet

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1621A / SST34HF1641A / SST34HF1681

56-BALL L OW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 8MM X 10MM

SST PACKAGE CODE: LFP

TABLE 16: REVISION HISTORY

Number Description Date

00 •Initial Release Jul 2002

01 •Added the LFP package and corresponding mark eting part numbers Nov 2002

02 •Corrected signal references in Section “Ready/Busy# (RY/BY#)” on page 4

•Corrected the Test Conditions for IDD in Table 8 on page 14

•Added Revision History

Jun 2003

03 •Removed 80 ns parts

•Added non-Pb MPNs (See page 32) Sep 2003

04 •2004 Data Book

•Updated the L1 P, LS, and LFP package diagrams Nov 2003

05 •End-of-Life product data sheet for all parts in S71217

•Recommended repl acement parts are in S71252:

– SST34HF1621A is replaced by SST34HF1621C

– SST34HF1641A is replaced by SST34HF1641C

– SST34HF1681 is replaced by SST34HF1681D

Mar 2005

A1 CORNER

H G F E D C B A

A B C D E F G H

BOTTOM VIEWTOP VIEW

SIDE VIEW

SEATING PLANE 0.32 ± 0.05

1.30 ± 0.10

0.12

8.00 ± 0.20

0.40 ± 0.0

(56X)

A1 CORNER

10.00 ± 0.20

0.80

5.60

0.80

5.60

56-lfbga-LFP-8x10-400mic-

ote: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.32 mm (± 0.05 mm)

1mm

Silicon Storage Technology, Inc. • 1171 Sonora Cour t • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036

www.SuperFlash.com or www.sst.com

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