DS07-13709-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX
MB90580B Series
MB90583B/587/F583B/V580B
■DESCRIPTION
The MB90580B series is a line of general-pur pose, Fujitsu 16-bit microcontrollers designed for process control
applications which require high-speed real-time processing, such as consumer products.
While inheriting the AT architecture of the F2MC*1 family, the instruction set for the F2MC-16LX CPU core of the
MB90580B series incor porates additional instructions for high-level languages, suppor ts extended addressing
modes, and contains enhanced multiplication and division instructions as well as a substantial collection of
improved bit manipulation instructions. In addition, the MB90580B has an on-chip 32-bit accumulator which
enables processing of long-word data.
The peripheral resources integrated in the MB90580B series include: an 8/10-bit A/D conver ter, an 8-bit D/A
converter, UARTs (SCI) 0 to 4, an 8/16-bit PPG timer, 16-bit I/O timers (16-bit free-run timer, input capture units
(ICUs) 0 to 3, output compare units (OCUs) 0 and 1), and an IEBusTM controller *2.
Notes: *1: F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.
*2: IEBusTM is a trademark of NEC Corporation.
■FEATURES
• Minimum execution time: 62.5 ns/4 MHz oscillation (Uses PLL clock multiplication) maximum multiplier = 4
• Maximum memory space
16 Mb yte
Linear/bank access
(Continued)
■PACKAGES
100 pin plastic LQFP 100 pin plastic QFP
(FPT-100P-M05) (FPT-100P-M06)
MB90580B Series
2
(Continued)
• Instruction set optimized for controller applications
Supported data types: bit, byte, word, and long-word types
Standard addressing modes: 23 types
32-bit accumulator enhancing high-precision operations
Signed multiplication/division and extended RETI instructions
• Enhanced high level language (C) and multitasking support instructions
Use of a system stack pointer
Symmetrical instruction set and barrel shift instructions
• Program patch function (for two address pointers)
• Enhanced execution speed : 4 byte instruction queue
• Enhanced interrupt function
Up to eight priority levels programmable
External interrupt inputs: 8 lines
• Automatic data transmission function independent of CPU operation
Up to 16 channels for the extended intelligent I/O service
DTP request inputs: 8 lines
• Internal ROM
FLASH: 128 Kbyte
MASKROM: 128 Kbyte (MB90583B) , 64 Kbyte (MB90587)
• Internal RAM
FLASH: 6 Kbyte
MASKROM: 6 Kbyte (MB90583B) , 4 Kbyte (MB90587)
• General-purpose ports
Up to 77 channels (Input pull-up resistor settable f or: 24 channels. Output open drain settable for: 8 channels)
•IEBus
TM controller*
Three different data transfer rates selectable
Mode 0: 3.9 Kbps (16 bytes/frame)
Mode 1: 17.0 Kbps (32 bytes/frame)
Mode 2: 26.0 Kbps (128 bytes/frame)
*: IEBusTM is a trademark of NEC Corporation.
• A/D Converter (RC) : 8 ch
8/10-bit resolution
Conversion time: 34.7 µs (Min.) , 12 MHz operation
• D/A Converter : 2 ch
8-bit resolutions
Setup time: 12.5 µs
•UART : 5 ch
• 8/16 bit PPG : 1 ch
8 bits × 2 channels: 16 bits × 1 channel: Mode switching function provided
• 16 bit reload timer: 3 ch
• 16-bit PWC timer: 1 channel
Noise filter provided. Available to pulse width counter
• 16 bit I/O timer
Input capture : 4 ch
Output compare : 2 ch
Free run timer: 1 ch
• Inter nal clock generator
• Time-base counter/watchdog timer: 18-bit
(Continued)
MB90580B Series
3
(Continued)
• Clock monitor function integrated
• Low-power consumption mode
Sleep mode
Stop mode
Hardware standby mode
CPU intermittent operation mode
• Package: LQFP-100 / QFP-100
•CMOS technology
MB90580B Series
4
■PRODUCT LINEUP
(Continued)
Item
Part number MB90587 MB90583B MB90F583B MB90V580B
Classification Mass-produced products
(MASK ROM) Mass-produced products
(Flash ROM)
Development/
evaluation
product
ROM size 64 Kbytes 128 Kbytes 128 Kbytes None
RAM size 4 Kbytes 6 Kbytes 6 Kbytes 6 Kbytes
CPU functions
The number of instructions: 340
Instruction bit length: 8 bits, 16 bits
Instruction length: 1 byte to 7 bytes
Data bit length: 1 bit, 8 bits, 16 bits
Minimum execution time: 62.5 ns (at machine clock of 16 MHz)
Interrupt processing time: 1.5 ms (at machine clock of 16 MHz, minimum value)
Ports
General-purpose I/O ports (CMOS output)
General-purpose I/O port (Can be set as open-drain)
General-purpose I/O ports (Input pull-up resistors available)
Total:
: 45
: 8
: 24
: 77
IEBusTM controller None
Communication mode: Half-duplex, asynchronous communication
Multi-master system
Access control: CDMA/CD
Three modes selectable for different transmission speeds
Transmit buffer: 8-byte FIFO buffer
Receive buffer: 8-byte FIFO buffer
Timebase timer 18-bit counter
Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms (At oscillation of 4 MHz)
Watchdog timer Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(at oscillation of 4 MHz, minimum value)
Clock timer 15-bit counter
Interrupt interval: 1 s, 0.5 s, 0.25 s, 31.25 ms (At oscillation of 32.768 kHz)
8/16-bit PPG timer
Number of channels: 1 (8-bit × 2 channels)
PPG operation of 8-bit or 16-bit
A pulse wave of given intervals and given duty ratios can be output.
Pulse interval: 62.5 ns to 1 ms (at oscillation of 4 MHz, machine clock of 16 MHz)
16-bit reload timer Number of channels: 3
Event count provided
Interval: 125 ns to 131 ms (at oscillation of 4 MHz, machine clock of 16 MHz)
PWC timer Number of channels: 1
Timer function (select the counter timer from three internal clocks.)
Pulse width measuring function (select the counter timer from three internal clocks.)
MB90580B Series
5
(Continued)
* : Varies with conditions such as the operating frequency (See section “■ ELECTRICAL CHARACTERISTICS”).
Assurance for the MB90V580B is given only for operation with a tool at a power supply voltage of 4.5 V to 5.5
V, an operating temperature of 0 to +25 °C, and an operating frequency of 1 MHz to 16 MHz.
■PACKAGE AND CORRESPONDING PRODUCTS
: Available × : Not available
Note: For more information about each package, see section “■ PACKAGE DIMENSIONS”.
Item
Part number MB90587 MB90583B MB90F583B MB90V580B
16-bit
I/O
timer
16-bit
free run timer Number of channels: 1
Overflow interrupts
Output compare
(OCU) Number of channels: 2
Pin input factor: A match signal of compare register
Input capture (ICU) Number of channels: 4
Rewriting a register value upon a pin input (rising, falling, or both edges)
DTP/external interrupt circuit Number of inputs: 8
Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.
External interrupt circuit or extended intelligent I/O service (EI2OS) can be used.
Delayed interrupt generation
module An interrupt generation module for switching tasks used in real time operating
systems.
UART0, 1, 2, 3, 4
Clock synchronized transmission (62.5 kbps to 1 Mbps)
Clock asynchronized transmission (1202 bps to 9615 bps)
Transmission can be performed by bi-directional serial transmission or by master/
slave connection.
A/D converter
Resolution: 8/10-bit changable
Number of inputs: 8
One-shot conversion mode (converts selected channel only once)
Scan conversion mode
(converts two or more successive channels and can program up to 8 channels.)
Continuous conversion mode (converts selected channel repeatedly)
Stop conversion mode (converts selected channel and stop operation repeatedly)
D/A converter 8-bit resolution
Number of channels: 2 channels
Based on the R-2R system
Low-power consumption
(standby) mode Sleep/stop/CPU intermittent operation/clock timer/hardware standby
Process CMOS
Power supply voltage for
operation* 4.5V to 5.5 V*
Package MB90583B MB90587 MB90F583B
FPT-100P-M05
FTP-100P-M06
MB90580B Series
6
■DIFFERENCES AMONG PRODUCTS
Memory Size
In evaluation with an evaluation product, note the difference between the evaluation product and the product
actually used. The following items must be taken into consideration.
• The MB90V580B does not have an inter nal ROM, however, operations equivalent to chips with an inter nal
R OM can be evaluated by using a dedicated de velopment tool, enabling selection of ROM size by settings of
the development tool.
• In the MB90V580B, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH to
mapped to bank FE and FF only. (This setting can be changed by configuring the deveolpment tool.)
• In the MB90583B/587/F583B, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to
FF3FFFH to bank FF only.
IEBusTM Controller
• MB90587 does not have an IEBusTM Controller.
MB90580B Series
7
■PIN ASSIGNMENT
(TOP VIEW)
(FPT-100P-M05)
P22/A18
P23/A19
P24/A20
P25/A21
P26/A22
P27/A23
P30/ALE
P31/RD
VSS
P32/WRL
P34/HRQ
P33/WRH
P35/HAK
P36/RDY
P37/CLK
P40/SIN0
P41/SOT0
P42/SCK0
P43/SIN1
P44/SOT1
VCC
P45/SCK1
P46/ADTG
P47
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
RST
PA1
PA0
P97/POT
P96/PWC
P95/TOT2/OUT1
P94/TOT1/OUT0
P93/TOT0/IN3
P92/TIN2/IN2
P91/TIN1/IN1
P90/TIN0/IN0
RX*
TX*
P65/CKOT
P64/PPG0
P63/PPG1
P62/SCK2
P61/SOT2
P60/SIN2
P87/IRQ7
P86/IRQ6
P85/IRQ5
P84/IRQ4
P83/IRQ3
P82/IRQ2
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P21/A17
P20/A16
P17/AD15
P16/AD14
P15/AD13
P14/AD12
P13/AD11
P12/AD10
P11/AD09
P10/AD08
P07/AD07
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
P01/AD01
P00/AD00
VCC
X1
X0
VSS
X0A
X1A
PA2
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P71
P72
DVRH
DVSS
P73/DA00
P74/DA01
AVCC
AVRH
AVRL
AVSS
P50/AN0/SIN3
P51/AN1/SOT3
P52/AN2/SCK3
P53/AN3
VSS
P54/AN4/SIN4
P55/AN5/SOT4
P56/AN6/SCK4
P57/AN7
P80/IRQ0
P81/IRQ1
MD0
MD1
MD2
HST
* : N.C. pin on the MB90587
MB90580B Series
8
(TOP VIEW)
(FPT-100P-M06)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P20/A16
P21/A17
P22/A18
P23/A19
P24/A20
P25/A21
P26/A22
P27/A23
P30/ALE
P31/RD
VSS
P32/WRL
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
P40/SIN0
P41/SOT0
P42/SCK0
P43/SIN1
P44/SOT1
VCC
P45/SCK1
P46/ADTG
P47
C
P71
P72
DVRH
X0A
PA2
RST
PA1
PA0
P97/POT
P96/PWC
P95/TOT2/OUT1
P94/TOT1/OUT0
P93/TOT0/IN3
P92/TIN2/IN2
P91/TIN1/IN1
P90/TIN0/IN0
RX*
TX*
P65/CKOT
P64/PPG0
P63/PPG1
P62/SCK2
P61/SOT2
P60/SIN2
P87/IRQ7
P86/IRQ6
P85/IRQ5
P84/IRQ4
P83/IRQ3
P82/IRQ2
HST
MD2
X1A
P17/AD15
P16/AD14
P15/AD13
P14/AD12
P13/AD11
P12/AD10
P11/AD09
P10/AD08
P07/AD07
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
P01/AD01
P00/AD00
VCC
X1
X0
VSS
DVSS
P73/DA00
P74/DA01
P50/AN0/SIN3
P51/AN1/SOT3
P52/AN2/SCK3
P53/AN3
VSS
P54/AN4/SIN4
P55/AN5/SOT4
P56/AN6/SCK4
P57/AN7
P80/IRQ0
P81/IRQ1
MD0
MD1
AVCC
AVRH
AVRL
AVSS
* : N.C. pin on the MB90587
MB90580B Series
9
■PIN DESCRIPTION
*1: FPT-100P-M06
*2: FPT-100P-M05
(Continued)
Pin no. Pin name Circuit
type Function
QFP*1LQFP*2
82 80 X0 A Oscillator pin
83 81 X1 A Oscillator pin
52 50 HST C Hardware standby input pin
77 75 RST B Reset input pin
85 to 92 83 to 90
P00 to
P07 D
(CMOS/H)
General-purpose I/O ports.
A pull-up resistor can be assigned (RD07 to RD00=“1”) by the pull-
up resistor setting register (RDR0). [These pins are disabled with
the output setting (DDR0 register: D07 to D00=“1”).]
AD00 to
AD07 In external bus mode, the pins function as the lower data I/O or low-
er address outputs (AD00 to AD07).
93 to
100 91 to 98
P10 to
P17 F
(CMOS/H)
General-purpose I/O ports.
A pull-up resistor can be assigned (RD17 to RD10=“1”) by the pull-
up resistor setting register (RDR1). [These pins are disabled with
the output setting (DDR1 register: D17 to D10 =“1”).]
AD08 to
AD15 In 16-bit external bus mode, the pins function as the upper data
I/O or middle address outputs (AD08 to AD15).
1 to 8 99,100,
1 to 6
P20 to
P27 F
(CMOS/H)
General-purpose I/O ports
In external bus mode, pins for which the corresponding bit in the
HACR register is “1” function as the A16 to A23 pins.
A16 to
A23
In external bus mode, pins for which the corresponding bit in the
HACR register is “1” function as the upper address output pins
(A16 to A23).
97P30 F
(CMOS/H)
General-purpose I/O port
Functions as the ALE pin in external bus mode.
ALE Functions as the address latch enable signal pin (ALE) in external
bus mode.
10 8 P31 F
(CMOS/H)
General-purpose I/O port
Functions as the RD pin in external bus mode.
RD Functions as the read strobe output pin (RD) in external bus mode.
12 10 P32 F
(CMOS/H)
General-purpose I/O port
Functions as the WRL pin in external bus mode if the WRE bit is
“1”.
WRL Functions as the lower data write strobe output pin (WRL) in
external bus mode.
13 11 P33 F
(CMOS/H)
General-purpose I/O port
Functions as the WRH pin in 16-bit external bus mode if the WRE
bit in the EPCR register is “1”
WRH Functions as the upper data write strobe output pin (WRH) in
external bus mode.
MB90580B Series
10
*1: FPT-100P-M06
*2: FPT-100P-M05
(Continued)
Pin no. Pin name Circuit
type Function
QFP*1LQFP*2
14 12 P34 F
(CMOS/H)
General-purpose I/O port
Functions as the HRQ pin in external bus mode if the HDE bit in the
EPCR register is “1”.
HRQ Functions as the hold request input pin (HRQ) in external bus mode.
15 13 P35 F
(CMOS/H)
General-purpose I/O port
Functions as the HAK pin in external bus mode if the HDE bit in the
EPCR register is “1”.
HAK Functions as the hold acknowledge output pin (HAK) in external bus
mode.
16 14 P36 F
(CMOS/H)
General-purpose I/O port
Functions as the RDY pin in external bus mode if the RYE bit in the
EPCR register is “1”.
RDY Functions as the external ready input pin (RDY) in external bus mode.
17 15 P37 F
(CMOS/H)
General-purpose I/O port
Functions as the CLK pin in external bus mode if the CKE bit in the
EPCR register is “1”.
CLK Functions as the machine cycle clock output pin (CLK) in external bus
mode.
18 16
P40
E
(CMOS/H)
General-purpose I/O port.
This pin serves as an open-drain output port with OD40 in the open-
drain control setting register (ODR4) set to “1”. [The pin is disabled
with the input setting (DDR4 register: D40=“0”).]
SIN0
UART0 serial data input (SIN0) pin.
When UART0 is operating for input, this input is used as required and
thus the output from any other function to the pin must be off unless
used intentionally.
19 17 P41 E
(CMOS/H)
General-purpose I/O port.
This pin serves as an open-drain output port with OD41 in the open-
drain control setting register (ODR4) set to “1”. [The pin is disabled
with the input setting (DDR4 register: D41=“0”).]
SOT0 UART0 serial data output pin (SOT0).
This pin is enabled with the UART0 serial data output enabled.
20 18 P42 E
(CMOS/H)
General-purpose I/O port.
This pin serves as an open-drain output port with OD42 in the open-
drain control setting register (ODR4) set to “1”. [The pin is disabled
with the input setting (DDR4 register: D42=“0”).]
SCK0 UART0 serial clock I/O pin (SCK0).
This pin is enabled with the UART0 clock output enabled.
MB90580B Series
11
*1: FPT-100P-M06
*2: FPT-100P-M05
(Continued)
Pin no. Pin name Circuit
type Function
QFP*1LQFP*2
21 19
P43
E
(CMOS/H)
General-purpose I/O port.
This pin serves as an open-drain output port with OD43 in the open-
drain control setting register (ODR4) set to “1”. [The pin is disabled
with the input setting (DDR4 register: D43=“0”).]
SIN1
UART1 serial data input (SIN1) pin.
When UART1 is operating for input, this input is used as required and
thus the output from any other function to the pin must be off unless
used intentionally.
22 20 P44 E
(CMOS/H)
General-purpose I/O port.
This pin serves as an open-drain output port with OD44 in the open-
drain control setting register (ODR4) set to “1”. [The pin is disabled
with the input setting (DDR4 register: D44=“0”).]
SOT1 UART1 serial data output pin (SOT1).
This pin is enabled with the UART1 serial data output enabled.
24 22 P45 E
(CMOS/H)
General-purpose I/O port.
This pin serves as an open-drain output port with OD45 in the open-
drain control setting register (ODR4) set to “1”. [The pin is disabled
with the input setting (DDR4 register: D45=“0”).]
SCK1 UART1 serial clock I/O pin (SCK1).
This pin is enabled with the UART1 clock output enabled.
25 23 P46 E
(CMOS/H)
General-purpose I/O port.
This pin serves as an open-drain output port with OD46 in the open-
drain control setting register (ODR4) set to “1”. [The pin is disabled
with the input setting (DDR4 register: D46=“0”).]
ADTG External trigger input pin (ADTG) for the A/D converter.
26 24 P47 E
(CMOS/H)
General-purpose I/O port.
This pin serves as an open-drain output port with OD47 in the open-
drain control setting register (ODR4) set to “1”. [The pin is disabled
with the input setting (DDR4 register: D47=“0”).]
38 36
P50
G
(CMOS/H)
General-purpose I/O port.
AN0 Analog input pin (AN0) for use during A/D converter operation.
SIN3
UART3 serial data input pin (SIN3).
When UART3 is operating for input, this input is used as required and
thus the output from any other function to the pin must be off unless
used intentionally.
39 37
P51
G
(CMOS/H)
General-purpose I/O port.
AN1 Analog input pin (AN1) for use during A/D converter operation.
SOT3 UART3 serial data output pin (SOT3).
This pin is enabled with the UART3 serial data output enabled.
MB90580B Series
12
*1: FPT-100P-M06
*2: FPT-100P-M05
(Continued)
Pin no. Pin name Circuit type Function
QFP*1LQFP*2
40 38
P52
G
(CMOS/H)
General-purpose I/O port.
AN2 Analog input pin (AN2) for use during A/D converter operation.
SCK3 UART3 serial clock I/O pin (SCK3).
This pin is enabled with the UART3 clock output enabled.
41 39 P53 G
(CMOS/H) General-purpose I/O port.
AN3 Analog input pin (AN3) for use during A/D converter operation.
43 41
P54
G
(CMOS/H)
General-purpose I/O port.
AN4 Analog input pin (AN4) for use during A/D converter operation.
SIN4
UART4 serial data input pin (SIN4).
When UART4 is operating for input, this input is used as required
and thus the output from any other function to the pin must be off
unless used intentionally.
44 42
P55
G
(CMOS/H)
General-purpose I/O port.
AN5 Analog input pin (AN5) for use during A/D converter operation.
SOT4 UART4 serial data output pin (SOT4).
This pin is enabled with the UART4 serial data output enabled.
45 43
P56
G
(CMOS/H)
General-purpose I/O port.
AN6 Analog input pin (AN6) for use during A/D converter operation.
SCK4 UART4 serial clock output pin (SCK4).
This pin is enabled with the UART4 clock output enabled.
46 44 P57 G
(CMOS/H) General-purpose I/O port.
AN7 Analog input pin (AN7) for use during A/D converter operation.
27 25 C 0.1 µF capacitor coupling pin for regulating the power supply.
28 26 P71 F (CMOS/H) General-purpose I/O port.
29 27 P72 F (CMOS/H) General-purpose I/O port.
32 30 P73 H
(CMOS/H)
General-purpose I/O port.
This pin serves as a D/A output pin (DA00) when the DAE0 bit in
the D/A control register (DACR) is “1”.
DA00 D/A converter output 0 (DA00) pin.
33 31 P74 H
(CMOS/H)
General-purpose I/O port.
This pin serves as a D/A output pin (DA01) when the DAE1 bit in
the D/A control register (DACR) is “1”.
DA01 D/A converter output 1 pin (DA01).
47 45 P80 F
(CMOS/H) General-purpose I/O port.
IRQ0 Functions as external interrupt request input 0 pin (IRQ0).
MB90580B Series
13
*1: FPT-100P-M06
*2: FPT-100P-M05
(Continued)
Pin no. Pin name Circuit type Function
QFP*1LQFP*2
48 46 P81 F
(CMOS/H) General-purpose I/O port.
IRQ1 Functions as external interrupt request input 1 pin (IRQ1).
53 51 P82 F
(CMOS/H) General-purpose I/O port.
IRQ2 Functions as external interrupt request input 2 pin (IRQ2).
54 52 P83 F
(CMOS/H) General-purpose I/O port.
IRQ3 Functions as external interrupt request input 3 pin (IRQ3).
55 53 P84 F
(CMOS/H) General-purpose I/O port.
IRQ4 Functions as external interrupt request input 4 pin (IRQ4).
56 54 P85 F
(CMOS/H) General-purpose I/O port.
IRQ5 Functions as external interrupt request input 5 pin (IRQ5).
57 55 P86 F
(CMOS/H) General-purpose I/O port.
IRQ6 Functions as external interrupt request input 6 pin (IRQ6).
58 56 P87 F
(CMOS/H) General-purpose I/O port.
IRQ7 Functions as external interrupt request input 7 pin (IRQ7).
59 57
P60
D
(CMOS/H)
General-purpose I/O port.
A pull-up resistor can be assigned (RD60=“1”) by the pull-up resistor
setting register (RDR6). [This pin is disabled with the output setting
(DDR6 register: D60=“1”).]
SIN2
UART2 serial data input pin (SIN2).
When UART2 is operating for input, this input is used as required
and thus the output from any other function to the pin must be off
unless used intentionally.
60 58 P61 D
(CMOS/H)
General-purpose I/O port.
A pull-up resistor can be assigned (RD61=“1”) by the pull-up resistor
setting register (RDR6). [This pin is disabled with the output setting
(DDR6 register: D61=“1”).]
SOT2 UART2 serial data output pin (SOT2).
This pin is enabled with the UART2 serial data output enabled.
61 59 P62 D
(CMOS/H)
General-purpose I/O port.
A pull-up resistor can be assigned (RD62=“1”) by the pull-up resistor
setting register (RDR6). [This pin is disabled with the output setting
(DDR6 register: D62=“1”).]
SCK2 UART2 serial clock I/O pin (SCK2).
This pin is enabled with the UART2 clock output enabled.
MB90580B Series
14
(Continued)
*1: FPT-100P-M06
*2: FPT-100P-M05
*3: N.C. pin on the MB90587.
(Continued)
Pin no. Pin name Circuit type Function
QFP*1LQFP*2
62 60 P63 D
(CMOS/H)
General-purpose I/O port.
A pull-up resistor can be assigned (RD63=“1”) by the pull-up resis-
tor setting register (RDR6). [This pin is disabled with the output
setting (DDR6 register: D63=“1”).]
PPG1 The pin serves as the PPG1 output when PPGs are enabled.
63 61 P64 D
(CMOS/H)
General-purpose I/O port.
A pull-up resistor can be assigned (RD64=“1”) by the pull-up resis-
tor setting register (RDR6). [This pin is disabled with the output
setting (DDR6 register: D64=“1”).]
PPG0 The pin serves as the PPG0 output when PPGs are enabled.
64 62 P65 D
(CMOS/H)
General-purpose I/O port.
A pull-up resistor can be assigned (RD65=“1”) by the pull-up resis-
tor setting register (RDR6). [This pin is disabled with the output
setting (DDR6 register: D65=“1”).]
CKOT This pin serves as the CKOT output during CKOT operation.
65 63 TX*3I This pin serves as the IEBusTM output.
66 64 RX*3J
(CMOS) This pin serves as the IEBusTM input.
67 to 69 65 to 67
P90 to
P92
F
(CMOS/H)
General-purpose I/O port.
TIN0 to
TIN2
Event input pins for reload timers 0, 1, and 2.
During reload timer input, these inputs are used continuously and
thus the output from any other function to the pins must be avoided
unless used intentionally.
IN0 to IN2 Trigger inputs for input capture channels 0 to 2
70 68
P93
F
(CMOS/H)
General-purpose I/O port.
TOT0 Reload timer output pin. This function is applied when the output
for reload timer 0 is enabled.
IN3 Trigger inputs for input capture channel 3.
71, 72 69, 70
P94, P95
F
(CMOS/H)
General-purpose I/O port.
TOT1,
TOT2 Reload timer output pins. This function is applied when the output
for reload timer 1 and 2 are enabled.
OUT0,
OUT1 Event output for channel 0 and 1 of the output compare
73 71 P96 F (CMOS/H) General-purpose I/O port.
PWC This pin serves as the PWC input with the PWC timer enabled.
MB90580B Series
15
(Continued)
*1: FPT-100P-M06
*2: FPT-100P-M05
Pin no. Pin name Circuit type Function
QFP*1LQFP*2
74 72 P97 F (CMOS/H) General-purpose I/O port.
POT This pin serves as the PWC output with the PWC timer enabled.
75, 76 73, 74 PA0, PA1 F (CMOS/H) General-purpose I/O port.
78 76 PA2 F (CMOS/H) General-purpose I/O port.
79 77 X1A A Oscillation input pin.
80 78 X0A A Oscillation input pin.
34 32 AVCC A/D converter power supply pin.
37 35 AVSS A/D converter power supply pin.
35 33 AVRH A/D converter external reference power supply pin.
36 34 AVRL A/D converter external reference power supply pin.
30 28 DVRH D/A converter external reference power supply pin.
31 29 DVSS D/A converter power supply pin.
49 to 51 47 to 49 MD0 to
MD2 CInput pin for specifying the operation mode.
Connect these pins directly to Vcc or Vss.
23, 84 21, 82 VCC Power supply (5 V) input pin.
11, 42,
81 9, 40,
79 VSS Power supply (0 V) input pin.
MB90580B Series
16
■I/O CIRCUIT TYPE
(Continued)
Type Circuit Remarks
A
• Oscillation feedback resistance
: Approx. 1 MΩ
B
• Hysteresis input with pull-up
Resistance approx. 50 kΩ
C
• Hysteresis input
D
• Incorporates pull-up resistor control
(for input)
• CMOS level output
• Hysteresis input with standby control
Resistance approx. 50 kΩ
X1, X1A
X0, X0A
HARD,SOFT
STANDBY
CONTROL
Clock input
Pull-up resistor
control
Sandby control signal
MB90580B Series
17
(Continued)
Type Circuit Remarks
E
• CMOS level output
• Hysteresis input with standby control
• Incorporates open-drain control
F
• CMOS level output
• Hysteresis input with standby control
G
• CMOS level output
• Hysteresis input with standby control
• Analog input
Standby control signal
• Open-drain
control signal
Standby control signal
Analog input
Standby control signal
MB90580B Series
18
(Continued)
Type Circuit Remarks
H
• CMOS level output
• Hysteresis input with standby control
• DA output
I
• CMOS level output
J
• CMOS input with standby control
DA output
Standby control signal
Standby control signal
MB90580B Series
19
■HANDLING DEVICES
1. Preventing Latchup
CMOS ICs may cause latchup in the following situations:
• When a voltage higher than Vcc or lower than Vss is applied to input or output pins.
• When a voltage exceeding the rating is applied between Vcc and Vss.
• When AVcc power is supplied prior to the Vcc voltage.
If latchup occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the
device. Use meticulous care not to let it occur.
F or the same reason, also be careful not to let the analog power-supply v oltage e xceed the digital pow er-supply
voltage.
2. Handling unused input pins
Unused input pins left open ma y cause abnormal operation, or latch-up leading to permanent damage. Unused
input pins should be pulled up or pulled down through at least 2 kΩ resistance.
Unused input/output pins may be left open in output state, but if such pins are in input state they should be
handled in the same way as input pins.
3. Treatment of the TX and RX pins with the IEBusTM unused
When the IEBus is not used, connect a pull-down resistor to the TX pin and a pull-down/pull-up resistor to the
RX pin.
4. Use of the subclock mode and external clock
Even when the subclock mode is not used, connect an oscillator to the X0A or X1A pin.
When the de vice uses an e xternal clock, driv e only the X0 pin while leaving the X1 pin open (See the illustration
below).
5. Power Supply Pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of a same potential are intern ally connected in the device to
avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to
low er the electro-magnetic emission level to prev ent abnormal operation of strobe signals caused by the rise in
the ground level, and to conform to the total current rating.
Make sure to connect VCC and VSS pins via lowest impedance to power lines.
X0
X1
MB90580B series
Open
MB90580B Series
20
It is recommended to provide a bypass capacitor of around 0.1 µF between VCC and VSS pin near the device.
6. Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines , and
make sure, to the utmost effort , that lines of oscillation circuit not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand
area for stabilizing the operation.
7. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D conver ter power supply (AVCC, AVSS, AVRH, AVRL) and analog inputs (AN0 to
AN7) after turning-on the digital power supply (VCC).
Turn-off the digital power after tur ning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage of AVRH dose not exceed AV CC (turning on/off the analog and digital power supplies simulta-
neously is acceptable).
8. Connection of Unused Pins of A/D Converter
Connect unused pin of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS.
9. Connection of Unused Pins of D/A Converter
Connect unused pin of D/A converter to DVRH = VSS, DVSS = VSS.
10. N.C. Pin
The N.C. (internally connected) pin must be opened for use.
11. Notes on Energization
To prevent the inter nal regulator circuit from malfunctioning,set the voltage rise time dur ing energization at 50
or more µs.
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS MB90580B
Series
MB90580B Series
21
12. Indeterminate outputs from ports 0 and 1
The outputs from por ts 0 and 1 become indeterminate dur ing a power-on reset after the power is turned on.
Pay attention to the port output timing shown as follow.
13. Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers
turning on the power again.
14. Return from standby state
If the powe r-supply voltage goes below the standby RAM holding voltage in the standby state, the device may
fail to return from the standby state. In this case, reset the device via the exter nal reset pin to return to the
normal state.
15. Precautions for Use of ’DIV A, Ri,’ and ’DIVW A, RWi’ Instructions
The signed multiplication-division instructions ’DIV A, Ri,’ and ’DIVW A, RWi’ should be used when the corre-
sponding bank registers (DTB, ADB , USB, SSB) are set to v alue ’00h.’ If the corresponding bank registers (DTB ,
ADB, USB, SSB) are set to a value other than ’00h,’ then the remainder obtained after the execution of the
instruction will not be placed in the instruction operand register.
VCC (Power-supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
KA (internal operation clock A) signal
KB (internal operation clock B) signal
PORT (port output) signal Period of indeterminate
Power-on reset*1
Oscillation settling time*2
*1: Power-on reset time: Period of “clock frequency x 217” (Clock frequency of 16 MHz: 8.192 ms)
*2: Oscillation settling time: Period of “clock frequency x 218” (Clock frequency of 16 MHz: 16.384 ms)
MB90580B Series
22
■BLOCK DIAGRAM
X0, X1
X0A, X1A
RST
HST
6
8
3
3
8
8
3
P00 to P07/
AD00 to AD07
P10 to P17/
AD08 to AD15
P20 to P27/
A16 to A23
P30/ALE
P31/RD
P32/WRL
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
P47
SIN0, SOT0, SCK0/
P40 to P42 3
8
8
SIN1, SOT1, SCK1/
P43 to P45
P90 to P92/
TIN0 to TIN2/
IN0 to IN2
2P94, P95/
TOT1, TOT2/
OUT0, OUT1
22 P63, P64/
PPG1, PPG0
3SIN2, SOT2,
SCK2/
P60 to P62
8P80 to P87/
IRQ0 to IRQ7
2P71, P72
2P73, P74
/DA00, DA01
P93/
TOT0/
IN3
PA0 to PA2
P96/PWC
P97/POT
P65/CKOT
DVRH
DVSS
ADTG, P46
AVCC
AVRH, AVRL
AVSS
SIN3, SOT3, SCK3/
P50 to P52/
AN0 to AN2
P53/AN3, P57/AN7
SIN4, SOT4, SCK4/
P54 to P56/
AN4 to AN6
TX
RX
ROM
UART
× 2 ch UART × 1 ch
8 + 8 PPG × 1 ch
UART
× 2 ch
RAM
*
Other pins
MOD2 to MOD0
C,VCC,VSS
Clock control
circuit
CMOS I/O port 0
CMOS I/O port 1
CMOS I/O port 2
CMOS I/O port 3
Prescaler
× 2 ch
A/Dconverter
(8/10 bit)
Interrupt controller
CMOS I/O port A
CMOS I/O port 9
CMOS I/O port 8
CMOS I/O port 7
External interrupt
D/A converter
(8 bit) × 2 ch
Evaluation device (MB90V580B)
This chip has no internal ROM.
Internal RAM is 6K bytes.
Internal resources are common.
The package is PGA-256C-A02.
IEBusTM controller
Prescaler × 2 ch
CMOS I/O port 6
CMOS I/O port 5
F2MC-16LX bus
I/O timer
16 bit ICU × 4 ch
16 bit OCU × 2 ch
16 bit free run timer
16 bit reload
timer × 3 ch
Noise fillter
PWCt imer
16 bit × 1 ch
Prescaler × 1 ch
P00 to 07 (8 channels): Provided with a register available as an input pull-up resistor.
P10 to 17(8 channels): Provided with a register available as an input pull-up resistor.
P60 to 65(6 channels): Provided with a register available as an input pull-up resistor.
P40 to 47 (8 channels): Provided with a register available as an open drain.
*: The MB90587 has no IEBusTM controller. The TX and RX pins are N.C. pins.
Clock monitor
CPU Core of
F2MC-16LX family
CMOS I/O port 4
MB90580B Series
23
■MEMORY MAP
Note: The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C
compiler small model. The low er 16-bit is assigned to the same address, enab ling ref erence of the tab le on
the ROM without stating “far”. For example, if an attempt has been made to access 00C000H, the contents
of the ROM at FFC000 H are accessed actually. Since the ROM area of the FF bank e xceeds 48 Kbytes , the
whole area cannot be reflected in the image f or the 00 bank. The R OM data at FF4000H to FFFFFFH looks,
theref ore, as if it w ere the image f or 00400H to 00FFFFH. Thus, it is recommended that the R OM data tab le
be stored in the area of FF4000H to FFFFFFH.
RAM RAM RAM
FFFFFFH
FC0000H
010000H
004000H
002000H
000100H
0000C0H
000000H
ROM area ROM area
ROM area
(image of bank
FF)
ROM area
(image of bank
FF)
Register
Peripheral Peripheral Peripheral
Single chip mode
A mirror function
is supported
Internal ROM
external bus mode
A mirror function is
supported
External ROM
external bus
mode
: Internal
: External
: Inhibited
Parts No. Address#1 Address#2 Address#3
MB90583B FE0000H004000H001900H
MB90F583B FE0000H004000H001900H
MB90587 FF0000H004000H001100H
MB90V580B (FE0000H) 004000H001900H
Address#1
Address#2
Address#3 Register Register
MB90580B Series
24
■F2MC-16LX CPU PROGRAMMING MODEL
• Dedicated registers
AH AL
USP
SSP
PS
PC
DPR
PCB
DTB
USB
SSB
ADB
8 bit
16 bit
32 bit
: Accumlator (A)
Dual 16-bit register used for storing results of calculation
etc. The two 16-bit registers can be combined to be used
as a 32-bit register.
: User stack pointer (USP)
The 16-bit pointer indicating a user stack address.
: System stack pointer (SSP)
The 16-bit pointer indicating the status of the system stack
address.
: Processor status (PS)
The 16-bit register indicating the system status.
: Program counter (PC)
The 16-bit register indicating storing location of the current
instruction code.
: Direct page register (DPR)
The 8-bit register indicating bit 8 through 15 of the operand
address in the short direct addressing mode.
: Program bank register (PCB)
The 8-bit register indicating the program space.
: Data bank register (DTB)
The 8-bit register indicating the data space.
: User stack bank register (USB)
The 8-bit register indicating the user stack space.
: System stack bank register (SSB)
The 8-bit register indicating the system stack space.
: Additional data bank register (ADB)
The 8-bit register indicating the additional data space.
MB90580B Series
25
• General-purpose registers
• Processor status (PS)
R7 R6
R5 R4
R3 R2
R1
RW3
RW2
RW1
RW0
16 bit
R0
RW7
RW6
RW5
RW4
RL3
RL2
RL1
RL0
000180H + (RP × 10H)
Maximum of 32 banks
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4
ILM RP CCR
bit 3 bit 2 bit 1 bit 0
ILM2PS ILM1 ILM0 B4 B3 B2 B1 B0 ISTNZVC
0000000001XXXXX
Initial value
X : Unused
: Undefined
MB90580B Series
26
■I/O MAP
(Continued)
Address Register name Abbreviated
register
name Read/write Resource name Initial value
00HPort 0 data register PDR0 R/W Port 0 XXXXXXXXB
01HPort 1 data register PDR1 R/W Port 1 XXXXXXXXB
02HPort 2 data register PDR2 R/W Port 2 XXXXXXXXB
03HPort 3 data register PDR3 R/W Port 3 XXXXXXXXB
04HPort 4 data register PDR4 R/W Port 4 XXXXXXXXB
05HPort 5 data register PDR5 R/W Port 5 1 1 1 1 1 1 1 1B
06HPort 6 data register PDR6 R/W Port 6 XXXXXXXXB
07HPort 7 data register PDR7 R/W Port 7 − − − XXXX −B
08HPort 8 data register PDR8 R/W Port 8 XXXXXXXXB
09HPort 9 data register PDR9 R/W Port 9 XXXXXXXXB
0AHPort A data register PDRA R/W Port A − − − − − XXXB
0BH to 0FH(Disabled)
10HPort 0 direction register DDR0 R/W Port 0 0 0 0 0 0 0 0 0B
11HPort 1 direction register DDR1 R/W Port 1 0 0 0 0 0 0 0 0B
12HPort 2 direction register DDR2 R/W Port 2 0 0 0 0 0 0 0 0B
13HPort 3 direction register DDR3 R/W Port 3 0 0 0 0 0 0 0 0B
14HPort 4 direction register DDR4 R/W Port 4 0 0 0 0 0 0 0 0B
15HPort 5 direction register DDR5 R/W Port 5 0 0 0 0 0 0 0 0B
16HPort 6 direction register DDR6 R/W Port 6 0 0 0 0 0 0 0 0B
17HPort 7 direction register DDR7 R/W Port 7 − − − 0 0 0 0 − B
18HPort 8 direction register DDR8 R/W Port 8 0 0 0 0 0 0 0 0B
19HPort 9 direction register DDR9 R/W Port 9 0 0 0 0 0 0 0 0B
1AHPort A direction register DDRA R/W Port A − − − − − 0 0 0B
1BHPort 4 output pin register ODR4 R/W Port 4 0 0 0 0 0 0 0 0B
1CHPort 5 analog input enable
register ADER R/W Port 4, A/D 1 1 1 1 1 1 1 1B
1DH to 1FH(Disabled)
20HSerial mode register 0 SMR0 R/W
UART0
0 0 0 0 0 0 0 0B
21HSerial control register 0 SCR0 R/W 0 0 0 0 0 1 0 0B
22HSerial input data register 0/
serial output data register 0 SIDR0/
SODR0 R/W XXXXXXXXB
23HSerial status register 0 SSR0 R/W 0 0 0 0 1 − 0 0B
MB90580B Series
27
(Continued)
Address Register name Abbreviated
register
name Read/
write Resource name Initial value
24HSerial mode register 1 SMR1 R/W
UART1
0 0 0 0 0 0 0 0B
25HSerial control register 1 SCR1 R/W 0 0 0 0 0 1 0 0B
26HSerial input data register 1/
serial output data register 1 SIDR1/
SODR1 R/W XXXXXXXXB
27HSerial status register 1 SSR1 R/W 0 0 0 0 1 − 0 0B
28HSerial mode register 2 SMR2 R/W
UART2
0 0 0 0 0 0 0 0B
29HSerial control register 2 SCR2 R/W 0 0 0 0 0 1 0 0B
2AHSerial input data register 2/
serial output data register 2 SIDR2/
SODR2 R/W XXXXXXXXB
2BHSerial status register 2 SSR2 R/W 0 0 0 0 1 − 0 0B
2CHClock division control register 0 CDCR0 R/W Communications
prescaler 0 0 − − − 1 1 1 1B
2DH(Disabled)
2EHClock division control register 1 CDCR1 R/W Communications
prescaler 1 0 − − − 1 1 1 1B
2FH(Disabled)
30HDTP/interrupt enable register ENIR R/W
DTP/external
interrupt
0 0 0 0 0 0 0 0B
31HDTP/interrupt factor register EIRR R/W XXXXXXXXB
32HRequest level setting register
lower ELVR R/W 0 0 0 0 0 0 0 0B
33HRequest level setting register
upper 0 0 0 0 0 0 0 0B
34HClock division control register 2 CDCR2 R/W Communications
prescaler 2 0 − − − 1 1 1 1B
35H(Disabled)
36HControl status register lower ADCS1 R/W
A/D converter
0 0 0 0 0 0 0 0B
37HControl status register upper ADCS2 R/W 0 0 0 0 0 0 0 0B
38HData register lower ADCR1 R XXXXXXXXB
39HData register upper ADCR2 R/W 0 0 0 0 1 − XXB
3AHD/A converter data register 0 DAT0 R/W
D/A converter
0 0 0 0 0 0 0 0B
3BHD/A converter data register 1 DAT1 R/W 0 0 0 0 0 0 0 0B
3CHD/A control register 0 DACR0 R/W − − − − − − − 0B
3DHD/A control register 1 DACR1 R/W − − − − − − − 0B
3EHClock output enable register CLKR R/W Clock monitor
function − − − − 0 0 0 0B
3FH(Disabled)
MB90580B Series
28
(Continued)
Address Register name Abbreviated
register
name Read/
write Resource name Initial value
40HReload register L (ch.0) PRLL0 R/W
8/16 bit
PPG0/1
XXXXXXXXB
41HReload register H (ch.0) PRLH0 R/W XXXXXXXXB
42HReload register L (ch.1) PRLL1 R/W XXXXXXXXB
43HReload register H (ch.1) PRLH1 R/W XXXXXXXXB
44HPPG0 operating mode control
register PPGC0 R/W 0 X 0 0 0 X X 1B
45HPPG1 operating mode control
register PPGC1 R/W 0 X 0 0 0 0 0 1B
46HPPG0 and 1 operating output control
registers PPGOE R/W 0 0 0 0 0 0 0 0B
47H(Disabled)
48HTimer control status register lower TMCSR0 R/W
16 bit
reload timer 0
0 0 0 0 0 0 0 0B
49HTimer control status register upper − − − − 0 0 0 0B
4AH16 bit timer register lower/
16 bit reload register lower TMR0/
TMRLR0 R/W XXXXXXXXB
4BH16 bit timer register upper/
16 bit reload register upper XXXXXXXXB
4CHTimer control status register lower TMCSR1 R/W
16 bit
reload timer 1
0 0 0 0 0 0 0 0B
4DHTimer control status register upper − − − − 0 0 0 0B
4EH16bit timer register lower/
16 bit reload register lower TMR1/
TMRLR1 R/W XXXXXXXXB
4FH16 bit timer register upper/
16 bit reload register upper XXXXXXXXB
50HTimer control status register lower TMCSR2 R/W
16 bit
reload timer 2
0 0 0 0 0 0 0 0B
51HTimer control status register upper − − − − 0 0 0 0B
52H16 bit timer register lower/
16 bit reload register lower TMR2/
TMRLR2 R/W XXXXXXXXB
53H16 bit timer register upper/
16 bit reload register upper XXXXXXXXB
54HPWC control status register lower PWCSR R/W
16 bit
PWC timer
0 0 0 0 0 0 0 0B
55HPWC control status register upper 0 0 0 0 0 0 0 0B
56HPWC data buffer register lower PWCR R/W XXXXXXXXB
57HPWC data buffer register upper XXXXXXXXB
58HDivide ratio control register DIVR R/W − − − − − − 0 0B
59H(Disabled)
MB90580B Series
29
(Continued)
Address Register name Abbreviated
register
name Read/write Resource name Initial value
5AHCompare register lower OCCP0 R/W Output compare
(ch.0) XXXXXXXXB
5BHCompare register upper XXXXXXXXB
5CHCompare register lower OCCP1 R/W Output compare
(ch.1) XXXXXXXXB
5DHCompare register upper XXXXXXXXB
5EHCompare control status register 0 OCS0 R/W Output compare
(ch.0) 0 0 0 0 − − 0 0B
5FHCompare control status register 1 OCS1 R/W Output compare
(ch.1) − − − 0 0 0 0 0B
60HInput capture register lower IPCP0 R Input capture
(ch.0) XXXXXXXXB
61HInput capture register upper XXXXXXXXB
62HInput capture register lower IPCP1 R Input capture
(ch.1) XXXXXXXXB
63HInput capture register upper XXXXXXXXB
64HInput capture register lower IPCP2 R Input capture
(ch.2) XXXXXXXXB
65HInput capture register upper XXXXXXXXB
66HInput capture register lower IPCP3 R Input capture
(ch.3) XXXXXXXXB
67HInput capture register upper XXXXXXXXB
68HInput capture control status
register 01 ICS01 R/W Input capture
(ch.0, ch.1) 0 0 0 0 0 0 0 0B
69H(Disabled)
6AHInput capture control status
register 23 ICS23 R/W Input capture
(ch.2, ch.3) 0 0 0 0 0 0 0 0B
6BH(Disabled)
6CHTimer data register lower TCDTL R/W
Free-run timer
0 0 0 0 0 0 0 0B
6DHTimer data register upper TCDTH R/W 0 0 0 0 0 0 0 0B
6EHTimer control status register TCCS R/W 0 0 0 0 0 0 0 0B
6FHROM mirroring function selection
register ROMM W ROM mirror function − − − − − − − 1B
70HLocal-office address setting
register L MAWL R/W
IEBusTM
controller
XXXXXXXXB
71HLocal-office address setting
register H MAWH R/W XXXXXXXXB
72HSlave address setting register L SAWL R/W XXXXXXXXB
73HSlave address setting register H SAWH R/W XXXXXXXXB
74HMessage length bit setting register DEWR R/W 0 0 0 0 0 0 0 0B
75HBroadcast control bit setting
register DCWR R/W 0 0 0 0 0 0 0 0B
MB90580B Series
30
(Continued)
Address Register name Abbreviated
register
name Read/write Resource name Initial value
76HCommand register L CMRL R/W
IEBusTM
controller
1 1 0 0 0 0 0 0B
77HCommand register H CMRH R/W 0 0 0 0 0 0 0 XB
78HStatus register L STRL R 0 0 1 1 XXXXB
79HStatus register H STRH R/W 0 0 XX 0 0 0 0B
7AHLock read register L LRRL R XXXXXXXXB
7BHLock read register H LRRH R/W 1 1 1 0 XXXXB
7CHMaster address read register L MARL R XXXXXXXXB
7DHMaster address read register H MARH R 1 1 1 1 XXXXB
7EHMessage length bit read register DERR R XXXXXXXXB
7FHBroadcast control bit read register DCRR R 0 0 0 XXXXXB
80HWrite data buffer WDB W XXXXXXXXB
81HRead data buffer RDB R XXXXXXXXB
82HSerial mode register 3 SMR3 R/W
UART3
0 0 0 0 0 0 0 0B
83HSerial control register 3 SCR3 R/W 0 0 0 0 0 1 0 0B
84HSerial input register 3/
serial output register 3 SIDR3/
SODR3 R/W XXXXXXXXB
85HSerial status register 3 SSR3 R/W 0 0 0 0 1 − 0 0B
86HPWC noise filter register RNCR R/W PWC noisefilter − − − − − 0 0 0B
87HClock division control register 3 CDCR3 R/W Communications
prescaler 3 0 − − − 1 1 1 1B
88HSerial mode register 4 SMR4 R/W
UART4
0 0 0 0 0 0 0 0B
89HSerial control register 4 SCR4 R/W 0 0 0 0 0 1 0 0B
8AHSerial input register 4/
serial output register 4 SIDR4/
SODR4 R/W XXXXXXXXB
8BHSerial status register 4 SSR4 R/W 0 0 0 0 1 − 0 0B
8CHPort 0 input pull-up resistor setup
register RDR0 R/W Port 0 0 0 0 0 0 0 0 0B
8DHPort 1 input pull-up resistor setup
register RDR1 R/W Port 1 0 0 0 0 0 0 0 0B
8EHPort 6 input pull-up resistor setup
register RDR6 R/W Port 2 0 0 0 0 0 0 0 0B
8FHClock division control register 4 CDCR4 R/W Communications
prescaler 4 0 − − − 1 1 1 1B
90H to
9DH(Disabled)
MB90580B Series
31
(Continued)
Address Register name Abbreviated
register
name Read/
write Resource name Initial value
9EHProgram address detection control/
status register PACSR R/W Address match
detection
function 0 0 0 0 0 0 0 0B
9FHDelayed interrupt generation/release
register DIRR R/W Delayed interrupt
generation module − − − − − − − 0B
A0HLow-power consumption mode
control register LPMCR R/W Low-power
consumption mode 0 0 0 1 1 0 0 −B
A1HClock selection register CKSCR R/W 1 1 1 1 1 1 0 0B
A2H to
A4H(Disabled)
A5HA uto-ready function selection register ARSR W
External bus pin
control circuit
0 0 1 1 − − 0 0B
A6HExternal address output control
register HACR W 0 0 0 0 0 0 0 0B
A7HBus control signal selection register ECSR W 0 0 0 0 0 0 0 −B
A8HWatch dog timer control register WDTC R/W Watch dog timer XXXXX 1 1 1B
A9HTime-base timer control register TBTC R/W Timebase timer 1 − − 0 0 1 0 0B
AAHClock timer control register WTC R/W Clock timer 1 X 0 0 0 0 0 0B
ABH to
ADH(Disabled)
AEHFlash memory control status register FMCS R/W Flash interface 0 0 0 X 0 0 0 0B
AFH(Disabled)
B0HInterrupt control register 00 ICR00 R/W
Interrupt controller
0 0 0 0 0 1 1 1B
B1HInterrupt control register 01 ICR01 R/W 0 0 0 0 0 1 1 1B
B2HInterrupt control register 02 ICR02 R/W 0 0 0 0 0 1 1 1B
B3HInterrupt control register 03 ICR03 R/W 0 0 0 0 0 1 1 1B
B4HInterrupt control register 04 ICR04 R/W 0 0 0 0 0 1 1 1B
B5HInterrupt control register 05 ICR05 R/W 0 0 0 0 0 1 1 1B
B6HInterrupt control register 06 ICR06 R/W 0 0 0 0 0 1 1 1B
B7HInterrupt control register 07 ICR07 R/W 0 0 0 0 0 1 1 1B
B8HInterrupt control register 08 ICR08 R/W 0 0 0 0 0 1 1 1B
B9HInterrupt control register 09 ICR09 R/W 0 0 0 0 0 1 1 1B
BAHInterrupt control register 10 ICR10 R/W 0 0 0 0 0 1 1 1B
BBHInterrupt control register 11 ICR11 R/W 0 0 0 0 0 1 1 1B
BCHInterrupt control register 12 ICR12 R/W 0 0 0 0 0 1 1 1B
BDHInterrupt control register 13 ICR13 R/W 0 0 0 0 0 1 1 1B
BEHInterrupt control register 14 ICR14 R/W 0 0 0 0 0 1 1 1B
BFHInterrupt control register 15 ICR15 R/W 0 0 0 0 0 1 1 1B
MB90580B Series
32
(Continued)
• Explanation of initial values→“0” : initial value“0” / “1” : initial value“1” / “X” : undefined / “−” : undefined (not used)
• The addresses following 00FFH are reserved. No external bus access signal is generated.
• Boundary #H between the RAM area and the reserved area varies with the product model.
Note: For bits that is initialized by an reset operation, the initial v alue set by the reset operation is listed as an initial
v alue . Note that the values are diff erent from reading results . For LPMCR/CKSCR/WDTC , there are cases
where initialization is perf ormed or not performed, depending on the types of the reset. Howe ver initial v alue
for resets that initializes the value are listed.
Address R egister name Abbreviated
register
name Read/write Resource name Initial value
C0H to
FFH(External area)
100H to
#H (RAM area)
#H to
1FEFH(Reserved area)
1FF0HProgram address detection register 0
(lower)
PADR0
R/W
Address match
detection
function
XXXXXXXXB
1FF1HProgram address detection register 1
(middle) R/W XXXXXXXXB
1FF2HProgram address detection register 2
(upper) R/W XXXXXXXXB
1FF3HProgram address detection register 3
(lower)
PADR1
R/W XXXXXXXXB
1FF4HProgram address detection register 4
(middle) R/W XXXXXXXXB
1FF5HProgram address detection register 5
(upper) R/W XXXXXXXXB
1FF6H to
1FFFH(Reserved area)
MB90580B Series
33
■INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
: Indicates that the interrupt request flag is cleared by the EI2OS interrupt clear signal (stop request present).
: Indicates that the interrupt request flag is cleared by the EI2OS interrupt clear signal.
× : Indicates that the interrupt request flag is not cleared by the EI2OS interrupt clear signal.
Interrupt source EI2OS
support Interrupt vector Interrupt control
register Priority
No. Address ICR Address
Reset ×#08 FFFFDCHHigh
INT9 instruction ×#09 FFFFD8H
Exception ×#10 FFFFD4H
A/D converter #11 FFFFD0HICR00 0000B0H
Timebase timer ×#12 FFFFCCH
DTP0 (external interrupt #0) /UART3 reception
complete #13 FFFFC8HICR01 0000B1H
DTP1 (external interrupt #1) /UART4 reception
complete #14 FFFFC4H
DTP2 (external interrupt #2) /UART3 transmission
complete #15 FFFFC0HICR02 0000B2H
DTP3 (external interrupt #3) /UART4 transmission
complete #16 FFFFBCH
DTP4 to 7 (external interrupt #4 to #7) #17 FFFFB8HICR03 0000B3H
Output compare (ch.1) match (I/O timer) #18 FFFFB4H
UART2 reception complete #19 FFFFB0HICR04 0000B4H
UART1 reception complete #20 FFFFACH
Input capture (ch.3) include (I/O timer) #21 FFFFA8HICR05 0000B5H
Input capture (ch.2) include (I/O timer) #22 FFFFA4H
Input capture (ch.1) include (I/O timer) #23 FFFFA0HICR06 0000B6H
Input capture (ch.0) include (I/O timer) #24 FFFF9CH
8/16 bit PPG0 counter borrow ×#25 FFFF98HICR07 0000B7H
16 bit reload timer 2 to 0 #26 FFFF94H
Clock prescaler ×#27 FFFF90HICR08 0000B8H
Output compare (ch.0) match (I/O timer) #28 FFFF8CH
UART2 transmission complete #29 FFFF88HICR09 0000B9H
PWC timer measurement complete / over flow #30 FFFF84H
UART1 transmission complete #31 FFFF80HICR10 0000BAH
16-bit free run timer (I/O timer) over flow #32 FFFF7CH
UART0 transmission complete #33 FFFF78HICR11 0000BBH
8/16 bit PPG1 counter borrow ×#34 FFFF74H
IEBus reception complete #35 FFFF70HICR12 0000BCH
IEBus transmission start #37 FFFF68HICR13 0000BDH
UART0 reception complete #39 FFFF60HICR14 0000BEH
Flash memory status ×#41 FFFF58HICR15 0000BFH
Delayed interrupt ×#42 FFFF54HLow
MB90580B Series
34
■PERIPHERAL RESOURCES
1. I/O Ports
(1) Outline of I/O ports
When a data register serving for control output is read, the data output from it as a control output is read regardless
of the value in the direction register. Note that, if a read modify wr ite instr uction (such as a bit set instr uction)
is used to preset output data in the data register when changing its setting from input to output, the data read
is not the data register latched value but the input data from the pin.
Ports 0 to 4 and 6 to A are input/output ports which ser ve as inputs when the direction register value is “0” or
as outputs when the value is “1”.
On the MB90580B series, ports 0 to 3 also serve as e xternal bus pins. When the de vice is used in e xternal bus
mode, therefore, these ports are restricted on use.
Ports 2 and 3 can be used as ports even in exter nal bus mode depending on the setting of the corresponding
function select bit.
(2) Register configuration
(Continued)
• Port 0 data register (PDR0) bit
Address : 000000HAccess
Initial value
• Port 1 data register (PDR1) bit
Address : 000001HAccess
Initial value
• Port 2 data register (PDR2) bit
Address : 000002HAccess
Initial value
• Port 3 data register (PDR3) bit
Address : 000003HAccess
Initial value
• Port 4 data register (PDR4) bit
Address : 000004HAccess
Initial value
(PDR1) P07 P06 P05 P04 P03 P02 P01 P00
76543210
(R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X)
15 8
…………
(PDR0)P17 P16 P15 P14 P13 P12 P11 P10
15 14 13 12 11 10 9 8
(R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X)
70
…………
(PDR3) P27 P26 P25 P24 P23 P22 P21 P20
76543210
(R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X)
15 8
…………
(PDR2)P37 P36 P35 P34 P33 P32 P31 P30
15 14 13 12 11 10 9 8
(R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X)
70
…………
(PDR5) P47 P46 P45 P44 P43 P42 P41 P40
76543210
(R/W)
(X) (RW)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X)
15 8
…………
MB90580B Series
35
(Continued)
(Continued)
• Port 5 data register (PDR5) bit
Address : 000005HAccess
Initial value
• Port 6 data register (PDR6) bit
Address : 000006HAccess
Initial value
• Port 7 data register (PDR7) bit
Address : 000007HAccess
Initial value
• Port 8 data register (PDR8) bit
Address : 000008HAccess
Initial value
• Port 9 data register (PDR9) bit
Address : 000009HAccess
Initial value
• Port A data register (PDRA) bit
Address : 00000AHAccess
Initial value
• Port 0 direction register (DDR0)
bit
Address : 000010HAccess
Initial value
(PDR4)P57 P56 P55 P54 P53 P52 P51 P50
15 14 13 12 11 10 9 8
(R/8)
(1) (R/W)
(1) (R/W)
(1) (R/W)
(1) (R/W)
(1) (R/W)
(1) (R/W)
(1) (R/W)
(1)
70
…………
(PDR7) P67 P66 P65 P64 P63 P62 P61 P60
76543210
(R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X)
15 8
…………
(PDR6)P74 P73 P72 P71
15 14 13 12 11 10 9 8
()
() ()
() ()
() (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) ()
()
70
…………
(PDR9) P87 P86 P85 P84 P83 P82 P81 P80
76543210
(R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X)
15 8
…………
(PDR8)P97 P96 P95 P94 P93 P92 P91 P90
15 14 13 12 11 10 9 8
(R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X) (R/W)
(X)
70
…………
PA2 PA1 PA0
76543210
()
() ()
() ()
() ()
() ()
() (R/W)
(X) (R/W)
(X) (R/W)
(X)
15 8
…………
(Disab led)
(DDR1) D07 D06 D05 D04 D03 D02 D01 D00
76543210
(R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0)
15 8
…………
MB90580B Series
36
(Continued)
(Continued)
• Port 1 direction register (DDR1)
bit
Address : 000011HAccess
Initial value
• Port 2 direction register (DDR2)
bit
Address : 000012HAccess
Initial value
• Port 3 direction register (DDR3)
bit
Address : 000013HAccess
Initial value
• Port 4 direction register (DDR4)
bit
Address : 000014HAccess
Initial value
• Port 5 direction register (DDR5)
bit
Address : 000015HAccess
Initial value
• Port 6 direction register (DDR6)
bit
Address : 000016HAccess
Initial value
• Port 7 direction register (DDR7)
bit
Address : 000017HAccess
Initial value
(DDR0)D17 D16 D15 D14 D13 D12 D11 D10
15 14 13 12 11 10 9 8
(R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0)
70
…………
(DDR3) D27 D26 D25 D24 D23 D22 D21 D20
76543210
(R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0)
15 8
…………
(DDR2)D37 P36 P35 P34 P33 P32 P31 P30
15 14 13 12 11 10 9 8
(R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0)
70
…………
(DDR5) D47 D46 D45 D44 D43 D42 D41 D40
76543210
(R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0)
15 8
…………
(DDR4)D57 D56 D55 D54 D53 D52 D51 D50
15 14 13 12 11 10 9 8
(R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0)
70
…………
(DDR7) D67 D66 D65 D64 D63 D62 D61 D60
76543210
(R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0)
15 8
…………
(DDR6)D74 D73 D72 D71
15 14 13 12 11 10 9 8
()
() ()
() ()
() (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) ()
()
70
…………
MB90580B Series
37
• Port 8 direction register (DDR8)
bit
Address : 000018HAccess
Initial value
• Port 9 direction register (DDR9)
bit
Address : 000019HAccess
Initial value
• Port A direction register (DDRA)
bit
Address : 00001AHAccess
Initial value
• Port 4 output pin register (ODR4)
bit
Address : 00001BHAccess
Initial value
• Port 5 analog input enable register (ADER)
bit
Address : 00001CHAccess
Initial value
• Port 0 input pull-up resistor setup register (RDR0)
bit
Address : 00008CHAccess
Initial value
• Port 1 input pull-up resistor setup register (RDR1)
bit
Address : 00008DHAccess
Initial value
• Port 6 input pull-up resistor setup register (RDR6)
bit
Address : 00008EHAccess
Initial value
(DDR9) D87 D86 D85 D84 D83 D82 D81 D80
76543210
(R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0)
15 8
…………
(RDR1) RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00
76543210
(R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0)
15 8
…………
(DDR8)D97 D96 D95 D94 D93 D92 D91 D90
15 14 13 12 11 10 9 8
(R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0)
70
…………
(ODR4) DA2 DA1 DA0
76543210
()
() ()
() ()
() ()
() ()
() (R/W)
(0) (R/W)
(0) (R/W)
(0)
15 8
…………
(DDRA)OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40
15 14 13 12 11 10 9 8
(R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0)
70
…………
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
76543210
(R/W)
(1) (R/W)
(1) (R/W)
(1) (R/W)
(1) (R/W)
(1) (R/W)
(1) (R/W)
(1) (R/W)
(1)
15 8
…………
(RDR1) RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00
76543210
(R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0)
15 8
…………
(RDR0)RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD10
15 14 13 12 11 10 9 8
(R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0)
70
…………
(CDCR4) RD67 RD66 RD65 RD64 RD63 RD62 RD61 RD60
76543210
(R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0) (R/W)
(0)
15 8
…………
MB90580B Series
38
(3) Block Diagram
• Input/output port
• Input pull-up resistor setup register
Data register read
Data register write
Direction register write
Direction register read
Data register
Direction register
Pin
Data register
Direction register
Input pull-up resistor
setup register
Pull-up resistor (About 50 kΩ)
Port I/O
Internal data bus
Bus
MB90580B Series
39
• Output pin register
Data register
Direction register
Pin register
Port I/O
Bus
MB90580B Series
40
2. Timebase Timer
The time-base timer consists of a 18-bit timer and an inter val interrupt control circuit. Note that the time-base
timer uses the oscillation clock regardless of the setting of the MCS bit in the CKSCR.
(1) Register configuration
(2) Block Diagram
• Timebase timer control register
bit15 1413121110 9 8
Address : 0000A9HReserved TBIE TBOF TBR TBC1 TBC0 TBTC
Access () () () (R/W) (R/W) (W) (R/W) (R/W)
Initial value (1) () () (0) (0) (1) (0) (0)
TBTC
PONR
STBR
WRST
ERST
SRST
TBC0
TBR
TBIE
TBOF
TBC1
WT1
WT0
WTE
WTC
WDCS
SCE
WTC2
WTC0
WTR
WTIE
WTOF
WDTC
WDTC
AND
CLR OF CLR
212
214
216
219
TBTRES
210
213
214
215
WTRES
211 213 215 218
210 213 214 215
QR
S
AND QR
S
AND
QR
S
WT2
WTC1
Time-base
interrupt
Clock
interrupt
Selector
Selector
Selector
Main clock
Clock input
Time-base timer
Watchdog reset
generator
2-bit
counter
Clock timer
Clock input
To WDGRST
internal reset
generator
From power-on reset
generator
Subclock
From RST bit in STBYC
register
From RST pin
F2MC-16LX bus
From hardware standby
control circuit
MB90580B Series
41
3. Watchdog Timer
The watchdog timer consists of a 2-bit w atchdog counter using carry signals from the 18-bit time-base timer as
the clock source, a control register, and a watchdog reset control section.
(1) Register configuration
(2) Block Diagram
• Watchdog timer control registerbit 76543210
Address : 0000A8HPONR STBR WRST ERST SRST WTE WT1 WT0 WDTC
Access (R) (R) (R) (R) (R) (W) (W) (W)
Initial value (X) (X) (X) (X) (X) (1) (1) (1)
TBTC
PONR
STBR
WRST
ERST
SRST
TBC0
TBR
TBIE
TBOF
TBC1
WT1
WT0
WTE
WTC
WDCS
SCE
WTC2
WTC0
WTR
WTIE
WTOF
WDTC
WDTC
AND
CLR OF CLR
212
214
216
219
TBTRES
210
213
214
215
WTRES
211 213 215 218
210 213 214 215
QR
S
AND QR
S
AND
QR
S
WT2
WTC1
Time-base
interrupt
Clock
interrupt
Selector
Selector
Selector
Main clock
Clock input
Time-base timer
Watchdog reset
generator
2-bit
counter
Clock timer
Clock input
To WDGRST
internal reset
generator
From power-on reset
generator
Subclock
From RST bit in STBYC
register
From RST pin
F2MC-16LX bus
From hardware
standby control circuit
MB90580B Series
42
4. Clock timer
The clock timer has the functions of a watchdog timer clock source, a subclock oscillation settling time wait timer ,
and of a periodically interrupt generating interval timer.
(1) Register configuration
(2) Block Diagram
• Clock timer control register bit 76543210.
Address : 0000AAHWDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 WTC
Access (R/W) (R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (1) (X) (0) (0) (0) (0) (0) (0)
TBTC
PONR
STBR
WRST
ERST
SRST
TBC0
TBR
TBIE
TBOF
TBC1
WT1
WT0
WTE
WTC
WDCS
SCE
WTC2
WTC0
WTR
WTIE
WTOF
WDTC
WDTC
AND
CLR OF CLR
212
214
216
219
TBTRES
210
213
214
215
WTRES
211 213 215 218
210 213 214 215
QR
S
AND QR
S
AND
QR
S
WT2
WTC1
Time-base
interrupt
Clock
interrupt
Selector
Selector
Selector
Main clock
Clock input
Time-base timer
Watchdog reset
generator
2-bit
counter
Clock timer
Clock input
To WDGRST
internal reset
generator
From power-on reset
generator
Subclock
From RST bit in STBYC
register
From RST pin
F2MC-16LX bus
From hardware standby
control circuit
MB90580B Series
43
5. External Memory Access (External Bus Pin Control Circuit)
The exter nal bus pin control circuit controls external bus pins used to expand the address/data buses of the
CPU outside.
(1) Register configuration
(2) Block Diagram
• Automatic ready function selection register
bit
Address : 0000A5H
Access
Initial value
• External address output control register
bit
Address : 0000A6H
Access
Initial value
• Bus control signal selection register
bit
Address : 0000A7H
Access
Initial value
ARSRIOR1 IOR0 HMR1 HMR0 LMR1 LMR0
15 14 13 12 11 10 9 8
(W)
(0) (W)
(0) (W)
(1) (W)
(1) ()
() ()
() (W)
(0) (W)
(0)
HACRE23 E22 E21 E20 E19 E18 E17 E16
76543210
(W)
(0) (W)
(0) (W)
(0) (W)
(0) (W)
(0) (W)
(0) (W)
(0) (W)
(0)
ECSRCKE RYE HDE IOBS HMBS WRE LMBS
15 14 13 12 11 10 9 8
(W)
(0) (W)
(0) (W)
(0) (W)
(0) (W)
(0) (W)
(0) (W)
(0) ()
()
P0
RB
P0
P1 P2 P3
P3
P0 data
Access control
P0 direction
Data control
Address control
Access control
MB90580B Series
44
6. PWC Timer
The PWC (pulse width count) timer is a 16-bit multifunction up-counter with reload timer functions and input-
signal pulse-width count functions as well.
The PWC timer consists of a 16-bit counter, a input pulse divider, a divide ratio control register, a count input
pin, a pulse output pin, and a 16-bit control register.
(1) Features of the PWC timer
The PWC timer has the following features:
• Timer functions
Generates an interrupt request at set time intervals.
Outputs pulse signals synchronized with the timer cycle.
Selects the counter clock from among three internal clocks.
• Pulse-width count functions
Counts the time between external pulse input events.
Selects the counter clock from among three internal clocks.
Count mode
•H pulse width (rising edge to falling edge)/L pulse width (falling edge to rising edge)
•Rising-edge cycle (rising edge to falling edge)/Falling-edge cycle (falling edge to rising edge)
•Count between edges (rising or falling edge to falling or rising edge)
Capable of counting cycles by dividing input pulses by 22, 24, 26, 28 using an 8-bit input divider.
Generates an interrupt request upon the completion of count operation.
Selects single or consecutive count operation.
MB90580B Series
45
(2) Register configuration
• PWC control status register (Upper byte)
bit151413121110 9 8
Address : 000055HSTRT STOP EDIR EDIE OVIR OVIE ERR POUT PWCSR upper
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (0) (0) (0) (0) (0) (0) (0) (0)
• PWC control status register (Lower byte)
bit76543210
Address : 000054HCKS1 CKS0 ReservedReserved S/C MOD2 MOD1 MOD0 PWCSR lower
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (0) (0) (0) (0) (0) (0) (0) (0)
• PWC data buffer register (Upper byte)
bit151413121110 9 8
Address : 000057HPWCR upper
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (X) (X) (X) (X) (X) (X) (X) (X)
• PWC data buffer register (Lower byte)
bit76543210
Address : 000056HPWCR lower
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (X) (X) (X) (X) (X) (X) (X) (X)
• Divide ratio control register bit76543210
Address : 000058HDIV1 DIV0 DIVR
Access () () () () () () (R/W) (R/W)
Initial value () () () () () () (0) (0)
• PWC noise filter register bit76543210
Address : 000086HEN SW1 SW0 RNCR
Access () () () () () (R/W) (R/W) (R/W)
Initial value () () () () () (0) (0) (0)
MB90580B Series
46
(3) Block Diagram
ERR
PWCR
16
16 16
16
CKS1, CKS0
15
ERR CKS1
CKS0
PWCSR
DIVR
F.F. POT
2
22
23
PWC
PWCR read Error
detection
Write enable
Reload
Data
transfer
Overflow 16-bit up-count timer Clock
Internal clock
(Machine clock/4)
Clock
divider
Control circuit
Timer
clear Count
enable Divider clear
Flag set
Control bit output
Edge
detec-
tion
Divider ON/OFF
Count
start edge
Overflow interrupt
request
Divide
ratio selection
8-bit
divider
Overflow
F2MC-16LX bus
Count end interrupt request
Start edge
selection
Count end
edge
End edge
selection
MB90580B Series
47
7. 16-bit I/O timer
The 16-bit I/O timer module consists of one 16-bit free run timer, four input capture circuits, and two output
comparators. This module allows two independent wavefo rms to be output on the basis of the 16-bit free r un
timer. Input pulse width and external clock periods can, therefore, be measured.
(1) 16-bit free-run timer (1 channel)
The 16-bit free run timer consists of a 16-bit up-counter, a control register, and a prescaler. The value output
from this timer/counter is used as the base time for the input capture and output compare modules.
• Counter operation clock (Selectable from among the following four)
Four internal clock cycles: φ/4, φ/16, φ/64, φ/256
φ: Machine clock
• Interrupts
An interrupt can be generated when the 16-bit free-run timer causes a counter overflo w or b y compare/match
operation with compare register 0. (The compare/match operation requires the mode setting).
• Counter value
An interrupt can be generated when the 16-bit free-run timer causes a counter ov erflow or when a match with
compare register 0 occurs (The compare/match function can be used by the appropriate mode setting).
• Initialization
The counter value can be initialized to “0000H” at a reset, soft clear operation, or a match with compare register
0.
(2) Output compare module (2 channels)
The output compare module consists of two 16-bit compare registers, compare output latches, and control
registers. When the 16-bit free-run timer v alue matches the compare register value, this module generates an
interrupt while inverting the output level.
• Two compare registers can operate independently.
Output pin and interrupt flag for each compare register
• A pair of compare registers can be used to control the output pin.
Two compare registers can be used to invert the output pin polarity.
• The initial value for each output pin can be set.
• An interrupt can be generated by compare/match operation.
(3) Input capture module (4 channels)
The input capture module consists of capture registers and control registers respectively associated with four
independent e xternal input pins. This module can hold the 16-bit free run timer v alue in the capture register . In
addition, it can detect an arbitrary edge of the signal input from each external input pin to generate an interrupt.
• The external input signal edge to be detected can be selected.
One or both of the rising and falling edges can be selected.
• Four input capture channels can operate independently.
• An interrupt can be generated at a valid edge of the external input signal.
The extended intelligent I/O service can be activated by the interrupt by the input capture module.
MB90580B Series
48
(4) Register configuration
(Continued)
• Timer data register (upper) bit 151413121110 9 8
Address : 00006DHT15 T14 T13 T12 T11 T10 T09 T08 TCDTH
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (0) (0) (0) (0) (0) (0) (0) (0)
• Timer data register (lower) bit 76543210
Address : 00006CHT07 T06 T05 T04 T03 T02 T01 T00 TCDTL
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (0) (0) (0) (0) (0) (0) (0) (0)
• Timer control status register bit 76543210
Address : 00006EHRe-
served IVF IVFE STOPMODE CLR CLK1 CLK0 TCCS
Access () (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (0) (0) (0) (0) (0) (0) (0) (0)
• Compare register (upper) bit 151413121110 9 8
OCCP0
OCCP1
Address : ch0 00005BHC15 C14 C13 C12 C11 C10 C09 C08
: ch1 00005DH
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (X) (X) (X) (X) (X) (X) (X) (X)
• Compare register (lower) bit 76543210
OCCP0
OCCP1
Address : ch0 00005AHC07 C06 C05 C04 C03 C02 C01 C00
: ch1 00005CH
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (X) (X) (X) (X) (X) (X) (X) (X)
• Compare control status register 1
bit 151413121110 9 8
Address : ch1 00005FHCMOD OTE1 OTE0 OTD1 OTD0 OCS1
Access () () () (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value () () () (0) (0) (0) (0) (0)
• Compare control status register 0
bit 7 6 5 4 3 2 1 0
Address : ch0 00005EHICP1 ICP0 ICE1 ICE0 CST1 CST0 OCS0
Access (R/W) (R/W) (R/W) (R/W) () () (R/W) (R/W)
Initial value (0) (0) (0) (0) () () (0) (0)
MB90580B Series
49
(Continued)
• Input capture register (upper)
bit 151413121110 98
Address : ch0 000061H
: ch1 000063H
: ch2 000065H
: ch3 000067H
IPCP0 upper
IPCP1 upper
CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 IPCP2 upper
IPCP3 upper
Access (R) (R) (R) (R) (R) (R) (R) (R)
Initial value (X) (X) (X) (X) (X) (X) (X) (X)
• Input capture register (lower)
bit 76543210
Address : ch0 000060HIPCP0 lower
: ch1 000062HIPCP1 lower
: ch2 000064HCP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 IPCP2 lower
: ch3 000066HIPCP3 lower
Access (R) (R) (R) (R) (R) (R) (R) (R)
Initial value (X) (X) (X) (X) (X) (X) (X) (X)
• Control status register 01 bit 76543210
Address : 000068HICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 ICS01
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (0) (0) (0) (0) (0) (0) (0) (0)
• Control status register 23 bit 76543210
Address : 00006AHICP3 ICP2 ICE3 ICE2 EG31 EG30 EG21 EG20 ICS23
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (0) (0) (0) (0) (0) (0) (0) (0)
MB90580B Series
50
(5) Block Diagram
ICP1 ICP0 ICE1 ICE0
EG11 EG10 EG01 EG00
ICP1 ICP0 ICE1 ICE0
T
T
Q
Q
CMOD
OTE1
OTE0 OUT0
OUT1
IVF IVFE STOP MODE CLR CLK1 CLK0
φ
IN0, IN2
IN1, IN3
Edge
detection
Compare control
Compare interrupt 0
Compare interrupt 1
Interrupt
request
Comparator 0
16-bit up-counter
Output count value (T15 to T00)
Frequency
devider
Clock
F2MC-16LX bus
Compare register ch.0
Compare control
Compare register ch.1
Control block
Input capture data register ch.0, ch.2
Input capture data register ch.1, ch.3
Capture interrupt 1/3
Capture interrupt 0/2
Each control block
Edge
detection
MB90580B Series
51
8. 16-bit Reload Timer
The 16-bit reload timer has three channels, each of which consists of a 16-bit down counter, a 16-bit reload
register, an input pin (TIN), an output pin (TOT), and a control register. The input clock can be selected from
among three internal clocks and one external clock.
(1) Register configuration
• Timer control status register (upper)
bit 151413121110 9 8
Address : ch0 000049HTMCSR0 upper
: ch1 00004DHCSL1 CSL0 MOD2 MOD1 TMCSR1 upper
: ch2 000051HTMCSR2 upper
Access () () () () (R/W) (R/W) (R/W) (R/W)
Initial value () () () () (0) (0) (0) (0)
• Timer control status register (lower)
bit 765432 1 0
Address : ch0 000048HTMCSR0 lower
: ch1 00004CHMOD0OUTEOUTLRELD INTE UF CNTE TRG TMCSR1 lower
: ch2 000050HTMCSR2 lower
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (0) (0) (0) (0) (0) (0) (0) (0)
• 16-bit timer register (upper) /16 bit reload register (upper) (read)
bit 15 14 13 12 11 10 9 8 TMR0 upper
Address : ch0 00004BHTMR1 upper
: ch1 00004FHTMR2 upper
: ch2 000053H(write)
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) TMRLR0 upper
Initial value (X) (X) (X) (X) (X) (X) (X) (X) TMRLR1 upper
TMRLR2 upper
• 16-bit timer register (lower) /16 bit reload register (lower) (read)
bit 765432 1 0 TMR0 lower
Address : ch0 00004AHTMR1 lower
: ch1 00004EHTMR2 lower
: ch2 000052H(write)
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) TMRLR0 lower
Initial value (X) (X) (X) (X) (X) (X) (X) (X) TMRLR1 lower
TMRLR2 lower
MB90580B Series
52
(2) Block Diagram
OUT
CTL.
CSL1
CSL0
MOD2
MOD1
MOD0
16
8
16
2
3
2
CTLIN
φ
—
2
φ
—
2
φ
—
2
135
3
EXCK
GATE IRQ
RELD
OUTE
OUTL
INTE
UF
CNTE
TRG
Retrigger
16-bit reload register
16-bit down-counter UF
Reload
Clock selector
Machine clock
Prescaler
clear
Clear
EI2OSCLR
Port (TIN)
Port (TOT)
Serial baud rate
(channel n)
Output
enable
F2MC-16LX bus
Note: Reload timer channels and UART channels are connected as follows
•Reload timer channel 0 : UART0, UART3
•Reload timer channel 1 : UART1, UART4
•Reload timer channel 2 : UART2
MB90580B Series
53
9. 8/16-bit PPG
8/16-bit PPG is an 8/16-bit reload timer module. The block perfor ms PPG output in which the pulse output is
controlled by the operation of the timer.
The hardware consists of two 8-bit down-counters, four 8-bit reload registers, one 16-bit control register, two
external pulse output pins, and two interrupt outputs. The PPG has the following functions.
• 8-bit PPG output in two channels independent operation mode:
Two independent PPG output channels are available.
• 16-bit PPG output operation mode :
One 16-bit PPG output channel is available.
• 8 + 8-bit PPG output operation mode :
Variable-period 8-bit PPG output operation is available by using the output of channel 0 as the clock input to
channel 1.
• PPG output operation :
Outputs pulse waveforms with variable period and duty ratio. Can be used as a D/A converter in conjunction
with an external circuit.
(1) Register configuration
• PPG0 operating mode control register
bit 7654321 0
Address : ch0 0000044HPEN0 POE0 PIE0 PUF0 Re-
served PPGC0
Access (R/W) () (R/W) (R/W) (R/W) () () ()
Initial value (0) (X) (0) (0) (0) (X) (X) (1)
• PPG1 operating mode control register
bit 151413121110 9 8
Address : ch1 0000045HPEN1 POE1 PIE1 PUF1 MD1 MD0 Re-
served PPGC1
Access (R/W) () (R/W) (R/W) (R/W) (R/W) (R/W) ()
Initial value (0) (X) (0) (0) (0) (0) (0) (1)
• PPG0 and 1 output control registers
bit 7654321 0
Address : ch0, 1 0000046HPCS2 PCS1 PCS0PCM2PCM1PCM0 Re-
served Re-
served PPGOE
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) () ()
Initial value (0) (0) (0) (0) (0) (0) (0) (0)
• Reload register H bit 151413121110 9 8
Address : ch0 000041HPRLH0
: ch1 000043HPRLH1
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (X) (X) (X) (X) (X) (X) (X) (X)
• Reload register L bit 76543210
Address : ch0 000040HPRLL0
: ch1 000042HPRLL1
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (X) (X) (X) (X) (X) (X) (X) (X)
MB90580B Series
54
(2) Block Diagram
• Block diagram (8 bit PPG (ch.0) )
S
R
Q
PRLBH0
PPGC0
PRLL0
PRLH0
PPG0
PEN0
IRQ
PIE0
PUF0
Machine clock divided by 16
Machine clock divided by 8
Machine clock divided by 4
Machine clock divided by 2
Machine clock
Count clock selection
Timebase counter output
oscillation clock divided
by 512
PPG0 output enable
Invert Clear
PPG0
output latch
L/H select L/H Selector
PCNT (Down-counter)
Reload
(Operation mode control)
L-side data bus
H-side data bus
ch.1 borrow
MB90580B Series
55
• Block Diagram (8/16 bit PPG (ch.1) )
S
R
Q
PRLBH1
PPGC1
PRLL1
PRLH1
PPG1
PEN1
IRQ
PIE
PUF
Machine clock divided by 16
Machine clock divided by 8
Machine clock divided by 4
Machine clock divided by 2
Machine clock
PPG1 output enable
L/H Selector
ch0 borrow
A/D converter
PPG1
output latch
ClearInvert
Reload
PCNT (Down-counter)
Count clock selection
Timebase counter output
oscillation clock divided
by 512
(Operation mode control)
L-side data bus
H-side data bus
L/H select
MB90580B Series
56
10. DTP/External Interrupts
The DTP (Data Transf er Peripheral) is a peripheral bloc k that interfaces external peripherals to the F2MC-16LX
CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the
requests to the F2MC-16LX CPU to activate the intelligent I/O service or interrupt processing. Two request le vels
(“H” and “L”) are provided for the intelligent I/O service. For e xternal interrupt requests, gener ation of interrupts
on a rising or falling edge as well as on “H” and “L” levels can be selected, giving a total of four types.
(1) Register configuration
(2) Block Diagram
• Interrupt/DTP enable register bit 76543210
Address : 0000030HEN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 ENIR
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (0) (0) (0) (0) (0) (0) (0) (0)
• Interrupt/DTP source register bit 151413121110 9 8
Address : 0000031HER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 EIRR
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (X) (X) (X) (X) (X) (X) (X) (X)
• Request level setting register (lower)
bit 76543210
Address : 0000032HLB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 ELVR lower
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (0) (0) (0) (0) (0) (0) (0) (0)
• Request level setting register (upper)
bit 151413121110 9 8
Address : 0000033HLB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 ELVR upper
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (0) (0) (0) (0) (0) (0) (0) (0)
8
8
8
8
8
Interrupt/DTP enable register
Interrupt/DTP source register
Request level setting register
Gate Source F/F Edge detect circuit Request input
F2MC-16LX bus
MB90580B Series
57
11. Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate the task switching interr upt. Interr upt requests to
the F2MC-16LX CPU can be generated and cleared by software using this module.
(1) Register configuration
The DIRR register controls generation and clearing of delayed interrupt requests. Writing “1” to the register
generates a delayed interrupt request. Writing “0” to the register clears the delayed interrupt request. The register
is set to the interrupt cleared state by a reset. Either “0” or “1” can be written to the reser ved bits. However,
considering possible future e xtensions , it is recommended that the set bit and clear bit instructions are used f or
register access.
(2) Block Diagram
• Delayed interrupt generation/release register
bit 151413121110 9 8
Address : 00009FHR0 DIRR
Access () () () () () () () (R/W)
Initial value () () () () () () () (0)
Delayed interrupt generation/
release decode
Interrupt
latch
F2MC-16LX bus
MB90580B Series
58
12. A/D Converter
The A/D conv erter conv erts analog input voltages to digital values. The A/D conv erter has the following features.
• Conversion time: Minimum of 34.7 µs per channel (for a 12 MHz machine clock)
• Uses RC-type successive approximation conversion with a sample and hold circuit.
• 8/10-bit resolution
• Eight program-selectable analog input channels
Single conversion mode: Selectively convert one channel.
Scan conv ersion mode: Continuously conv ert multiple channels. Maximum of 8 prog ram selectable channels .
Continuous conversion mode : Repeatedly convert specified channels.
Stop conv ersion mode:Convert one channel then halt until the next activation. (Enables synchronization of the
conversion start timing.)
• An A/D conversion completion interrupt request.
An A/D conversion completion interrupt request to the CPU can be generated on the completion of A/D
conv ersion. This interrupt can activate EI2OS to transf er the result of A/D conversion to memory and is suitable
for continuous operation.
• Activation by software, external trigger (falling edge), or timer (rising edge) can be selected.
(1) Register configuration
• Control status register (upper) bit 151413121110 9 8
Address : 000037HBUSY INT INTE PAUS STS1 STS0 STRT Re-
served ADCS2
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (W) ()
Initial value (0) (0) (0) (0) (0) (0) (0) (0)
• Control status register (lower) bit 76543210
Address : 000036HMD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 ADCS1
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (0) (0) (0) (0) (0) (0) (0) (0)
• Data register (upper) bit 151413121110 9 8
Address : 000039HSELB ST1 ST0 CT1 CT0 D9 D8 ADCR2
Access (W) (W) (W) (W) (W) () (R) (R)
Initial value (0) (0) (0) (0) (1) () (X) (X)
• Data register (lower) bit 76543210
Address : 000038HD7 D6 D5 D4 D3 D2 D1 D0 ADCR1
Access (R) (R) (R) (R) (R) (R) (R) (R)
Initial value (X) (X) (X) (X) (X) (X) (X) (X)
MB90580B Series
59
(2) Block Diagram
AVCC
AVRH,AVRL
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
MPX
ADCR1, 2
ADCS1, 2
ADTG
φ
AVSS
Sample and
hold circuit
Comparator
D/A converter
Data register
Successive approxi-
mation register
Trigger activation
Control status
register lower
F2
M
C
1
6
L
X
b
u
s
Control status
register upper
Timer activation Operating
clock
PPG1 output
Decoder
Input circuit
Prescaler
MB90580B Series
60
13. D/A Converter
D/A converter is an R-2R type D/A converter with 8-bit resolution. The device contains two D/A converters. The
D/A control register controls the output of the two D/A converters independently.
(1) Register configuration
• D/A converter data register 1 bit151413121110 9 8
Address : 00003BHDA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10 DAT1
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (0) (0) (0) (0) (0) (0) (0) (0)
• D/A converter data register 0 bit76543210
Address : 00003AHDA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00 DAT0
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (0) (0) (0) (0) (0) (0) (0) (0)
• D/A control register 1 bit151413121110 9 8
Address : 00003DHDAE1 DACR1
Access () () () () () () () (R/W)
Initial value () () () () () () () (0)
• D/A control register 0 bit76543210
Address : 00003CHDAE0 DACR0
Access () () () () () () () (R/W)
Initial value () () () () () () () (0)
MB90580B Series
61
(2) Block Diagram
DA
17 DA
16 DA
15 DA
14 DA
13 DA
12 DA
11 DA
10 DA
07 DA
06 DA
05 DA
04 DA
03 DA
02 DA
01 DA
00
DAE1
2R 2R
2R
2R
R
R
R
DVR
DA17
DA16
DA15
DA11
DA10
DAE0
2R 2R
2R
2R
R
R
R
DVR
DA07
DA06
DA05
DA01
DA00
2R 2R
F2MC16LX - BUS
DA output
channel 1 DA output
channel 0
Standby control Standby control
MB90580B Series
62
14. Communication Prescaler
The register (clock division control register) of the communication prescaler controls division of the machine
clock frequency. It is designed to provide a fix ed baud rate f or a variety of machine clock frequencies depending
on the user setting.
The output from the communication prescaler is used by the UARTs.
(1) Register configuration
• Clock division control registers 0 to 4
bit151413121110 9 8
Address : 00002CH
00002EH
000034H
000087H
00008FH
MD DIV3 DIV2 DIV1 DIV0 CDCR0
CDCR1
CDCR2
CDCR3
CDCR4
Access (R/W) () () () (R/W) (R/W) (R/W) (R/W)
Initial value (0) () () () (1) (1) (1) (1)
MB90580B Series
63
15. UART
The UART is a serial I/O port for asynchronous (start-stop) communication or clock-synchronous communication.
The UART has the following features:
• Full-duplex double buffering
• Capable of asynchronous (start-stop) and CLK-synchronous communications
• Support for the multiprocessor mode
• Dedicated baud rate generator integratedBaud rate
* : Assuming internal machine clock frequencies of 6, 8, 10, 12, and 16 MHz
• Capable of setting an arbitrary baud rate using an external clock
• Error detection functions (parity, framing, overrun)
• HRz sign transfer signal
(1) Register configuration
Operation Baud rate
Asynchronous 31250/9615/4808/2404/1202 bps
CLK synchronous 2 M/1 M/500 K/250 K/125 K/62.5 Kbps
• Serial mode register
Address : 0000020H
0000024H
0000028H
0000082H
0000088H
bit 76543210 SMR0
SMR1
SMR2
SMR3
SMR4
MD1 MD0 CS2 CS1 CS0 Re-
served SCKE SOE
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (0) (0) (0) (0) (0) (0) (0) (0)
• Serial control register
Address : 0000021H
0000025H
0000029H
0000083H
0000089H
bit 151413121110 9 8 SCR0
SCR1
SCR2
SCR3
SCR4
PEN P SBL CL A/D REC RXE TXE
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (0) (0) (0) (0) (0) (1) (0) (0)
• Serial input register/serial output register
bit 76543210 (read) (write)
Address : 0000022H
0000026H
000002AH
0000084H
000008AH
D7 D6 D5 D4 D3 D2 D1 D0 SIDR0
SIDR1
SIDR2
SIDR3
SIDR4
SODR0
SODR1
SODR2
SODR3
SODR4
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (X) (X) (X) (X) (X) (X) (X) (X)
• Serial status register
Address : 0000023H
0000027H
000002BH
0000085H
000008BH
bit 151413121110 9 8 SSR0
SSR1
SSR2
SSR3
SSR4
PE ORE FRE RDRFTDRE RIE TIE
Access (R/W) (R/W) (R/W) (R/W) (R/W) () (R/W) (R/W)
Initial value (0) (0) (0) (0) (1) () (0) (0)
MB90580B Series
64
(2) Bloc k Diagram
SIN0 ∼ SIN4
SIDR0 to SIDR4 SODR0 to SODR4
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
SOT0 to SOT4
PEN
P
SBL
CL
A/D
REC
RXE
TXE
PE
ORE
FRE
RDRF
TDRE
RIE
TIE
SCK0 to SCK4
Control
signals
Dedicated baud
rate generator
16 bit reload timer
channel 0 to 2
External clock
Clock select
circuit
Receive condition
decision circuit
Reception error
generation
signal for EI2OS
(to CPU)
Receive clock
Receive control
circuit
Start bit
detection circuit
Receive bit
counter
Receive parity
counter
Shift register
for reception
Reception
complete
F2MC-16LX bus
Transmit clock
Receive interrupt
signal (to CPU)
Transmit interrupt
signal (to CPU)
Transmit start
circuit
Transmit bit
counter
Transmit parity
counter
Shift register
for transmission
Start
transmission
SMR0 to
SMR4
register
Control signal
SCR0 to
SCR4
register
SSR0 to
SSR4
register
Transmit control
circuit
MB90580B Series
65
16. IEBusTM Controller
The IEBusTM (Inter-Equipment Bus) is a small-scale, two-wire serial bus interface designed for data transfer
between pieces of equipment.
This interface is applicable, for example, as a bus interface for controlling vehicle-mounted devices.
IEBusTM has the following features:
•Multitasking
Any of the units connected to the IEBusTM can transmit data to another one.
• Broadcast function (Communication from one unit to multiple units)
Group broadcast : Broadcast to a group of units
All-unit broadcast : Broadcast to all units
• Three modes can be selected for different transmission speeds.
• Data buffer for transmission
8-byte FIFO buffer
• Data buffer for reception
8-byte FIFO buffer
• CPU internal operating frequency (12 MHz, 12.58 MHz)
• Frequency tolerance
In mode 0 or 1 : ±1.5%
In mode 2 : ±0.5%
(1) Register configuration
(Continued)
IEBusTM internal frequency
6 MHz 6.29 MHz
Mode 0 About 3.9 Kbps About 4.1 Kbps
Mode 1 About 17 Kbps About 18 Kbps
Mode 2 About 26 Kbps About 27 Kbps
• Local-office address setting register H
bit 15 14 13 12 11 10 9 8
Address : 000071HReservedReservedReservedReserved MA11 MA10 MA09 MA08 MAWH
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (X) (X) (X) (X) (X) (X) (X) (X)
• Local-office address setting register L
bit7 6543210
Address : 000070HMA07 MA06 MA05 MA04 MA03 MA02 MA01 MA00 MAWL
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (X) (X) (X) (X) (X) (X) (X) (X)
• Slave address setting register Hbit 15 14 13 12 11 10 9 8
Address : 000073HReservedReservedReservedReserved SA11 SA10 SA09 SA08 SAWH
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (X) (X) (X) (X) (X) (X) (X) (X)
MB90580B Series
66
(Continued)
• Slave address setting register Lbit7654321 0
Address : 000072HSA07 SA06 SA05 SA04 SA03 SA02 SA01 SA00 SAWL
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (X) (X) (X) (X) (X) (X) (X) (X)
• Broadcast control bit setting register
bit151413121110 9 8
Address : 000075HDO3 DO2 DO1 DO0 C3 C2 C1 C0 DCWR
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (0) (0) (0) (0) (0) (0) (0) (0)
• Broadcast control bit read register
bit151413121110 9 8
Address : 00007FHDO3 DO2 DO1 DO0 C3 C2 C1 C0 DCRR
Access (R) (R) (R) (R) (R) (R) (R) (R)
Initial value (0) (0) (0) (X) (X) (X) (X) (X)
• Message length bit setting register
bit7654321 0
Address : 000074HDE7 DE6 DE5 DE4 DE3 DE2 DE1 DE0 DEWR
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (0) (0) (0) (0) (0) (0) (0) (0)
• Message length bit read register
bit7654321 0
Address : 00007EHDE7 DE6 DE5 DE4 DE3 DE2 DE1 DE0 DERR
Access (R) (R) (R) (R) (R) (R) (R) (R)
Initial value (X) (X) (X) (X) (X) (X) (X) (X)
• Command register H bit151413121110 9 8
Address : 000077HMD1 MD0 PCOM RIE TIE GOTMGOTSReserved CMRH
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (0) (0) (0) (0) (0) (0) (0) (X)
• Command register L bit7654321 0
Address : 000076HRXS TXS TIT1 TIT0 CS1 CS0 RDBC WDBC CMRL
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (1) (1) (0) (0) (0) (0) (0) (0)
• Status register H bit151413121110 9 8
Address : 000079HCOM TE PEF ACK RIF TIF TSL EOD STRH
Access (R) (R/W) (R) (R) (R/W) (R/W) (R) (R)
Initial value (0) (0) (X) (X) (0) (0) (0) (0)
MB90580B Series
67
(Continued)
• Status register L bit76543210
Address : 000078HWDBF RDBF WDBE RDBE ST3 ST2 ST1 ST0 STRL
Access (R) (R) (R) (R) (R) (R) (R) (R)
Initial value (0) (0) (1) (1) (X) (X) (X) (X)
• Lock read register H bit15141312111098.
Address : 00007BHReserved ReservedReserved LOC LD11 LD10 LD09 LD08 LRRH
Access (R) (R) (R) (R/W) (R) (R) (R) (R)
Initial value (1) (1) (1) (0) (X) (X) (X) (X)
• Lock read register L bit76543210
Address : 00007AHLD07 LD06 LD05 LD04 LD03 LD02 LD01 LD00 LRRL
Access (R) (R) (R) (R) (R) (R) (R) (R)
Initial value (X) (X) (X) (X) (X) (X) (X) (X)
• Master address read register Hbit15141312111098.
Address : 00007DHReserved ReservedReservedReserved MA11 MA10 MA09 MA08 MARH
Access (R) (R) (R) (R) (R) (R) (R) (R)
Initial value (1) (1) (1) (1) (X) (X) (X) (X)
• Master address read register L bit76543210
Address : 00007CHMA07 MA06 MA05 MA04 MA03 MA02 MA01 MA00 MARL
Access (R) (R) (R) (R) (R) (R) (R) (R)
Initial value (X) (X) (X) (X) (X) (X) (X) (X)
• Read data buffer bit15141312111098
Address : 000081HRD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 RDB
Access (R) (R) (R) (R) (R) (R) (R) (R)
Initial value (X) (X) (X) (X) (X) (X) (X) (X)
• Write data buffer bit76543210
Address : 000080HWD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 WDB
Access (W) (W) (W) (W) (W) (W) (W) (W)
Initial value (X) (X) (X) (X) (X) (X) (X) (X)
MB90580B Series
68
(2) Block Diagram
The control circuit in the IEBusTM controller executes the following control functions:
• Controls the number of bytes in data to be transmitted and received.
• Controls the maximum number of bytes transmitted.
• Detects the results of arbitration.
• Evaluates the return of acknowledgment of each field.
• Generates interrupt signals.
2
TX
RX
6 MHz/6.29 MHz
Local-office address setting register
Slave address setting register
Broadcast control bit setting register
Message length bit setting register
8-byte FIFO, write data buffer
Master address read register
Broadcast control bit read register
Message length bit read register
Lock read register
8-byte FIFO, read data buffer
Command register
Status register
F2MC-16LX internal bus
Control circuit
IEBusTM protocol controller
Prescaler
IEBusTM
controller
Interrupt request signal
(transmission/reception)
Internal clock
12 MHz/12.58 MHz
MB90580B Series
69
17. Clock Monitor Function
The clock monitor function outputs the frequency-divided machine clock signal (for monitoring purposes) from
the CKOT pin.
(1) Register configuration
(2) Block Diagram
• Clock output enable register bit 76543210
Address : 00003EHCKENFRQ2FRQ1FRQ0 CLKR
Access () () () () (R/W) (R/W) (R/W) (R/W)
Initial value () () () () (0) (0) (0) (0)
CKEN
FRQ2
FRQ1
FRQ0 P65/CKOT
F2MC-16LX bus
Divider
circuit
Machine clock φ
MB90580B Series
70
18. Address Match Detection Function
When an address matches the v alue set in the address detection register , the instruction code to be loaded into
the CPU is forced to be replaced with the INT9 instr uction code (01H). When executing a set instruction, the
CPU e x ecutes the INT9 instruction. The address match detection function is implemented by processing using
the INT9 interrupt routine.
The de vice contains two address detection registers, each pro vided with a compare enable bit. When the v alue
set in the address detection register matches an address and the interrupt enable bit is “1”, the instruction code
to be loaded into the CPU is forced to be replaced with the INT9 instruction code.
(1) Register configuration
• Program address detection register 0 to 2 (PADR0)
bit
PADR0 (lower) Address : 001FF0H
Access
Initial value
bit
PADR0 (middle) Address : 001FF1H
Access
Initial value
bit
PADR0 (upper) Address : 001FF2H
Access
Initial value
• Program address detection register 3 to 5 (PADR1)
bit
PADR1 (lower) Address : 001FF3H
Access
Initial value
bit
PADR1 (middle) Address : 001FF4H
Access
Initial value
bit
PADR1 (upper) Address : 001FF5H
Access
Initial value
• Program address detection control/status register (PACSR)
bit 76543210
Address : 00009EHRe-
served Re-
served Re-
served Re-
served AD1E AD1D AD0E AD0D
Access (−) (−) (−) (−) (R/W) (−) (R/W) (−)
Initial value (0) (0) (0) (0) (0) (0) (0) (0)
76543210
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
17 16 15 14 13 12 11 10
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
76543210
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
17 16 15 14 13 12 11 10
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
76543210
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
17 16 15 14 13 12 11 10
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
(R/W)
(
X
)
MB90580B Series
71
(2) Block Diagram
Address latch
Address detection
register
Enable bit
INT9
Instruction F2MC-16LX
CPU core
F2MC-16LX bus
Compare
MB90580B Series
72
19. ROM Mirroring Function Selection Module
The ROM mirroring function selection module can select what the FF bank allocated the R OM sees through the
00 bank according to register settings.
(1) Register configuration
(2) Block Diagram
• ROM mirroring register bit151413121110 9 8
Address : 00006FHMI ROMM
Access () () () () () () () (W)
ROM
Address area
Data
FF bank 00 bank
Address
F2MC-16LX bus ROM mirroring function
selection register
MB90580B Series
73
20. One-Megabit Flash Memory
The 1Mbit flash memor y is allocated in the FEH to FFH banks on the CPU memory map. Like masked RO M,
flash memor y is read-accessible and program-accessible to the CPU using the flash memory interface circuit.
The flash memor y can be programmed/erased by the instr uction from the CPU via the flash memory interface
circuit. The flash memory can therefore be reprogrammed (updated) while still on the circuit board under
integrated CPU control, allowing program code and data to be improved efficiently.
Note that sector operations such as “enable sector protect” cannot be used.
Features of 1Mbit flash memory
• 128K words x 8 bits or 64K words x 16 bits (16K + 512 x 2 + 7K + 8K + 32K + 64K) sector configuration
• Automatic program algorithm (Embedded Algorithm*: Same as the MBM29F400TA)
• Erasure suspend/resume function integrated
• Detection of programming/erasure completion using the data polling or toggle bit
• Detection of programming/erasure completion using CPU interrupts
• Compatible with JEDEC standard commands
• Capable of erasing data sector by sector (arbitrary combination of sectors)
• Minimum number of times of programming/erasure: 100,000
* : Embedded Algorithm is a trademark of Advanced Micro Devices, Inc.
(1) Register configuration
• Flash memory control status register
bit76543210
Address : 0000AEHINTE RDY-
INT WE RDY Reserved LPM1 Reserved LPM0 FMCS
Access (R/W) (R/W) (R/W) (R) (W) (R/W) (W) (R/W)
Initial value (0) (0) (0) (X) (0) (0) (0) (0)
MB90580B Series
74
(2) Sector configuration of 1Mbit flash memory
The 1Mbit flash memory has the sector configuration illustrated belo w. The addresses in the illustration are the
upper and lower addresses of each sector.
When accessed from the CPU , SA0 and SA1 to SA4 are allocated in the FE and FF bank registers, respectiv ely.
* : Programmer addresses correspond to CPU addresses when data is progr ammed in flash memory by a parallel
programmer. Programmer addresses are used to program/erase data using a general-purpose programmer.
Flash memory CPU address Programmer
address *
FFFFFFh 7FFFFh
SA4 (16K bytes) FFC000h 7C000h
FFBFFFh 7BFFFh
SA3 (8 K bytes) FFA000h 7A000h
FF9FFFh 79FFFh
SA2 (8 K bytes) FF8000h 78000h
FF7FFFh 77FFFh
SA1 (32 K bytes) FF0000h 70000h
FEFFFFh 6FFFFh
SA0 (64 K bytes) FE0000h 60000h
MB90580B Series
75
21. Low-Power Consumption Control Circuit
The operation modes of the MB90580B series are the PLL clock, PLL sleep, watch, main clock, main sleep,
stop , and hardw are standb y modes . The oper ation modes e xcluding the PLL cloc k mode are classified as lo w-
power consumption modes.
The low power consumption circuit has the following functions.
• Main clock mode/Main sleep mode
In either mode, the microcontroller operates only with the main clock (OSC oscillation clock), using the main
clock as the operating clock while suspending the PLL clock (VCO oscillation clock).
• PLL sleep mode/Main sleep mode
These modes stop only the operation clock of the CPU, leaving the other clocks active.
• Watch mode
The watch mode allows only the time-base timer to operate.
• Stop mode/Hardware standby mode
These modes stop oscillation while retaining data at the lowest power consumption. The CPU inter mittent
operation function causes the clock supplied to the CPU to operate intermittently when the CPU accesses a
register, internal memory, internal resource, or external bus. This function saves power consumption by
decreasing the e xecution speed of the CPU while providing high-speed clock signals to the internal resources.
The PLL clock multiplication factor can be selected from among 1, 2, 3, and 4 using the CS1 and CS0 bits in
the clock selection register.
The WS1 and WS0 bits can be used to set the oscillation settling time for the main clock, which is taken to
wake up from the stop or hardware standby mode.
(1) Register configuration
• Low-power consumption mode control register
bit 76543210
Address : 0000A0HSTP SLP SPL RST TMD CG1 CG0 LPMCR
Access (W) (W) (R/W) (W) () (R/W) (R/W) ()
Initial value (0) (0) (0) (1) (1) (0) (0) ()
• Clock selection register bit 151413121110 9 8
Address : 0000A1HSCM MCM WS1 WS0 SCS MCS CS1 CS0 CKSCR
Access (R) (R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (1) (1) (1) (1) (1) (1) (0) (0)
MB90580B Series
76
(2) Block Diagram
MCM
MCS
CS1
CS0
CG1
CG0
SLP
STP
TMD
1234
RST
SCM SLEEP
STOP
MSTP
WS1
WS0
SPL
RST
210
213
215
218
219
216
214
212
LPMCR
LPMCR
CKSCR
CKSCR
SCM
SCS
CKSCR
CKSCR
LPMCR
LPMCR
WDGRST
1/2 S
Subclock switching
controller
CPU clock selector
Oscillation
stability
waiting time
selector
HST
Start
Standby
control
circuit
CPU intermittent
operation cycle
selector
PLL multiplication
circuit
Pin hi-impedance
control circuit
Internal reset
generation signal circuit
CPU clock
generation CPU clock
0/9/17/33
intermittent
cycle selection
Peripheral clock
generation
Sub clock
(OSC oscillation)
Interrupt request
or RST
Sub OSC stop
Main OSC stop
Peripheral clock
To watchdog timer
Internal RST
RST pin
Pin Hi-Z
Clock input
Timebase timer
F2MC-16LX bus
Cancel
HST pin
Main clock
(OSC oscillation)
MB90580B Series
77
■ELECTRICAL CHARACTERISTICS
1. Absolute Maximu m Ratings (VSS = AVSS = 0.0 V)
*1 : AVCC shall never exceed VCC when power on.
*2 : VI and VO shall never exceed VCC + 0.3 V.
*3 : The maximum output current is a peak value for a corresponding pin.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Parameter Symbol Rating Unit Remarks
Min. Max.
Power supply voltage
VCC VSS − 0.3 VSS + 6.0 V
AVCC VSS − 0.3 VSS + 6.0 V VCC ≥ AVCC Åñ1
AVRH, AVRL VSS − 0.3 VSS + 6.0 V AVCC ≥ AVRH/L, AVRH ≥ AVRL
DVCC VSS − 0.3 VSS + 6.0 V VCC ≥ DVCC
Input voltage VIVSS − 0.3 VSS + 6.0 V *2
Output voltage VOVSS − 0.3 VSS + 6.0 V *2
“L” level maximum output
current IOL 15 mA *3
“L” level average output
current IOLAV 4mA
Average output current = operating
× operating efficiency
“L” level total maximum
output current ΣIOL 100 mA
“L” level total average
output current ΣIOLAV 50 mA Average output current = oper ating
× operating efficiency
“H” level maximum output
current IOH −15 mA *3
“H” level average output
current IOHAV −4mA
Average output current = operating
× operating efficiency
“H” level total maximum
output current ΣIOH −100 mA
“H” level total average
output current ΣIOHAV −50 mA Average output current = operating
× operating efficiency
Power consumption PD300 mW
Operating temperature TA−40 +85 °C
Storage temperature Tstg −55 +150 °C
MB90580B Series
78
2. Recommended Operating Conditions (VSS = AVSS = 0.0 V)
WARNING: The recommended operating conditions are required in order to ensure the nor mal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating conditionranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter Symbol Value Unit Remarks
Min. Max.
Power supply
voltage VCC 3.0 5.5 V Normal operation (MB90583B, MB90587,
MB90V580)
4.5 5.5 V Normal operation (MB90F583B)
VCC 3.0 5.5 V Retains status at the time of operation stop
“H” level input
voltage
VIH 0.7 VCC VCC+0.3 V CMOS input pin
VIHS 0.8 VCC VCC+0.3 V CMOS hysteresis input pin
VIHM VCC − 0.3 VCC+0.3 V MD pin input
“L” level input
voltage
VIL VSS − 0.3 0.3 VCC V CMOS input pin
VILS VSS − 0.3 0.2 VCC V CMOS hysteresis input pin
VILM VSS − 0.3 VSS+0.3 V MD pin input
Smoothing
capacitor CS0.1 1.0 µF
Use a ceramic capacitor or a capacitor with
equivalent frequency characteristics. The
smoothing capacitor to be connected to the VCC
pin must have a capacitance value higher than
CS.
Operating
temperature TA−40 +85 °C
• C pin connection circuit
C
CS
MB90580B Series
79
3. DC Characteristics (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
(Continued)
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Typ. Max.
“H” le v el output
voltage VOH All output
pins VCC = 4.5 V,
IOH = −2.0 mA VCC − 0.5 V
“L” level output
voltage VOL All output
pins VCC = 4.5 V,
IOL = 2.0 mA 0.4 V
Input leakage
current IIL All input
pins VCC = 5.5 V,
VSS < VI< VCC −55µA
Power supply
current*
ICC
VCC
VCC = 5.0 V,
Internal operation
at 16 MHz,
Normal operation
27 33 mA MB90583B,
MB90587
40 50 mA MB90F583B
VCC = 5.0 V,
Internal operation
at 12.58 MHz,
Normal operation
22 26 mA MB90583B
35 45 mA MB90F583B
VCC = 5.0 V,
Internal operation
at 16 MHz,
When data written
in flash mode pro-
gramming of er asing
45 60 mA
MB90F583B
VCC = 5.0 V,
Internal operation
at 12.58 MHz,
When data written
in flash mode pro-
gramming of er asing
40 50 mA
ICCS
VCC = 5.0 V,
Internal operation
at 16 MHz, ,
In sleep mode
7 12 mA MB90587
15 20 mA MB90583B,
MB90F583B
VCC = 5.0 V
Internal operation
at 12.58 MHz,
In sleep mode
6 10 mA MB90587
12 18 mA MB90583B,
MB90F583B
ICCL
VCC = 5.0 V,
Internal operation
at 8 kHz,
Subsystem opera-
tin, TA = 25 °C
0.1 1.0 mA MB90583B,
MB90587
4 7 mA MB90F583B
MB90580B Series
80
(Continued)
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
* The current value is preliminary value and may be subject to change for enhanced characteristics without previous
notice. The power supply current is measured with an external clock.
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Typ. Max.
Power supply
current*
ICCLS
VCC
VCC = 5.0 V,
Internal operation
at 8 kHz,
In subsleep mode,
TA = 25 °C
30 50 µAMB90583B,
MB90587,
MB90F583
ICCT
VCC = 5.0 V,
Internal operation
at 8 kHz,
In clock mode,
TA = 25 °C
15 30 µAMB90583B,
MB90587,
MB90F583B
ICCH In stop mode,
TA = 25 °C520µAMB90583B
MB90587,
MB90F583B
Input
capacitance CIN Except AVCC,
AVSS, C, VCC
and VSS 10 80 pF
Open-drain
output
leakage
current Ileak P40 to P47 0.1 5 µAOpen-drain
output setting
Pull-up
resistance RUP
P00 to P07
P10 to P17
P60 to P65
RST
25 50 100 kΩ
Pull-down
resistance RDOWN MD2 25 50 100 kΩ
MB90580B Series
81
4. AC Characteristics
(1) Clock Timings (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
*: The frequency fluctuation rate is the maxim um de viation r ate of the preset center frequency when the multiplied
PLL signal is loc ked.
Parameter Symbol Pin name Con-
dition Value Unit Remarks
Min. Typ. Max.
Clock frequency fCX0, X1
316 MHz
fCL X0A, X1A 32.768 kHz
Clock cycle time tHCYL X0, X1 62.5 333 ns
tLCYL X0A, X1A 30.5 µs
Frequency fluctuation
rate locked* ∆f5%
Input clock pulse width
PWH
PWL X0 10 ns Recommened duty
ratio of 30% to 70%
PWLH
PWLL X0A 15.2 µs
Input clock rise/fall time tCR
tCF X0 5ns
External clock
operation
Internal operating clock
frequency fCP 1.5 16 MHz Main clock operation
fLCP 8.192 kHz Subclock operation
Internal operating clock
cycle time tCP 62.5 — 666 ns Main clock operation
tLCP 122.1 µs Subclock operation
+
+α
α fo
fo −α
−
∆f = × 100 (%) Center
frequency
X0
tHCYL
tCF tCR
0.8 VCC
0.2 VCC
PWH PWL
• X0, X1 clock timing
X0A
tLCYL
tCF tCR
0.8 VCC
0.2 VCC
PWLH PWLL
• X0A, X1A clock timing
MB90580B Series
82
The AC ratings are measured for the following measurement reference voltages
• PLL operation guarantee range
5.5
4.5
3.3
3.0
16
12
8
9
4
34 8 16
13 8 12 16
Power supply voltage VCC (V)
Operation guarantee range of PLL
Operation guarantee
range of MB90583B/7,
MB90V580B
Internal clock fCP (MHz)
Relationship between internal operating clock frequency and power supply voltage
Operation guarantee range of MB90F583B
Relationship between oscillating frequency and internal operating clock frequency
Oscillation clock fCP (MHz)
Internal clock fCP (MHz)
Not multiplied
Multiplied-
by-4 Multiplied-
by-3 Multiplied-
by-2 Multiplied-
by-1
0.8 VCC
0.2 VCC
2.4 V
0.8 V
0.7 VCC
0.3 VCC
• Input signal waveform
Hystheresis input pin
Pins other than hystheresis input/MD input
• Output signal waveform
Onput pin
MB90580B Series
83
(2) Clock Output Timings (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
(3) Reset, Hardware Standby Input Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
Clock cycle time tCYC CLK VCC = 5 V ± 10% 62.5 ns
CLK↑ → CLK↓tCHCL 20 ns
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
Reset input time tRSTL RST 4 tCP ns
Hardware standby input time tHSTL HST 4 tCP ns
CLK
tCYC
2.4 V 2.4 V
0.8 V
tCHCL
RST
HST 0.2 VCC
tRSTL, tHSTL
0.2 VCC
MB90580B Series
84
(4) Power-on Reset (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
* : VCC must be kept lower than 0.2 V before power-on.
Note The above values are used for causing a power-on reset.
If HST = “L”, be sure to turn the power supply on using the abo v e values to cause a pow er-on reset whether
or not the power-on reset is required.
Some registers in the de vice are initialized only upon a power-on reset. To initialize these registers, turn the
power supply using the above values.
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
Power supply rising time tRVCC 0.05 30 ms
Power supply cut-off time tOFF VCC 4ms Due to repeated
operations
VCC
VCC
VSS
3.0 V
tR
tOFF
2.7 V
0.2 V 0.2 V0.2 V
Sudden changes in the power supply voltage may cause a power-on reset.
To change the power supply v oltage while the de vice is in operation, it is recom-
mended to raise the v oltage smoothly to suppress fluctuations as sho wn below.
In this case, change the supply voltage with the PLL clock not used. If the volt-
age drop is 1 mV or fewer per second, however, you can use the PLL clock.
It is recommended to keep the
rising speed of the supply voltage
at 50 mV/ms or slower.
RAM data hold
MB90580B Series
85
(5) Bus Timing (Read) (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
ALE pulse width tLHLL ALE
tCP/2 − 20 ns
Effective address →
ALE ↓ time tAVLL ALE, A23 to A16,
AD15 to AD00 tCP/2 − 20 ns
ALE ↓ → address
effective time tLLAX ALE, AD15 to AD00 tCP/2 − 15 ns
Effective address →
RD ↓ time tAVRL A23 to A16,
AD15 to AD00, RD tCP − 15 ns
Effective address →
valid data input tAVDV A23 to A16,
AD15 to AD00 5 tCP/2 − 60 ns
RD pulse width tRLRH RD 3 tCP/2 − 20 ns
RD ↓ → valid data
input tRLDV RD, AD15 to AD00 3 tCP/2 − 60 ns
RD ↑ → data hold
time tRHDX RD, AD15 to AD00 0 ns
RD ↑ → ALE ↑ time tRHLH RD, ALE tCP/2 − 15 ns
RD ↑ → address
effective time tRHAX ALE, A23 to A16 tCP/2 − 10 ns
Effective address →
CLK ↑ time tAVCH A23 to A16,
AD15 to AD00, CLK tCP/2 − 20 ns
RD ↓ → CLK ↑ time tRLCH RD, CLK tCP/2 − 20 ns
ALE ↓ → RD ↓ time tLLRL ALE, RD tCP/2 − 15 ns
MB90580B Series
86
0.8 V
0.8 V
2.4 V
2.4 V
2.4 V
2.4 V
0.8 V
2.4 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.2 VCC
0.8 VCC
0.2 VCC
0.8 VCC
CLK
ALE
RD
A23 ∼ A16
AD15 ∼
AD00
2.4 V
tAVCH
tLHLL
tRHLH
tAVLL
tAVRL tRLDV
tRLRH
tRHAX
tRHDX
tLLAX
tLLRL
tRLCH
tAVDV
• Bus Timing (Read)
Address Write data
MB90580B Series
87
(6) Bus Timing (Write) (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter Symbol Pin name Conditio n Value Unit Remarks
Min. Max.
Effective address →
WRH, WRL↓ time tAVWL A23 to A16,
AD15 to AD00,
WRH, WRL
tCP − 15 ns
WRH, WRL pulse
width tWLWH WRH, WRL 3 tCP/2 − 20 ns
Effective data output
→ WRH, WRL ↑
time tDVWH AD15 to AD00,
WRH, WRL 3 tCP/2 − 20 ns
WRH, WRL ↑ →
data hold time tWHDX WRH, WRL,
AD15 to AD00 20 ns
WRH, WRL ↑ → ad-
dress
effective time tWHAX WRH, WRL, A23 to A16 tCP/2 − 10 ns
WRH, WRL ↑ →
ALE ↑ time tWHLH WRH, WRL, ALE tCP/2 − 15 ns
WRH, WRL ↓ →
CLK ↑ time tWLCH WRH, WRL, CLK tCP/2 − 20 ns
0.8 V
0.8 V
2.4 V
2.4 V
2.4 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
CLK
ALE
A23 to A16
AD15 to
AD00
tWHLH
tAVWL
tWLWH
tWHAX
tWHDX
tWLCH
tDVWH
WRH, WRL
Address Write data
• Bus Timing (Write)
MB90580B Series
88
(7) Ready Input Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Note: Use the automatic ready function when the setup time for the rising edge of the RDY signal is not sufficient.
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
RDY setup time tRYHS RDY 45 ns
RDY hold time tRYHH 0ns
tRYHH
2.4 V 2.4 V
0.2 VCC0.2 VCC
0.8 VCC 0.8 VCC
CLK
ALE
RD/WR
tRYHS tRYHS
RDY
(wait not
inserted)
RDY
(wait inserted)
MB90580B Series
89
(8) Hold Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Note: More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched.
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
Pins in floating status → HAK ↓ time tXHAL HAK 30 tCP ns
HAK ↑ → pin valid time tHAHV HAK tCP 2 tCP ns
HAK
tXHAL tHAHV
2.4 V
0.8 V 2.4 V
2.4 V
0.8 V
0.8 V
Pins High impedance
MB90580B Series
90
(9) UART0 to UART4 (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Note •These are AC ratings in the CLK synchronous mode.
•CL is the load capacitance value connected to pins while testing.
•tCP is machine cycle time (unit:ns).
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
Serial clock cycle time tSCYC SCK0 to SCK4
CL = 80 pF + 1 TTL
for an output pin of
internal shift clock
mode
8 tCP ns
SCK ↓ → SOT delay time tSLOV SCK0 to SCK4,
SOT0 to SOT4 −80 80 ns
Valid SIN → SCK ↑ tIVSH SCK0 to SCK4,
SIN0 to SIN4 100 ns
SCK ↑ → valid SIN hold time tSHIX SCK0 to SCK4,
SIN0 to SIN4 60 ns
Serial clock “H” pulse width tSHSL SCK0 to SCK4
CL = 80 pF + 1 TTL
for an output pin of
external shift clock
mode
4 tCP ns
Serial clock “L” pulse width tSLSH SCK0 to SCK4 4 tCP ns
SCK ↓ → SOT delay time tSLOV SCK0 to SCK4,
SOT0 to SOT4 150 ns
Valid SIN → SCK ↑ tIVSH SCK0 to SCK4,
SIN0 to SIN4 60 ns
SCK ↑ → valid SIN hold time tSHIX SCK0 to SCK4,
SIN0 to SIN4 60 ns
MB90580B Series
91
SCK
SOT
SIN
SCK
SOT
SIN
tSCYC
tSLOV
tIVSH tSHIX
0.8 V 0.8 V
2.4 V
2.4 V
0.8 V
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tSLSH tSHSL
tSLOV
tIVSH tSHIX
0.2 VCC 0.2 VCC
0.8 VCC 0.8 VCC
2.4 V
0.8 V
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
• Internal shift clock mode
• External shift clock mode
MB90580B Series
92
(10)Timer Input Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
(11) Timer Output Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
Input pulse width tTIWH
tTIWL IN0 to IN3,
TIN0 to TIN2 4 tCP ns
Parameter Symbol Pin nam e Condition Value Unit Remarks
Min. Max.
CLK↑→TOUT transition time tTO OUT0, OUT1,
PPG0, PPG1,
TOT0 to TOT2 30 ns
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tTIWH tTIWL
2.4 V
CLK
TOUT 0.8 V
2.4 V
tTO
MB90580B Series
93
(12) Trigger Input Timimg (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
Input pulse width tTRGL IRQ0 to IRQ7,
ADTG 5 tCP ns
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tTRGH tTRGL
MB90580B Series
94
(13) IEBusTM Timing
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
TX → RX delay time (rise) tDLY1 TX, RX 0 1000 ns
TX → RX delay time (fall) tDLY2 TX, RX 0 1000 ns
0.7 VCC
TX
RX
0.3 VCC
0.7 VCC
0.3 VCC
tDLY1
tDLY2
MB90580B
TX
RX
TX
RX
BUS+
BUS−
IEBusTM
Driver/ receiver
MB90580B Series
95
5. A/D Converter Electrical Characteristics
(3.0 V ≤ AVRH − AVRL, VCC = AVCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
* : The current when the A/D conv erter is not operating or the CPU is in stop mode (f or VCC = AVCC = AVRH = 5.0 V)
Note: • The error increases proportionally as |AVRH - AV RL| decreases.
•The output impedance of the external circuits connected to the analog inputs should be in the following
range.
•The output impedance of the external circuit : TBD
•If the output impedance of the external circuit is too high, the sampling time might be insufficient.
Parameter Symbol Pin name Value Unit Remarks
Min. Typ. Max.
Resolution 10 bit
Total error ±5.0 LSB
Non-linear error ±2.5 LSB
Differential linearity error ±1.9 LSB
Zero transition voltage VOT AN0 to
AN7 AVSS − 3.5 +0.5 AVSS + 4.5 mV
Full-scale transition voltage VFST AN0 to
AN7 AVRH − 6.5 AVRH − 1.5 AVRH + 1.5 mV
Conversion time 176 tCP ns
Sampling period 64 tCP ns
Analog port input current IAIN AN0 to
AN7 10 µA
Analog input voltage VAIN AN0 to
AN7 AVRL AVRH V
Reference voltage AVRH AVRL + 2.7 AVCC V
AVRL 0 AVRH − 2.7 V
Power supply current IAAVCC 5mA
IAH AVCC 5µA*
Reference voltage supply
current IRAVRH 400 µA
IRH AVRH 5µA*
Offset between channels — AN0 to
AN7 4LSB
C0
C1
Analog input
Comparator
MB90580B Series
96
6. A/D Converter Glossary
Resolution : Analog changes that are identifiable with the A/D converter
Linearity error : The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00
0000 0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual
conversion characteristics
Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value
Total error : The total error is defined as a difference between the actual value and the theoretical value, which
includes zero-transition error/full-scale transition error and linearity error.
(Continued)
3FF
3FE
3FD
004
003
002
001
AVRL AVRH
VNT
{1 LSB × (N − 1) + 0.5 LSB}
0.5 LSB
0.5 LSB
Total error
Actual conversion
value
Analog input
Total error for digital output N = VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB [LSB]
1 LSB = (Theoretical value) AVRH − AVRL
1024 [V]
VOT(Theoretical value) = AVRL + 0.5 LSB [V]
VFST(Theoretical value) = AVRH − 1.5 LSB [V]
VNT : Voltage at a transition of digital output from (N - 1) to N
Actual conversion
value
Theoretical
characteristics
(Measured value)
Digital output
MB90580B Series
97
(Continued)
3FF
3FE
3FD
004
003
002
001
AVRL AVRH AVRL AVRH
N + 1
N
N − 1
N − 2
VNT
VNT
V(N + 1)T
VOT
VFST
{1 LSB × (N − 1)
+ VOT }
Linearity error
Theoretical
characteristics
(Measured value)
Digital output
Differential linearity error
(Measured value)
(Measured value)
Linearity error of
digital output N VNT − {1 LSB × (N − 1) + VOT}
1 LSB [LSB]
=
Differential linearity error
of digital output N V (N + 1) T − VNT
1 LSB − 1 LSB[LSB]
=
VFST − VOT
1022 [V]
1 LSB =
VOT : Voltage at transition of digital output from “000H” to “001H”
VFST : Voltage at transition of digital output from “3FEH” to “3FFH”
Actual conversion
value Actual conversion
value
Actual conversion
value
Actual conversion
value
Theoretical
characteristics
(mesured value)
(Measured
value)
Digital output
Analog input Analog input
MB90580B Series
98
7. Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the f ollowing conditions.
Output impedance values of the external circuit of 7 kΩ or lower are recommended.
When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor
value is recommended to minimized the effect of voltage distribution between the e xternal capacitor and internal
capacitor.
When the output impedance of the external circuit is too high, the sampling period f or analog voltages ma y not
be sufficient (sampling period = 4.00 µs @machine clock of 16 MHz)
• Error
The smaller the | AVRH - AVRL |, the greater the error would become relatively.
8. D/A Converter Electrical Characteristics
(VCC = AVCC = 5.0 V±10%, VSS = AVSS = DVSS = 0.0 V, TA = −40 °C to +85 °C)
*1 : Load capacitance: 20 pF
*2 : In sleep mode
Parameter Symbol Pin name Value Unit Remarks
Min. Typ. Max.
Resolution 8bit
Differential linearity error ±0.9 LSB
Absolute accuracy ±1.2 %
Linearity error ±1.5 LSB
Conversion time 10 20 µs*1
Analog reference voltage DVRH VSS + 3.0 AVCC V
Reference voltage supply
current IDVR DVRH 120 300 µA
IDVRS 10 µA*2
Analog output impedance 20 kΩ
• Equipment of analog input circuit model
C0
C1
Analog input Comparator
Note: Listed values must be considered as standards.
MB90587, MB90V580B R ≅ 1.5 kΩ, C ≅ 30 pF
MB90F583B R ≅ 3.0 kΩ, C ≅ 65 pF
MB90583B R ≅ 2.2 kΩ, C ≅ 45 pF
MB90580B Series
99
■EXAMPLE CHARACTERISTICS
• Power Suppy Current of MB90F583B
(Continued)
VCC (V)
ICCS (mA)
20
15
10
5
023456
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
VCC (V)
ICC (mA)
45
40
35
30
25
20
15
10
5
023456
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
VCC (V)
ICCL (µA)
70
60
50
40
30
20
10
023456
f = 8 kHz
VCC (V)
ICCLS (µA)
50
45
40
35
30
25
20
15
10
5
023456
f = 8 kHz
V
CC
(V)
I
CCT
(µA)
30
28
26
24
22
20
28
16
14
12
10
8
6
4
2
023456
f = 8 kHz
ICC vs. VCC
TA = 25 °C, external clock input
ICCL vs. VCC
TA = 25 °C, external clock input
ICCT vs. VCC
TA = 25 °C, external clock input
ICCS vs. VCC
TA = 25 °C, external clock input
ICCLS vs. VCC
TA = 25 °C, external clock input
MB90580B Series
100
(Continued)
VCC - VOH (mV)
IOH (mA)
1000
900
800
700
600
500
400
300
200
100
0
013579112 4 6 8 10 12
VOL (V)
IOL (mA)
1000
900
800
700
600
500
400
300
200
100
0
0146
810
122 357911
VOH vs. IOH
TA = 25 °C, VCC = 4.5 V VOL vs. IOL
TA = 25 °C, VCC = 4.5 V
MB90580B Series
101
Power Suppy Current of MB90583B
(Continued)
VCC (V)
ICC (mA)
30
25
20
15
10
5
023456
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
VCC (V)
ICCS (mA)
20
15
10
5
023456
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
VCC (V)
ICCL (µA)
70
60
50
40
30
20
10
023456
f = 8 kHz
VCC (V)
ICCLS (µA)
50
45
40
35
30
25
20
15
10
5
023456
f = 8 kHz
VCC (V)
ICCT (µA)
30
28
26
24
22
20
28
16
14
12
10
8
6
4
2
023456
f = 8 kHz
ICC vs. VCC
TA = 25 °C, external clock input
ICCL vs. VCC
TA = 25 °C, external clock input
ICCT vs. VCC
TA = 25 °C, external clock input
ICCS vs. VCC
TA = 25 °C, external clock input
ICCLS vs. VCC
TA = 25 °C, external clock input
MB90580B Series
102
(Continued)
VCC - VOH (mV)
IOH (mA)
1000
900
800
700
600
500
400
300
200
100
0
01
234567891011
12
VOL (V)
IOL (mA)
1000
900
800
700
600
500
400
300
200
100
0
0123456789
10 11 12
VOH vs. IOH
TA = 25 °C, VCC = 4.5 V VOL vs. IOL
TA = 25 °C, VCC = 4.5 V
MB90580B Series
103
■INSTRUCTIONS (351 INSTRUCTIONS)
Table 1 Explanation of Items in Tables of Instructions
• Number of execution cycles
The number of cycles required for instruction execution is acquired by adding the number of cycles for each
instruction, a corrective value depending on the condition, and the number of cycles required for program fetch.
Whenever the instruction being executed exceeds the two-byte (word) boundary, a program on an internal
R OM connected to a 16-bit bus is f etched. If data access is interf ered with, theref ore, the n umber of e x ecution
cycles is increased.
F or each byte of the instruction being e xecuted, a program on a memory connected to an 8-bit e xternal data
bus is fetched. If data access in interfered with, therefore, the number of execution cycles is increased.
When a general-purpose register, an internal ROM, an internal RAM, an internal I/O device, or an external
bus is accessed during intermittent CPU operation, the CPU clock is suspended by the number of cycles
specified by the CG1/0 bit of the low-power consumption mode control register . When determining the number
of cycles required f or instruction execution during intermittent CPU operation, therefore, add the value of the
number of times access is done × the number of cycles suspended as the corrective value to the number of
ordinary e xecution cycles.
Item Meaning
Mnemonic Upper-case letters and symbols: Represented as they appear in assembler.
Lower-case letters: Replaced when described in assembler.
Numbers after lower-case letters:Indicate the bit width within the instruction code.
# Indicates the number of bytes.
~ Indicates the number of cycles.
m: When branching
n : When not branching
See Table 4 for details about meanings of other letters in items.
RG Indicates the number of accesses to the register during execution of the instruction.
It is used calculate a correction value for intermittent operation of CPU.
B Indicates the correction value for calculating the number of actual cycles during execution of the
instruction. (Table 5)
The number of actual cycles during execution of the instruction is the correction value summed
with the value in the “~” column.
Operation Indicates the operation of instruction.
LH Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator.
Z : Transfers “0”.
X : Extends with a sign before transferring.
– : Transfers nothing.
AH Indicates special operations involving the upper 16 bits in the accumulator.
* : Transfers from AL to AH.
– : No transfer.
Z : Transfers 00H to AH.
X : Transfers 00H or FFH to AH by signing and extending AL.
IIndicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit),
N (negative), Z (zero), V (overflow), and C (carry).
* : Changes due to execution of instruction.
– : No change.
S : Set by execution of instruction.
R : Reset by execution of instruction.
S
T
N
Z
V
C
RMW Indicates whether the instruction is a read-modify-write instruction. (a single instruction that
reads data from memory, etc., processes the data, and then writes the result to memory.)
* : Instruction is a read-modify-write instruction.
– : Instruction is not a read-modify-wr ite instruction.
Note: A read-modify-write instruction cannot be used on addresses that have different
meanings depending on whether they are read or written.
MB90580B Series
104
Table 2 Explanation of Symbols in Tables of Instructions
Symbol Meaning
A 32-bit accumulator
The bit length varies according to the instruction.
Byte : Lower 8 bits of AL
Word : 16 bits of AL
Long : 32 bits of AL and AH
AH
AL Upper 16 bits of A
Lower 16 bits of A
SP Stack pointer (USP or SSP)
PC Program counter
PCB Program bank register
DTB Data bank register
ADB Additional data bank register
SSB System stack bank register
USB User stack bank register
SPB Current stack bank register (SSB or USB)
DPR Direct page register
brg1 DTB, ADB, SSB, USB, DPR, PCB, SPB
brg2 DTB, ADB, SSB, USB, DPR, SPB
Ri R0, R1, R2, R3, R4, R5, R6, R7
RWi RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj RW0, RW1, RW2, RW3
RLi RL0, RL1, RL2, RL3
dir Compact direct addressing
addr16
addr24
ad24 0 to 15
ad24 16 to 23
Direct addressing
Physical direct addressing
Bit 0 to bit 15 of addr24
Bit 16 to bit 23 of addr24
io I/O area (000000H to 0000FFH)
imm4
imm8
imm16
imm32
ext (imm8)
4-bit immediate data
8-bit immediate data
16-bit immediate data
32-bit immediate data
16-bit data signed and extended from 8-bit immediate data
disp8
disp16 8-bit displacement
16-bit displacement
bp Bit offset
vct4
vct8 Vector number (0 to 15)
Vector number (0 to 255)
( )b Bit address
rel PC relative addressing
ear
eam Effective addressing (codes 00 to 07)
Effective addressing (codes 08 to 1F)
rlst Register list
MB90580B Series
105
Table 3 Effective Address Fields
Note : The number of bytes in the address extension is indicated by the “+” symbol in the “#” (number of bytes)
column in the tables of instructions.
Code Notation Address format Number of bytes in address
extension *
00
01
02
03
04
05
06
07
R0
R1
R2
R3
R4
R5
R6
R7
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
RL0
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
Register direct
“ea” corresponds to byte, word, and
long-word types, starting from the left —
08
09
0A
0B
@RW0
@RW1
@RW2
@RW3
Register indirect 0
0C
0D
0E
0F
@RW0 +
@RW1 +
@RW2 +
@RW3 +
Register indirect with post-increment 0
10
11
12
13
14
15
16
17
@RW0 + disp8
@RW1 + disp8
@RW2 + disp8
@RW3 + disp8
@RW4 + disp8
@RW5 + disp8
@RW6 + disp8
@RW7 + disp8
Register indirect with 8-bit
displacement
1
18
19
1A
1B
@RW0 + disp16
@RW1 + disp16
@RW2 + disp16
@RW3 + disp16
Register indirect with 16-bit
displacement 2
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
0
0
2
2
MB90580B Series
106
Table 4 Number of Execution Cycles for Each Type of Addressing
Note : “(a)” is used in the “~” (number of states) column and column B (correction v alue) in the tables of instructions.
Table 5 Compensation Values for Number of Cycles Used to Calculate Number of Actual Cycles
Notes: •“(b)”, “(c)”, and “(d)” are used in the “~” (number of states) column and column B (correction value)
in the tables of instructions.
•When the external data bus is used, it is necessary to add in the number of wait cycles used for ready
input and automatic ready.
Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles
Notes: •When the external data bus is used, it is necessary to add in the number of wait cycles used for ready
input and automatic ready.
•Because instruction execution is not slowed down by all program fetches in actuality, these correction
values should be used for “worst case” calculations.
Code Operand (a) Number of register accesses
for each type of addressing
Number of execution cycles
for each type of addressing
00 to 07 Ri
RWi
RLi Listed in tables of instructions Listed in tables of instructions
08 to 0B @RWj 2 1
0C to 0F @RWj + 4 2
10 to 17 @RWi + disp8 2 1
18 to 1B @RWj + disp16 2 1
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
4
4
2
1
2
2
0
0
Operand (b) byte (c) word (d) long
Cycles Access Cycles Access Cycles Access
Internal register +0 1 +0 1 +0 2
Internal memory even address
Internal memory odd address +0
+0 1
1+0
+2 1
2+0
+4 2
4
Even address on external data bus (16 bits)
Odd address on external data bus (16 bits) +1
+1 1
1+1
+4 1
2+2
+8 2
4
External data bus (8 bits) +1 1 +4 2 +8 4
Instruction Byte boundary Word boundary
Internal memory — +2
External data bus (16 bits) — +3
External data bus (8 bits) +3 —
MB90580B Series
107
Table 7 Transfer Instructions (Byte) [41 Instructions]
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW
MOV A, dir
MOV A, addr16
MOV A, Ri
MOV A, ear
MOV A, eam
MOV A, io
MOV A, #imm8
MOV A, @A
MOV A, @RLi+disp8
MOVN A, #imm4
MOVX A, dir
MOVX A, addr16
MOVX A, Ri
MOVX A, ear
MOVX A, eam
MOVX A, io
MOVX A, #imm8
MOVX A, @A
MOVX A,@RWi+disp8
MOVX A, @RLi+disp8
MOV dir, A
MOV addr16, A
MOV Ri, A
MOV ear, A
MOV eam, A
MOV io, A
MOV @RLi+disp8, A
MOV Ri, ear
MOV Ri, eam
MOV ear, Ri
MOV eam, Ri
MOV Ri, #imm8
MOV io, #imm8
MOV dir, #imm8
MOV ear, #imm8
MOV eam, #imm8
MOV @AL, AH
/MOV @A, T
XCH A, ear
XCH A, eam
XCH Ri, ear
XCH Ri, eam
2
3
1
2
2+
2
2
2
3
1
2
3
2
2
2+
2
2
2
2
3
2
3
1
2
2+
2
3
2
2+
2
2+
2
3
3
3
3+
2
2
2+
2
2+
3
4
2
2
3+ (a)
3
2
3
10
1
3
4
2
2
3+ (a)
3
2
3
5
10
3
4
2
2
3+ (a)
3
10
3
4+ (a)
4
5+ (a)
2
5
5
2
4+ (a)
3
4
5+ (a)
7
9+ (a)
0
0
1
1
0
0
0
0
2
0
0
0
1
1
0
0
0
0
1
2
0
0
1
1
0
0
2
2
1
2
1
1
0
0
1
0
0
2
0
4
2
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
0
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
(b)
(b)
0
0
(b)
(b)
(b)
0
(b)
0
(b)
0
(b)
(b)
0
(b)
(b)
0
2× (b)
0
2× (b)
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
by te (A) ← ((RLi)+disp8)
byte (A) ← imm4
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
b yte (A) ← ((R Wi)+disp8)
by te (A) ← ((RLi)+disp8)
byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte ((RLi) +disp8) ← (A)
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
byte ((A)) ← (AH)
byte (A) ↔ (ear)
byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
byte (Ri) ↔ (eam)
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Z
Z
–
–
*
*
*
*
*
*
*
–
*
*
*
*
*
*
*
*
*
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
R
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
*
–
*
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MB90580B Series
108
Table 8 Transfer Instructions (Word/Long Word) [38 Instructions]
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Mnemonic # ~ RG BOperation
LH AH I S T N Z V C RMW
MOVW A, dir
MOVW A, addr16
MOVW A, SP
MOVW A, RWi
MOVW A, ear
MOVW A, eam
MOVW A, io
MOVW A, @A
MOVW A, #imm16
MOVW A, @RWi+disp8
MOVW A, @RLi+disp8
MOVW dir, A
MOVW addr16, A
MOVW SP, A
MOVW RWi, A
MOVW ear, A
MOVW eam, A
MOVW io, A
MOVW @RWi+disp8, A
MOVW @RLi+disp8, A
MOVW RWi, ear
MOVW RWi, eam
MOVW ear, RWi
MOVW eam, RWi
MOVW RWi, #imm16
MOVW io, #imm16
MOVW ear, #imm16
MOVW eam, #imm16
MOVW @AL, AH
/MOVW@A, T
XCHW A, ear
XCHW A, eam
XCHW RWi, ear
XCHW RWi, eam
2
3
1
1
2
2+
2
2
3
2
3
2
3
1
1
2
2+
2
2
3
2
2+
2
2+
3
4
4
4+
2
2
2+
2
2+
3
4
1
2
2
3+ (a)
3
3
2
5
10
3
4
1
2
2
3+ (a)
3
5
10
3
4+ (a)
4
5+ (a)
2
5
2
4+ (a)
3
4
5+ (a)
7
9+ (a)
0
0
0
1
1
0
0
0
0
1
2
0
0
0
1
1
0
0
1
2
2
1
2
1
1
0
1
0
0
2
0
4
2
(c)
(c)
0
0
0
(c)
(c)
(c)
0
(c)
(c)
(c)
(c)
0
0
0
(c)
(c)
(c)
(c)
(0)
(c)
0
(c)
0
(c)
0
(c)
(c)
0
2× (c)
0
2× (c)
word (A) ← (dir)
word (A) ← (addr16)
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← (io)
word (A) ← ((A))
word (A) ← imm16
word (A) ← ((RWi) +disp8)
word (A) ← ((RLi) +disp8)
word (dir) ← (A)
word (addr16) ← (A)
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
word (eam) ← (A)
word (io) ← (A)
word ((RWi) +disp8) ← (A)
word ((RLi) +disp8) ← (A)
word (RWi) ← (ear)
word (RWi) ← (eam)
word (ear) ← (RWi)
word (eam) ← (RWi)
word (RWi) ← imm16
word (io) ← imm16
word (ear) ← imm16
word (eam) ← imm16
word ((A)) ← (AH)
word (A) ↔ (ear)
word (A) ↔ (eam)
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
–
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
*
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVL A, ear
MOVL A, eam
MOVL A, #imm32
MOVL ear, A
MOVL eam, A
2
2+
5
2
2+
4
5+ (a)
3
4
5+ (a)
2
0
0
2
0
0
(d)
0
0
(d)
long (A) ← (ear)
long (A) ← (eam)
long (A) ← imm32
long (ear) ← (A)
long (eam) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MB90580B Series
109
Table 9 Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions]
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Mnemonic # ~ RG BOperation
LH AH I S T N Z V C RMW
ADD A,#imm8
ADD A, dir
ADD A, ear
ADD A, eam
ADD ear, A
ADD eam, A
ADDC A
ADDC A, ear
ADDC A, eam
ADDDC A
SUB A, #imm8
SUB A, dir
SUB A, ear
SUB A, eam
SUB ear, A
SUB eam, A
SUBC A
SUBC A, ear
SUBC A, eam
SUBDC A
2
2
2
2+
2
2+
1
2
2+
1
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4+ (a)
3
5+ (a)
2
3
4+ (a)
3
2
5
3
4+ (a)
3
5+ (a)
2
3
4+ (a)
3
0
0
1
0
2
0
0
1
0
0
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2× (b)
0
0
(b)
0
0
(b)
0
(b)
0
2× (b)
0
0
(b)
0
byte (A) ← (A) +imm8
byte (A) ← (A) +(dir)
byte (A) ← (A) +(ear)
byte (A) ← (A) +(eam)
byte (ear) ← (ear) + (A)
byte (eam) ← (eam) + (A)
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear) + (C)
byte (A) ← (A) + (eam) + (C)
byte (A) ← (AH) + (AL) + (C) (decimal)
byte (A) ← (A) –imm8
byte (A) ← (A) – (dir)
byte (A) ← (A) – (ear)
byte (A) ← (A) – (eam)
byte (ear) ← (ear) – (A)
byte (eam) ← (eam) – (A)
byte (A) ← (AH) – (AL) – (C)
byte (A) ← (A) – (ear) – (C)
byte (A) ← (A) – (eam) – (C)
byte (A) ← (AH) – (AL) – (C) (decimal)
Z
Z
Z
Z
–
Z
Z
Z
Z
Z
Z
Z
Z
Z
–
–
Z
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
*
–
–
–
–
ADDW A
ADDW A, ear
ADDW A, eam
ADDW A, #imm16
ADDW ear, A
ADDW eam, A
ADDCWA, ear
ADDCWA, eam
SUBW A
SUBW A, ear
SUBW A, eam
SUBW A, #imm16
SUBW ear, A
SUBW eam, A
SUBCWA, ear
SUBCWA, eam
1
2
2+
3
2
2+
2
2+
1
2
2+
3
2
2+
2
2+
2
3
4+ (a)
2
3
5+ (a)
3
4+ (a)
2
3
4+ (a)
2
3
5+ (a)
3
4+ (a)
0
1
0
0
2
0
1
0
0
1
0
0
2
0
1
0
0
0
(c)
0
0
2× (c)
0
(c)
0
0
(c)
0
0
2× (c)
0
(c)
word (A) ← (AH) + (AL)
word (A) ← (A) +(ear)
word (A) ← (A) +(eam)
word (A) ← (A) +imm16
word (ear) ← (ear) + (A)
word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)
word (A) ← (A) + (eam) + (C)
word (A) ← (AH) – (AL)
word (A) ← (A) – (ear)
word (A) ← (A) – (eam)
word (A) ← (A) –imm16
word (ear) ← (ear) – (A)
word (eam) ← (eam) – (A)
word (A) ← (A) – (ear) – (C)
word (A) ← (A) – (eam) – (C)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
–
–
–
–
–
–
*
–
–
ADDL A, ear
ADDL A, eam
ADDL A, #imm32
SUBL A, ear
SUBL A, eam
SUBL A, #imm32
2
2+
5
2
2+
5
6
7+ (a)
4
6
7+ (a)
4
2
0
0
2
0
0
0
(d)
0
0
(d)
0
long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) +imm32
long (A) ← (A) – (ear)
long (A) ← (A) – (eam)
long (A) ← (A) –imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
MB90580B Series
110
Tabl e 10 Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions]
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 11 Compare Instructions (Byte/Word/Long Word) [11 Instructions]
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW
INC ear
INC eam
DEC ear
DEC eam
2
2+
2
2+
2
5+ (a)
3
5+ (a)
2
0
2
0
0
2× (b)
0
2× (b)
byte (ear) ← (ear) +1
byte (eam) ← (eam) +1
byte (ear) ← (ear) –1
byte (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
*
INCW ear
INCW eam
DECW ear
DECW eam
2
2+
2
2+
3
5+ (a)
3
5+ (a)
2
0
2
0
0
2× (c)
0
2× (c)
word (ear) ← (ear) +1
word (eam) ← (eam) +1
word (ear) ← (ear) –1
word (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
*
INCL ear
INCL eam
DECL ear
DECL eam
2
2+
2
2+
7
9+ (a)
7
9+ (a)
4
0
4
0
0
2× (d)
0
2× (d)
long (ear) ← (ear) +1
long (eam) ← (eam) +1
long (ear) ← (ear) –1
long (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
*
Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW
CMP A
CMP A, ear
CMP A, eam
CMP A, #imm8
1
2
2+
2
1
2
3+ (a)
2
0
1
0
0
0
0
(b)
0
byte (AH) – (AL)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPW A
CMPW A, ear
CMPW A, eam
CMPW A, #imm16
1
2
2+
3
1
2
3+ (a)
2
0
1
0
0
0
0
(c)
0
word (AH) – (AL)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPL A, ear
CMPL A, eam
CMPL A, #imm32
2
2+
5
6
7+ (a)
3
2
0
0
0
(d)
0
word (A) ← (ear)
word (A) ← (eam)
word (A) ← imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
MB90580B Series
111
Table 12 Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions]
*1: 3 when the result is zero, 7 when an overflow occurs, and 15 normally.
*2: 4 when the result is zero, 8 when an overflow occurs, and 16 normally.
*3: 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally.
*4: 4 when the result is zero, 7 when an overflow occurs, and 22 normally.
*5: 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally.
*6: (b) when the result is zero or when an overflow occurs, and 2 × (b) normally.
*7: (c) when the result is zero or when an overflow occurs, and 2 × (c) normally.
*8: 3 when byte (AH) is zero, and 7 when byte (AH) is not zero.
*9: 4 when byte (ear) is zero, and 8 when byte (ear) is not zero.
*10: 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0.
*11: 3 when word (AH) is zero, and 11 when word (AH) is not zero.
*12: 4 when word (ear) is zero, and 12 when word (ear) is not zero.
*13: 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW
DIVU A
DIVU A, ear
DIVU A, eam
DIVUW A, ear
DIVUW A, eam
MULU A
MULU A, ear
MULU A, eam
MULUW A
MULUW A, ear
MULUW A, eam
1
2
2+
2
2+
1
2
2+
1
2
2+
*1
*2
*3
*4
*5
*8
*9
*10
*11
*12
*13
0
1
0
1
0
0
1
0
0
1
0
0
0
*6
0
*7
0
0
(b)
0
0
(c)
word (AH) /byte (AL)
Quotient → byte (AL) Remainder → byte (AH)
word (A)/byte (ear)
Quotient → byte (A) Remainder → byte (ear)
word (A)/byte (eam)
Quotient → byte (A) Remainder → byte (eam)
long (A)/word (ear)
Quotient → word (A) Remainder → word (ear)
long (A)/word (eam)
Quotient → word (A) Remainder → word (ear)
byte (AH) *byte (AL) → word (A)
b yte (A) *byte (ear) → word (A)
byte (A) *byte (eam) → word (A)
word (AH) *word (AL) → long (A)
word (A) *word (ear) → long (A)
word (A) *word (eam) → long (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
–
–
–
–
–
–
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MB90580B Series
112
Table 13 Signed Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions]
*1: Set to 3 when the division-by-0, 8 or 18 for an overflow, and 18 for normal operation.
*2: Set to 3 when the division-by-0, 10 or 21 for an overflow, and 22 for normal operation.
*3: Set to 4 + (a) when the division-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation.
*4: Positive dividend: Set to 4 when the division-by-0, 10 or 29 for an overflow, and 30 for normal operation.
Negative dividend: Set to 4 when the division-by-0, 11 or 30 for an overflow and 31 for normal operation.
*5: Positive dividend:Set to 4 + (a) when the division-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for
normal operation.
Negative dividend:Set to 4 + (a) when the division-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for
normal operation.
*6: When the division-by-0, (b) for an overflow, and 2 × (b) for normal operation.
*7: When the division-by-0, (c) for an overflow, and 2 × (c) for normal operation.
*8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative.
*10: Set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative.
*11: Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*12: Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative.
*13: Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is
negative.
Notes: • When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes
two values because of detection before and after an operation.
• When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed.
• For (a) to (d), refer to “Table 4 Number of Execution Cycles for Effective Address in Addressing Modes”
and “Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles.”
Mnemonic # ~ RG BOperation
LH AH I S T N Z V C RMW
DIV A
DIV A, ear
DIV A, eam
DIVW A, ear
DIVW A, eam
MULU A
MULU A, ear
MULU A, eam
MULUW A
MULUW A, ear
MULUW A, eam
2
2
2 +
2
2+
2
2
2 +
2
2
2 +
*1
*2
*3
*4
*5
*8
*9
*10
*11
*12
*13
0
1
0
1
0
0
1
0
0
1
0
0
0
*6
0
*7
0
0
(b)
0
0
(c)
word (AH) /byte (AL)
Quotient → byte (AL)
Remainder → byte (AH)
word (A)/byte (ear)
Quotient → byte (A)
Remainder → byte (ear)
word (A)/byte (eam)
Quotient → byte (A)
Remainder → byte (eam)
long (A)/word (ear)
Quotient → word (A)
Remainder → word (ear)
long (A)/word (eam)
Quotient → word (A)
Remainder → word (eam)
byte (AH) *byte (AL) → word (A)
byte (A) *byte (ear) → word (A)
byte (A) *byte (eam) → word (A)
word (AH) *word (AL) → long (A)
word (A) *word (ear) → long (A)
word (A) *word (eam) → long (A)
Z
Z
Z
–
–
–
–
–
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*
*
*
*
*
–
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*
*
*
*
*
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MB90580B Series
113
Table 14 Logical 1 Instructions (Byte/Word) [39 Instructions]
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW
AND A, #imm8
AND A, ear
AND A, eam
AND ear, A
AND eam, A
OR A, #imm8
OR A, ear
OR A, eam
OR ear, A
OR eam, A
XOR A, #imm8
XOR A, ear
XOR A, eam
XOR ear, A
XOR eam, A
NOT A
NOT ear
NOT eam
2
2
2+
2
2+
2
2
2+
2
2+
2
2
2+
2
2+
1
2
2+
2
3
4+ (a)
3
5+ (a)
2
3
4+ (a)
3
5+ (a)
2
3
4+ (a)
3
5+ (a)
2
3
5+ (a)
0
1
0
2
0
0
1
0
2
0
0
1
0
2
0
0
2
0
0
0
(b)
0
2× (b)
0
0
(b)
0
2× (b)
0
0
(b)
0
2× (b)
0
0
2× (b)
byte (A) ← (A) and imm8
byte (A) ← (A) and (ear)
byte (A) ← (A) and (eam)
byte (ear) ← (ear) and (A)
byte (eam) ← (eam) and (A)
byte (A) ← (A) or imm8
byte (A) ← (A) or (ear)
byte (A) ← (A) or (eam)
byte (ear) ← (ear) or (A)
byte (eam) ← (eam) or (A)
byte (A) ← (A) xor imm8
byte (A) ← (A) xor (ear)
byte (A) ← (A) xor (eam)
byte (ear) ← (ear) xor (A)
byte (eam) ← (eam) xor (A)
byte (A) ← not (A)
byte (ear) ← not (ear)
byte (eam) ← not (eam)
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*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
–
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*
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*
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*
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*
ANDW A
ANDW A, #imm16
ANDW A, ear
ANDW A, eam
ANDW ear, A
ANDW eam, A
ORW A
ORW A, #imm16
ORW A, ear
ORW A, eam
ORW ear, A
ORW eam, A
XORW A
XORW A, #imm16
XORW A, ear
XORW A, eam
XORW ear, A
XORW eam, A
NOTW A
NOTW ear
NOTW eam
1
3
2
2+
2
2+
1
3
2
2+
2
2+
1
3
2
2+
2
2+
1
2
2+
2
2
3
4+ (a)
3
5+ (a)
2
2
3
4+ (a)
3
5+ (a)
2
2
3
4+ (a)
3
5+ (a)
2
3
5+ (a)
0
0
1
0
2
0
0
0
1
0
2
0
0
0
1
0
2
0
0
2
0
0
0
0
(c)
0
2× (c)
0
0
0
(c)
0
2× (c)
0
0
0
(c)
0
2× (c)
0
0
2× (c)
word (A) ← (AH) and (A)
word (A) ← (A) and imm16
word (A) ← (A) and (ear)
word (A) ← (A) and (eam)
word (ear) ← (ear) and (A)
word (eam) ← (eam) and (A)
word (A) ← (AH) or (A)
word (A) ← (A) or imm16
word (A) ← (A) or (ear)
word (A) ← (A) or (eam)
word (ear) ← (ear) or (A)
word (eam) ← (eam) or (A)
word (A) ← (AH) xor (A)
word (A) ← (A) xor imm16
word (A) ← (A) xor (ear)
word (A) ← (A) xor (eam)
word (ear) ← (ear) xor (A)
word (eam) ← (eam) xor (A)
word (A) ← not (A)
word (ear) ← not (ear)
word (eam) ← not (eam)
–
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–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
–
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*
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*
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*
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*
MB90580B Series
114
Table 15 Logical 2 Instructions (Long Word) [6 Instructions]
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 16 Sign Inversion Instructions (Byte/Word) [6 Instructions]
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 17 Normalize Instruction (Long Word) [1 Instruction]
*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count).
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Mnemonic # ~ RG BOperation
LH AH I S T N Z V C RMW
ANDL A, ear
ANDL A, eam
ORL A, ear
ORL A, eam
XORL A, ea
XORL A, eam
2
2+
2
2+
2
2+
6
7+ (a)
6
7+ (a)
6
7+ (a)
2
0
2
0
2
0
0
(d)
0
(d)
0
(d)
long (A) ← (A) and (ear)
long (A) ← (A) and (eam)
long (A) ← (A) or (ear)
long (A) ← (A) or (eam)
long (A) ← (A) xor (ear)
long (A) ← (A) xor (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
–
Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW
NEG A
NEG ear
NEG eam
1
2
2+
2
3
5+ (a)
0
2
0
0
0
2× (b)
byte (A) ← 0 – (A)
byte (ear) ← 0 – (ear)
byte (eam) ← 0 – (eam)
X
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
*
NEGW A
NEGW ear
NEGW eam
1
2
2+
2
3
5+ (a)
0
2
0
0
0
2× (c)
word (A) ← 0 – (A)
word (ear) ← 0 – (ear)
word (eam) ← 0 – (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
*
Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW
NRML A, R0 2 *11 0 long (A) ← Shift until first digit is “1”
byte (R0) ← Current shift count ––––––*–– –
MB90580B Series
115
Table 18 Shift Instructions (Byte/Word/Long Word) [18 Instructions]
*1: 6 when R0 is 0, 5 + (R0) in all other cases.
*2: 6 when R0 is 0, 6 + (R0) in all other cases.
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Mnemonic # ~ RG BOperation
LH AH I S T N Z V C RMW
RORC A
ROLC A
RORC ear
RORC eam
ROLC ear
ROLC eam
ASR A, R0
LSR A, R0
LSL A, R0
2
2
2
2+
2
2+
2
2
2
2
2
3
5+ (a)
3
5+ (a)
*1
*1
*1
0
0
2
0
2
0
1
1
1
0
0
0
2× (b)
0
2× (b)
0
0
0
byte (A) ← Right rotation with carry
byte (A) ← Left rotation with carry
byte (ear) ← Right rotation with carry
byte (eam) ← Right rotation with carry
byte (ear) ← Left rotation with carry
byte (eam) ← Left rotation with carry
byte (A) ← Arithmetic right barrel shift (A, R0)
byte (A) ← Logical right barrel shift (A, R0)
byte (A) ← Logical left barrel shift (A, R0)
–
–
–
–
–
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–
–
*
*
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
–
–
–
*
–
*
–
–
–
ASRWA
LSR W A/SHRW A
LSLW A/SHL W A
ASRWA, R0
LSRW A, R0
LSLW A, R0
1
1
1
2
2
2
2
2
2
*1
*1
*1
0
0
0
1
1
1
0
0
0
0
0
0
word (A) ← Arithmetic right shift (A, 1 bit)
word (A) ← Logical right shift (A, 1 bit)
word (A) ← Logical left shift (A, 1 bit)
word (A) ← Arithmetic right barrel shift (A,
R0)
word (A) ← Logical right barrel shift (A, R0)
word (A) ← Logical left barrel shift (A, R0)
–
–
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–
–
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–
–
–
–
–
–
–
–
*
*
–
*
*
–
*
R
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
ASRL A, R0
LSRL A, R0
LSLL A, R0
2
2
2
*2
*2
*2
1
1
1
0
0
0
long (A) ← Arithmetic right shift (A, R0)
long (A) ← Logical right barrel shift (A, R0)
long (A) ← Logical left barrel shift (A, R0)
–
–
–
–
–
–
–
–
–
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–
*
*
–
*
*
*
*
*
*
–
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*
*
*
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–
MB90580B Series
116
Table 19 Branch 1 Instructions [31 Instructions]
*1: 4 when branching, 3 when not branching.
*2: (b) + 3 × (c)
*3: Read (word) branch address.
*4: W: Save (word) to stack; R: read (word) branch address.
*5: Save (word) to stack.
*6: W: Save (long word) to W stack; R: read (long word) R branch address.
*7: Save (long word) to stack.
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Mnemonic # ~ RG BOperation
LH AH I S T N Z V C RMW
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BV rel
BNV rel
BT rel
BNT rel
BLT rel
BGE rel
BLE rel
BGT rel
BLS rel
BHI rel
BRA rel
JMP @A
JMP addr16
JMP @ear
JMP @eam
JMPP @ear *3
JMPP @eam *3
JMPP addr24
CALL @ear *4
CALL @eam *4
CALL addr16 *5
CALLV #vct4 *5
CALLP @ear *6
CALLP @eam *6
CALLP addr24 *7
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
3
2
2+
2
2+
4
2
2+
3
1
2
2+
4
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
2
3
3
4+ (a)
5
6+ (a)
4
6
7+ (a)
6
7
10
11+ (a)
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
2
0
0
1
0
0
0
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(c)
0
(d)
0
(c)
2× (c)
(c)
2× (c)
2× (c)
*2
2× (c)
Branch when (Z) = 1
Branch when (Z) = 0
Branch when (C) = 1
Branch when (C) = 0
Branch when (N) = 1
Branch when (N) = 0
Branch when (V) = 1
Branch when (V) = 0
Branch when (T) = 1
Branch when (T) = 0
Branch when (V) xor (N) = 1
Branch when (V) xor (N) = 0
Branch when ((V) xor (N)) or (Z) = 1
Branch when ((V) xor (N)) or (Z) = 0
Branch when (C) or (Z) = 1
Branch when (C) or (Z) = 0
Branch unconditionally
word (PC) ← (A)
word (PC) ← addr16
word (PC) ← (ear)
word (PC) ← (eam)
word (PC) ← (ear), (PCB) ← (ear +2)
word (PC) ← (eam), (PCB) ← (eam +2)
word (PC) ← ad24 0 to 15,
(PCB) ← ad24 16 to 23
word (PC) ← (ear)
word (PC) ← (eam)
word (PC) ← addr16
Vector call instruction
word (PC) ← (ear) 0 to 15,
(PCB) ← (ear) 16 to 23
word (PC) ← (eam) 0 to 15,
(PCB) ← (eam) 16 to 23
word (PC) ← addr0 to 15,
(PCB) ← addr16 to 23
–
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MB90580B Series
117
Table 20 Branch 2 Instructions [19 Instructions]
*1: 5 when branching, 4 when not branching
*2: 13 when branching, 12 when not branching
*3: 7 + (a) when branching, 6 + (a) when not branching
*4: 8 when branching, 7 when not branching
*5: 7 when branching, 6 when not branching
*6: 8 + (a) when branching, 7 + (a) when not branching
*7: Set to 3 × (b) + 2 × (c) when an interrupt request occurs, and 6 × (c) for return.
*8: Retrieve (word) from stack
*9: Retrieve (long word) from stack
*10: In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode.
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Mnemonic # ~ RG BOperation
LH AH I S T N Z V C RMW
CBNE A, #imm8, rel
CWBNEA, #imm16, rel
CBNE ear, #imm8, rel
CBNE eam, #imm8, rel*10
CWBNEear, #imm16, rel
CWBNE eam, #imm16, rel*10
DBNZ ear, rel
DBNZ eam, rel
DWBNZ ear, rel
DWBNZ eam, rel
INT #vct8
INT addr16
INTP addr24
INT9
RETI
LINK #local8
UNLINK
RET *8
RETP *9
3
4
4
4+
5
5+
3
3+
3
3+
2
3
4
1
1
2
1
1
1
*1
*1
*2
*3
*4
*3
*5
*6
*5
*6
20
16
17
20
15
6
5
4
6
0
0
1
0
1
0
2
2
2
2
0
0
0
0
0
0
0
0
0
0
0
0
(b)
0
(c)
0
2× (b)
0
2× (c)
8× (c)
6× (c)
6× (c)
8× (c)
*7
(c)
(c)
(c)
(d)
Branch when byte (A) ≠ imm8
Branch when word (A) ≠ imm16
Branch when byte (ear) ≠ imm8
Branch when b yte (eam) ≠ imm8
Branch when word (ear) ≠ imm16
Branch when word (eam) ≠ imm16
Branch when byte (ear) =
(ear) – 1, and (ear) ≠ 0
Branch when byte (eam) =
(eam) – 1, and (eam) ≠ 0
Branch when word (ear) =
(ear) – 1, and (ear) ≠ 0
Branch when word (eam) =
(eam) – 1, and (eam) ≠ 0
Software interrupt
Software interrupt
Software interrupt
Software interrupt
Return from interrupt
At constant entry, save old
frame pointer to stack, set
new frame pointer, and
allocate local pointer area
At constant entry, retriev e old
frame pointer from stack.
Return from subroutine
Return from subroutine
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R
R
R
R
*
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S
S
S
S
*
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*
*
*
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*
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*
*
*
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*
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*
*
*
*
*
*
*
*
*
*
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*
*
*
*
*
*
*
*
*
*
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*
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*
*
*
*
*
*
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*
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MB90580B Series
118
Tabl e 21 Other Control Instructions (Byte/Word/Long Word) [28 Instructions]
*1: PCB, ADB, SSB, USB, and SPB : 1 state
DTB, DPR : 2 states
*2: 7 + 3 × (pop count) + 2 × (last register number to be popped), 7 when rlst = 0 (no transfer register)
*3: 29 + (push count) – 3 × (last register number to be pushed), 8 when rlst = 0 (no transfer register)
*4: Pop count × (c), or push count × (c)
*5: Pop count or push count.
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW
PUSHW A
PUSHW AH
PUSHW PS
PUSHW rlst
POPW A
POPW AH
POPW PS
POPW rlst
JCTX @A
AND CCR, #imm8
OR CCR, #imm8
MOV RP, #imm8
MOV ILM, #imm8
MOVEA RWi, ear
MOVEA RWi, eam
MOVEA A, ear
MOVEA A, eam
ADDSP #imm8
ADDSP #imm16
MOV A, brgl
MOV brg2, A
NOP
ADB
DTB
PCB
SPB
NCC
CMR
1
1
1
2
1
1
1
2
1
2
2
2
2
2
2+
2
2+
2
3
2
2
1
1
1
1
1
1
1
4
4
4
*3
3
3
4
*2
14
3
3
2
2
3
2+ (a)
1
1+ (a)
3
3
*1
1
1
1
1
1
1
1
1
0
0
0
*5
0
0
0
*5
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
(c)
(c)
(c)
*4
(c)
(c)
(c)
*4
6× (c)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
word (SP) ← (SP) –2, ((SP)) ← (A)
word (SP) ← (SP) –2, ((SP)) ← (AH)
word (SP) ← (SP) –2, ((SP)) ← (PS)
(SP) ← (SP) –2n, ((SP)) ← (rlst)
word (A) ← ((SP)), (SP) ← (SP) +2
word (AH) ← ((SP)), (SP) ← (SP) +2
word (PS) ← ((SP)), (SP) ← (SP) +2
(rlst) ← ((SP)), (SP) ← (SP) +2n
Context switch instruction
byte (CCR) ← (CCR) and imm8
byte (CCR) ← (CCR) or imm8
byte (RP) ←imm8
byte (ILM) ←imm8
word (RWi) ←ear
word (R Wi) ←eam
word(A) ←ear
word (A) ←eam
word (SP) ← (SP) +ext (imm8)
word (SP) ← (SP) +imm16
byte (A) ← (brgl)
byte (brg2) ← (A)
No operation
Prefix code for accessing AD space
Prefix code for accessing DT space
Prefix code for accessing PC space
Prefix code for accessing SP space
Prefix code for no flag change
Prefix code for common register bank
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Z
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*
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*
*
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*
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*
*
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*
*
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MB90580B Series
119
Tabl e 22 Bit Manipulation Instructions [21 Instructions]
*1: 8 when branching, 7 when not branching
*2: 7 when branching, 6 when not branching
*3: 10 when condition is satisfied, 9 when not satisfied
*4: Undefined count
*5: Until condition is satisfied
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 23 Accumulator Manipulation Instructions (Byte/Word) [6 Instructions]
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW
MOVB A, dir:bp
MOVB A, addr16:bp
MOVB A, io:bp
MOVB dir:bp, A
MOVB addr16:bp, A
MOVB io:bp, A
SETB dir:bp
SETB addr16:bp
SETB io:bp
CLRB dir:bp
CLRB addr16:bp
CLRB io:bp
BBC dir:bp, rel
BBC addr16:bp, rel
BBC io:bp, rel
BBS dir:bp , rel
BBS addr16:bp, rel
BBS io:bp, rel
SBBS addr16:bp, rel
WBTS io:bp
WBTC io:bp
3
4
3
3
4
3
3
4
3
3
4
3
4
5
4
4
5
4
5
3
3
5
5
4
7
7
6
7
7
7
7
7
7
*1
*1
*2
*1
*1
*2
*3
*4
*4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(b)
(b)
(b)
2× (b)
2× (b)
2× (b)
2× (b)
2× (b)
2× (b)
2× (b)
2× (b)
2× (b)
(b)
(b)
(b)
(b)
(b)
(b)
2× (b)
*5
*5
byte (A) ← (dir:bp) b
byte (A) ← (addr16:bp) b
byte (A) ← (io:bp) b
bit (dir:bp) b ← (A)
bit (addr16:bp) b ← (A)
bit (io:bp) b ← (A)
bit (dir:bp) b ← 1
bit (addr16:bp) b ← 1
bit (io:bp) b ← 1
bit (dir:bp) b ← 0
bit (addr16:bp) b ← 0
bit (io:bp) b ← 0
Branch when (dir:bp) b = 0
Branch when (addr16:bp) b = 0
Branch when (io:bp) b = 0
Branch when (dir:bp) b = 1
Branch when (addr16:bp) b = 1
Branch when (io:bp) b = 1
Branch when (addr16:bp) b = 1, bit = 1
Wait until (io:bp) b = 1
Wait until (io:bp) b = 0
Z
Z
Z
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*
*
*
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*
*
*
*
*
*
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*
*
*
*
*
*
*
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*
*
*
*
*
*
*
*
*
–
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–
–
–
–
*
–
–
Mnemonic # ~ RG BOperationLH AH I S T N Z V C RMW
SWAP
SWAPW
EXT
EXTW
ZEXT
ZEXTW
1
1
1
1
1
1
3
2
1
2
1
1
0
0
0
0
0
0
0
0
0
0
0
0
byte (A) 0 to 7 ↔ (A) 8 to 15
word ( AH) ↔ (AL)
byte sign extension
word sign extension
byte zero extension
word zero extension
–
–
X
–
Z
–
–
*
–
X
–
Z
–
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*
*
R
R
–
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*
*
*
*
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MB90580B Series
Table 24 String Instructions [10 Instructions]
m: RW0 value (counter value)
n: Loop count
*1: 5 when RW0 is 0, 4 + 7 × (RW0) for count out, and 7 × n + 5 when match occurs
*2: 5 when RW0 is 0, 4 + 8 × (RW0) in any other case
*3: (b) × (RW0) + (b) × (RW0) when accessing different areas for the source and destination, calculate (b) sepa-
rately for each.
*4: (b) × n
*5: 2 × (RW0)
*6: (c) × (RW0) + (c) × (RW0) when accessing different areas for the source and destination, calculate (c)
separately for each.
*7: (c) × n
*8: 2 × (RW0)
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Mnemonic # ~ RG BOperationLH AH I S T N Z V C RMW
MOVS/MOVSI
MOVSD
SCEQ/SCEQI
SCEQD
FISL/FILSI
2
2
2
2
2
*2
*2
*1
*1
6m +6
*5
*5
*5
*5
*5
*3
*3
*4
*4
*3
Byte transfer @AH+ ← @AL+, counter = R W0
Byte transfer @AH– ← @AL–, counter = R W0
Byte retrieval (@AH+) – AL, counter = R W0
Byte retrieval (@AH–) – AL, counter = R W0
Byte filling @AH+ ← AL, counter = RW0
–
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*
*
*
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–
*
*
*
–
–
*
*
–
–
–
*
*
–
–
–
–
–
–
MOVSW/MOVSWI
MOVSWD
SCWEQ/SCWEQI
SCWEQD
FILSW/FILSWI
2
2
2
2
2
*2
*2
*1
*1
6m +6
*8
*8
*8
*8
*8
*6
*6
*7
*7
*6
Word transfer @AH+ ← @AL+, counter = RW0
Word transfer @AH– ← @AL–, counter = RW0
W ord retrieval (@AH+) – AL, counter = R W0
W ord retrieval (@AH–) – AL, counter = R W0
Word filling @AH+ ← AL, counter = RW0
–
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*
*
*
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*
*
*
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*
*
–
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*
*
–
–
–
–
–
–
MB90580B Series
121
■ORDERING INFORMATION
Part number Package Remarks
MB90F583BPFV
MB90583BPFV
MB90587PFV
100-pin Plastic LQFP
(FPT-100P-M05)
MB90F583BPF
MB90583BPF
MB90587PF
100-pin Plastic QFP
(FPT-100P-M06)
MB90580B Series
122
■PACKAGE DIMENSIONS
* : The external dimensions show here are for reference only.
For official dimensions, contact a FUJITSU representative.
100-pin plastic LQFP
(FPT-100P-M05)
C
1995 FUJITSU LIMITED F100007S-2C-3
Details of "B" part
16.00±0.20(.630±.008)SQ
14.00±0.10(.551±.004)SQ
0.50(.0197)TYP .007 –.001
+.003
–0.03
+0.08
0.18
INDEX
0.10(.004)
0.08(.003) M
.059 –.004
+.008
–0.10
+0.20
1.50
.005 –.001
+.002
–0.02
+0.05
0.127
15.0012.00
(.472)
REF (.591)
NOM
"B"
"A" 25
26
1
100
75 51
5076
0.50±0.20(.020±.008)
Details of "A" part
0.40(.016)MAX
0.15(.006)MAX
0.15(.006)
0.15(.006)
0.10±0.10
(.004±.004) (STAND OFF)
0~10°
LEAD No.
(Mouting height)
Dimensions in mm (inches)
MB90580B Series
123
* : The external dimensions show here are for reference only.
For official dimensions, contact a FUJITSU representative.
100-pin plastic QFP
(FPT-100P-M06)
C
1994 FUJITSU LIMITED F100008-3C-2
"A"
"B"
0.10(.004)
0.53(.021)MAX
0.18(.007)MAX
Details of "A" part
0 10°
Details of "B" part
12.35(.486)
REF 16.30±0.40
(.642±.016)
0.05(.002)MIN
(STAND OFF)
0.15±0.05(.006±.002)
INDEX
23.90±0.40(.941±.016)
20.00±0.20(.787±.008)
17.90±0.4014.00±0.20
(.551±.008) (.705±.016)
0.13(.005) M
18.85(.742)REF
22.30±0.40(.878±.016)
130
31
50
5180
81
100
0.25(.010)
0.30(.012)
0.65(.0256)TYP 0.30±0.10
(.012±.004)
LEAD No.
0.80±0.20
(.031±.008)
3.35(.132)MAX
(Mounting height)
Dimensions in mm (inches)
MB90580B Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka,
Nakahara-ku, Kawasaki-shi,
Kanagawa 211-8588, Japan
Tel: +81-44-754-3763
Fax: +81-44-754-3329
http://www.fujitsu.co.jp/
Nor th and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, USA
Tel: +1-408-922-9000
Fax: +1-408-922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: +1-800-866-8608
Fax: +1-408-922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTRONICS EUR OPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific
FUJITSU MICROELECTR ONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmap.com.sg/
F0002
FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without
notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipments, industrial, communications, and
measurement equipments, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded
(such as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.
