CONFIDENTIAL DRAFT/ADVANCE
SLDRAM HYSL8M18D600A
CONSORTIUM 8 MEG x 18 SLDRAM
8M x 18 SLDRAM 1 HYUNDAI Electronics Confidential
Rev. 12/20/97 ¨¸1997, SLDRAM Consortium
600 Mb/s/pin 8M x 18 SLDRAM
SLDRAM
FEATURES
¡Ü Very High Speed - 600MHz data rate
¡Ü 1.2 GB/s peak I/O Bandwidth - provides very high
bandwidth over narrow system memory bus
¡Ü Pipelined (Concurrent) operation - Up to 8
transaction (in one bank, or spread across
multiple banks)
¡Ü Eight (this data sheet) or more internal banks for
hiding row access/precharge
¡Ü Programmable burst lengths of 4 or 8
100% peak bandwidth sustainable over random
row as well as random column access, even with
8 byte bursts.
¡Ü Packet Oriented Protocol - Provided pin `
compatibility access multiple densities.
¡Ü Auto Refresh and Self Refresh
¡Ü Command Clock for commands and addresses;
Bidirectional Data Clocks for read and write data
¡Ü Dual Data Clocks provide smooth handoff from
one data source to another
¡Ü Programmable Offset between Data and Data
Clocks
¡Ü Programmable Read Delays - Adjustable in
coarse increments equal to one data bit time, and
fine increments which are a fraction of a bit time;
allows for specific temporal placement of data at
the memory controller data pins
¡Ü Programmable Write Delays - Adjustable in
coarse increments equal to one data bit time.
Allows for optimally adjusted write data placement
by the memory controller
¡Ü Supports bank accesses (bank initially idle) and
page accesses (bank active, row open)
¡Ü 128ms, 16K-cycle refresh
¡Ü SLIO Interface Technology -
Drivers: calibrated VOH and VOL levels,
Receivers: narrow set-up and hold windows
¡Ü Single +2.5V ± 5% power supply
OPTIONS MARKING
¡Ü Timing
600MHz data rate -600
¡Ü Plastic Package
64-pin VSMP (400mil width, .4 / .8 mm pitch) VS
¡Ü Part Number Example: HYSL4M18DR600A
VDD
VSS
TEST
RESET
VSS
VDDQ
DQ17
LINKON
VSS
VDD
LISTEN
VSSQ
DQ0
DQ2
DQ4
VSSQ
DQ1
DQ6
DQ3
VDDQ
DQ5
DQ7
DCLK0
DCLK1
CCLK
CA1
VDD
CA3 VSS
CA2
CA0
DCLK#
DCLK1#
DCLK0#
CA5
CA7
CA9
DQ8
DQ10
VDDQ
DQ12
DQ14
DQ16
VDDQ
VSS
SI
VSS
VDD
VSSQ
VDD
VREF
SO
VSS
VDD
FLAG
DQ9
VSSQ
DQ11
DQ13
DQ15
CA4
CA6
CA8
VDD
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31 30
32
26
28
22
24
18
20
14
16
33
35
37
39
41
43
45
47
34
36
38
40
42
44
46
48
50
52
54
56
49
51
53
55
57
59
61
63
58
60
62
64
2
4
6
8
10
12
GENERAL DESCRIPTION
The HYSL8M18DR600A SLDRAM is a
synchronous, very high-speed, packet-oriented,
pipelined dynamic random access memory
containing 150,994,944 bits. The HYSL8M18DR-
600A SLDRAM is internally configured as eight
banks of 256K × 72; each of the 256K × 72 banks is
organized as 2048 rows by 128 columns by 72 bits.
The 72bits per column access are transferred over
the I/O interface in a burst of four 18-bit words.
All transitions begin with a request packet. Read
and write request packets contain the specific
command and address information required. Read
and write data are transferred in packets; a single
PIPELINED, EIGHT BANK, 2.5V
OPERATION
PIN ASSIGNMENT (TOP VIEW)
64 – Pin VSMP
CONFIDENTIAL DRAFT/ADVANCE
SLDRAM HYSL8M18D600A
CONSORTIUM 8 MEG x 18 SLDRAM
8M x 18 SLDRAM 2 HYUNDAI Electronics Confidential
Rev. 12/20/97 ¨¸1997, SLDRAM Consortium
column access involves the transfer of single data
packet, which is a burst of four 18-bit words.
Data from either or two columns in page may be
accessed with a single request packet; the latter
results in a continuous burst of eight 18-bit data
words. Read or write requests may be issued to idle
banks, or to the open row in active banks. Read or
write requests indicate whether to leave the row
open after access, or to perform a self-timed
precharge at the completion of the access (auto-
precharge).
The HYSL8M18DR600A uses a pipelined
architecture and multiple internal banks to achieve
high-speed operation and high effective bandwidth.
Precharging one bank while accessing another bank
will hide the precharge cycles, and provide seamless
high-speed random access operation.
The HYSL8M18DR600A is designed to operate in
2.5V memory systems. An auto-refresh mode is
provided along with two power saving modes,
standby and shutdown. The HYSL8M18DR600A
includes SLIO interface technology.
SLDRAMs offer substantial advances in DRAM
operating performance, including the ability to
synchronously burst data at a very high data rate
with automatic column address generation, the ability
to interleave between several internal banks in order
to hide precharge time, and the capability to provide
a continuous burst of data across random row and /
or column locations, even with 8-byte granularity.
FUNCTIONAL BLOCK DIAGRAM
Terminology – the term “tick” is used throughout this
data sheet as the equivalent of one-half of the CCLK
clock period. Also, for simplicity the clocks will be
referred to and shown as CCLK, DCLK0 and DCLK1.
It should be understood that these are differential
clocks and that each has a complementary signal.
Any reference to a specific edge of a particular clock
refers to the true version of that clock (e.g. CCLK) not
the complement (e.g. CCLK#)
CMD
&
ADDR.
CAPTURE
ID
REG. CMD
DEC.
&
SEQUENC
-ER
BANK0
MEMORY ARRAY
1024 ROWS
x 128 COLUMNS
x 72 BITS
BANK0
ROW
LATCH/
DEC/
DRVR
BANK
CTRL
LOGIC
BANK
ADDR.
REG.
PRE-
DEC
MUX
I/O GATING
COLUMN
LATCH/
DECODER
READ
LATCH
WRITE
LATCH/
DRVR
PROG.
DELAY
DRVRS
RCVRS
CLOCK
GENERATION
CLOCK
DIVIDERS
&
DELAYS
ROW
ADDR.
REG.
REFRESH
COUNTER
ADDR.
SEQUENC
-ER
SENSE AMPS
clk clk
in out
WCLK
INPUT
REGISTERS
WRITE
FIFO
clk in clk out
READ FIFO
MUX
RCLK
ICLK
BANK7 BANK7
DATA
DCLKs
RCLK
CCLK
ICLK
RCLK
WCLK
OTHER
CLOCK
CCLK#
(300MHz)
FLAG
CA0
- CA9 3
11
21
7
72
72
72
18
18
18
18
18 18
2
18
18
18
18
18
72
72
2
DQ0 -
DQ17
DCLK0, DCLK0#
DCLK1, DCLK1#
9216
CONFIDENTIAL DRAFT/ADVANCE
SLDRAM HYSL8M18D600A
CONSORTIUM 8 MEG x 18 SLDRAM
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PIN DESCRIPTIONS
VSMP
PIN NUMBER SYMBOL TYPE DESCRIPTION
29,28 CCLK,
CCLK# SLIO
Input Command Clock (differential): CCLK is driven by the memory
controller (or a separate clock chip) coincident with the leading
edges of the command bits. SLDRAM command input signals
are effectively sampled at each crossing of internally delayed
versions of CCLK/CCLK#. Read clocks, write clocks, and other
internal clocks are derived from CCLK.
25, 24, 27, 26 DCLK0,
DCLK0#,
DCLK1,
DCLK1#
SLIO
Input/
Output
Data Clocks (differential): For a read access, the specified pair
of DCLK0/DCLK0# or DCLK1/DCLK1# is driven by the
SLDRAM, and for write accesses, the SLDRAM provides 2
crossing on the selected DCLK pair prior to, and then 1 crossing
coincident with, the beginning of each valid data word. During
write accesses, the SLDRAM uses a delayed version of the
DCLK pair received with the data to capture the data.
59,60 SI, SO LVCMOS
Input,
Output
Select In, Select Out: The controller and all SLDRAM on a
channel are connected in series using these pins. This
connection is used to initialize the SLDRAM.
6LINKON LVCMOS
Input Link On: Used to enter and exit Shutdown mode.
7RESET# LVCMOS
Input Reset#: Provides a hardware reset; resets all logic, including the
ID register. Memory contains are not affected. An SLDRAM
must be initialized following hardware reset.
8LISTEN LVCMOS
Input Listen: Used to enter and exit Standby mode.
42 FLAG SLIO
Input Flag: FLAG HIGH indicates the start of a valid request packet;
FLAG then goes LOW for the remainder of the packet. FLAG
LOW at any other time is interpreted as a NOP.
30-32, 35-41 CA0-CA9 SLIO
Input Command, Address: Commands, Addresses and/or Register
Write Data be transferred on these signals, in packets of four
words.
14-18, 21-23,
43-45, 48-53,
13
DQ0-DQ17 SLIO
Input/
Output
Data I/O: Data bus.
5TEST -Test Pin: Should be tied to Vss during normal operation.
58 VREF -Reference voltage
11, 19, 47, 55 VDDQSupply DQ Power: Provide isolated power to DQs for improved noise
immunity.
12, 20, 46, 54 VSSQSupply DQ Ground: Provide isolated ground to DQs for improved noise
immunity.
1, 3, 9, 33,
57, 62, 64 VDD Supply Power Supply: +2.5V ± 5%.
2, 4, 10,34,
56, 61, 63 VSS Supply Ground.
CONFIDENTIAL DRAFT/ADVANCE
SLDRAM HYSL8M18D600A
CONSORTIUM 8 MEG x 18 SLDRAM
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FUNCTIONAL DESCRIPTION
The specific SLDRAM described in this data
sheet is an octal 256K×72 DRAM which operates at
2.5V and includes a high speed, packet-oriented,
synchronous 18-bit interface, and a pipelined
architecture. Each of the 256K×72 bit banks is
organized as 2048 rows by 128 columns by 72 bits.
Read and write accesses begin with the
application of a request packet, which includes all
necessary address bits. The request packet is
followed, after a specific programmed delay, by a
data packet, to complete the transaction.
Prior to normal operation, the SLDRAM must be
initialized. The following sections provide detailed
information covering device initialization, packet
definition, and device operation.
Initialization
POWER-UP/HARDWARE RESET
SLDRAMs must be powered-up and initialized in
a predefined manner. Operational procedures other
than those specified may result in undefined
operation. Power must be applied to VDD, VREF, and
VDDQ, then after a delay of tVTD, power must be
applied to system VTERM. VTERM must be applied
after VDDQ to avoid device latch-up, which may
cause permanent damage to the device. VREF can
be applied any time after VDDQ, but is expected to
be nominally coincident with VTERM. Inputs are not
recognized as valid until after VREF is applied. Upon
power-up, the SLDRAM DQ and DCLK outputs will
be driven LOW. The RESET# input should be held
active for at least tRST. This hardware reset sets the
internal ID Register to a value of 255, the SUB-ID
Register to a value of 15, and sets programmable
read and write delays to the minimum values.
EXIT SHUTDOWN/CONTROLLER DRIVER ADJUST
A LOW level on LINKON must be applied prior to
deasserting RESET#; then after deasserting
RESET#, continue the initialization sequence as if
existing the Shutdown mode (LISTEN LOW before
LINKON HIGH, bring LINKON HIGH, wait tLHHC for
DLLs to lock, then bring LISTEN HIGH). [Note;
external buffer devices may require that LISTEN be
LOW prior to deasserting RESET#, and that an
additional lock delay must occur between LICKON
going HIGH and LISTEN going HIGH]. After the exit
Shutdown sequence, the device is active, and the
command and write timing synchronization should be
performed.
At some point prior to the start of command and
write timing synchronization, the controller must
perform a self-calibration of VOH and VOL on it’s
SLIO outputs and I/O pins.
COMMAND AND WRITE TIMING SYNCHRONIZATION
For command and write timing synchronization,
the controller transmits the specified pattern on the
FLAG, CA, DQ, and DCLK signals, repetitively, until
a LOW-to-HIGH transition is eventually detected on
it’s SI input (which occurs only after all devices on
the channel are successfully synchronized). The
controller brings it’s SO output HIGH after
transmitting the first cycle of the specified pattern.
The packets are broadcast to all devices connected
directly to the controller and are identified by a two-
tick HIGH level on the Flag input. During this
operation, the SLDRAM devices use the SI/SO
daisy-chain link to communicate to the controller that
command and write timing synchronization has been
completed. This is achieved by passing a LOW-to-
HIGH transition from the controller SO output to the
first SLDRAM SI input, and then from the first
SLDRAM SO output to the second SLDRAM SI input,
etc. through the last SLDRAM SO output driving SI
input of the controller. Each SLDRAM device begins
command and write timing synchronization upon
detecting the specified pattern but does not drive it’s
SO output until both transition at it’s SI input, and the
completion of command and write timing
synchronization have occurred.
The receipt of the special pattern on FLAG with
the LOW-to-HIGH transition on SI differentiates this
activity on the SI/So link from the similar procedure
used during ID assignment. The controller stops
sending the specified patterns after detecting SI
HIGH, and then waits 16 ticks before sending a valid
command. This delay allows the SLDRAM devices to
detect the absence of the special pattern on the
FLAG input and to recognize the next HIGH level on
the FLAG input as being the start of a valid
command packet. The controller also resets the
SI/SO link by bringing it’s SO LOW; HIGH-to-LOW
transitions propagate through the link independent of
device status or operation.
ID ASSIGNMENT
Next, each SLDRAM on the channel(s) is
sequentially assigned a unique ID and SUB-ID
combination. Each SLDRAM individually selected in
turn by using the SI/SO link. This mode of operation
is identified by a LOW-to-HIGH transition on SI
followed by an ID Register Write Request Packet.
Each ID Register Write Request will be followed by a
corresponding SUB-ID Register Packet, and n of
these request pairs will be broadcast,(where n
equals the number of SLDRAM devices in the
system). Only the SLDRAM which has SI HIGH,
ID=255 and SUB-ID=15 will react to any given
request pair. Each SLDRAM in turn, reacts by writing
the ID contained in the first packet to it’s internal ID
CONFIDENTIAL DRAFT/ADVANCE
SLDRAM HYSL8M18D600A
CONSORTIUM 8 MEG x 18 SLDRAM
8M x 18 SLDRAM 5 HYUNDAI Electronics Confidential
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Register, writing the SUB-ID contained in the second
packet to it’s internal SUB-ID Register, and then
driving it’s SO HIGH. The controller provides enough
delay (tID plus related maximum routing delays)
between the assertion of it’s SO output HIGH and the
first issued request pair (and between subsequent
issued request pairs) to allow for SO to propagate to
the SI of the next device. ID assignment is complete
when SI of the controller goes HIGH. Then the
controller again resets the SI/SO link, as before.
PRE-CONFIGURATION/SLDRAM DRIVER ADJUST
At this point the SLDRAMs can receive
commands, and each SLDRAM is uniquely
addressable. Next, the SLDRAM operating frequency
should be programmed, and then VOH and VOL
calibration should be performed. The information
indicating the appropriate operating frequency will
either the contained in the controller itself, or can be
obtained by the controller by polling some other
component (jumpers, Serial Presence Detect device,
etc.). The appropriate values and then written to the
respective registers of each SLDRAM. For
programmed operating frequencies other than
300MHz (600Mb/s/p) the command and write
synchronization would be repeated at this point, for
the new frequency.
VOH calibration is performed for each SLDRAM
by sending a DCLK HIGH command and iteratively
sending Increment/Decrement VOH commands and
observing the output level until the desired level is
achieved. VOL calibration is performed similarly using
the Drive DCLK LOW and Increment/Decrement VOL
commands. The controller should then issue a
Disable DCLKs command packet.
READ TINING SYNCHRONIZATION
At this point the controller can send commands to
individual SLDRAMs, and the operating frequency is
selected, so read timing synchronization can be
performed.
For each SLDRAM, the controller should send a
Read Sync Request packet. The specified data
pattern is returned by the SLDRAM, with a delay
equal to the Actual Page Read Delay (which, after
reset, equals the Minimum Page Read Delay,
measured in integer clock ticks at the maximum
rated frequency of the device). The actual delay from
each SLDRAM module will be different, and the
specific delays, are unknown to the controller at this
point. The controller should enable the data
synchronization circuitry immediately after sending a
Read Sync Request command.
The controller should then adjust internal timing
to capture data. This is accomplished by adjusting
the Fine Read and Data Offset Verniers until the
known data pattern is captured and the capture
timing is optimized. At this point, the controller should
issue another Read Sync Packet Request, which
instructs the SLDRAM to discontinue sending the
sync pattern. After this is done for each SLDRAM,
the controller can read data from each SLDRAM at
the minimum latency for that particular device.
Command and Write Timing Synchronization,
Write Timing Synchronization, Read Timing
Synchronization or output level calibration may be
repeated periodically if necessary for a given system
design and environment. Such re-synchronization or
re-calibrations should be performed when no
accesses are in progress.
DETECTING AND REPROGRAMMING READ AND
WRITE LATENCIES
The controller may now detect the actual read
latency in the system for each SLDRAM by sending
a DRIVE DCLKs LOW command followed (after tDD)
by a Read Status Register Request. The controller
should enable data capture immediately after issuing
the Read Status Register Request and should count
clocks between sending the command and receiving
the data. With the latency (including system delays)
now known, the remaining status registers can be
read as in normal operation (i.e. without first issuing
the DRIVE DCLKs LOW command). Data from
status registers is provided in a burst of 4 by the
SLDRAM, at the Actual Read Latency of the device
(which appears as the observed system latency at
the controller)
After reading the status registers all SLDRAMs,
the controller uses the data provided, as well as the
observed latencies, to determine the appropriate
read latency to be programmed into the SLDRAMs.
In one suggested system design approach, the
devices with shorter observed read latencies would
be programmed with additional latency so as to
match that of the SLDRAM(s) with the longest
observed latency (for both bank and page accesses).
This way all read data arrives at the controller with
the same latency from command to data, regardless
of which SLDRAM device provides the data.
At this point the controller determines the
optimum write latency corresponding to the above
read latency at the controller I/O pins (optimizing the
tradeoff of internal bus turnaround time and external
bus turnaround time) and then must determine the
corresponding write latency value for each SLDRAM
(the write latency at a given SLDRAM may be
different than that at the controller I/O pins, and may
be different from that of other SLDRAMs). The
controller must observe the system write latency for
each SLDRAM compared to the corresponding
programmed write latency for that device. This is
CONFIDENTIAL DRAFT/ADVANCE
SLDRAM HYSL8M18D600A
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accomplished by driving the DCLKs continually
(toggling), issuing a Page Write to a specific address
and sending a counting pattern on the DQs (starting
at the end of the write packet and continuing beyond
the latency period, e.g. a count of 0-31 for
600Mb/s/p). Reading back the value from the
addressed location and comparing it with the value
associated with the desired latency provides the
delta to be used to reprogram the write latencies (for
bank and page access) for a given SLDRAM.
Once the Ids have been assigned and the timing
adjusted for each SLDRAM, the channel is ready for
normal operation.
Figure 1
Command and Data Sync
SIGNAL REPEATING PATTERN
Flag 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ...
CA9 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ...
CA8 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ...
CA7 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ...
CA6 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ...
CA5 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ...
CA4 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ...
CA3 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ...
CA2 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ...
CA1 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ...
CA0 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ...
DQ17 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ...
DQ16 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ...
DQ15 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ...
DQ14 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ...
DQ13 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ...
DQ12 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ...
DQ11 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ...
DQ10 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ...
DQ9 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ...
DQ8 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ...
DQ7 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ...
DQ6 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ...
DQ5 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ...
DQ4 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ...
DQ3 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ...
DQ2 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ...
DQ1 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ...
DQ0 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ...
DCLK1 0 1 ...
DCLK0 0 1 ...
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Packet Definition
General definitions for the various packets
included in the protocol are shown in the following
figures. More specific definitions are included, when
necessary, in the Register Definition, Command
Description and Device Operation selections of this
data sheet.
READ, WRITE, OR ROW OP RESQUEST PACKET
The Read, Write, Or Row Op Request Packet is
used to initiate any Read or Write Access, or to open
or close a specific row in a specific bank.
A Read or Write request will result in the transfer
of a Data Packet on the data bus at a specific time
later. The Data Packet is driven by the SLDRAM for
a READ or by the memory controller for a Write. An
Open Row or Close Row request generates no
response.
Although unused address bits are not recognized
by the SLDRAM device, zeroes should be applied for
those bits, as shown.
REGISTER READ REQUEST PACKET
The Register Read Request Packet is used to
initiate a Read access to a register address. In
response to a Register Read Request Packet, the
SLDRAM will provide a Data Packet on the data bus
at a specific time later.
Although bits REG6 - REG4, and the last 18 bits
of the packet are not needed or recognized by the
SLDRAM, zeroes should be applied for those bits, as
shown.
Figure 2
READ, WRITE, OR ROW OP REQUEST PACKET DEFINITION
Flag CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
0X X X X X X X X X X
1ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 CMD5
0CMD4 CMD3 CMD2 CMD1 CMD0 BNK0BNK1 BNK2BNK3 BNK4
0ROW0ROW1ROW2ROW3ROW4ROW5ROW6ROW7ROW8 ROW9
0ROW10 ROW11 ROW12 COL6 COL5 COL4 COL3 COL2 COL1 COL0
ID - ID0 = Device ID Value ROW12 - ROW0 = Row Address
CMD5 - CMD0 = Command Code COL6 - COL0 = Column Address
BNK4 - BNK0 = Bank Address if Unused, apply 0 for this bit
Figure 3
REGISTER READ PACKET DEFINITION
Flag CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
0X X X X X X X X X X
1ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 CMD5
0CMD4 CMD3 CMD2 CMD1 CMD0 0 0 0 0 0
0REG0REG1REG2 REG3 REG4=0 REG5=0REG6=0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
ID8 - ID0 = Device ID Value REG6 - REG0 = Register Address
CMD5 - CMD0 = Command Code 0 = Unused, applied 0 for this bit
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REGISTER WRITE REQUEST PACKET
The Register Write Request Packet is used to
initiate a Write access to a register address. This
packet consists of four words, with the latter two
being the data to be written to the selected register.
Although bits REG6 - REG4 are not needed or
recognized by the SLDRAM, zeroes should be
applied for those bits, as shown.
EVENT REQUEST PACKET
The Event Request is used to initiate a hard or
soft reset, an Autorefresh, or a Close All Rows
command, or to enter or exit Self Refresh, adjust
output voltage levels, adjust the Fine Read Vernier or
adjust the Data Offset Vernier.
The output voltage levels or fine read or data
offset verniers can be adjusted using a dedicated
Adjust Settings Event Request Packet or as part of
an Autorefresh Event. In either case, the bits ADJ0-
ADJ4 and DO0-DO4 determine the specific
adjustment to be made, according to Truth Table3.
An autorefresh without adjustment is performed
when ADJ0-ADJ4 is all 0.
The default values shown should be applied to
the unused bits. For events other than Autorefresh or
Adjust Setting, the ADJ0-ADJ4 bits are unused and
zeroes and zeroes should be applied to these bits.
Note: bits DO1-DO4 is defined for future use, the
default value for these bits is, and will be, all ones.
Figure 4
REGISTER WRITE PACKET DEFINITION
Flag CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
0X X X X X X X X X X
1ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 CMD5
0CMD4 CMD3 CMD2 CMD1 CMD0 SID4 SID3 SID2 SID1 SID0
0REG0 REG1 REG2 REG3REG4=0 REG5=0 REG6=0 0 0 0
0RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
ID8 - ID0 = Device ID Value CMD5 - CMD0 = Command Code
SID4 - 0 = Device Sub-ID Value REG6 -REG0 = Register Address
RD9 - RD0 = Register Data
Figure 5
EVENT PACKET DEFINITION
Flag CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
0XXXXXXXXXX
1ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 CMD5
0CMD4 CMD3 CMD2 CMD1 CMD0 SID4 SID3 SID2 SID1 SID0
0E6 E5 E4 E3 E2 E1 E0 000
0ADJ4* ADJ3* ADJ2* ADJ1* ADJ0* DO4* DO3* DO2* DO1* DO0*
*= For Autorefresh and Adjust Settings events only, otherwise unused (ADJx = 0, DOx = 1)
ID8 - ID0 = Device ID Value CMD5 - CMD0 = Command Code
SID4 - 0 = Device Sub-ID Value E6 - E0 = Event Index Code
ADJ4 - 0 = Adjust Setting Code DO4 - 0 = Data Offset DQ Select (future use)
CONFIDENTIAL DRAFT/ADVANCE
SLDRAM HYSL8M18D600A
CONSORTIUM 8 MEG x 18 SLDRAM
8M x 18 SLDRAM 9 HYUNDAI Electronics Confidential
Rev. 12/20/97 ¨¸1997, SLDRAM Consortium
DATA PACKET
A Data Packet is provided by the controller for
each Write Request and by the SLDRAM for each
Read Request. Each Data Packet contains either 8
bytes or 16 bytes, depending on whether the burst
length was set to 4 or 8, respectively, in the
corresponding request packet. There are no output
disable or write masking capabilities within the data
packet.
When the burst length of 8 is selected, the first 8
bytes in the Packet correspond to the column
address contained in the request packet, and the
second 8 bytes correspond to the same column
address except with an inverted LSB (i.e. the burst
‘wraps’).
Figure 6
DATA PACKET DEFINITION (FOR BURST LENGTH = 4)
DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Byte 0 Byte 1
Byte 2 Byte 3
Byte 4 Byte 5
Byte 6 Byte 7
Figure 7
DATA PACKET DEFINITION (FOR BURST LENGTH = 8)
DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Byte 0 Byte 1
Byte 2 Byte 3
Byte 4 Byte 5
Byte 6 Byte 7
Byte 8 Byte 9
Byte 10 Byte 11
Byte 12 Byte 13
Byte 14 Byte 15
CONFIDENTIAL DRAFT/ADVANCE
SLDRAM HYSL8M18D600A
CONSORTIUM 8 MEG x 18 SLDRAM
8M x 18 SLDRAM 10 HYUNDAI Electronics Confidential
Rev. 12/20/97 ¨¸1997, SLDRAM Consortium
Truth Table 1 –Commands
MD5 CMD4 CMD3 Command CMD2 CMD1 CMD0 Subcommand
0 0 0 0 0 0 Read Access, Leave Row Open, Drive DCLK0
0 0 0 0 0 1 Read Access, Leave Row Open, Drive DCLK1
0 0 0 0 1 0 Read Access, Close Row , Drive DCLK0
0 0 0 Page Access 0 1 1 Read Access, Close Row , Drive DCLK1
0 0 0 Burst of 4 1 0 0 Write Access, Leave Row Open, Drive DCLK0
0 0 0 1 0 1 Write Access, Leave Row Open, Drive DCLK1
0 0 0 1 1 0 Write Access, Close Row , Drive DCLK0
0 0 0 1 1 1 Write Access, Close Row , Drive DCLK1
0 0 1 0 0 0 Read Access, Leave Row Open, Drive DCLK0
0 0 1 0 0 1 Read Access, Leave Row Open, Drive DCLK1
0 0 1 0 1 0 Read Access, Close Row , Drive DCLK0
0 0 1 Page Access 0 1 1 Read Access, Close Row , Drive DCLK1
0 0 1 Burst of 8 1 0 0 Write Access, Leave Row Open, Drive DCLK0
0 0 1 1 0 1 Write Access, Leave Row Open, Drive DCLK1
0 0 1 1 1 0 Write Access, Close Row , Drive DCLK0
0 0 1 1 1 1 Write Access, Close Row , Drive DCLK1
0 1 0 0 0 0 Read Access, Leave Row Open, Drive DCLK0
0 1 0 0 0 1 Read Access, Leave Row Open, Drive DCLK1
0 1 0 0 1 0 Read Access, Close Row , Drive DCLK0
0 1 0 Bank Access 0 1 1 Read Access, Close Row , Drive DCLK1
0 1 0 Burst of 4 1 0 0 Write Access, Leave Row Open, Drive DCLK0
0 1 0 1 0 1 Write Access, Leave Row Open, Drive DCLK1
0 1 0 1 1 0 Write Access, Close Row , Drive DCLK0
0 1 0 1 1 1 Write Access, Close Row , Drive DCLK1
0 1 1 0 0 0 Read Access, Leave Row Open, Drive DCLK0
0 1 1 0 0 1 Read Access, Leave Row Open, Drive DCLK1
0 1 1 0 1 0 Read Access, Close Row , Drive DCLK0
0 1 1 Bank Access 0 1 1 Read Access, Close Row , Drive DCLK1
0 1 1 Burst of 8 1 0 0 Write Access, Leave Row Open, Drive DCLK0
0 1 1 1 0 1 Write Access, Leave Row Open, Drive DCLK1
0 1 1 1 1 0 Write Access, Close Row , Drive DCLK0
0 1 1 1 1 1 Write Access, Close Row , Drive DCLK1
1 0 0 0 0 0 Reserved
1 0 0 0 0 1 Open Row
1 0 0 Register 0 1 0 Close Row
1 0 0 Access 0 1 1 Register Write
1 0 0 Row Op. 1 0 0 Register Read, Use DCLK0
1 0 0 or Event 1 0 1 Register Read, Use DCLK1
1 0 0 1 1 0 Reserved
1 0 0 1 1 1 Event
CONFIDENTIAL DRAFT/ADVANCE
SLDRAM HYSL8M18D600A
CONSORTIUM 8 MEG x 18 SLDRAM
8M x 18 SLDRAM 11 HYUNDAI Electronics Confidential
Rev. 12/20/97 ¨¸1997, SLDRAM Consortium
1 0 1 0 0 0 Read Sync (Drive both DCLKs)
1 0 1 0 0 1 Stop Read Sync
1 0 1 0 1 0 Drive DCLKs LOW
1 0 1 Data 0 1 1 Drive DCLKs HIGH
101Sync 1 0 0 Write Sync (Both DCLKs toggling)
1 0 1 1 0 1 Reserved
1 0 1 1 1 0 Disable DCLKs
1 0 1 1 1 1 Drive DCLKs Toggling
1 1 0 Reserved X X X Reserved
1 1 1 Reserved X X X Reserved
Figure 8
Event Index Codes
*Index Range Description
0 - 15 Defined Events - See Event Truth Table
16 - 63 Reserved
64 - 127 Vendor Dependent
*Index = value of E6 - E0 in Event Request Packet
Truth Table 2 – Events
E6 – E3 E2 E1 E0 Event
0 0 0 0 Set ID Register to 255, SUB-ID to 15, reset device
0 0 0 1 Reset device, except ID and SUB-ID Register
0 0 1 0 Autorefresh
0 0 1 1 Close all rows
0 1 0 0 Enter Self Refresh
0 1 0 1 Exit Self Refresh
0 1 1 0 Adjust Settings
0 1 1 1 Reserved
CONFIDENTIAL DRAFT/ADVANCE
SLDRAM HYSL8M18D600A
CONSORTIUM 8 MEG x 18 SLDRAM
8M x 18 SLDRAM 12 HYUNDAI Electronics Confidential
Rev. 12/20/97 ¨¸1997, SLDRAM Consortium
Truth Table 3 - Adjust Settings
ADJ
4ADJ3 ADJ2 ADJ1 ADJ0 ADJUSTMENT
0 0 0 0 0 Reserved
0 0 0 0 1 Decrement Write Data Offset Vernier (delay DQs relative to DCLKs)
0 0 0 1 0 Increment Write Data Offset Vernier (advance DQs relative to DCLKs)
0 0 0 1 1 Reset Write Data Offset Vernier to Zero
0 0 1 0 0 Reserved
0 0 1 0 1 Decrement Fine Read Vernier for DQs and DCLKs
0 0 1 1 0 Increment Fine Read Vernier for DQs and DCLKs
0 0 1 1 1 Reset Fine Read Vernier for DQs and DCLKs and Zero
0 1 0 0 0 Reserved
0 1 0 0 1 Decrement Read Data Offset Vernier (delay DQs relative to DCLKs)
0 1 0 1 0 Increment Read Data Offset Vernier (advance DQs relative to DCLKs)
0 1 0 1 1 Reset Read Data Offset Vernier to Zero
0 1 1 0 0 Reserved
0 1 1 0 1 Decrement VOH Level
0 1 1 1 0 Increment VOH Level
0 1 1 1 1 Reset VOH to center of range
1 0 0 0 0 Reserved
1 0 0 0 1 Decrement VOL Level
1 0 0 1 0 Increment VOL Level
1 0 0 1 1 Reset VOL to center of range
1 0 1 0 0 Reserved
1 0 1 0 1 Reserved
1 0 1 1 0 Reserved
1 0 1 1 1 Reserved
1 1 0 0 0 Reserved
1 1 0 0 1 Reserved
1 1 0 1 0 Reserved
1 1 0 1 1 Reserved
1 1 1 0 0 Reserved
1 1 1 0 1 Reserved
1 1 1 1 0 Reserved
1 1 1 1 1 Reserved
