CONFIDENTIAL DRAFT/ADVANCE SLDRAM CONSORTIUM HYSL8M18D600A 8 MEG x 18 SLDRAM 600 Mb/s/pin SLDRAM 8M x 18 SLDRAM PIPELINED, EIGHT BANK, 2.5V OPERATION FEATURES Very High Speed - 600MHz data rate 1.2 GB/s peak I/O Bandwidth - provides very high bandwidth over narrow system memory bus UPipelined (Concurrent) operation - Up to 8 transaction (in one bank, or spread across multiple banks) UEight (this data sheet) or more internal banks for hiding row access/precharge UProgrammable burst lengths of 4 or 8 100% peak bandwidth sustainable over random row as well as random column access, even with 8 byte bursts. UPacket Oriented Protocol - Provided pin compatibility access multiple densities. UAuto Refresh and Self Refresh UCommand Clock for commands and addresses; Bidirectional Data Clocks for read and write data UDual Data Clocks provide smooth handoff from one data source to another UProgrammable Offset between Data and Data Clocks UProgrammable Read Delays - Adjustable in coarse increments equal to one data bit time, and fine increments which are a fraction of a bit time; allows for specific temporal placement of data at the memory controller data pins UProgrammable Write Delays - Adjustable in coarse increments equal to one data bit time. Allows for optimally adjusted write data placement by the memory controller USupports bank accesses (bank initially idle) and page accesses (bank active, row open) U128ms, 16K-cycle refresh USLIO Interface Technology Drivers: calibrated VOH and VOL levels, Receivers: narrow set-up and hold windows USingle +2.5V 5% power supply U PIN ASSIGNMENT (TOP VIEW) U OPTIONS 64 - Pin VSMP 3 TEST 5 RESET 7 VSS 9 13 DQ1 15 VDDQ VDD 4 VSS 6 LINKON 8 LISTEN 10 VDD 12 VSSQ 14 DQ0 16 DQ2 17 18 DQ4 20 VSSQ 19 DQ5 21 DQ7 23 DCLK0 25 DCLK1 27 CCLK 29 CA1 31 VDD 33 CA3 35 CA5 37 CA7 39 CA9 41 DQ8 43 DQ10 45 VDDQ 47 DQ12 49 DQ14 2 11 DQ17 DQ3 22 DQ6 24 DCLK0# 26 DCLK1# 28 DCLK# 30 CA0 32 CA2 34 VSS 36 CA4 38 CA6 40 CA8 42 FLAG 44 DQ9 46 VSSQ 48 DQ11 50 DQ13 51 DQ16 53 VDDQ 55 VSS 57 SI 59 VSS 61 VDD 63 52 DQ15 54 VSSQ 56 VDD 58 VREF 60 SO 62 VSS 64 VDD GENERAL DESCRIPTION The HYSL8M18DR600A SLDRAM is a synchronous, very high-speed, packet-oriented, pipelined dynamic random access memory containing 150,994,944 bits. The HYSL8M18DR600A SLDRAM is internally configured as eight banks of 256K x 72; each of the 256K x 72 banks is organized as 2048 rows by 128 columns by 72 bits. The 72bits per column access are transferred over the I/O interface in a burst of four 18-bit words. All transitions begin with a request packet. Read and write request packets contain the specific command and address information required. Read and write data are transferred in packets; a single MARKING Timing 600MHz data rate -600 UPlastic Package 64-pin VSMP (400mil width, .4 / .8 mm pitch) VS UPart Number Example: HYSL4M18DR600A 8M x 18 SLDRAM 1 VSS VDDQ U Rev. 12/20/97 VDD 1 HYUNDAI Electronics Confidential 1997, SLDRAM Consortium CONFIDENTIAL DRAFT/ADVANCE SLDRAM CONSORTIUM HYSL8M18D600A 8 MEG x 18 SLDRAM includes SLIO interface technology. SLDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a very high data rate with automatic column address generation, the ability to interleave between several internal banks in order to hide precharge time, and the capability to provide a continuous burst of data across random row and / or column locations, even with 8-byte granularity. column access involves the transfer of single data packet, which is a burst of four 18-bit words. Data from either or two columns in page may be accessed with a single request packet; the latter results in a continuous burst of eight 18-bit data words. Read or write requests may be issued to idle banks, or to the open row in active banks. Read or write requests indicate whether to leave the row open after access, or to perform a self-timed precharge at the completion of the access (autoprecharge). The HYSL8M18DR600A uses a pipelined architecture and multiple internal banks to achieve high-speed operation and high effective bandwidth. Precharging one bank while accessing another bank will hide the precharge cycles, and provide seamless high-speed random access operation. The HYSL8M18DR600A is designed to operate in 2.5V memory systems. An auto-refresh mode is provided along with two power saving modes, standby and shutdown. The HYSL8M18DR600A Terminology - the term "tick" is used throughout this data sheet as the equivalent of one-half of the CCLK clock period. Also, for simplicity the clocks will be referred to and shown as CCLK, DCLK0 and DCLK1. It should be understood that these are differential clocks and that each has a complementary signal. Any reference to a specific edge of a particular clock refers to the true version of that clock (e.g. CCLK) not the complement (e.g. CCLK#) FUNCTIONAL BLOCK DIAGRAM ID REG. FLAG CA0 - CA9 CMD DEC. & SEQUENC -ER RCLK CMD & ADDR. CAPTURE 21 BANK7 BANK ADDR. REG. 3 BANK7 PROG. DELAY BANK CTRL LOGIC ICLK 18 RCLK DATA 18 11 ROW ADDR. REG. MUX BANK0 ROW LATCH/ DEC/ DRVR PREDEC REFRESH COUNTER clk in BANK0 MEMORYARRAY 72 clk out 18 READ LATCH MUX DRVRS 2 18 1024ROWS x128COLUMNS x 72 BITS 18 READ FIFO 18 DCLKs DQ0 DQ17 SENSEAMPS 9216 I/OGATING ADDR. SEQUENC -ER 18 WRITE FIFO 7 COLUMN LATCH/ DECODER 72 WRITE LATCH/ DRVR 18 72 72 18 CCLK# (300MHz) CLOCK DIVIDERS & DELAYS 8M x 18 SLDRAM Rev. 12/20/97 CLOCK GENERATION WCLK ICLK RCVRS 18 18 clk clk in out CCLK DCLK0, DCLK0# DCLK1, DCLK1# INPUT REGISTERS 72 2 RCLK WCLK OTHER CLOCK 2 HYUNDAI Electronics Confidential 1997, SLDRAM Consortium CONFIDENTIAL DRAFT/ADVANCE SLDRAM CONSORTIUM HYSL8M18D600A 8 MEG x 18 SLDRAM PIN DESCRIPTIONS VSMP SYMBOL TYPE DESCRIPTION 29,28 CCLK, CCLK# SLIO Input 25, 24, 27, 26 DCLK0, DCLK0#, DCLK1, DCLK1# SLIO Input/ Output 59,60 SI, SO 6 LINKON 7 RESET# LVCMOS Input, Output LVCMOS Input LVCMOS Input Command Clock (differential): CCLK is driven by the memory controller (or a separate clock chip) coincident with the leading edges of the command bits. SLDRAM command input signals are effectively sampled at each crossing of internally delayed versions of CCLK/CCLK#. Read clocks, write clocks, and other internal clocks are derived from CCLK. Data Clocks (differential): For a read access, the specified pair of DCLK0/DCLK0# or DCLK1/DCLK1# is driven by the SLDRAM, and for write accesses, the SLDRAM provides 2 crossing on the selected DCLK pair prior to, and then 1 crossing coincident with, the beginning of each valid data word. During write accesses, the SLDRAM uses a delayed version of the DCLK pair received with the data to capture the data. Select In, Select Out: The controller and all SLDRAM on a channel are connected in series using these pins. This connection is used to initialize the SLDRAM. Link On: Used to enter and exit Shutdown mode. 8 LISTEN 42 FLAG 30-32, 35-41 CA0-CA9 SLIO Input 14-18, 21-23, 43-45, 48-53, 13 5 58 11, 19, 47, 55 DQ0-DQ17 TEST VREF VDDQ SLIO Input/ Output Supply 12, 20, 46, 54 VSSQ Supply 1, 3, 9, 33, 57, 62, 64 2, 4, 10,34, 56, 61, 63 VDD Supply Test Pin: Should be tied to Vss during normal operation. Reference voltage DQ Power: Provide isolated power to DQs for improved noise immunity. DQ Ground: Provide isolated ground to DQs for improved noise immunity. Power Supply: +2.5V 5%. VSS Supply Ground. PIN NUMBER 8M x 18 SLDRAM Rev. 12/20/97 LVCMOS Input SLIO Input Reset#: Provides a hardware reset; resets all logic, including the ID register. Memory contains are not affected. An SLDRAM must be initialized following hardware reset. Listen: Used to enter and exit Standby mode. Flag: FLAG HIGH indicates the start of a valid request packet; FLAG then goes LOW for the remainder of the packet. FLAG LOW at any other time is interpreted as a NOP. Command, Address: Commands, Addresses and/or Register Write Data be transferred on these signals, in packets of four words. Data I/O: Data bus. 3 HYUNDAI Electronics Confidential 1 997, SLDRAM Consortium CONFIDENTIAL DRAFT/ADVANCE SLDRAM CONSORTIUM HYSL8M18D600A 8 MEG x 18 SLDRAM COMMAND AND WRITE TIMING SYNCHRONIZATION FUNCTIONAL DESCRIPTION The specific SLDRAM described in this data sheet is an octal 256Kx72 DRAM which operates at 2.5V and includes a high speed, packet-oriented, synchronous 18-bit interface, and a pipelined architecture. Each of the 256Kx72 bit banks is organized as 2048 rows by 128 columns by 72 bits. Read and write accesses begin with the application of a request packet, which includes all necessary address bits. The request packet is followed, after a specific programmed delay, by a data packet, to complete the transaction. Prior to normal operation, the SLDRAM must be initialized. The following sections provide detailed information covering device initialization, packet definition, and device operation. Initialization POWER-UP/HARDWARE RESET SLDRAMs must be powered-up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must be applied to VDD, VREF, and VDDQ, then after a delay of tVTD, power must be applied to system VTERM. VTERM must be applied after VDDQ to avoid device latch-up, which may cause permanent damage to the device. VREF can be applied any time after VDDQ, but is expected to be nominally coincident with VTERM. Inputs are not recognized as valid until after VREF is applied. Upon power-up, the SLDRAM DQ and DCLK outputs will be driven LOW. The RESET# input should be held active for at least tRST. This hardware reset sets the internal ID Register to a value of 255, the SUB-ID Register to a value of 15, and sets programmable read and write delays to the minimum values. EXIT SHUTDOWN/CONTROLLER DRIVER ADJUST A LOW level on LINKON must be applied prior to deasserting RESET#; then after deasserting RESET#, continue the initialization sequence as if existing the Shutdown mode (LISTEN LOW before LINKON HIGH, bring LINKON HIGH, wait tLHHC for DLLs to lock, then bring LISTEN HIGH). [Note; external buffer devices may require that LISTEN be LOW prior to deasserting RESET#, and that an additional lock delay must occur between LICKON going HIGH and LISTEN going HIGH]. After the exit Shutdown sequence, the device is active, and the command and write timing synchronization should be performed. At some point prior to the start of command and write timing synchronization, the controller must perform a self-calibration of VOH and VOL on it' s SLIO outputs and I/O pins. 8M x 18 SLDRAM Rev. 12/20/97 4 For command and write timing synchronization, the controller transmits the specified pattern on the FLAG, CA, DQ, and DCLK signals, repetitively, until a LOW-to-HIGH transition is eventually detected on it' s SI input (which occurs only after all devices on the channel are successfully synchronized). The controller brings it' s SO output HIGH after transmitting the first cycle of the specified pattern. The packets are broadcast to all devices connected directly to the controller and are identified by a twotick HIGH level on the Flag input. During this operation, the SLDRAM devices use the SI/SO daisy-chain link to communicate to the controller that command and write timing synchronization has been completed. This is achieved by passing a LOW-toHIGH transition from the controller SO output to the first SLDRAM SI input, and then from the first SLDRAM SO output to the second SLDRAM SI input, etc. through the last SLDRAM SO output driving SI input of the controller. Each SLDRAM device begins command and write timing synchronization upon detecting the specified pattern but does not drive it' s SO output until both transition at it' s SI input, and the completion of command and write timing synchronization have occurred. The receipt of the special pattern on FLAG with the LOW-to-HIGH transition on SI differentiates this activity on the SI/So link from the similar procedure used during ID assignment. The controller stops sending the specified patterns after detecting SI HIGH, and then waits 16 ticks before sending a valid command. This delay allows the SLDRAM devices to detect the absence of the special pattern on the FLAG input and to recognize the next HIGH level on the FLAG input as being the start of a valid command packet. The controller also resets the SI/SO link by bringing it' s SO LOW; HIGH-to-LOW transitions propagate through the link independent of device status or operation. ID ASSIGNMENT Next, each SLDRAM on the channel(s) is sequentially assigned a unique ID and SUB-ID combination. Each SLDRAM individually selected in turn by using the SI/SO link. This mode of operation is identified by a LOW-to-HIGH transition on SI followed by an ID Register Write Request Packet. Each ID Register Write Request will be followed by a corresponding SUB-ID Register Packet, and n of these request pairs will be broadcast,(where n equals the number of SLDRAM devices in the system). Only the SLDRAM which has SI HIGH, ID=255 and SUB-ID=15 will react to any given request pair. Each SLDRAM in turn, reacts by writing the ID contained in the first packet to it' s internal ID HYUNDAI Electronics Confidential 1 997, SLDRAM Consortium CONFIDENTIAL DRAFT/ADVANCE SLDRAM CONSORTIUM HYSL8M18D600A 8 MEG x 18 SLDRAM Register, writing the SUB-ID contained in the second packet to it' s internal SUB-ID Register, and then driving it' s SO HIGH. The controller provides enough delay (tID plus related maximum routing delays) between the assertion of it' s SO output HIGH and the first issued request pair (and between subsequent issued request pairs) to allow for SO to propagate to the SI of the next device. ID assignment is complete when SI of the controller goes HIGH. Then the controller again resets the SI/SO link, as before. PRE-CONFIGURATION/SLDRAM DRIVER ADJUST At this point the SLDRAMs can receive commands, and each SLDRAM is uniquely addressable. Next, the SLDRAM operating frequency should be programmed, and then VOH and VOL calibration should be performed. The information indicating the appropriate operating frequency will either the contained in the controller itself, or can be obtained by the controller by polling some other component (jumpers, Serial Presence Detect device, etc.). The appropriate values and then written to the respective registers of each SLDRAM. For programmed operating frequencies other than 300MHz (600Mb/s/p) the command and write synchronization would be repeated at this point, for the new frequency. VOH calibration is performed for each SLDRAM by sending a DCLK HIGH command and iteratively sending Increment/Decrement VOH commands and observing the output level until the desired level is achieved. VOL calibration is performed similarly using the Drive DCLK LOW and Increment/Decrement VOL commands. The controller should then issue a Disable DCLKs command packet. READ TINING SYNCHRONIZATION At this point the controller can send commands to individual SLDRAMs, and the operating frequency is selected, so read timing synchronization can be performed. For each SLDRAM, the controller should send a Read Sync Request packet. The specified data pattern is returned by the SLDRAM, with a delay equal to the Actual Page Read Delay (which, after reset, equals the Minimum Page Read Delay, measured in integer clock ticks at the maximum rated frequency of the device). The actual delay from each SLDRAM module will be different, and the specific delays, are unknown to the controller at this point. The controller should enable the data synchronization circuitry immediately after sending a Read Sync Request command. The controller should then adjust internal timing to capture data. This is accomplished by adjusting the Fine Read and Data Offset Verniers until the 8M x 18 SLDRAM Rev. 12/20/97 5 known data pattern is captured and the capture timing is optimized. At this point, the controller should issue another Read Sync Packet Request, which instructs the SLDRAM to discontinue sending the sync pattern. After this is done for each SLDRAM, the controller can read data from each SLDRAM at the minimum latency for that particular device. Command and Write Timing Synchronization, Write Timing Synchronization, Read Timing Synchronization or output level calibration may be repeated periodically if necessary for a given system design and environment. Such re-synchronization or re-calibrations should be performed when no accesses are in progress. DETECTING AND REPROGRAMMING READ AND WRITE LATENCIES The controller may now detect the actual read latency in the system for each SLDRAM by sending a DRIVE DCLKs LOW command followed (after tDD) by a Read Status Register Request. The controller should enable data capture immediately after issuing the Read Status Register Request and should count clocks between sending the command and receiving the data. With the latency (including system delays) now known, the remaining status registers can be read as in normal operation (i.e. without first issuing the DRIVE DCLKs LOW command). Data from status registers is provided in a burst of 4 by the SLDRAM, at the Actual Read Latency of the device (which appears as the observed system latency at the controller) After reading the status registers all SLDRAMs, the controller uses the data provided, as well as the observed latencies, to determine the appropriate read latency to be programmed into the SLDRAMs. In one suggested system design approach, the devices with shorter observed read latencies would be programmed with additional latency so as to match that of the SLDRAM(s) with the longest observed latency (for both bank and page accesses). This way all read data arrives at the controller with the same latency from command to data, regardless of which SLDRAM device provides the data. At this point the controller determines the optimum write latency corresponding to the above read latency at the controller I/O pins (optimizing the tradeoff of internal bus turnaround time and external bus turnaround time) and then must determine the corresponding write latency value for each SLDRAM (the write latency at a given SLDRAM may be different than that at the controller I/O pins, and may be different from that of other SLDRAMs). The controller must observe the system write latency for each SLDRAM compared to the corresponding programmed write latency for that device. This is HYUNDAI Electronics Confidential 1 997, SLDRAM Consortium CONFIDENTIAL DRAFT/ADVANCE SLDRAM CONSORTIUM HYSL8M18D600A 8 MEG x 18 SLDRAM associated with the desired latency provides the delta to be used to reprogram the write latencies (for bank and page access) for a given SLDRAM. Once the Ids have been assigned and the timing adjusted for each SLDRAM, the channel is ready for normal operation. accomplished by driving the DCLKs continually (toggling), issuing a Page Write to a specific address and sending a counting pattern on the DQs (starting at the end of the write packet and continuing beyond the latency period, e.g. a count of 0-31 for 600Mb/s/p). Reading back the value from the addressed location and comparing it with the value Figure 1 Command and Data Sync 8M x 18 SLDRAM Rev. 12/20/97 SIGNAL REPEATING PATTERN Flag CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 DCLK1 DCLK0 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ... 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ... 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ... 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ... 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ... 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ... 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ... 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ... 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ... 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ... 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ... 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ... 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ... 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ... 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ... 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ... 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ... 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ... 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ... 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ... 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ... 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ... 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ... 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ... 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ... 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ... 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ... 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 ... 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ... 0 1 ... 0 1 ... 6 HYUNDAI Electronics Confidential 1 997, SLDRAM Consortium CONFIDENTIAL DRAFT/ADVANCE SLDRAM CONSORTIUM HYSL8M18D600A 8 MEG x 18 SLDRAM Open Row or Close Row request generates no response. Although unused address bits are not recognized by the SLDRAM device, zeroes should be applied for those bits, as shown. Packet Definition General definitions for the various packets included in the protocol are shown in the following figures. More specific definitions are included, when necessary, in the Register Definition, Command Description and Device Operation selections of this data sheet. REGISTER READ REQUEST PACKET The Register Read Request Packet is used to initiate a Read access to a register address. In response to a Register Read Request Packet, the SLDRAM will provide a Data Packet on the data bus at a specific time later. Although bits REG6 - REG4, and the last 18 bits of the packet are not needed or recognized by the SLDRAM, zeroes should be applied for those bits, as shown. READ, WRITE, OR ROW OP RESQUEST PACKET The Read, Write, Or Row Op Request Packet is used to initiate any Read or Write Access, or to open or close a specific row in a specific bank. A Read or Write request will result in the transfer of a Data Packet on the data bus at a specific time later. The Data Packet is driven by the SLDRAM for a READ or by the memory controller for a Write. An Figure 2 READ, WRITE, OR ROW OP REQUEST PACKET DEFINITION Flag 0 1 0 0 0 CA9 X ID8 CMD4 ROW0 ROW10 CA8 X ID7 CMD3 ROW1 ROW11 CA7 X ID6 CMD2 ROW2 ROW12 CA6 X ID5 CMD1 ROW3 COL6 CA5 X ID4 CMD0 ROW4 COL5 ID - ID0 = Device ID Value CMD5 - CMD0 = Command Code BNK4 - BNK0 = Bank Address CA4 X ID3 BNK0 ROW5 COL4 CA3 X ID2 BNK1 ROW6 COL3 CA2 X ID1 BNK2 ROW7 COL2 CA1 X ID0 BNK3 ROW8 COL1 CA0 X CMD5 BNK4 ROW9 COL0 ROW12 - ROW0 = Row Address COL6 - COL0 = Column Address if Unused, apply 0 for this bit Figure 3 REGISTER READ PACKET DEFINITION Flag 0 1 0 0 0 CA9 X ID8 CMD4 REG0 0 CA8 X ID7 CMD3 REG1 0 CA7 X ID6 CMD2 REG2 0 CA6 X ID5 CMD1 REG3 0 CA5 X ID4 CMD0 REG4=0 0 ID8 - ID0 = Device ID Value CMD5 - CMD0 = Command Code 8M x 18 SLDRAM Rev. 12/20/97 CA4 X ID3 CA3 X ID2 CA2 X ID1 0 0 0 REG5=0 0 REG6=0 0 0 0 CA1 X ID0 0 0 0 CA0 X CMD5 0 0 0 REG6 - REG0 = Register Address 0 = Unused, applied 0 for this bit 7 HYUNDAI Electronics Confidential 1 997, SLDRAM Consortium CONFIDENTIAL DRAFT/ADVANCE SLDRAM CONSORTIUM HYSL8M18D600A 8 MEG x 18 SLDRAM REGISTER WRITE REQUEST PACKET The output voltage levels or fine read or data offset verniers can be adjusted using a dedicated Adjust Settings Event Request Packet or as part of an Autorefresh Event. In either case, the bits ADJ0ADJ4 and DO0-DO4 determine the specific adjustment to be made, according to Truth Table3. An autorefresh without adjustment is performed when ADJ0-ADJ4 is all 0. The default values shown should be applied to the unused bits. For events other than Autorefresh or Adjust Setting, the ADJ0-ADJ4 bits are unused and zeroes and zeroes should be applied to these bits. Note: bits DO1-DO4 is defined for future use, the default value for these bits is, and will be, all ones. The Register Write Request Packet is used to initiate a Write access to a register address. This packet consists of four words, with the latter two being the data to be written to the selected register. Although bits REG6 - REG4 are not needed or recognized by the SLDRAM, zeroes should be applied for those bits, as shown. EVENT REQUEST PACKET The Event Request is used to initiate a hard or soft reset, an Autorefresh, or a Close All Rows command, or to enter or exit Self Refresh, adjust output voltage levels, adjust the Fine Read Vernier or adjust the Data Offset Vernier. Figure 4 REGISTER WRITE PACKET DEFINITION Flag 0 1 0 0 0 CA9 X ID8 CMD4 REG0 RD9 CA8 X ID7 CMD3 REG1 RD8 CA7 X ID6 CMD2 REG2 RD7 CA6 X ID5 CMD1 REG3 RD6 CA5 X ID4 CMD0 REG4=0 RD5 ID8 - ID0 = Device ID Value SID4 - 0 = Device Sub-ID Value RD9 - RD0 = Register Data CA4 X ID3 SID4 REG5=0 RD4 CA3 X ID2 SID3 REG6=0 RD3 CA2 X ID1 SID2 0 RD2 CA1 X ID0 SID1 0 RD1 CA0 X CMD5 SID0 0 RD0 CMD5 - CMD0 = Command Code REG6 -REG0 = Register Address Figure 5 EVENT PACKET DEFINITION Flag CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 CA1 0 X X X X X X X X X 1 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0 CMD4 CMD3 CMD2 CMD1 CMD0 SID4 SID3 SID2 SID1 0 E6 E5 E4 E3 E2 E1 E0 0 0 0 ADJ4* ADJ3* ADJ2* ADJ1* ADJ0* DO4* DO3* DO2* DO1* *= For Autorefresh and Adjust Settings events only, otherwise unused (ADJx = 0, DOx = 1) ID8 - ID0 = Device ID Value SID4 - 0 = Device Sub-ID Value ADJ4 - 0 = Adjust Setting Code 8M x 18 SLDRAM Rev. 12/20/97 CA0 X CMD5 SID0 0 DO0* CMD5 - CMD0 = Command Code E6 - E0 = Event Index Code DO4 - 0 = Data Offset DQ Select (future use) 8 HYUNDAI Electronics Confidential 1 997, SLDRAM Consortium CONFIDENTIAL DRAFT/ADVANCE SLDRAM CONSORTIUM HYSL8M18D600A 8 MEG x 18 SLDRAM DATA PACKET packet. When the burst length of 8 is selected, the first 8 bytes in the Packet correspond to the column address contained in the request packet, and the second 8 bytes correspond to the same column address except with an inverted LSB (i.e. the burst ` wraps' ). A Data Packet is provided by the controller for each Write Request and by the SLDRAM for each Read Request. Each Data Packet contains either 8 bytes or 16 bytes, depending on whether the burst length was set to 4 or 8, respectively, in the corresponding request packet. There are no output disable or write masking capabilities within the data Figure 6 DATA PACKET DEFINITION (FOR BURST LENGTH = 4) DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 Byte 0 Byte 2 Byte 4 Byte 6 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Byte 1 Byte 3 Byte 5 Byte 7 Figure 7 DATA PACKET DEFINITION (FOR BURST LENGTH = 8) DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 Byte 0 Byte 2 Byte 4 Byte 6 Byte 8 Byte 10 Byte 12 Byte 14 8M x 18 SLDRAM Rev. 12/20/97 9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Byte 1 Byte 3 Byte 5 Byte 7 Byte 9 Byte 11 Byte 13 Byte 15 HYUNDAI Electronics Confidential 1 997, SLDRAM Consortium CONFIDENTIAL DRAFT/ADVANCE SLDRAM CONSORTIUM HYSL8M18D600A 8 MEG x 18 SLDRAM Truth Table 1 -Commands MD5 CMD4 CMD3 CMD2 CMD1 CMD0 Subcommand 0 0 0 0 0 0 Read Access, Leave Row Open, Drive DCLK0 0 0 0 0 0 1 Read Access, Leave Row Open, Drive DCLK1 0 0 0 0 1 0 Read Access, Close Row , Drive DCLK0 0 0 0 Page Access 0 1 1 Read Access, Close Row , Drive DCLK1 0 0 0 Burst of 4 1 0 0 Write Access, Leave Row Open, Drive DCLK0 0 0 0 1 0 1 Write Access, Leave Row Open, Drive DCLK1 0 0 0 1 1 0 Write Access, Close Row , Drive DCLK0 0 0 0 1 1 1 Write Access, Close Row , Drive DCLK1 0 0 1 0 0 0 Read Access, Leave Row Open, Drive DCLK0 0 0 1 0 0 1 Read Access, Leave Row Open, Drive DCLK1 0 0 1 0 1 0 Read Access, Close Row , Drive DCLK0 0 0 1 Page Access 0 1 1 Read Access, Close Row , Drive DCLK1 0 0 1 Burst of 8 1 0 0 Write Access, Leave Row Open, Drive DCLK0 0 0 1 1 0 1 Write Access, Leave Row Open, Drive DCLK1 0 0 1 1 1 0 Write Access, Close Row , Drive DCLK0 0 0 1 1 1 1 Write Access, Close Row , Drive DCLK1 0 1 0 0 0 0 Read Access, Leave Row Open, Drive DCLK0 0 1 0 0 0 1 Read Access, Leave Row Open, Drive DCLK1 0 1 0 0 1 0 Read Access, Close Row , Drive DCLK0 0 1 0 Bank Access 0 1 1 Read Access, Close Row , Drive DCLK1 0 1 0 Burst of 4 1 0 0 Write Access, Leave Row Open, Drive DCLK0 0 1 0 1 0 1 Write Access, Leave Row Open, Drive DCLK1 0 1 0 1 1 0 Write Access, Close Row , Drive DCLK0 0 1 0 1 1 1 Write Access, Close Row , Drive DCLK1 0 1 1 0 0 0 Read Access, Leave Row Open, Drive DCLK0 0 1 1 0 0 1 Read Access, Leave Row Open, Drive DCLK1 0 1 1 0 1 0 Read Access, Close Row , Drive DCLK0 0 1 1 Bank Access 0 1 1 Read Access, Close Row , Drive DCLK1 0 1 1 Burst of 8 1 0 0 Write Access, Leave Row Open, Drive DCLK0 0 1 1 1 0 1 Write Access, Leave Row Open, Drive DCLK1 0 1 1 1 1 0 Write Access, Close Row , Drive DCLK0 0 1 1 1 1 1 Write Access, Close Row , Drive DCLK1 1 0 0 0 0 0 Reserved 1 0 0 0 0 1 Open Row 1 0 0 Register 0 1 0 Close Row 1 0 0 Access 0 1 1 Register Write 1 0 0 Row Op. 1 0 0 Register Read, Use DCLK0 1 0 0 or Event 1 0 1 Register Read, Use DCLK1 1 0 0 1 1 0 Reserved 1 0 0 1 1 1 Event 8M x 18 SLDRAM Rev. 12/20/97 Command 10 HYUNDAI Electronics Confidential 1 997, SLDRAM Consortium CONFIDENTIAL DRAFT/ADVANCE SLDRAM CONSORTIUM HYSL8M18D600A 8 MEG x 18 SLDRAM 1 0 1 0 0 0 Read Sync (Drive both DCLKs) 1 0 1 0 0 1 Stop Read Sync 1 0 1 0 1 0 Drive DCLKs LOW 1 0 1 Data 0 1 1 Drive DCLKs HIGH 1 0 1 Sync 1 0 0 Write Sync (Both DCLKs toggling) 1 0 1 1 0 1 Reserved 1 0 1 1 1 0 Disable DCLKs 1 0 1 1 1 1 Drive DCLKs Toggling 1 1 0 Reserved X X X Reserved 1 1 1 Reserved X X X Reserved Figure 8 Event Index Codes *Index Range 0 - 15 16 - 63 64 - 127 Description Defined Events - See Event Truth Table Reserved Vendor Dependent *Index = value of E6 - E0 in Event Request Packet Truth Table 2 - Events E6 - E3 0 0 0 0 0 0 0 0 8M x 18 SLDRAM Rev. 12/20/97 E2 0 0 0 0 1 1 1 1 E1 0 0 1 1 0 0 1 1 E0 0 1 0 1 0 1 0 1 Event Set ID Register to 255, SUB-ID to 15, reset device Reset device, except ID and SUB-ID Register Autorefresh Close all rows Enter Self Refresh Exit Self Refresh Adjust Settings Reserved 11 HYUNDAI Electronics Confidential 1 997, SLDRAM Consortium CONFIDENTIAL DRAFT/ADVANCE SLDRAM CONSORTIUM HYSL8M18D600A 8 MEG x 18 SLDRAM Truth Table 3 - Adjust Settings ADJ 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ADJ3 ADJ2 ADJ1 ADJ0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8M x 18 SLDRAM Rev. 12/20/97 ADJUSTMENT Reserved Decrement Write Data Offset Vernier (delay DQs relative to DCLKs) Increment Write Data Offset Vernier (advance DQs relative to DCLKs) Reset Write Data Offset Vernier to Zero Reserved Decrement Fine Read Vernier for DQs and DCLKs Increment Fine Read Vernier for DQs and DCLKs Reset Fine Read Vernier for DQs and DCLKs and Zero Reserved Decrement Read Data Offset Vernier (delay DQs relative to DCLKs) Increment Read Data Offset Vernier (advance DQs relative to DCLKs) Reset Read Data Offset Vernier to Zero Reserved Decrement VOH Level Increment VOH Level Reset VOH to center of range Reserved Decrement VOL Level Increment VOL Level Reset VOL to center of range Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 12 HYUNDAI Electronics Confidential 1 997, SLDRAM Consortium