512Kx36 & 1Mx18 DDRII+ CIO b2 SRAM
K7K1636T2C
K7K1618T2C
- 1 - Rev. 1.4 August 2008
18Mb DDRII+ SRAM Specification
* Samsung Electronics reserves the right to change products or specification without notice.
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure couldresult in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
165 FBGA with Pb & Pb-Free
(RoHS compliant)
512Kx36 & 1Mx18 DDRII+ CIO b2 SRAM
K7K1636T2C
K7K1618T2C
- 2 - Rev. 1.4 August 2008
Document Title
512Kx36-bit, 1Mx18-bit DDRTM II+ CIO b2 SRAM
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Revision History
Rev. No.
0.0
0.1
0.2
0.3
0.4
0.5
0.6
1.0
1.1
1.2
1.3
1.4
Remark
Advance
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Final
Final
Final
Final
Final
History
1. Initial document.
1. Modify the READ/WRITE timing diagram
1. Add comment Pb Free and Industrial
1. Remove speed bin : 375MHz
1. Change Max of clock cycle time
1. Correct errors
1. Change Samsung JEDEC Code in ID REGISTER DEFINITION
1. Correct typo
1. Change ICC measure condition
2. Change programmable impedence output buffer operation
3. Add AC Timing Characteristics
1. Add AC/DC parameter of 450MHz
1. Correct Boundary Scan.
1. Delete AC/DC parameter of 450MHz
Draft Date
Nov. 25, 2005
Dec. 12, 2005
Mar. 03, 2006
Mar. 03, 2006
Mar. 03, 2006
May. 03. 2006
June. 03. 2006
Aug. 23, 2006
Jan. 30, 2007
Mar. 16, 2007
Jun. 20. 2008
Aug. 27, 2008
512Kx36 & 1Mx18 DDRII+ CIO b2 SRAM
K7K1636T2C
K7K1618T2C
- 3 - Rev. 1.4 August 2008
512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM
FEATURES
FUNCTIONAL BLOCK DIAGRAM
• 1.8V+0.1V/-0.1V Power Supply.
• DLL circuitry for wide output data valid window and future
freguency scaling.
• I/O Supply Voltage 1.5V+0.1V/-0.1V
• Pipelined, double-data rate operation.
• Common data input/output bus .
• HSTL I/O
• Full data coherency, providing most current data.
• Synchronous pipeline read with self timed late write.
• Read latency : 2 clock cycles
• Registered address, control and data input/output.
• DDR(Double Data Rate) Interface on read and write ports.
• Fixed 2-bit burst for both read and write operation.
• Clock-stop supports to reduce current.
• Two input clocks(K and K) for accurate DDR timing at clock
rising edges only.
• Two echo clocks (CQ and CQ) to enhance output data
traceability.
• Data Valid pin(QVLD) supported
• Single address bus.
• Byte write (x18, x36) function.
• Simple depth expansion with no data contention.
• Programmable output impedance(ZQ).
• JTAG 1149.1 compatible test access port.
• 165FBGA(11x15 ball aray FBGA) with body size of 15x17mm
LD
ADDRESS
R/W
Doff
DATA
REG
CLK
GEN
CTRL
LOGIC
512Kx36
(1Mx18)
MEMORY
ARRAY
WRITE DRIVER
K
K
BWX4(or 2)
DQ
SELECT OUTPUT CONTROL
SENSE AMPS
WRITE/READ DECODE
OUTPUT REG
OUTPUT SELECT
OUTPUT DRIVER
Notes: 1. Numbers in ( ) are for x18 device
18
18 (or 19)
36 (or 18)
36
72
(Echo Clock out)
CQ, CQ
36 (or 18)
DDR SRAM and Double Data Rate comprise a new family of products developed by Cypress, Renesas, IDT, NEC and Samsung technology.
(or 19)
(or 18)
(or 36) 36 (or 18)
* -F(E)C(I)
F(E) [Package type] : E-Pb Free, F-Pb
C(I) [Operating Temperature] : C-Commercial, I-Industrial
Organiza-
tion
Part
Number
Cycle
Time
Access
Time Unit
X36 K7K1636T2C-F(E)C(I)40 2.5 0.45 ns
K7K1636T2C-F(E)C(I)33 3.0 0.45 ns
X18 K7K1618T2C-F(E)C(I)40 2.5 0.45 ns
K7K1618T2C-F(E)C(I)33 3.0 0.45 ns
ADD
REG
QVLD
512Kx36 & 1Mx18 DDRII+ CIO b2 SRAM
K7K1636T2C
K7K1618T2C
- 4 - Rev. 1.4 August 2008
PIN CONFIGURATIONS(TOP VIEW) K7K1636T2C(512Kx36)
Notes : 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 3A for 36Mb, 10A for 72Mb, 2A for 144Mb .
2. BW0 controls write to DQ0:DQ8, BW1 controls write to DQ9:DQ17, BW2 controls write to DQ18:DQ26 and BW3 controls write to DQ27:DQ35.
12345678910 11
ACQ NC/SA* NC/SA* R/W BW2KBW1LD SA NC/SA* CQ
BNC DQ27 DQ18 SA BW3KBW0SA NC NC DQ8
CNC NC DQ28 VSS SA NC SA VSS NC DQ17 DQ7
DNC DQ29 DQ19 VSS VSS VSS VSS VSS NC NC DQ16
ENC NC DQ20 VDDQ VSS VSS VSS VDDQ NC DQ15 DQ6
FNC DQ30 DQ21 VDDQ VDD VSS VDD VDDQ NC NC DQ5
GNC DQ31 DQ22 VDDQ VDD VSS VDD VDDQ NC NC DQ14
HDoff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
JNC NC DQ32 VDDQ VDD VSS VDD VDDQ NC DQ13 DQ4
KNC NC DQ23 VDDQ VDD VSS VDD VDDQ NC DQ12 DQ3
LNC DQ33 DQ24 VDDQ VSS VSS VSS VDDQ NC NC DQ2
MNC NC DQ34 VSS VSS VSS VSS VSS NC DQ11 DQ1
NNC DQ35 DQ25 VSS SA SA SA VSS NC NC DQ10
PNC NC DQ26 SA SA QVLD SA SA NC DQ9 DQ0
RTDO TCK SA SA SA NC SA SA SA TMS TDI
PIN NAME
Notes:
1. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it
cannot be connected to ground or left unconnected
.
2. Not connected to chip pad internally.
3. K, K can not be set to VREF voltage.
SYMBOL PIN NUMBERS DESCRIPTION NOTE
K, K 6B, 6A Input Clock
QVLD 6P Q Valid output
CQ, CQ 11A, 1A Output Echo Clock
Doff 1H DLL Disable
SA 9A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R Address Inputs
DQ0-35
2B,3B,11B,3C,10C,11C,2D,3D,11D,3E,10E,11E,2F,3F
11F,2G,3G,11G,3J,10J,11J,3K,10K,11K,2L,3L,11L
3M,10M,11M,2N,3N,11N,3P,10P,11P
Data Inputs Outputs
R/W 4A Read, Write Control Pin, Read active
when high
LD 8A Synchronous Load Pin, bus Cycle
sequence is to be defined when low
BW0, BW1,BW2, BW37B,7A,5A,5B Block Write Control Pin,active when low
VREF 2H,10H Input Reference Voltage
ZQ 11H Output Driver Impedance Control Input 1
VDD 5F,7F,5G,7G,5H,7H,5J,7J,5K,7K Power Supply ( 1.8 V )
VDDQ 4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L Output Power Supply ( 1.5 )
VSS 4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,
4M-8M,4N,8N Ground
TMS 10R JTAG Test Mode Select
TDI 11R JTAG Test Data Input
TCK 2R JTAG Test Clock
TDO 1R JTAG Test Data Output
NC
2A,10A,1B,9B,10B,1C,2C,6C,9C,1D,9D,10D,1E,2E,9E,
1F,9F,10F,1G,9G,10G,1J,2J,9J,1K,2K,9K
1L,9L,10L,1M,2M,9M,1N,9N,10N,1P,2P,9P,6R
No Connect 2
512Kx36 & 1Mx18 DDRII+ CIO b2 SRAM
K7K1636T2C
K7K1618T2C
- 5 - Rev. 1.4 August 2008
PIN CONFIGURATIONS(TOP VIEW) K7K1618T2C(1Mx18)
Notes: 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 10A for 36Mb and 2A for 72Mb.
2. BW0 controls write to DQ0:DQ8 and BW1 controls write to DQ9:DQ17.
12345678910 11
ACQ NC/SA* SA R/W BW1KNC LD SA NC/SA* CQ
BNC DQ9 NC SA NC K BW0SA NC NC DQ8
CNC NC NC VSS SA NC SA VSS NC DQ7 NC
DNC NC DQ10 VSS VSS VSS VSS VSS NC NC NC
ENC NC DQ11 VDDQ VSS VSS VSS VDDQ NC NC DQ6
FNC DQ12 NC VDDQ VDD VSS VDD VDDQ NC NC DQ5
GNC NC DQ13 VDDQ VDD VSS VDD VDDQ NC NC NC
HDoff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
JNC NC NC VDDQ VDD VSS VDD VDDQ NC DQ4 NC
KNC NC DQ14 VDDQ VDD VSS VDD VDDQ NC NC DQ3
LNC DQ15 NC VDDQ VSS VSS VSS VDDQ NC NC DQ2
MNC NC NC VSS VSS VSS VSS VSS NC DQ1 NC
NNC NC DQ16 VSS SA SA SA VSS NC NC NC
PNC NC DQ17 SA SA QVLD SA SA NC NC DQ0
RTDO TCK SA SA SA NC SA SA SA TMS TDI
PIN NAME
Notes:
1. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it
cannot be connected to ground or left unconnected
.
2. Not connected to chip pad internally.
3. K, K can not be set to VREF voltage.
SYMBOL PIN NUMBERS DESCRIPTION NOTE
K, K 6B, 6A Input Clock
QVLD 6P Q Valid output
CQ, CQ 11A, 1A Output Echo Clock
Doff 1H DLL Disable
SA 3A,9A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R Address Inputs
DQ0-17 2B,11B,10C,3D,3E,11E,2F,11F,3G,10J,3K,11K,2L,11L
10M,3N,3P,11P Data Inputs Outputs
R/W 4A Read, Write Control Pin, Read active
when high
LD 8A Synchronous Load Pin, bus Cycle
sequence is to be defined when low
BW0, BW17B, 5A Block Write Control Pin,active when low
VREF 2H,10H Input Reference Voltage
ZQ 11H Output Driver Impedance Control Input 1
VDD 5F,7F,5G,7G,5H,7H,5J,7J,5K,7K Power Supply ( 1.8 V )
VDDQ 4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L Output Power Supply ( 1.5V )
VSS 4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N Ground
TMS 10R JTAG Test Mode Select
TDI 11R JTAG Test Data Input
TCK 2R JTAG Test Clock
TDO 1R JTAG Test Data Output
NC
2A,7A,1B,3B,5B,9B,10B,1C,2C,3C,6C,9C,11C,1D,2D,9D,10D
11D,1E,2E,9E,10E,1F,3F,9F,10F,1G,2G,9G,10G,11G
1J,2J,3J,9J,11J,1K,2K,9K,10K,1L,3L,9L,10L
1M,2M,3M,9M,11M,1N,2N,9N,10N,11N,1P,2P,9P,10P,6R
No Connect 2
512Kx36 & 1Mx18 DDRII+ CIO b2 SRAM
K7K1636T2C
K7K1618T2C
- 6 - Rev. 1.4 August 2008
The K7K1636T2C and K7K1618T2C are 18,874,368-bits DDR Common I/O Synchronous Pipelined Burst SRAMs.
They are organized as 524,288 words by 36bits for K7K1636T2C and 1,048,576 words by 18 bits for K7K1618T2C .
Address, data inputs, and all control signals are synchronized to the input clock ( K or K ).
Read data are referenced to echo clock ( CQ or CQ ) outputs.
Read address and write address are registered on rising edges of the input K clocks.
Common address bus is used to access address both for read and write operations.
The internal burst counter is fixed to 2-bit sequential for both read and write operations.
Synchronous pipeline read and late write enable high speed operations.
Simple depth expansion is accomplished by using LD for port selection.
Byte write operation is supported with BW0 and BW1 ( BW2 and BW3) pins for x18 ( x36 ) device.
IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.
The K7K1636T2C and K7K1618T2C are implemented with SAMSUNG's high performance 6T CMOS technology
and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.
GENERAL DESCRIPTION
Read Operations
Read cycles are initiated by initiating R/W as high at the rising edge of the positive input clock K.
Address is presented and stored in the read address register synchronized with K clock.
For 2-bit burst DDR operation, it will access two 36-bit or 18-bit data words with each read command.
The first pipelined data is transfered out of the device triggered by K clock rising edge.
Next burst data is triggered by the rising edge of following K clock rising edge.
Continuous read operations are initated with K clock rising edge.
And pipelined data are transferred out of device on every rising edge of both K and K clocks.
Initial read data latency is 2 clock cycles when DLL is on.
When the LD is disabled after a read operation, the K7K1636T2C and K7K1618T2C will first complete
burst read operation before entering into deselect mode at the next K clock rising edge.
Then output drivers disabled automatically to high impedance state.
Write cycles are initiated by activating R/W as low at the rising edge of the positive input clock K.
Address is presented and stored in the write address register synchronized with next K clock.
For 2-bit burst DDR operation, it will write two 36-bit or 18-bit data words with each write command.
The first "late writed" data is transfered and registered in to the device synchronous with next K clock rising edge.
Next burst data is transfered and registered synchronous with following K clock rising edge.
Continuous write operations are initated with K rising edge.
And "late writed" data is presented to the device on every rising edge of both K and K clocks.
When the LD is disabled, the K7K1636T2C and K7K1618T2C will enter into deselect mode.
The device disregards input data presented on the same cycle R/W disabled.
The K7K1636T2C and K7K1618T2C support byte write operations.
With activating BW0 or BW1 ( BW2 or BW3 ) in write cycle, only one byte of input data is presented.
In K7K1618T2C, BW0 controls write operation to D0:D8, BW1 controls write operation to D9:D17.
And in K7K1636T2C, BW2 controls write operation to D18:D26, BW3 controls write operation to D27:D35.
Write Operations
512Kx36 & 1Mx18 DDRII+ CIO b2 SRAM
K7K1636T2C
K7K1618T2C
- 7 - Rev. 1.4 August 2008
Programmable Impedance Output Buffer Operation
Depth Expansion
The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to VSS through a precision resistor(RQ).
The allowable range of RQ is between 175Ωand 350Ω.
The value of RQ (within 15%) is five times the output impedance desired.
For example, 250Ω resistor will give an output impedance of 50Ω.
Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles.
In all cases impedance updates are transparent to the user and do not produce access time "push-outs"
or other anomalous behavior in the SRAM.
To guarantee optimum output driver impedance after power up, the SRAM needs 1024 non-read cycles.
Each port can be selected and deselected independently with R/W be shared among all SRAMs
and provide a new LD signal for each bank.
Before chip deselected, all read and write pending operations are completed.
Echo clock operation
To assure the output tracibility, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ,
which are synchronized with internal data output. Echo clocks run free during normal operation.
The Echo clock is triggered by internal output clock signal, and transfered to external through same structures as output driver.
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied
simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ
does not exceed VDD by more than 0.5V during power-down.
Power-Up/Power-Down Supply Voltage Sequencing
Output Valid Pin (QVLD)
The Q Valid indicates valid output data. QVLD is activated half cycle before the read data for the receiver to be ready for capturing
the data. QVLD is edge aligned with CQ and CQ.
512Kx36 & 1Mx18 DDRII+ CIO b2 SRAM
K7K1636T2C
K7K1618T2C
- 8 - Rev. 1.4 August 2008
Detail Specification of Power-Up Sequence in DDRII+ SRAM
DDRII+ SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
• Power-Up Sequence
1. Apply power and keep Doff at low state (All other inputs may be undefined)
- Apply VDD before VDDQ
- Apply VDDQ before VREF or the same time with VREF
2. Just after the stable power and clock(K,K), take Doff to be high.
3. The additional 2048 cycles of clock input is required to lock the DLL after enabling DLL
* Notes: If you want to tie up the Doff pin to High with unstable clock, then you must stop the clock for a few seconds
(Min. 30ns) to reset the DLL after it become a stable clock status.
• DLL Constraints
1. DLL uses K clock as its synchronizing input, the input should have low phase jitter which is specified as TK var.
2. The lower end of the frequency at which the DLL can operate is 120MHz.
3. If the incoming clock is unstable and the DLL is enabled, then the DLL may lock onto a wrong frequency
and this may cause the failure in the initial stage.
Status
Power-Up
K,K
* Notes: When the operating frequency is changed, DLL reset should be required again.
After DLL reset again, the minimum 2048 cycles of clock input is needed to lock the DLL.
~
~
Unstable
CLKstage
2048 cycle
~
~
DLL Locking Range Any
Command
Power up & Initialization Sequence (Doff pin Fixed high, Clock controlled)
K,K
~
~
Min 30ns
V
DD
V
DDQ
V
REF
Doff
V
DD
V
DDQ
V
REF
~
~
~
~
2048 cycle
~
~
Status
Power-Up Unstable
CLKstage DLL Locking Range Any
Command
Stop Clock
~
~
Inputs Clock
must be stable
~
~
~
~
~
~
~
~
~
~
~
~
~
~
Power up & Initialization Sequence (Doff pin controlled)
Inputs Clock
must be stable
512Kx36 & 1Mx18 DDRII+ CIO b2 SRAM
K7K1636T2C
K7K1618T2C
- 9 - Rev. 1.4 August 2008
WRITE TRUTH TABLE(x18)
Notes: 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ↑ ).
3. Assumes a WRITE cycle was initiated.
4. This table illustates operation for x18 devices.
K K BW0BW1OPERATION
↑L L WRITE ALL BYTEs ( K↑ )
↑L L WRITE ALL BYTEs ( K↑ )
↑L H WRITE BYTE 0 ( K↑ )
↑L H WRITE BYTE 0 ( K↑ )
↑H L WRITE BYTE 1 ( K↑ )
↑H L WRITE BYTE 1 ( K↑ )
↑H H WRITE NOTHING ( K↑ )
↑H H WRITE NOTHING ( K↑ )
WRITE TRUTH TABLE(x36)
Notes: 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ↑ ).
3. Assumes a WRITE cycle was initiated.
K K BW0BW1BW2BW3OPERATION
↑LLLL WRITE ALL BYTEs ( K↑ )
↑LLLL WRITE ALL BYTEs ( K
↑ )
↑L H H H WRITE BYTE 0 ( K↑ )
↑L H H H WRITE BYTE 0 ( K↑ )
↑H L H H WRITE BYTE 1 ( K↑ )
↑H L H H WRITE BYTE 1 ( K↑ )
↑H H L L WRITE BYTE 2 and BYTE 3 ( K↑ )
↑H H L L WRITE BYTE 2 and BYTE 3 ( K↑ )
↑H H H H WRITE NOTHING ( K↑ )
↑H H H H WRITE NOTHING ( K↑ )
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
Notes: 1. X means "Don′t Care".
2. The rising edge of clock is symbolized by ( ↑ ).
3. Before enter into clock stop status, all pending read and write operations will be completed.
KLD R/W DQ OPERATION
DQ(A1) DQ(A2)
Stopped X X Previous state Previous state Clock Stop
↑H X High-Z High-Z No Operation
↑LHQ
OUT at K(t+2) QOUT at K(t+2) Read
↑L L Din at K(t+1) Din at K(t+1) Write
512Kx36 & 1Mx18 DDRII+ CIO b2 SRAM
K7K1636T2C
K7K1618T2C
- 10 - Rev. 1.4 August 2008
ABSOLUTE MAXIMUM RATINGS
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
PARAMETER SYMBOL RATING UNIT
Voltage on VDD Supply Relative to VSS VDD -0.5 to 2.9 V
Voltage on VDDQ Supply Relative to VSS VDDQ -0.5 to VDD V
Voltage on Input Pin Relative to VSS VIN -0.5 to VDD+0.3 V
Storage Temperature TSTG -65 to 150 °C
Operating Temperature Commercial / Industrial TOPR 0 to 70 / -40 to 85 °C
Storage Temperature Range Under Bias TBIAS -10 to 85 °C
OPERATING CONDITIONS (0°C ≤ TA ≤ 70°C)
Note: 1. VDDQ must not exceed VDD during normal operation.
2. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring
timing parameters.
3. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.5V(pulse width ≤ 3ns).
4. VIH (Max)DC=VDDQ+0.3V, VIH (Max)AC=VDDQ+0.85V(pulse width ≤ 3ns).
5. Overshoot : VIH (AC) ≤ VDDQ+0.5V for t ≤ 50% tKHKH(MIN).
Undershoot : VIL (AC) ≤ VSS-0.5V for t ≤ 50% tKHKH(MIN).
6. This condition is for AC function test only, not for AC parameter test.
7. To maintain a valid level, the transitioning edge of the input must :
a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC)
b) Reach at least the target AC level
c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC)
PARAMETER SYMBOL MIN TYP MAX UNIT
Supply Voltage VDD 1.7 1.8 1.9 V
VDDQ 1.4 1.5 1.6 V
Reference Voltage VREF 0.7 0.75 0.8 V
Input Low Voltage(DC) 2,3) VIL(DC) -0.3 - VREF-0.1 V
Input High Voltage(DC) 2,4) VIH(DC) VREF+0.1 - VDDQ+0.3 V
Input High Voltage(AC) 6,7) VIL(AC) VREF + 0.2 - - V
Input Low Voltage(AC) 6,7) VIH(AC) --VREF - 0.2 V
512Kx36 & 1Mx18 DDRII+ CIO b2 SRAM
K7K1636T2C
K7K1618T2C
- 11 - Rev. 1.4 August 2008
DC ELECTRICAL CHARACTERISTICS (VDD=1.8V ±0.1V, TA=0°C to +70°C)
Notes: 1. Minimum cycle. IOUT=0mA.
2. |IOH|=(VDDQ/2)/(RQ/5)±15% for 175Ω ≤ RQ ≤ 350Ω. |IOL|=(VDDQ/2)/(RQ/5)±15% for 175Ω ≤ RQ ≤ 350Ω.
3. Minimum Impedance Mode when ZQ pin is connected to VDD.
4. Operating current is calculated with 100% read cycles or 100% write cycles.
5. Standby Current is only after all pending read and write burst opeactions are completed.
6. Programmable Impedance Mode.
PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNIT NOTES
Input Leakage Current IIL VDD=Max ; VIN=VSS to VDDQ -2 +2 µA
Output Leakage Current IOL Output Disabled, -2 +2 µA
Operating Current (x36): QDR ICC VDD=Max , IOUT=0mA
Cycle Time ≥ tKHKH Min
-40 - 900 mA 1,4
-33 - 800
Operating Current (x18): QDR ICC VDD=Max , IOUT=0mA
Cycle Time ≥ tKHKH Min
-40 - 800 mA 1,4
-33 - 700
Standby Current(NOP): QDR ISB1 Device deselected,
IOUT=0mA, f=Max,
All Inputs≤0.2V or ≥ VDD-0.2V
-40 - 350
mA 1,5
-33 - 300
Output High Voltage VOH1 VDDQ/2-0.12 VDDQ/2+0.12 V 2,6
Output Low Voltage VOL1 VDDQ/2-0.12 VDDQ/2+0.12 V 2,6
Output High Voltage VOH2 IOH=-1.0mA VDDQ-0.2 VDDQ V3
Output Low Voltage VOL2 IOL=1.0mA VSS 0.2 V 3
512Kx36 & 1Mx18 DDRII+ CIO b2 SRAM
K7K1636T2C
K7K1618T2C
- 12 - Rev. 1.4 August 2008
AC TIMING CHARACTERISTICS (VDD=1.8V±0.1V, TA=0°C to +70°C)
Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control signals are R/ W and LD.
However BWx does not apply to this parameters. BWx signals obey the data setup and hold times.
3. To avoid bus contention, at a given voltage and temperature tKLZ is bigger than tKHZ.
The specs as shown do not imply bus contention because tKLZ is a MIN parameter that is worst case at totally different test conditions
(0°C, 1.9V) than tKHZ, which is a MAX parameter(worst case at 70°C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
4. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
5. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
6. This parameter is extrapolated from the input timing parameters (tKHKH - 200ps where 200ps is the internal jitter.) This parameter is only
guaranteed by design and not tested in production.
PARAMETER SYMBOL -40 -33 UNIT NOTE
MIN MAX MIN MAX
Clock
Clock Cycle Time (K, K)tKHKH 2.5 8.4 3.0 8.4 ns
Clock Phase Jitter (K, K)tK var 0.20 0.20 ns 4
Clock High Time (K, K)tKHKL 0.4 0.4 ns
Clock Low Time (K, K)tKLKH 0.4 0.4 ns
Clock to Clock (K↑ → K↑)tKHKH1.06 1.3 ns
DLL Lock Time (K) tK lock 2048 2048 cycle 5
K Static to DLL reset tK reset 30 30 ns
Output Times
K, K High to Output Valid tKHQV 0.45 0.45 ns
K, K High to Output Hold tKHQX -0.45 -0.45 ns
K, K High to Echo Clock Valid tKHCQV 0.45 0.45 ns
K, K High to Echo Clock Hold tKHCQX -0.45 -0.45 ns
CQ, CQ High to Output Valid tCQHQV 0.2 0.2 ns
CQ, CQ High to Output Hold tCQHQX -0.2 -0.2 ns
CQ High to CQ High tCQHCQH0.86 1.1 ns 6
K, K High to Output High-Z tKHZ 0.45 0.45 ns
K, K High to Output Low-Z tKLZ -0.45 -0.45 ns
CQ, CQ High to QVLD Valid tQVLD -0.2 0.2 -0.2 0.2 ns
Setup Times
Address valid to K rising edge tAVKH 0.40 0.40 ns
Control inputs valid to K rising edge tIVKH 0.40 0.40 ns 2
Data-in valid to K, K rising edge tDVKH 0.28 0.28 ns
Hold Times
K rising edge to address hold tKHAX 0.40 0.40 ns
K rising edge to control inputs hold tKHIX 0.40 0.40 ns
K, K rising edge to data-in hold tKHDX 0.28 0.28 ns
512Kx36 & 1Mx18 DDRII+ CIO b2 SRAM
K7K1636T2C
K7K1618T2C
- 13 - Rev. 1.4 August 2008
THERMAL RESISTANCE
Note: Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site
thermal impedance. TJ=TA + PD x θJA
PRMETER SYMBOL TYP Unit NOTES
Junction to Ambient θJA 20.8 °C/W
Junction to Case θJC 2.3 °C/W
Junction to Pins θJB 4.3 °C/W
PIN CAPACITANCE
Note: 1. Parameters are tested with RQ=250Ω and VDDQ=1.5V.
2. Periodically sampled and not 100% tested.
PRMETER SYMBOL TESTCONDITION TYP MAX Unit NOTES
Address Control Input Capacitance CIN VIN=0V 3.5 4 pF
Input and Output Capacitance COUT VOUT=0V 4 5 pF
Clock Capacitance CCLK -34pF
VDDQ/2
50Ω
SRAM Zo=50Ω
0.75V
VREF
ZQ
250Ω
AC TEST OUTPUT LOAD
AC TEST CONDITIONS
Note: Parameters are tested with RQ=250Ω
Parameter Symbol Value Unit
Core Power Supply Voltage VDD 1.7~1.9 V
Output Power Supply Voltage VDDQ 1.4~1.6 V
Input High/Low Level VIH/VIL 1.25/0.25 V
Input Reference Level VREF 0.75 V
Input Rise/Fall Time TR/TF0.3/0.3 ns
Output Timing Reference Level VDDQ/2 V
512Kx36 & 1Mx18 DDRII+ CIO b2 SRAM
K7K1636T2C
K7K1618T2C
- 14 - Rev. 1.4 August 2008
APPLICATION INRORMATION
SRAM#1
SA R/W BW0
DQ
ZQ
K
SRAM#4
R
Vt
R=50Ω Vt=VREF
Vt
R
R=250ΩR=250Ω
BW1KSA R/WLD3BW0
CQ
ZQ
KBW1K
DQ
Address
R/W
LD
BW
Return CLK
Source CLK
Return CLK
Source CLK
MEMORY
CONTROLLER
LD0
DQ
CQ
CQ
CQ
SRAM1 Input CQ
SRAM1 Input CQ
SRAM4 Input CQ
SRAM4 Input CQ
512Kx36 & 1Mx18 DDRII+ CIO b2 SRAM
K7K1636T2C
K7K1618T2C
- 15 - Rev. 1.4 August 2008
NOP
K
K
SA
12 3456781012
11
LD
READ
WRITE
9
t
KHKH
UNDEFINED
DON
′
T CARE
NOTE
1. Q1-1 refers to output from address A1. Q1-2 refers to output from the next internal burst address following A, etc.
2. Outputs are disabled(High-Z) two clock cycle after a NOP .
3. Two NOP cycle is the mandatory and 3rd NOP cycle is not necessary for correct DDRII+ READ/WRITE operation.
However at high clock frequencies, considering the delay of real system board condition, it may be required to prevent bus contention.
t
KHKH
t
KLKH
R/W
NOP
t
KHKL
TIMING WAVE FORMS OF READ, WRITE AND NOP
NOP WRITE
READ
NOP NOP
NOP
(Note3)
DQ
CQ
CQ
QVLD
t
IVKH
t
KHIX
A
1
A
4
A
2
A
3
A
5
t
QVLD
Q1-1 Q1-2
t
KHQV
t
KHQX
t
KHCQV
D2-1 D2-2 D5-1 D5-2Q3-1 Q3-2 Q4-1 Q4-2
READ
WRITE
A
6
t
CQHQV
512Kx36 & 1Mx18 DDRII+ CIO b2 SRAM
K7K1636T2C
K7K1618T2C
- 16 - Rev. 1.4 August 2008
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not
driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-
ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,
therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without
interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an
undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be
tied to VDD through a resistor. TDO should be left unconnected.
TAP Controller State Diagram
JTAG Block Diagram
SRAM
CORE
BYPASS Reg.
Identification Reg.
Instruction Reg.
Control Signals
TAP Controller
TDO
TDI
TMS
TCK
Test Logic Reset
Run Test Idle
011
1
1
0
0
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
1
1
1
1
1
JTAG Instruction Coding
NOTE :
1. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs. This instruction is not IEEE 1149.1 compliant.
2. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs.
3. TDI is sampled as an input to the first ID register to allow for the serial shift
of the external TDI data.
4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The
Bypass Register also holds serially loaded TDI when exiting the Shift DR
states.
5. SAMPLE instruction dose not places DQs in Hi-Z.
6. This instruction is reserved for future use.
IR2 IR1 IR0 Instruction TDO Output Notes
0 0 0 EXTEST Boundary Scan Register 1
0 0 1 IDCODE Identification Register 3
0 1 0 SAMPLE-Z Boundary Scan Register 2
0 1 1 RESERVED Do Not Use 6
1 0 0 SAMPLE Boundary Scan Register 5
1 0 1 RESERVED Do Not Use 6
1 1 0 RESERVED Do Not Use 6
1 1 1 BYPASS Bypass Register 4
512Kx36 & 1Mx18 DDRII+ CIO b2 SRAM
K7K1636T2C
K7K1618T2C
- 17 - Rev. 1.4 August 2008
ID REGISTER DEFINITION
Note : Part Configuration
/def=001 for 18Mb, /wx=11 for x36, 10 for x18
/t=1 for DLL Ver., 0 for non-DLL Ver. /q=1 for QDR, 0 for DDR /b=1 for 4Bit Burst, 0 for 2Bit Burst /s=1 for Separate I/O, 0 for Common I/O
Part Revision Number
(31:29)
Part Configuration
(28:12)
Samsung JEDEC Code
(11: 1) Start Bit(0)
512Kx36 000 00def0wx0t0q0b0s0 00011001110 1
1Mx18 000 00def0wx0t0q0b0s0 00011001110 1
SCAN REGISTER DEFINITION
Part Instruction Register Bypass Register ID Register Boundary Scan
512Kx36 3 bits 1 bit 32 bits 107 bits
1Mx18 3 bits 1 bit 32 bits 107 bits
Note: 1. NC pins are read as "X" ( i.e. don′t care.)
ORDER PIN ID
37 10D
38 9E
39 10C
40 11D
41 9C
42 9D
43 11B
44 11C
45 9B
46 10B
47 11A
48 10A
49 9A
50 8B
51 7C
52 6C
53 8A
54 7A
55 7B
56 6B
57 6A
58 5B
59 5A
60 4A
61 5C
62 4B
63 3A
64 2A
65 1A
66 2B
67 3B
68 1C
69 1B
70 3D
71 3C
72 1D
ORDER PIN ID
73 2C
74 3E
75 2D
76 2E
77 1E
78 2F
79 3F
80 1G
81 1F
82 3G
83 2G
84 1H
85 1J
86 2J
87 3K
88 3J
89 2K
90 1K
91 2L
92 3L
93 1M
94 1L
95 3N
96 3M
97 1N
98 2M
99 3P
100 2N
101 2P
102 1P
103 3R
104 4R
105 4P
106 5P
107 5N
108 5R
109 Internal
ORDER PIN ID
16R
26P
36N
47P
57N
67R
78R
88P
99R
10 11P
11 10P
12 10N
13 9P
14 10M
15 11N
16 9M
17 9N
18 11L
19 11M
20 9L
21 10L
22 11K
23 10K
24 9J
25 9K
26 10J
27 11J
28 11H
29 10G
30 9G
31 11F
32 11G
33 9F
34 10F
35 11E
36 10E
BOUNDARY SCAN EXIT ORDER
512Kx36 & 1Mx18 DDRII+ CIO b2 SRAM
K7K1636T2C
K7K1618T2C
- 18 - Rev. 1.4 August 2008
JTAG DC OPERATING CONDITIONS
Note: 1. The input level of SRAM pin is to follow the SRAM DC specification.
Parameter Symbol Min Typ Max Unit Note
Power Supply Voltage VDD 1.7 1.8 1.9 V
Input High Level VIH 1.3 - VDD+0.3 V
Input Low Level VIL -0.3 - 0.5 V
Output High Voltage(IOH=-2mA) VOH 1.4 - VDD V
Output Low Voltage(IOL=2mA) VOL VSS -0.4V
JTAG TIMING DIAGRAM
JTAG AC Characteristics
Parameter Symbol Min Max Unit Note
TCK Cycle Time tCHCH 50 - ns
TCK High Pulse Width tCHCL 20 - ns
TCK Low Pulse Width tCLCH 20 - ns
TMS Input Setup Time tMVCH 5-ns
TMS Input Hold Time tCHMX 5-ns
TDI Input Setup Time tDVCH 5-ns
TDI Input Hold Time tCHDX 5-ns
SRAM Input Setup Time tSVCH 5-ns
SRAM Input Hold Time tCHSX 5-ns
Clock Low to Output Valid tCLQV 010ns
JTAG AC TEST CONDITIONS
Note: 1. See SRAM AC test output load on page 11.
Parameter Symbol Min Unit Note
Input High/Low Level VIH/VIL 1.8/0.0 V
Input Rise/Fall Time TR/TF 1.0/1.0 ns
Input and Output Timing Reference Level 0.9 V 1
TCK
TMS
TDI
PI
tCHCH
tMVCH tCHMX
tCHCL tCLCH
tDVCH tCHDX
tCLQV
TDO
(SRAM)
tSVCH tCHSX
512Kx36 & 1Mx18 DDRII+ CIO b2 SRAM
K7K1636T2C
K7K1618T2C
- 19 - Rev. 1.4 August 2008
165 FBGA PACKAGE DIMENSIONS
CSide View
13mm x 15mm Body, 1.0mm Bump Pitch, 11x15 Ball Array
FB
∅ H
G
A
Bottom View
Top View
B
A
D
E
E
Symbol Value Units Note Symbol Value Units Note
A13 ± 0.1 mm E1.0 mm
B15 ± 0.1 mm F14.0 mm
C1.3 ± 0.1 mm G10.0 mm
D0.35 ± 0.05 mm H0.5 ± 0.05 mm
