FQD17N08L - Fairchild - Product.Network

December 2000

Rev. A2, December 2000

FQD17N08L / FQU17N08L

QFET

QFETQFET

QFETTM

FQD17N08L / FQ U17N08L

80V LOGIC N-Channel MOSFET

General Description

These N-Channel enhancement mode power field effect

transistors are produced using Fairchild’s proprietary,

planar stripe, DMOS technology.

This advanced technology is especially tailored to minimize

on-state resistance, provide superior switching

performance, and withstand a high energy pulse in the

avalanche and commutation modes. These devices are

well suited for low voltage appl ications such as automotive,

high efficiency switching for DC/DC converters, and DC

motor control.

Features

• 12.9A, 80V, RDS(on) = 0.1Ω @VGS = 10 V

• Low gate charge ( typical 8.8 nC)

• Low Crss ( typical 29 pF)

• Fast switching

• 100% avalanche tested

• Improved dv/dt capability

• Low level gate drive requirements allowing

direct operation from logic drives

Absolute Maxim um Ratings TC = 25°C unless otherwise noted

Thermal Char acteristics

Symbol Parameter FQD17N08L / FQU17N08L Units

VDSS Drain-Source Voltage 80 V

IDDrain Current - Continuous (TC = 25°C) 12.9 A

- Continuous (TC = 100°C) 8.2 A

IDM Drain Current - Pulsed (Note 1) 51.6 A

VGSS Gate-Source Voltage ± 20 V

EAS Single Pulsed Avalanche Energy (Note 2) 100 mJ

IAR Avalanche Current (Note 1) 12.9 A

EAR Repetitive Avalanche Energy (Note 1) 4.0 mJ

dv/dt Peak Diode Recovery dv/dt (Note 3) 6.5 V/ns

PDPower Dissipation (TA = 25°C) * 2.5 W

Power Dissipation (TC = 25°C) 40 W

- Derate above 25°C 0.32 W/°C

TJ, TSTG Operating and Storage Temperature Range -55 to +150 °C

TLMaximum lead temperature for soldering purposes,

1/8” from case for 5 seconds 300 °C

Symbol Parameter Typ Max Units

RθJC Thermal Resistance, Junction-to-Case -- 3.13 °C/W

RθJA Thermal Resistance, Junction-to-Ambient * -- 50 °C/W

RθJA Thermal Resistance, Junction-to-Ambient -- 110 °C/W

* When mounted on the minimum pad size recommended (PCB Mount)

I-PAK

FQU Series

D-P AK

FQD Series GS

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Rev. A2, December 2000

FQD17N08L / FQU17N08L

(Note 4)

(Note 4, 5)

(Note 4)

Electrical Characteristics TC = 25°C unless otherwise noted

Notes:

1. Repetitive Rating : Pulse width limited by maximum junction temperature

2. L = 0.83mH, IAS = 12.9A, VDD = 25V, RG = 25 Ω, Starting TJ = 25°C

3. ISD ≤ 16.5A, di/dt ≤ 300A/µs, VDD ≤ BVDSS, Starting TJ = 25°C

4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%

5. Essentially independent of operating temperature

Symbol Parame ter Test Condit i ons Min Typ Max Units

Off Characteristics

BVDSS Drain-S ource Breakdown Voltage VGS = 0 V, I D = 250 µA80 -- -- V

∆BVDSS

/ ∆TJ

Breakdown Vo ltage Temperature

Coefficient ID = 250 µA, Referenced to 25°C -- 0.08 -- V/°C

IDSS Zero Gate Voltage Drain Current VDS = 80 V, VGS = 0 V -- -- 1 µA

VDS = 64 V, TC = 125°C -- -- 10 µA

IGSSF Gate-Body Leakage Current, Forward VGS = 20 V, VDS = 0 V -- -- 100 nA

IGSSR Gate-Body Leakage Current, Reverse VGS = -20 V, VDS = 0 V -- -- -100 nA

On Characteri st ics

VGS(th) Gate Threshold Volt age VDS = VGS, ID = 250 µA1.0 -- 2.0 V

RDS(on) Static Drain-Source

On-Resistance VGS = 10 V, ID = 6.45 A

VGS = 5 V, I D = 6.45 A -- 0.076

0.090 0.100

0.115 Ω

gFS Forward Transconductance VDS = 25 V, ID = 6.45 A -- 11.7 -- S

Dynamic Characteristics

Ciss Input Capacitance VDS = 25 V, VGS = 0 V,

f = 1.0 MHz

-- 400 520 pF

Coss Output Capacitance -- 120 155 pF

Crss Reverse Transfer Capacit ance -- 29 37 pF

Switching Characteristics

td(on) Turn-On Delay Time VDD = 40 V, ID = 16.5 A,

RG = 25 Ω

-- 7 25 ns

trTurn-On Rise Time -- 290 590 ns

td(off) Turn-Off Del a y Time -- 20 50 ns

tfTurn-Off Fa ll Time -- 75 160 n s

QgTotal Gate Ch arge VDS = 64 V, ID = 16.5 A,

VGS = 5 V

-- 8.8 11.5 nC

Qgs Gate-Source Charge -- 2.0 -- nC

Qgd Gate-Drain Charge -- 5.4 -- nC

Drain-Source Diode Characteristics and Maximum Ratings

ISMaximum Continuous Drain-Source Diode Forward Current -- -- 12.9 A

ISM Maximum Pulsed Drain-Source Diode Forward Current -- -- 51.6 A

VSD Drain-Source Diode Forward V oltage VGS = 0 V, I S = 12.9 A -- -- 1.5 V

trr Reverse Recovery Time VGS = 0 V, I S = 16.5 A,

dIF / dt = 100 A/µs

-- 55 -- ns

Qrr Reverse Recovery Charge -- 85 -- nC

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FQD17N08L / FQU17N08L

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

10-1

100

101

25℃

150℃※ Notes :

1. VGS = 0V

2. 250μ

s Pu lse T es t

IDR , Reverse Drain Current [A]

VSD , Source-Drain Voltage [V]

0246810

10-1

100

101

※ No tes :

1. VDS = 25V

2. 250μ

s Pulse Test

-55℃

150℃

25℃

ID , Drain Cu r re n t [A]

VGS , G ate-Sou r c e Voltag e [V ]

10-1 100101

100

101

VGS

Top : 10.0 V

8.0 V

6.0 V

5.0 V

4.5 V

4.0 V

3.5 V

Bo tto m : 3 .0 V

※ Notes :

1. 250μ

s Pu lse Te st

2. TC = 25℃

ID, Drain Current [A]

VDS, Drain-Source Voltage [V]

0 2 4 6 8 10121416

VDS = 40V

VDS = 64V

※ Note : ID = 16.5A

VGS, Gate-Source Voltage [V]

QG, T otal Gate Charge [nC ]

10-1 100101

100

200

300

400

500

600

700

800

900

1000

1100 Ciss = Cgs + Cgd (Cds = shorted)

Coss = C ds + Cgd

Crss = Cgd

※ Notes :

1. V GS = 0 V

2. f = 1 MHz

Crss

Coss

Ciss

Capacitance [pF]

VDS, Drain-Source Voltage [V]

0 1020304050

0.0

0.1

0.2

0.3

0.4

※ N o te : TJ = 25℃

VGS = 10V

VGS = 5V

RDS(on) [Ω],

Drain-Source O n-Resistance

ID , Dr a in C u rrent [A]

Typical Characteristics

Figure 5. Capacitanc e C haracteri st i cs Figure 6. Gate Char ge Character is tics

Figure 3. On-Resist anc e Variation vs.

Drain Current and Gate Voltage Figure 4. Body Diode Fo rwa rd Voltage

Variation vs. Source Current

and Temperature

Figure 2. Transfer CharacteristicsFigure 1. On- R egi on Charact er ist ic s

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FQD17N08L / FQU17N08L

Rev. A2, December 2000

10-5 10-4 10-3 10-2 10-1 100101

10-1

100

※ No tes :

1 . Z θJC(t) = 3.13 ℃/W M ax .

2 . D u ty Fa c to r , D= t1/t2

3 . T JM - T C = PDM * Z θJC(t)

single pulse

D=0.5

0.02

0.2

0.05

0.1

0.01

ZθJC

(t), Therm al Response

t1, Sq u a re W a ve P u ls e Du ra tio n [se c ]

25 50 75 100 125 150

ID, Drain Current [A]

TC, Case Temperature [℃

]

100101102

10-1

100

101

102

DC 10 ms

1 ms 100 µs

Operation in This Area

is Limited by R DS(on)

※ Notes :

1. TC = 25 oC

2. TJ = 150 oC

3. Single Pulse

ID, Drain Current [A]

VDS, Drain-Source Voltage [V]

-100 -50 0 50 100 150 200

0.0

0.5

1.0

1.5

2.0

2.5

3.0

※ Notes :

1. VGS = 10 V

2. ID = 6.45 A

RDS(ON) , (Normalized)

Drain-Source On-Resistance

TJ, Junction Temperature [oC]

-100 -50 0 50 100 150 200

0.8

0.9

1.0

1.1

1.2

※ Notes :

1 . VGS = 0 V

2 . ID = 250 μ

BV DSS , (N ormaliz e d )

Drain-Source Breakdown V oltage

TJ, Junction Tempe rature [oC]

Typical Characteristics (Continued)

Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current

vs. Case Temperature

Figu re 7. Breakdown Volta g e Variat i on

vs. Temperature Figure 8. On-Resistance Variation

vs. Temperature

Figure 11. Tr ansient Thermal Res pons e Cur ve

PDM

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FQD17N08L / FQU17N08L

Charge

VGS

5V Qg

Qgs Qgd

3mA

VGS

DUT

VDS

300nF

50KΩ

200nF

12V

Same Type

as DUT

Charge

VGS

5V Qg

Qgs Qgd

3mA

VGS

DUT

VDS

300nF

50KΩ

200nF

12V

Same Type

as DUT

VGS

VDS

10%

90%

td(on) tr

ton toff

td(off) tf

VDD

VDS RL

DUT

VGS

VDS

10%

90%

td(on) tr

ton toff

td(off) tf

VDD

VDS RL

DUT

VGS

EAS =LI

AS2

----

1--------------------

BVDSS -V

BVDSS

VDD

VDS

BVDSS

t p

VDD

IAS

VDS (t)

ID (t)

Time

10V DUT

t p

EAS =LI

AS2

----

EAS =LI

AS2

----

1--------------------

BVDSS -V

BVDSS

VDD

VDS

BVDSS

t p

VDD

IAS

VDS (t)

ID (t)

Time

10V DUT

t p

Gate Charge Test Circuit & Waveform

Resistive Switching Test Circuit & Waveforms

Unclamped Inductive Switching Test Circuit & Waveforms

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FQD17N08L / FQU17N08L

Rev. A2, December 2000

Peak Diode Recover y dv/dt Test Circ ui t & Waveform s

DUT

VDS

Driver

RGSame Typ e

as DUT

VGS • dv/dt controlled by RG

•I

SD con trolled by pulse per iod

VDD

ISD

10V

VGS

( Driver )

ISD

( DUT )

VDS

( DUT )

VDD

Body Diode

Forward Voltage Drop

VSD

IFM , Body Diode Forward Current

Body Diode Reverse Current

IRM

Body Diode Recovery dv/dt

di/dt

D = Gate Pulse Width

Gate Pu lse P eri od

--------------------------

DUT

VDS

Driver

RGSame Typ e

as DUT

VGS • dv/dt controlled by RG

•I

SD con trolled by pulse per iod

VDD

ISD

10V

VGS

( Driver )

ISD

( DUT )

VDS

( DUT )

VDD

Body Diode

Forward Voltage Drop

VSD

IFM , Body Diode Forward Current

Body Diode Reverse Current

IRM

Body Diode Recovery dv/dt

di/dt

D = Gate Pulse Width

Gate Pu lse P eri od

--------------------------

D = Gate Pulse Width

Gate Pu lse P eri od

--------------------------

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FQD17N08L / FQU17N08L

Package Dimensions

6.60 ±0.20

2.30 ±0.10

0.50 ±0.10

5.34 ±0.30

0.70 ±0.20

0.60 ±0.20

0.80 ±0.20

9.50 ±0.30

6.10 ±0.20

2.70 ±0.20 9.50 ±0.30

6.10 ±0.20

2.70 ±0.20

MIN0.55

0.76 ±0.10 0.50 ±0.10

1.02 ±0.20

2.30 ±0.20

6.60 ±0.20

0.76 ±0.10

(5.34)

(1.50)

(2XR0.25)

(5.04)

0.89 ±0.10

(0.10) (3.05)

(1.00)

(0.90)

(0.70)

0.91 ±0.10

2.30TYP

[2.30±0.20]

2.30TYP

[2.30±0.20]

MAX0.96

(4.34)(0.50) (0.50)

DPAK

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FQD17N08L / FQU17N08L

Rev. A2, December 2000

Package Dimensions (Continued)

6.60 ±0.20

0.76 ±0.10

MAX0.96

2.30TYP

[2.30±0.20] 2.30TYP

[2.30±0.20]

0.60 ±0.20

0.80 ±0.10

1.80 ±0.20

9.30 ±0.30

16.10 ±0.30

6.10 ±0.20

0.70 ±0.20

5.34 ±0.20

0.50 ±0.10

2.30 ±0.20

(0.50) (0.50)(4.34)

IPAK

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PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY

LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;

NEITHER DOES IT CONVEY A NY LICENSE UNDER ITS PATENT RIGHTS, N OR THE RIGHTS OF OTHERS.

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which, (a) ar e intended for surgical implant into the body,

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when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

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PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In

Design This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semiconduct or reserv es the right to make

changes at any time without notice in order to improve

design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at

any time without notice in order to improve design.

Obsolete Not In Production This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.

Rev. F1

VCX™

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