TI Confidential - NDA Restrictions LM49151 www.ti.com SNAS482F - MARCH 2009 - REVISED MARCH 2013 LM49151 BoomerTM Audio Power Amplifier Series Mono Class D Audio Subsystem with Earpiece Driver, Ground Referenced Headphone Amplifiers, Speaker Protection and No Clip with Clip Control Check for Samples: LM49151 FEATURES 1 * * 23 * * * * * * * * 2 E S Class D Amplifier Ground Referenced Outputs -- Eliminates Output Coupling Capacitors I2C Programmable No Clip Function with Clip Control Voltage Limiter Speaker Protection I2C Volume and Mode Control Ear Piece Amplifier Advanced Click-and-Pop Suppression Low Supply Current Micro-Power Shutdown 20-bump DSBGA Package APPLICATIONS * * * * * Mobile Phones PDAs Notebook PCs Portable Electronics Devices MP3 Players KEY SPECIFICATIONS * * * Output Power at VDD = 3.3V THD+N 1% - LS Mode, RL = 8 520mW (Typ) - HP Mode, RL = 32 40mW (Typ) Output Power at VDD = 5V THD+N 1% - LS Mode, RL = 8 1.25W (Typ) - HP Mode, RL = 32 42mW (Typ) Output Offset - LS Mode 15 6mV (Typ) - HP Mode 15 2mV (Typ) DESCRIPTION The LM49151 is a fully integrated audio subsystem designed for portable handheld applications such as cellular phones. The LM49151 combines a 1.25W mono E2S class D amplifier, 125mW Class AB earpiece driver, 42mW/channel stereo ground referenced headphone drivers, volume control, input mixer/multiplexer, and speaker protection into a single device. The LM49151 class D speaker amplifier features Texas Instruments' unique Automatic Level Control (ALC) that provides both a I2C programmable no-clip feature with Clip Controls and speaker protection. The E2S (Enhanced Emission Suppression) class D amplifier features a patented, ultra low EMI PWM architecture that significantly reduces RF emissions while preserving audio quality and efficiency while delivering 1.25W into an 8 load with <1% THD+N with a 5V supply. The 42mW/channel headphone drivers feature Texas Instruments' ground referenced architecture that creates a ground-referenced output from a single supply, eliminating the need for bulky and expensive DC-blocking capacitors, saving space and minimizing system cost. The LM49151 features separate volume controls for the loudspeaker and headphone inputs. Mode selection, shutdown control, and volume are controlled through an I2C compatible interface. The LM49151's superior click and pop suppression eliminates audible transients on power-up/down and during shutdown. 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Boomer is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2009-2013, Texas Instruments Incorporated TI Confidential - NDA Restrictions LM49151 SNAS482F - MARCH 2009 - REVISED MARCH 2013 www.ti.com Typical Application VDD LSVDD Cs1 Cs2 Cs3 10 F 1 F 1 F BYPASS Ci 1 F INM+ Audio Differential Input VOLUME -80 dB to +18 dB INMCi 1 F LSOUT- SET INL LDO VOLUME -80 dB to +18 dB CSET RSET 0.1 F (Optional) MIXER AND OUTPUT MODE SELECT Ci Audio Single-Ended Inputs LSOUT+ CLASS D +12 dB, +18 dB ALC -6 dB 0.22 F INR HPL -18 dB to 0 dB VOLUME -80 dB to +18 dB Ci 0.22 F BYPASS -18 dB to 0 dB BIAS CB HPR 2.2 F 2 I CVDD SDA CHARGE PUMP 2 I C INTERFACE SCL CPP GND CPVSS 2.2 F CPN CPGND C1 2.2 F Figure 1. Typical Audio Amplifier Application Circuit 2 Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 TI Confidential - NDA Restrictions LM49151 www.ti.com SNAS482F - MARCH 2009 - REVISED MARCH 2013 Connection Diagram 4 LSOUT+ LSVDD CPVSS C1P CPGND 3 LSOUT- SCL BYPASS C1N HPL 2 GND SDA INR SET HPR 1 I CVDD VDD INL INM- INM+ A B C D E 2 Figure 2. 20 Bump DSBGA Package Top View (See Package Number YZR0020) BUMP DESCRIPTIONS Bump Name A1 I2CVDD Description I2C Power Supply A2 GND A3 LSOUT- Ground Inverting Loudspeaker Output A4 LSOUT+ Non-Inverting Loudspeaker Output B1 VDD Analog Power Supply B2 SDA I2C Data Input B3 SCL I2C Clock Input B4 LSVDD Loudspeaker Power Supply C1 INL Left Channel Input C2 INR Right Channel Input C3 BYPASS C4 CPVSS D1 INM- Mono Channel Inverting Input D2 SET ALC Timing Control D3 CPN Charge Pump Flying Capacitor - Negative Terminal D4 CPP Charge Pump Flying Capacitor - Positive Terminal E1 INM+ Mono Channel Non-Inverting Input E2 HPR Right Channel Headphone Amplifier Output E3 HPL Left Channel Headphone Amplifier Output E4 CPGND Mid-Rail Supply Bypass Charge Pump Output Charge Pump Ground These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 3 TI Confidential - NDA Restrictions LM49151 SNAS482F - MARCH 2009 - REVISED MARCH 2013 www.ti.com Absolute Maximum Ratings (1) (2) (3) Supply Voltage (1) 6.0V -65C to +150C Storage Temperature Input Voltage -0.3 to VDD +0.3 Power Dissipation (4) Internally Limited ESD Rating (5) 2.0kV ESD Rating (6) 200V Junction Temperature 150C Soldering Information See AN-1112 (SNVA009) "DSBGA Wafer Level Chip Scale Package" Thermal Resistance JA (typ) - YZR0020 (1) (2) (3) (4) (5) (6) 46.1C/W "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, JA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / JA or the number given in Absolute Maximum Ratings, whichever is lower. Human body model, applicable std. JESD22-A114C. Machine model, applicable std. JESD22-A115-A. Operating Ratings -40C TA +85C Temperature Range 2.7V VDD 5.5V Supply Voltage (VDD, LSVDD) 1.7V I2CVDD 5.5V Supply Voltage (I2CVDD) I2CVDD VDD Electrical Characteristics 3.3V (1) (2) The following specifications apply for LS and HP VOLUMEGAIN = 0dB, LSGAIN =12dB, HPGAIN = 0dB RL = 8+30H (Loudspeaker), RL = 32 (Headphone), RL = 8 (Earpiece), CSET = 0.1F, ALC disabled, f = 1kHz, unless otherwise specified. Limits apply for TA = 25C. (Note 7). LM49151 Symbol Typical Limits (4) Units (Limits) 3.7 5.5 mA (max) 4 6 mA (max) HP Mode 8 4.9 7 mA (max) EP Bypass Mode Parameter Conditions (3) VIN = 0, No Load LS mode 1 LS Mode 1, ALC enabled IDD (1) (2) (3) (4) 4 Supply Current 0.8 1.3 mA (max) LS+HP Mode 5 and 10 7 10.5 mA (max) LS Mode 1, GAMP_SD = 1 3 mA HP Mode 8, GAMP_SD = 1 4.3 mA "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Typical values represent most likely parametric norms at TA = +25C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. Datasheet min/max specification limits are specified by test or statistical analysis. Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 TI Confidential - NDA Restrictions LM49151 www.ti.com SNAS482F - MARCH 2009 - REVISED MARCH 2013 Electrical Characteristics 3.3V(1)(2) (continued) The following specifications apply for LS and HP VOLUMEGAIN = 0dB, LSGAIN =12dB, HPGAIN = 0dB RL = 8+30H (Loudspeaker), RL = 32 (Headphone), RL = 8 (Earpiece), CSET = 0.1F, ALC disabled, f = 1kHz, unless otherwise specified. Limits apply for TA = 25C. (Note 7). LM49151 Symbol Parameter Conditions Typical Limits (4) Units (Limits) 0.04 1 A (max) (3) ISD Shutdown Current VIN = 0 VOS Output Offset Voltage tWU Wake Up Time AVOL Volume Control LS Mode 5, mono input 10 HP Mode 5, mono input 2 6 mV (max) EP Bypass Mode, 1mono input 0.8 5 mV (max) LS Mode 10, stereo input 10 HP Mode 10, stereo input 2 6 mV (max) LS Mode 15, stereo + mono input 10 HP Mode 15, stereo + mono input 2 6 mV (max) HP Mode, CBYPASS = 2.2F Normal, TURN_ON_TIME = 0 Fast, TURN_ON_TIME = 1 27 15 ms ms Minimum Gain Setting -80 dB (min) dB (max) Maximum Gain Setting mV mV mV 18 dB 0.2 dB Gain 0 12 dB Gain 1 18 dB Gain 0 0 dB Gain 1 -1.5 dB Gain 2 -3 dB Gain 3 -6 dB Gain 4 -9 dB Gain 5 -12 dB Gain 6 -15 dB Gain 7 -18 dB LS Output, HP Mode POUT = 20mW -96 dB HP Output, LS Mode POUT = 250mW -96 dB Volume Control Step Error LS Mode HP Mode AV AVMUTE Gain Mute Attention MONO, RIN, LIN, Inputs RIN Input Resistance Maximum Gain Setting 13 11 15.5 k (min) k (max) Minimum Gain Setting 110 90 130 k (min) k (max) EP Bypass Mode 62 50 80 k (min) k (max) LS Mode 1 520 450 mW (min) HP Mode 8, RL = 16 40 HP Mode 8, RL = 32 40 30 mW (min) EP Bypass Mode, RL = 8 35 26 mW (min) f = 1kHz, THD+N = 1% Two channels in phase PO Output Power mW Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 5 TI Confidential - NDA Restrictions LM49151 SNAS482F - MARCH 2009 - REVISED MARCH 2013 www.ti.com Electrical Characteristics 3.3V(1)(2) (continued) The following specifications apply for LS and HP VOLUMEGAIN = 0dB, LSGAIN =12dB, HPGAIN = 0dB RL = 8+30H (Loudspeaker), RL = 32 (Headphone), RL = 8 (Earpiece), CSET = 0.1F, ALC disabled, f = 1kHz, unless otherwise specified. Limits apply for TA = 25C. (Note 7). LM49151 Symbol Parameter Conditions Typical (3) Limits (4) Units (Limits) f = 1kHz THD+N Total Harmonic Distortion + Noise LS Mode 1, PO = 250mW 0.02 % HP Mode 8, PO = 20mW 0.015 % EP Bypass Mode, RL = 8 0.15 % f = 217Hz, VRIPPLE = 200mVPP; CB = 2.2F All audio inputs terminated to AC GND, output referred PSRR Power Supply Rejection Ratio LS Mode 1, mono input 72 dB LS Mode 2, stereo input 67 dB LS mode 3, mono + stereo input 71 dB HP Mode 4, mono input 91 dB HP Mode 8, stereo input 83 dB HP Mode 12, mono + stereo input 81 dB EP Bypass Mode, mono input 95 dB LS Mode 1 55 dB HP Mode 4 61 dB EP Bypass Mode 55 dB VRIPPLE = 200mVP-P, fRIPPLE = 217Hz, mono input CMRR Common Mode Rejection Ratio Efficiency LS Mode, PO = 500mW 88 % XTALK Crosstalk HP Mode 8, PO = 12mW, RL = 32, f = 1kHz 78 dB LS Mode 1, mono input 40 V LS Mode 2, stereo input 47 V LS Mode 3, mono + stereo input 48 V HP Mode 4, mono input 9 V HP Mode 8, stereo input 10 V HP Mode 12, mono + stereo input 11 V EP Bypass Mode, mono input 10 V Signal to Noise Ratio LS Mode 1, PO = 500mW HP Mode 4, PO = 40mW 90 102 dB dB TA Attack Time ATTACK_TIME = 00 0.75 ms TR Release Time RELEASE_TIME = 00 1 s Output Voltage Limit LS Mode 1, THD+N 1%, VOLTAGE_LEVEL 001 010 011 4 4.8 5.6 VP-P VP-P VP-P A-weighted, Inputs AC GND OS Output Noise SNR VLIMIT 6 Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 TI Confidential - NDA Restrictions LM49151 www.ti.com SNAS482F - MARCH 2009 - REVISED MARCH 2013 Electrical Characteristics 5.0V (1) (2) The following specifications apply for LS and HP VOLUMEGAIN = 0dB, LSGAIN =12dB, HPGAIN = 0dB RL = 8+30H (Loudspeaker), RL = 32 (Headphone), RL = 8 (Earpiece), CSET = 0.1F, ALC disabled, f = 1kHz, unless otherwise specified. Limits apply for TA = 25C. (Note 7). Symbol Parameter Conditions LM49151 Typical (3) Limits (4) Units (Limits) VIN = 0, No Load IDD ISD Supply Current LS mode 1, ALC disabled 4.6 mA LS Mode 1, ALC enabled 5.0 mA HP Mode 8 5.0 mA EP Bypass Mode 0.9 mA LS+HP Mode 5 and 10 7.7 mA LS Mode 1, GAMP_SD = 1 3.7 mA HP Mode 8, GAMP_SD = 1 4.4 mA Shutdown Current 0.04 1 A (max) VIN = 0 LS Mode 5, mono input HP Mode 5, mono input VOS Output Offset Voltage tWU Wake Up Time AVOL Volume Control 10 mV 2 6 mV (max) EP Bypass Mode, mono input 1.2 5 mV (max) LS Mode 10, stereo input 10 mV HP Mode 10, stereo input 2 LS Mode 15, stereo + mono input 10 HP Mode 15, stereo + mono input 2 HP Mode, CBYPASS = 2.2F Normal, TURN_ON_TIME = 0 Fast, TURN_ON_TIME = 1 27 15 ms ms Minimum Gain Setting -80 dB (min) dB (max) Maximum Gain Setting 6 mV (max) 6 mV (max) mV 18 dB 0.2 dB Gain 0 12 dB Gain 1 18 dB Gain 0 0 dB Gain 1 -1.5 dB Gain 2 -3 dB Gain 3 -6 dB Gain 4 -9 dB Gain 5 -12 dB Gain 6 -15 dB Gain 7 -18 dB Volume Control Step Error LS Mode HP Mode AV (1) (2) (3) (4) Gain "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Typical values represent most likely parametric norms at TA = +25C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. Datasheet min/max specification limits are specified by test or statistical analysis. Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 7 TI Confidential - NDA Restrictions LM49151 SNAS482F - MARCH 2009 - REVISED MARCH 2013 www.ti.com Electrical Characteristics 5.0V(1)(2) (continued) The following specifications apply for LS and HP VOLUMEGAIN = 0dB, LSGAIN =12dB, HPGAIN = 0dB RL = 8+30H (Loudspeaker), RL = 32 (Headphone), RL = 8 (Earpiece), CSET = 0.1F, ALC disabled, f = 1kHz, unless otherwise specified. Limits apply for TA = 25C. (Note 7). Symbol AVMUTE Parameter Mute Attention LM49151 Conditions Typical (3) Limits (4) Units (Limits) LS Output, HP Mode POUT = 20mW -96 dB HP Output, LS Mode POUT = 250mW -96 dB Maximum Gain Setting 13 k Minimum Gain Setting 110 k EP Bypass Mode 62 k MONO, RIN, LIN, Inputs RIN Input Resistance f = 1kHz, THD+N = 1% Two channels in phase LS Mode 1 PO Output Power 1.25 W 42 mW HP Mode 8, RL = 32 43 mW EP Bypass Mode, RL = 8 137 mW LS Mode 1, PO = 600mW 0.015 % HP Mode 8, PO = 20mW 0.01 % EP Bypass Mode, PO = 60mW 0.09 % HP Mode 8, RL = 16 f = 1kHz THD+N Total Harmonic Distortion + Noise f = 217Hz, VRIPPLE = 200mVPP; CB = 2.2F All audio inputs terminated to AC GND, output referred PSRR Power Supply Rejection Ratio LS Mode 1, mono input, AV = 6dB 75 dB LS Mode 2, stereo input, AV = 6dB 71 dB LS mode 3, mono + stereo input, AV = 6dB 71 dB HP Mode 4, mono input 91 dB HP Mode 8, stereo input 80 dB HP Mode 12, mono + stereo input 79 dB EP Bypass Mode, mono input 97 dB LS Mode 1 55 dB HP Mode 4 61 dB EP Bypass Mode 55 dB VRIPPLE = 200mVP-P, fRIPPLE = 217Hz, mono input CMRR Common Mode Rejection Ratio Efficiency LS Mode, PO = 1W 88 % XTALK Crosstalk HP Mode 8, PO = 12mW, RL = 32, f = 1kHz 78 dB LS Mode 1, mono input 41 V LS Mode 2, stereo input 41 V LS Mode 3, mono + stereo input 43 V HP Mode 4, mono input 9 V HP Mode 8, stereo input 10 V HP Mode 12, mono + stereo input 12 V EP Bypass Mode, mono input 11 V LS Mode 1, PO = 1.25W HP Mode 4, PO = 40mW 96 102 dB dB A-weighted, Inputs AC GND OS SNR 8 Output Noise Signal to Noise Ratio Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 TI Confidential - NDA Restrictions LM49151 www.ti.com SNAS482F - MARCH 2009 - REVISED MARCH 2013 Electrical Characteristics 5.0V(1)(2) (continued) The following specifications apply for LS and HP VOLUMEGAIN = 0dB, LSGAIN =12dB, HPGAIN = 0dB RL = 8+30H (Loudspeaker), RL = 32 (Headphone), RL = 8 (Earpiece), CSET = 0.1F, ALC disabled, f = 1kHz, unless otherwise specified. Limits apply for TA = 25C. (Note 7). Symbol VLIMIT Parameter Output Voltage Limit Conditions LS Mode 1, THD+N 1%, VOLTAGE_LEVEL 001 010 011 101 110 LM49151 Typical (3) Limits (4) 4 4.8 5.6 6.4 7.2 8 Units (Limits) VP-P VP-P VP-P VP-P VP-P VP-P I2C Interface Characteristics VDD = 5V, 2.2V I2CVDD 5.5V (1) (2) The following specifications apply for LS and HP VOLUMEGAIN = 0dB, LSGAIN = 12dB, HPGAIN = 0dB RL = 8+30H (Loudspeaker), RL = 32 (Headphone), RL = 8 (Earpiece), CSET = 0.1F, ALC disabled, f = 1kHz, unless otherwise specified. Limits apply for TA = 25C. (Note 7). LM49151 Symbol (3) Typical Limits (3) Units (Limits) SCL Period 2.5 s (min) t2 SDA Setup Time 100 ns (min) t3 SDA Stable Time 0 ns (min) t4 Start Condition Time 100 ns (min) t5 Stop Condition Time 100 ns (min) t6 SDA Data Hold Time 100 ns (min) Input High Voltage 0.7xI2CVDD V (min) Input Low Voltage 2 V (max) VIL (2) Conditions t1 VIH (1) Parameter 0.3xI CVDD "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Datasheet min/max specification limits are specified by test or statistical analysis. Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 9 TI Confidential - NDA Restrictions LM49151 SNAS482F - MARCH 2009 - REVISED MARCH 2013 www.ti.com I2C Interface Characteristics VDD = 3.3V, 1.7V I2CVDD 2.2V (1) (2) The following specifications apply for LS and HP VOLUMEGAIN = 0dB, LSGAIN =12dB, HPGAIN = 0dB RL = 8 (Loudspeaker), RL = 32 (Headphone), RL = 8 (Earpiece), CSET = 0.1F, ALC disabled, f = 1kHz, unless otherwise specified. Limits apply for TA = 25C. (Note 7). LM49151 Symbol (1) (2) (3) 10 Parameter Conditions Typical Limits (3) Units (Limits) t1 SCL Period Time 2.5 s (min) t2 SCL Setup Time 250 ns (min) t3 SDA Stable Time 0 ns (min) t4 Start Condition Time 250 ns (min) t5 Stop Condition Time 250 ns (min) t6 I2C Data Hold Time 250 ns (min) VIH Input Voltage High 0.7xI2CVDD V (min) VIL Input Voltage Low 0.3xI2CVDD V (max) "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Datasheet min/max specification limits are specified by test or statistical analysis. Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 TI Confidential - NDA Restrictions LM49151 www.ti.com SNAS482F - MARCH 2009 - REVISED MARCH 2013 Typical Performance Characteristics (1) 10 10 1 1 THD+N (%) THD+N (%) THD+N vs Frequency VDD = 3.3V, RL = 8+30H, POUT = 250mW Speaker Mode 1 0.1 THD+N vs Frequency VDD = 3.3V, RL = 32, POUT = 20mW Headphone Mode 8 0.1 0.01 0.01 0.001 0.001 20 100 1k 20 10k 20k 100 FREQUENCY (Hz) Figure 4. THD+N vs Frequency VDD = 3.6V, RL = 8+30H, POUT = 300mW Speaker Mode 1 THD+N vs Frequency VDD = 3.6V, RL = 32, POUT = 20mW Headphone Mode 8 10 10 1 1 0.1 0.01 0.1 0.01 0.001 0.001 20 100 1k 10k 20k 20 100 1k 10k 20k FREQUENCY (Hz) Figure 5. Figure 6. THD+N vs Frequency VDD = 5V, RL = 8+30H, POUT = 600mW Speaker Mode 1 THD+N vs Frequency VDD = 5V, RL = 32, POUT = 20mW Headphone Mode 8 10 10 1 1 THD+N (%) THD+N (%) FREQUENCY (Hz) 0.1 0.01 0.1 0.01 0.001 20 100 1k 10k 20k 0.001 FREQUENCY (Hz) 20 100 1k 10k 20k FREQUENCY (Hz) Figure 7. (1) 10k 20k Figure 3. THD+N (%) THD+N (%) FREQUENCY (Hz) 1k Figure 8. Data taken with BW = 22kHz except where specified. Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 11 TI Confidential - NDA Restrictions LM49151 SNAS482F - MARCH 2009 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics(1) (continued) 10 THD+N vs Frequency VDD = 3.3V, RL = 8, POUT = 20mW Earpiece Bypass Mode THD+N vs Output Power VDD = 3.3V, RL = 8+30H, f = 1kHz Speaker Mode 1 10 THD+N (%) THD+N (%) 1 0.1 1 0.1 0.01 0.001 20 100 1k 0.01 10m 10k 20k FREQUENCY (Hz) 10 100m 1 OUTPUT POWER (W) Figure 9. Figure 10. THD+N vs Frequency VDD = 3.6V, RL = 8, POUT = 30mW Earpiece Bypass Mode THD+N vs Output Power VDD = 3.6V, RL = 8+30H, f = 1kHz Speaker Mode 1 10 THD+N (%) THD+N (%) 1 0.1 1 0.1 0.01 0.01 10m 0.001 20 100 1k 10k 20k FREQUENCY (Hz) 10 100m 1 OUTPUT POWER (W) Figure 11. Figure 12. THD+N vs Frequency VDD = 5V, RL = 8, POUT = 60mW Earpiece Bypass Mode THD+N vs Output Power VDD = 5V, RL = 8+30H, f = 1kHz Speaker Mode 1 10 THD+N (%) THD+N (%) 1 0.1 1 0.1 0.01 0.001 20 100 1k 10k 20k FREQUENCY (Hz) 100m 1 2 OUTPUT POWER (W) Figure 13. 12 0.01 10m Figure 14. Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 TI Confidential - NDA Restrictions LM49151 www.ti.com SNAS482F - MARCH 2009 - REVISED MARCH 2013 Typical Performance Characteristics(1) (continued) THD+N vs Output Power VDD = 3.3V, RL = 32, f = 1kHz Headphone Mode 8 10 10 1 1 THD+N (%) THD+N (%) THD+N vs Output Power VDD = 5V, RL = 32, f = 1kHz Headphone Mode 8 0.1 0.1 0.01 0.01 0.001 0.001 10m 1m OUTPUT POWER (W) 10 100m 10m 1m 100m OUTPUT POWER (W) Figure 15. Figure 16. THD+N vs Output Power VDD = 3.6V, RL = 32, f = 1kHz Headphone Mode 8 THD+N vs Output Power RL = 32, f = 1kHz Earpiece Bypass Mode 10 VDD = 5V VDD = 3.6V 1 THD+N (%) THD+N (%) 1 0.1 VDD = 3.3V 0.1 0.01 0.001 10m 1m 0.01 10m 100m OUTPUT POWER (W) 2000 OUTPUT POWER (W) Figure 17. Figure 18. Output Power vs Supply Voltage RL = 8, f = 1kHz Speaker Mode 1 Output Power vs Supply Voltage RL = 32, f = 1kHz Headphone Mode 8 70 THD+N = 10% 1750 60 OUTPUT POWER (mW) OUTPUT POWER (mW) 200m 50m 1500 THD+N = 10% 1250 1000 750 THD+N = 1% 500 40 30 THD+N = 1% 20 10 250 0 2.5 50 3 3.5 4 4.5 5 5.5 0 2.5 3 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 19. Figure 20. Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 13 TI Confidential - NDA Restrictions LM49151 SNAS482F - MARCH 2009 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics(1) (continued) Output Power vs Supply Voltage RL = 8, f = 1kHz Earpiece Bypass Mode CMRR vs Frequency VDD = 5V, VCM = 1VP-P, RL = 8 Loudspeaker Mode 1 -20 160 -30 THD+N = 10% CMRR (dB) OUTPUT POWER (mW) 200 120 80 -40 -50 THD+N = 1% 40 -60 0 2.5 3 3.5 4 4.5 5 -70 10 5.5 SUPPLY VOLTAGE (V) 1k 10k 100k FREQUENCY (Hz) Figure 21. Figure 22. CMRR vs Frequency VDD = 5V, VCM = 1VP-P, RL = 32 Headphone Mode 4 CMRR vs Frequency VDD = 3.3V, VCM = 1VP-P, RL = 8 Earpiece Bypass Mode -50 -20 -30 -55 CMRR (dB) CMRR (dB) 100 -40 -50 -60 -65 -60 -70 10 100 1k 10k -70 10 100k 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 23. Figure 24. Crosstalk vs Frequency VDD = 3.3V, VCM = 1VP-P, RL = 32 Headphone Mode 8 PSRR vs Frequency VDD = 3.3V, VRIPPLE = 200mVP-P, RL = 8 Loudspeaker Mode 1 -20 -50 -55 -30 -40 -65 PSRR (dB) CROSSTALK (dB) -60 -70 -75 -50 -60 -80 -70 -85 -90 10 100 1k 10k 100k -80 10 Figure 25. 14 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 26. Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 TI Confidential - NDA Restrictions LM49151 www.ti.com SNAS482F - MARCH 2009 - REVISED MARCH 2013 Typical Performance Characteristics(1) (continued) PSRR vs Frequency VDD = 3.3V, VRIPPLE = 200mVP-P, RL = 8 Loudspeaker Mode 2 PSRR vs Frequency VDD = 3.3V, VRIPPLE = 200mVP-P, RL = 32 Headphone Mode 4 -20 -50 -30 -60 PSRR (dB) PSRR (dB) -40 -50 -70 -80 -60 -90 -70 -80 10 100 1k 10k -100 10 100k 100 1k 10k 100k FREQUENCY (Hz) Figure 28. PSRR vs Frequency VDD = 3.3V, VRIPPLE = 200mVP-P, RL = 32 Headphone Mode 8 PSRR vs Frequency VDD = 3.3V, VRIPPLE = 200mVP-P, RL = 8 Earpiece Bypass Mode -40 -50 -50 -60 -60 -70 PSRR (dB) PSRR (dB) FREQUENCY (Hz) Figure 27. -70 -80 -90 -90 -100 -100 10 100 1k 10k -110 10 100k 100 1k 10k FREQUENCY (Hz) FREQUENCY (Hz) Figure 29. Figure 30. Efficiency vs Output Power VDD = 3.3V, RL = 8, f = 1kHz Speaker Mode 1 Efficiency vs Output Power VDD = 3.6V, RL = 8, f = 1kHz Speaker Mode 1 100 100 90 90 80 80 70 70 EFFICIENCY (%) EFFICIENCY (%) -80 60 50 40 30 60 50 40 30 20 20 10 10 0 100k 0 0 200 400 600 800 0 200 400 600 OUTPUT POWER (mW) OUTPUT POWER (mW) Figure 31. Figure 32. 800 Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 15 TI Confidential - NDA Restrictions LM49151 SNAS482F - MARCH 2009 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics(1) (continued) Efficiency vs Output Power VDD = 5V, RL = 8, f = 1kHz Speaker Mode 1 100 200 Power Dissipation vs Output Power RL = 8, f = 1kHz Speaker Mode 1 90 VDD = 5V POWER DISSIPATION (mW) EFFICIENCY (%) 80 70 60 50 40 30 20 150 100 V DD = 3.6V V DD = 3.3V 50 10 0 0 200 400 600 800 0 1000 1200 0 250 750 1000 1250 1500 OUTPUT POWER (mW) Figure 34. Power Dissipation vs Output Power RL = 32, f = 1kHz Headphone Mode 8 Power Dissipation vs Output Power RL = 32, f = 1kHz Earpiece Bypass Mode Figure 35. Figure 36. Supply Current vs Supply Voltage Headphone Mode 8, No Load Supply Current vs Supply Voltage Earpiece Bypass Mode, No Load 5.2 1 5 0.95 4.8 4.6 Gain Amp ON 4.4 4.2 4 2.5 3 3.5 4 4.5 5 0.9 0.85 0.8 0.75 Gain Amp OFF 5.5 SUPPLY VOLTAGE (V) 0.7 2.5 3 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE (V) Figure 37. 16 500 Figure 33. SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) OUTPUT POWER (mW) Figure 38. Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 TI Confidential - NDA Restrictions LM49151 www.ti.com SNAS482F - MARCH 2009 - REVISED MARCH 2013 Typical Performance Characteristics(1) (continued) Clip Control Levels VDD = 3.3V, VIN = 8VPP Shaped Burst, 1kHz Blue = No Clip Disabled, Gray = Low Light Green = Medium, Green = High, Yellow = Max Voltage Limiter Function VDD = 3.3V, RL = 8+30H fIN = 1kHz, LS_GAIN = 0 1.0 4 Voltage Limiter off OUTPUT VOLTAGE (V) OUTPUT POWER (W) 0.8 5.6VPP 0.6 4.8VPP 4VPP 0.4 2 0 -2 0.2 0 -4 1 0 3 2 4 5 6 7 0 1 INPUT VOLTAGE (VPP) 1.0 2 3 4 TIME (ms) Figure 39. Figure 40. Voltage Limiter Function VDD = 3.6V, RL = 8+30H fIN = 1kHz, LS_GAIN = 0 Clip Control Levels VDD = 3.6V, VIN = 8VPP Shaped Burst, 1kHz Blue = No Clip Disabled, Gray = Low Light Green = Medium, Green = High, Yellow = Max 4 Voltage Limiter off OUTPUT POWER (W) OUTPUT VOLTAGE (V) 6.4VPP 0.8 5.6VPP 0.6 4.8VPP 4VPP 0.4 2 0 -2 0.2 0 -4 1 0 2 3 4 5 6 7 8 0 1 INPUT VOLTAGE (VPP) 2 TIME (ms) 3 4 Figure 41. Figure 42. Voltage Limiter Function VDD = 5V, RL = 8+30H fIN = 1kHz, LS_GAIN = 0 Clip Control Levels VDD = 5V, VIN = 8VP-P Shaped Burst, 1kHz Blue = No Clip Disabled, Gray = Low Light Green = Medium, Green = High, Yellow = Max 5 2.0 OUTPUT POWER (W) 1.6 OUTPUT VOLTAGE (V) Voltage Limiter off 8VPP 7.2VPP 1.2 6.4VPP 5.6VPP 0.8 4.8VPP 4VPP 2.5 0 -2.5 0.4 0 0 1 2 3 4 5 6 7 8 9 10 11 -5 1 2 3 4 5 TIME (ms) INPUT VOLTAGE (VPP) Figure 43. Figure 44. Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 17 TI Confidential - NDA Restrictions LM49151 SNAS482F - MARCH 2009 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics(1) (continued) No Clip Function VDD = 3.3V, RLIN = 8+30H, fIN = 1kHz, LS_GAIN = 1 Blue, Green = Output Power vs Input Voltage Gray, Yellow = THD+N vs Input Voltage 1 10 1 No Clip Enabled 10m 0.1 OUTPUT POWER (W) THD+N (%) OUTPUT POWER (W) 1.0 100m 4 2 1 6 No Clip Disabled 100m 1.0 10m 0.1 No Clip Enabled 0.01 1m 10 TTT No Clip Disabled THD+N (%) No Clip Function VDD = 3.3V, RLIN = 8+30H, fIN = 1kHz, LS_GAIN = 0 Blue, Green = Output Power vs Input Voltage Gray, Yellow = THD+N vs Input Voltage 1m 8 0.01 4 2 1 6 8 INPUT VOLTAGE (VPP) INPUT VOLTAGE (VPP) Figure 45. Figure 46. No Clip Function VDD = 3.6V, RLIN = 8+30H, fIN = 1kHz, LS_GAIN = 0 Blue, Green = Output Power vs Input Voltage Gray, Yellow = THD+N vs Input Voltage No Clip Function VDD = 3.6V, RLIN = 8+30H, fIN = 1kHz, LS_GAIN = 1 Blue, Green = Output Power vs Input Voltage Gray, Yellow = THD+N vs Input Voltage 10 1 No Clip Enabled 10m 0.1 OUTPUT POWER (W) 1.0 100m THD+N (%) OUTPUT POWER (W) No Clip Disabled 0.01 1m 4 2 1 6 10 No Clip Disabled 100m 1.0 10m 0.1 No Clip Enabled 0.01 1m 8 THD+N (%) 1 INPUT VOLTAGE (VPP) 4 2 1 6 8 INPUT VOLTAGE (VPP) Figure 47. Figure 48. No Clip Function VDD = 5V, RLIN = 8+30H, fIN = 1kHz, LS_GAIN = 0 Blue, Green = Output Power vs Input Voltage Gray, Yellow = THD+N vs Input Voltage No Clip Function VDD = 5V, RLIN = 8+30H, fIN = 1kHz, LS_GAIN = 1 Blue, Green = Output Power vs Input Voltage Gray, Yellow = THD+N vs Input Voltage 2 20 2 20 10m 1m 0.1 1 2 4 6 8 0.01 12 10m 1.0 0.1 No Clip Enabled 1m INPUT VOLTAGE (VPP) 1 2 4 6 8 0.01 12 INPUT VOLTAGE (VPP) Figure 49. 18 No Clip Disabled 100m THD+N (%) 1.0 No Clip Enabled OUTPUT POWER (W) 100m THD+N (%) OUTPUT POWER (W) No Clip Disabled Figure 50. Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 TI Confidential - NDA Restrictions LM49151 www.ti.com SNAS482F - MARCH 2009 - REVISED MARCH 2013 APPLICATION INFORMATION WRITE-ONLY I2C COMPATIBLE INTERFACE The LM49151 is controlled through an I2C compatible serial interface that consists of a serial data line (SDA) and a serial clock (SCL). The SCL and SDA lines are uni-directional write only interface. The LM49151 and the master can communicate at clock rates up to 400kHz. Figure 51 shows the I2C interface timing diagram. Data on the SDA line must be stable during the HIGH period of SCL. The LM49151 is a slave-only device, reliant upon the master to generate the SCL signal. Each transmission sequence is framed by a START condition and a STOP condition (Figure 52). Each data word and device address transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse (Figure 53). The LM49151 device address is 11111000. I2C BUS FORMAT The bus format for the I2C interface is shown in Figure 53. The bus format diagram is broken up into six major sections: The "start" signal is generated by lowering the data signal while the clock signal is HIGH. The start signal will alert all devices attached to the I2C bus to check the incoming address against their own address. The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the clock. Each address bit must be stable while the clock level is HIGH. After the last bit of the address bit is sent, the master releases the data line HIGH (through a pull-up resistor). Then the master sends an acknowledge clock pulse. If the LM49151 has received the address correctly, then it holds the data line LOW during the clock pulse. If the data line is not held LOW during the acknowledge clock pulse, then the master should abort the rest of the data transfer to the LM49151. The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is stable HIGH. After the data byte is sent, the master must check for another acknowledge to see if the LM49151 received the data. If the master has more data bytes to send to the LM49151, then the master can repeat the previous two steps until all data bytes have been sent. The "stop" signal ends the transfer. To signal "stop", the data signal goes HIGH while the clock signal is HIGH. The data line should be held HIGH when not in use. I2C INTERFACE POWER SUPPLY PIN (I2CVDD) The LM49151's I2C interface is powered up through the I2CVDD pin. The LM49151 I2C interface operates at a voltage level set by the I2CVDD pin which can be set independent to that of the main power supply pin VDD. This is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is operating at a lower supply voltage than the main battery of a portable system. Figure 51. I2C Timing Diagram SDA SCL S P START condition STOP condition Figure 52. Start and Stop Diagram Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 19 TI Confidential - NDA Restrictions LM49151 SNAS482F - MARCH 2009 - REVISED MARCH 2013 www.ti.com SCL SDA START MSB DEVICE ADDRESS LSB ACK R/W MSB REGISTER DATA ACK LSB STOP Figure 53. Example I2C Write Cycle DEVICE ADDRESS REGISTER Table 1. Device Address B7 B6 B5 B4 B3 B2 B1 B0 (W) 1 1 1 1 1 0 0 0 Device Address I2C CONTROL REGISTER Table 2. I2C Control B7 B6 B5 B4 B3 B1 B0 I CVDD_SD TURN_ON _TIME PWR_ON Shutdown Control 0 0 0 GAMP_SD Mode Control 0 0 1 EP_BYPASS Voltage Limit Control 0 1 0 ATTACK_TIME VOLTAGE_LEVEL No Clip Control 0 1 1 RELEASE TIME OUTPUT_CLIP_CONTROL Gain Control 1 0 0 Mono Volume Control 1 0 1 MONO_VOL Stereo Volume Control 1 1 0 STEREO_VOL SS Control 1 1 1 INPUT_MUTE HPR_SD B2 2 MODE_CONTROL LS_GAIN 0 0 HP_GAIN 0 0 SS_EN SHUTDOWN CONTROL REGISTER This register is used to control shutdown operation of the device. Table 3. Shutdown Control Bit Name Value Description This enables or disables the device. B0 PWR_ON PWR_ON Status 0 Device disabled 1 Device enabled This control the turn on time of the device. B1 TURN_ON_TIME TURN_ON_TIME Status 0 Normal turn on time (27ms) 1 Fast turn on time (15ms) 2 B2 2 I CVDD_SD I CVDD_SD Status 0 I2CVDD acts as an active low RESET input. If I2CVDD drops below 1.1V, the device resets and the I2C registers are restored to their default state. 1 Normal Operation. I2CVDD voltage does not reset the device. This disables the right headphone output. B3 20 HPR_SD HPR_SD Status 0 Normal Operation 1 Headphone right disabled Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 TI Confidential - NDA Restrictions LM49151 www.ti.com SNAS482F - MARCH 2009 - REVISED MARCH 2013 Table 3. Shutdown Control (continued) Bit Name Value Description This disables the gain amplifiers that are not in use to minimize IDD. This setting is recommended for output modes 1, 2, 4, 5, 8, 10. B4 GAMP_SD GAMP_SD Status 0 Normal operation 1 Disable the unused gain amplifiers MODE CONTROL REGISTER This register is used to control shutdown operation of the device. Table 4. Output Mode Selection (see legend below (1)) Bits Field B3:B0 MODE _CONTROL Description This set the different mixers output modes. Mode_ Control Mode 0000 0001 0010 Loudspeaker Headphone Right Headphone Left 0 SD SD SD 1 GM x M SD SD 2 2 x (GL x L + GR x R) SD SD 0011 3 2 x (GL x L + GR x R) + GM x M SD SD 0100 4 SD GM x M/2 GM x M/2 0101 5 GM x M GM x M/2 GM x M/2 0110 6 2 x (GL x L + GR x R) GM x M/2 GM x M/2 0111 7 2 x (GL x L + GR x R) + GM x M GM x M/2 GM x M/2 1000 8 SD GR x R GL x L 1001 9 GM x M GR x R GL x L 1010 10 2 x (GL x L + GR x R) GR x R GL x L 1011 11 2 x (GL x L + GR x R) + GM x M GR x R GL x L 1100 12 SD GR x R + GM x M/2 GL x L + GM x M/2 1101 13 GM x M GR x R + GM x M/2 GL x L + GM x M/2 1110 14 2 x (GL x L + GR x R) GR x R + GM x M/2 GL x L + GM x M/2 15 2 x (GL x L + GR x R) + GM x M GR x R + GM x M/2 GL x L + GM x M/2 1111 B4 (1) EP_BYPASS This makes the loudspeaker and headphone amplifiers into shutdown mode and enables receiver bypass path. 0 Normal output mode operation 1 Enable the receiver bypass path M: Mono differential input R: Right channel stereo input L: Left channel stereo input SD: Shutdown GM : Differential input gain path GR: Right channel input gain path GL: Left channel input gain path Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 21 TI Confidential - NDA Restrictions LM49151 SNAS482F - MARCH 2009 - REVISED MARCH 2013 www.ti.com VOLTAGE LIMIT CONTROL REGISTER This register is used to control output voltage limiter settings and attack time of the automatic level circuit: Table 5. Voltage Limit Control Bits Field B2:B0 VOLTAGE_LEVEL Description This sets the output voltage limit level. 000 B4:B3 ATTACK _TIME Voltage limit disabled 001 VTH(VLIM) = 4VP-P 010 VTH(VLIM) = 4.8VP-P 011 VTH(VLIM) = 5.6VP-P 100 VTH(VLIM) = 6.4VP-P 101 VTH(VLIM) = 7.2VP-P 110 VTH(VLIM) = 8VP-P 111 Voltage limit disabled This sets the Attack time of automatic level control circuit. It is based on characterization data and CSET = 0.1F (see ATTACK TIME section) 00 0.75ms 01 1ms 10 1.5ms 11 2ms NO CLIP CONTROL REGISTER This register is used to control output clip control settings and release time of the automatic level circuit: Table 6. No Clip Control Bits Field B2:B0 OUTPUT_CLIP_CONTROL B4:B3 22 RELEASE_TIME Description This sets the output clip limit level. 000 No Clip disabled, output clip control disabled 001 No Clip enabled, output clip control disabled 010 Low 011 Medium 100 High 101 Max 110 No Clip enabled, output clip control disabled 111 No Clip enabled, output clip control disabled This sets the release time of automatic level control circuit. It is based on characterization data and CSET = 0.1F (see RELEASE TIME section) 00 1s 01 0.8s 10 0.65s 11 0.4s Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 TI Confidential - NDA Restrictions LM49151 www.ti.com SNAS482F - MARCH 2009 - REVISED MARCH 2013 GAIN CONTROL REGISTER This register is used to control gain level for on the outputs: Table 7. Gain Control Bits Field B2:B0 HP_GAIN B3 B4 LS_GAIN INPUT_MUTE Description This sets the headphone output gain level. 000 0dB 001 -1.5dB 010 -3dB 011 -6dB 100 -9dB 101 -12dB 110 -15dB 111 -18dB This sets the loudspeaker output gain level. 0 12dB 1 18dB This sets the inputs into lower power mute mode. 0 Normal operation 1 Device inputs are in mute mode Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 23 TI Confidential - NDA Restrictions LM49151 SNAS482F - MARCH 2009 - REVISED MARCH 2013 www.ti.com VOLUME CONTROL REGISTER These registers are used to control output volume control levels for Loudspeaker and Headphone: Table 8. LS GAIN / HP GAIN Bits Field B4:B0 MONO_VOL STEREO_VOL Description This programs the Earpiece, Loudspeaker, and Headphone volume level. VOL Level (dB) 00000 MUTE 00001 -46.5 00010 -40.5 00011 -34.5 00100 -30 00101 -27 00110 -24 00111 -21 01000 -18 01001 -15 01010 -13.5 01011 -12 01100 -10.5 01101 -9 01110 -7.5 01111 -6 10000 -4.5 10001 -3 10010 -1.5 10011 0 10100 1.5 10101 3 10110 4.5 10111 6 11000 7.5 11001 9 11010 10.5 11011 12 11100 13.5 11101 15 11110 16.5 11111 18 SPREAD SPECTRUM CONTROL REGISTER This register controls the spread spectrum mode of the class D amplifier: Table 9. SS Control 24 Bits Field B0 SS_ENB Description This sets the spread spectrum mode of the Class D amplifier. 0 Spread Spectrum Disabled 1 Spread Spectrum Enabled Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 TI Confidential - NDA Restrictions LM49151 www.ti.com SNAS482F - MARCH 2009 - REVISED MARCH 2013 DIFFERENTIAL AMPLIFIER EXPLANATION The LM49151 features a differential input stage, which offers improved noise rejection compared to a singleended input amplifier. Because a differential input amplifier amplifies the difference between the two input signals, any component common to both signals is cancelled. An additional benefit of the differential input structure is the possible elimination of the DC input blocking capacitors. Since the DC component is common to both inputs, and thus cancelled by the amplifier, the LM49151 can be used without input coupling capacitors when configured with a differential input signal. INPUT MIXER/MULTIPLEXER The LM49151 includes a comprehensive mixer multiplexer controlled through the I2C interface. The mixer/multiplexer allows any input combination to appear on any output of LM49151. Multiple input paths can be selected simultaneously. Under these conditions, the selected inputs are mixed together and output on the selected channel. Table 5 (MODE CONTROL) shows how the input signals are mixed together for each possible input selection. SHUTDOWN FUNCTION The LM49151 features the following shutdown controls: Bit B4 (GAMP_SD) of the SHUTDOWN CONTROL register controls the gain amplifiers. When GAMP_SD = 1, it disables the gain amplifiers that are not in use. For example, in Modes 1, 4 and 5, the Mono inputs are in use, so the Left and Right input gain amplifiers are disabled, causing the IDD to be minimized. Bit B0 (PWR_ON) of the SHUTDOWN CONTROL register is the global shutdown control for the entire device. Set PWR_ON = 0 for normal operation. PWR_ON = 1 overrides any other shutdown control bit. CLASS D AMPLIFIER The LM49151 features a mono class D audio power amplifier with a filterless modulation scheme that reduces external component count, conserving board space and reducing system cost. With no signal applied, the outputs (LSOUT+ and LSOUT-) switch between VDD and GND with 50% duty cycle, in phase, causing the two outputs to cancel. This cancellation results in no net voltage across the speaker, thus there is no current to the load in the idle state. With an input signal applied, the duty cycle (pulse width) of the class D output changes. For increasing output voltage, the duty cycle of LSOUT+ increases, while the duty cycle of LSOUT- decreases. For decreasing output voltages, the converse occurs. The difference between the two pulse widths yields the differential output voltage. ENHANCED EMISSIONS SUPPRESSION (E2S) The LM49151 class D amplifier features Texas Instruments' patent-pending E2S system that reduces EMI, while maintaining high quality audio reproduction and efficiency. The E2S system features selectable spread spectrum and advanced edge rate control (ERC). The LM49151 class D ERC greatly reduces the high frequency components of the output square waves by controlling the output rise and fall times, slowing the transitions to reduces RF emissions, while maximizing THD+N and efficiency performance. FIXED FREQUENCY The LM49151 class D amplifier features two modulation schemes, a fixed frequency mode and a spread spectrum mode. Select the fixed frequency mode by setting bit B0 (SS_EN) of the SS CONTROL register to 0. In fixed frequency mode, the loudspeaker outputs switch at a constant 300kHz. The output spectrum consists of the 300kHz fundamental and its associated harmonics. SPREAD SPECTRUM The selectable spread spectrum mode minimizes the need for output filters, ferrite beads or chokes. In spread spectrum mode, the switching frequency varies randomly by 30% about a 300kHz center frequency, reducing the wideband spectral content, improving EMI emission radiated by the speaker and associated cables and traces. Where a fixed frequency class D exhibits large amounts of spectral energy at multiples of the switching frequency, the spread spectrum architecture spreads that energy over a larger bandwidth. The cycle-to-cycle variation of the switching period does not affect the audio reproduction, efficiency, or PSRR. Set bit B0 (SS_EN) of the SS CONTROL register to 1 to enable spread spectrum mode. Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 25 TI Confidential - NDA Restrictions LM49151 SNAS482F - MARCH 2009 - REVISED MARCH 2013 www.ti.com GROUND REFERENCED HEADPHONE AMPLIFIER The LM49151 features a low noise inverting charge pump that generates an internal negative supply voltage. This allows the headphone outputs to be biased about GND instead of a nominal DC voltage, like traditional headphone amplifiers. Because there is no DC component, the large DC blocking capacitors (typically 220F) are not necessary. The coupling capacitors are replaced by two small ceramic charge pump capacitors, saving board space and cost. Eliminating the output coupling capacitors also improves low frequency response. In traditional headphone amplifiers, the headphone impedance and the output capacitor from a high-pass filter that not only blocks the DC component of the output, but also attenuates low frequencies, impacting the bass response. Because the LM49151 does not require the output coupling capacitors, the low frequency response of the device is not degraded by external components. In addition to eliminating the output coupling capacitors, the ground referenced output nearly doubles the available dynamic range of the LM49151 headphone amplifiers when compared to a traditional headphone amplifier operating from the same supply voltage. EARPIECE (EP) BYPASS When B4 of MODE_CONTROL register is set to 1, earpiece amplifier is enabled and differential inputs are passed down to speaker outputs. This in turn disables the class D amplifier. AUTOMATIC LIMITER CONTROL (ALC) When enabled, the ALC continuously monitors and adjusts the gain of the loudspeaker amplifier signal path if necessary. The ALC serves two functions: voltage limiter/speaker protection and output clip prevention (No-Clip) with four clip controls levels. The voltage limiter/speaker protection prevents an output overload condition by maintaining the loudspeaker output signal below a preset amplitude (See VOLTAGE LIMITER section). The No Clip feature monitors the output signal and maintains audio quality by preventing the loudspeaker output from exceeding the amplifier's headroom (see NO CLIP/OUTPUT CLIP CONTROL section). The voltage limiter thresholds, clip control levels, attack and release times are configured through the I2C interface. VOLTAGE LIMITER The voltage limiter function of the ALC monitors and prevents the audio signal from exceeding the voltage limit threshold (Figure 54). The voltage limit threshold (VTH(VLIM)) is set by bits B2:B0 in the Voltage Limit Threshold Register (see Table 6). Although the ALC reduces the gain of the speaker path to maintain the audio signal below the voltage limit threshold, it is still possible to overdrive the speaker output in which case loudspeaker output will exceed the voltage limit threshold and cause clipping on the output, and speaker damage is possible. Please see the ALC HEADROOM section for further details. 4VP-P 4.8VP-P 5.6VP-P 6.4VP-P 7.2VP-P 8VP-P OFF Figure 54. Voltage Limit Output Level NO CLIP/OUTPUT CLIP CONTROL The LM49151 No Clip circuitry detects when the loudspeaker output is near clipping and reduces the signal gain to prevent output clipping and preserve audio quality (Figure 55). Although the ALC reduces the gain of the speaker path to prevent output clipping, it is still possible to overdrive the speaker output. Please see the ALC HEADROOM section for further details. 26 Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 TI Confidential - NDA Restrictions LM49151 www.ti.com SNAS482F - MARCH 2009 - REVISED MARCH 2013 +VOUT(MAX) +VOUT(MAX) -VOUT(MAX) -VOUT(MAX) No Clip Enabled No Clip Disabled Figure 55. No Clip Function The LM49151 also features an output clip control that allows a certain amount of clipping at the output in order to increase the loudspeaker output power. The clip level is set by B2:B0 in the No Clip Control Register (see Table 7). The clip control works by allowing the output to enter clipping before the ALC turns on and maintains the output level. The clip control has four levels: low, medium, high and max. The low and max clip level control settings give the lowest distortion and highest distortion respectively on the output (see Figure 56). The actual output level of the device will depend upon the supply voltage, and the output power will depend upon the load impedance. OUTPUT VOLTAGE (V) 4 2 0 -2 -4 0 1 2 3 4 TIME (ms) Figure 56. Clip Control Levels VDD = 3.3V, VIN = 8VPP Shaped Burst, 1kHz Blue = No Clip Disabled, Gray = Low, Light Green = Medium Green = High, Yellow = Max ALC HEADROOM When either voltage limiter or no clip is enabled, it is still possible to drive LM49151 into clipping by overdriving the input volume stage of the signal path beyond its output dynamic range. In this case, clipping occurs at the input volume stage, and although ALC is active, the gain reduction will have no effect on the output clipping. The maximum input that can safely pass through the input volume stage can be calculated by following formula: VIN d VDD Av (volume gain) (1) So in the case of 0 dB volume gain, audio input has to be less than VDD for both voltage limiter or No clip settings. When voltage limiter is enabled, ALC can reach its max attenuation for lower voltage limit levels as shown in the Figure 57. Typically, after the ALC started working, with 6 dB of audio input change ALC is well within its regulation. Voltage limiter Input headroom can be increased by switching to the LS_GAIN to 18dB in the Gain Control Register (see Table 7). Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 27 TI Confidential - NDA Restrictions LM49151 SNAS482F - MARCH 2009 - REVISED MARCH 2013 www.ti.com 1.0 Voltage Limiter off OUTPUT POWER (W) 0.8 VIN > VDD 5.6VPP 0.6 4.8VPP 4VPP 0.4 0.2 ALC max attenuation 0 0 1 2 3 4 5 7 6 INPUT VOLTAGE (VPP) Figure 57. Voltage Limiter Function VDD = 3.3V, RL = 8+30H fIN = 1kHz, LS_GAIN = 0 1 10 1.0 100m THD+N (%) OUTPUT POWER (W) No Clip Disabled No Clip Enabled 10m 1m 0.1 0.01 1 2 4 6 8 INPUT VOLTAGE (VPP) Figure 58. No Clip Function VDD = 3.3V, RL = 8+30H fIN = 1kHz, LS_GAIN = 0 Blue, Green = Output Power vs Input Voltage Gray, Yellow = THD+N vs Input Voltage When No Clip is enabled, class D speaker output reduces when it's about to enter clipping region and power stay constant as long as VIN is less than VDD for 0 dB volume gain (see Figure 58). For example, in the case of VDD = 3.3V, there is a 6 dB of headroom for the change in input. Please see the ALC typical performance curves for additional plots relating to different supply voltages and LS_GAIN settings for specific application parameters. ATTACK TIME Attack time (tATK) is the time it takes for the gain to be reduced by 6dB (LS_GAIN=0) once the audio signal exceeds the ALC threshold. Fast attack times allow the ALC to react quickly and prevent transients such as symbol crashes from being distorted. However, fast attack times can lead to volume pumping, where the gain reduction and release becomes noticeable, as the ALC cycles quickly. Slower attack times cause the ALC to ignore the fast transients, and instead act upon longer, louder passages. Selecting an attack time that is too slow can lead to increased distortion in the case of the No Clip function, and possible output overload conditions in the case of the Voltage limiter. The attack time is set by a combination of the value of CSET and the attack time coefficient as given by Equation 2: tATK = 20kCSET / ATK (s) (2) Where ATK is the attack time coefficient (Table 10) set by bits B4:B3 in the Voltage Limit Control Register (see Table 7). The attack time coefficient allows the user to set a nominal attack time. The internal 20k resistor is subject to temperature change, and it has tolerance between -11% to +20%. 28 Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 TI Confidential - NDA Restrictions LM49151 www.ti.com SNAS482F - MARCH 2009 - REVISED MARCH 2013 Table 10. Attack Time Coefficient B5 B4 ATK 0 0 2.667 0 1 2 1 0 1.333 1 1 1 RELEASE TIME Release time (tRL) is the time it takes for the gain to return from 6dB (LS_GAIN=0) to its normal level once the audio signal returns below the ALC threshold. A fast release time allows the ALC to react quickly to transients, preserving the original dynamics of the audio source. However, similar to a fast attack time, a fast release time contributes to volume pumping. A slow release time reduces the effect of volume pumping. The release time is set by a combination of the value of CSET and release time coefficient as given by Equation 3: tRL = 20MCSET / RL (s) (3) where RL is the release time coefficient (Table 11) set by bits B4:B3 in the No Clip Control Register. The release time coefficient allows the user to set a nominal release time. The internal 20M is subject to temperature change, and it has tolerance between -11% to +20%. Table 11. Release Time Coefficient RL B5 B4 0 0 2 0 1 2.5 1 0 3 1 1 5 PROPER SELECTION OF EXTERNAL COMPONENTS ALC Timing (CSET) Capacitor Selection The recommended range value of CSET is between .01F to 1F. Lowering the value below .01F can increase the attack time but LM49151 ALC ability to regulate its output can be disrupted and approaches the hard limiter circuit. This in turn increases the THD+N and audio quality will be severely affected. Charge Pump Capacitor Selection Use low ESR ceramic capacitors (less than 100m) for optimum performance. Charge Pump Flying Capacitor (C1) The flying capacitor (C1), see Figure 1, affects the load regulation and output impedance of the charge pump. A C1 value that is too low results in a loss of current drive, leading to a loss of amplifier headroom. A higher valued C1 improves load regulation and lowers charge pump output impedance to an extent. Above 2.2F, the RDS(ON) of the charge pump switches and the ESR of C1 and CPVSS dominate the output impedance. A lower value capacitor can be used in systems with low maximum output power requirements. Charge Pump Hold Capacitor (CPVSS) The value and ESR of the hold capacitor (CPVSS) directly affects the ripple on CPVSS. (see Figure 1) Increasing the value of CPVSS reduces output ripple. Decreasing the ESR of CPVSS reduces both output ripple and charge pump output impedance. A lower value capacitor can be used in systems with low maximum output power requirements. Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 29 TI Confidential - NDA Restrictions LM49151 SNAS482F - MARCH 2009 - REVISED MARCH 2013 www.ti.com Input Capacitor Selection Input capacitors may be required for some applications, or when the audio source is single-ended. Input capacitors block the DC component of the audio signal, eliminating any conflict between the DC component of the audio source and the bias voltage of the LM49151. The input capacitors create a high-pass filter with the input resistors RIN. The -3dB point of the high-pass filter is found using Equation 4 below. f = 1/ 2RINCIN (Hz) (4) Where the value of RIN is given in the Electrical Characteristics Table. High-pass filtering the audio signal helps protect the speakers. When the LM49151 is using a single-ended source, power supply noise on the ground is seen as an input signal. Setting the high-pass filter point above the power supply noise frequencies, 217Hz in a GSM phone, for example, filters out the noise such that it is not amplified and heard on the output. Capacitors with a tolerance of 10% or better are recommended for impedance matching and improved CMRR and PSRR. Revision History 30 Rev Date Description 0.01 02/12/09 Initial PDF. 0.02 02/23/09 Text edits. 0.03 03/05/09 Text edits. 0.04 03/24/09 Text edits and added more graphs. 0.05 03/25/09 Cosmetic fixes. 0.06 03/26/09 Released 1-4 pages. 0.07 04/01/09 Text edits. 0.08 04/09/09 Text edits and edited the Ordering Information table. 0.09 04/15/09 Text edits. 0.10 05/19/09 Text edits. 0.11 09/04/09 Text edits. 0.12 09/18/09 Text edits. 0.13 10/29/09 Fixed typos on Table 4. 0.14 08/20/12 Full D/S to be released. F 03/21/2013 Changed layout of National Data Sheet to TI format Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM49151 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Top-Side Markings (3) (4) LM49151TL/NOPB ACTIVE DSBGA YZR 20 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 GL7 LM49151TLX/NOPB ACTIVE DSBGA YZR 20 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 GL7 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 21-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM49151TL/NOPB DSBGA YZR 20 250 178.0 8.4 LM49151TLX/NOPB DSBGA YZR 20 3000 178.0 8.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2.34 2.85 0.76 4.0 8.0 Q1 2.34 2.85 0.76 4.0 8.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 21-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM49151TL/NOPB DSBGA YZR LM49151TLX/NOPB DSBGA YZR 20 250 210.0 185.0 35.0 20 3000 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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