CYBLE-222005-00 EZ-BLETM Creator Module EZ-BLETM PRoCTM Module General Description The Cypress CYBLE-222005-00 is a fully certified and qualified module supporting Bluetooth Low Energy (BLE) wireless communication. The CYBLE-222005-00 is a turnkey solution and includes onboard crystal oscillators, chip antenna, passive components, and Cypress PSoC 4 BLE. Refer to the PSoC 4 BLE datasheet for additional details on the capabilities of the PSoC 4 BLE device used on this module. Functional Capabilities The CYBLE-222005-00 supports a number of peripheral functions (ADC, timers, counters, PWM) and serial communication protocols (I2C, UART, SPI) through its programmable architecture. The CYBLE-222005-00 includes a royalty-free BLE stack compatible with Bluetooth 4.1 and provides up to 16 GPIOs in a small 10 x 10 x 1.80 mm package. The CYBLE-222005-00 is a complete solution and an ideal fit for applications requiring BLE wireless connectivity. Module Description Module size: 10.0 mm x10.0 mm x 1.80 mm (with shield) Drop-in compatible with CYBLE-022001-00 and includes additional VREF input 256-KB flash memory, 32-KB SRAM memory Up to 16 GPIOs configurable as open drain high/low, pull-up/pull-down, HI-Z analog, HI-Z digial, or strong output Bluetooth 4.1 qualified single-mode module QDID: 79920 Declaration ID: D029884 Up to 15 capacitive sensors for buttons or sliders with best-in-class signal-to-noise ration (SNR) and liquid tolerance 12-bit, 1-Msps SAR ADC with internal sample-and-hold (S/H), and channel sequencer reference, Two serial communication blocks (SCBs) supporting I2C (master/slave), SPI (master/slave), or UART Four dedicated 16-bit timer, counter, or PWM blocks (TCPWMs) Programmable low voltage detect (LVD) from 1.8 V to 4.5 V I2S master interface Bluetooth Low Energy protocol stack supporting generic access profile (GAP) Central, Peripheral, Observer, or Broadcaster roles Switches between Central and Peripheral roles on-the-go Standard Bluetooth Low Energy profiles and services for interoperability Custom profile and service for specific use cases Benefits Certified to FCC, ISED, MIC, KC, and CE regulations FCC ID: WAP2005 IC ID: 7922A-2005 MIC ID: 203-JN0495 KC ID: MSIP-CRM-Cyp-2005 Industrial temperature range: -40 C to +85 C 32-bit processor (0.9 DMIPS/MHz) with single-cycle 32-bit multiply, operating at up to 48 MHz Watchdog timer with dedicated internal low-speed oscillator (ILO) Two-pin SWD for programming Power Consumption TX output power: -18 dbm to +3 dbm Received signal strength indicator (RSSI) with 1-dB resolution TX current consumption of 15.6 mA (radio only, 0 dbm) RX current consumption of 16.4 mA (radio only) Cypress Semiconductor Corporation Document Number: 002-00214 Rev. *H Low power mode support Deep Sleep: 1.3 A with watch crystal oscillator (WCO) on Hibernate: 150 nA with SRAM retention Stop: 60 nA with XRES wakeup The CYBLE-222005-00 module is provided as a turnkey solution, including all necessary hardware required to use BLE communication standards. Proven, qualified, and certified hardware design ready to use Small footprint (10 x 10 mm x 1.80 mm), perfect for space constrained applications Reprogrammable architecture Fully certified module eliminates the time needed for design, development and certification processes Bluetooth SIG qualified with QDID and Declaration ID Flexible communication protocol support PSoC CreatorTM provides an easy-to-use integrated design environment (IDE) to configure, develop, program, and test a BLE application 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Revised March 12, 2018 CYBLE-222005-00 More Information Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to quickly and effectively integrate the module into your design. Overview: EZ-BLE Module Portfolio, Module Roadmap PSoC 4 BLE Silicon Datasheet Application notes: Cypress offers a number of BLE application notes covering a broad range of topics, from basic to advanced level. Recommended application notes for getting started with EZ-BLE modules are: AN96841 - Getting Started with EZ-BLE Module AN91267 - Getting Started with PSoC(R) 4 BLE (R) AN97060 - PSoC 4 BLE and PRoCTM BLE - Over-The-Air (OTA) Device Firmware Upgrade (DFU) Guide AN91162 - Creating a BLE Custom Profile AN91184 - PSoC 4 BLE - Designing BLE Applications AN92584 - Designing for Low Power and Estimating Battery Life for BLE Applications (R) (R) AN85951 - PSoC 4 CapSense Design Guide (R) AN95089 - PSoC 4/PRoCTM BLE Crystal Oscillator Selection and Tuning Techniques AN91445 - Antenna Design and RF Layout Guidelines Technical Reference Manual (TRM): (R) PRoC BLE Technical Reference Manual Knowledge Base Articles KBA04069 - Pin Mapping Differences Between the EZ-BLETM Creator Evaluation Board (CYBLE-222005-EVAL) and the BLE Pioneer Kit (CY8CKIT-042-BLE) KBA97095 - EZ-BLETM Module Placement KBA210559 - RF Regulatory Certifications for EZ-BLETM Creator Module CYBLE-222005-00 - KBA210559 KBA213976 - FAQ for BLE and Regulatory Certifications with EZ-BLE modules KBA210802 - Queries on BLE Qualification and Declaration Processes KBA2108122 - 3D Model Files for EZ-BLE/EZ-BT Modules Development Kits: CYBLE-222005-EVAL, CYBLE-222005-00 Evaluation Board (R) CY8CKIT-042-BLE, Bluetooth Low Energy (BLE) Pioneer Kit (R) CY8CKIT-002, PSoC MiniProg3 Program and Debug Kit Test and Debug Tools: (R) CYSmart, Bluetooth LE Test and Debug Tool (Windows) (R) CYSmart Mobile, Bluetooth LE Test and Debug Tool (Android/iOS Mobile App) Two Easy-To-Use Design Environments to Get You Started Quickly PSoC(R) CreatorTM Integrated Design Environment (IDE) PSoC Creator is an Integrated Design Environment (IDE) that enables concurrent hardware and firmware editing, compiling and debugging of PSoC 3, PSoC 4, PSoC 5LP, PSoC 4 BLE, and EZ-BLE module systems with no code size limitations. PSoC peripherals are designed using schematic capture and simple graphical user interface (GUI) with over 120 pre-verified, production-ready PSoC ComponentsTM. PSoC Components are analog and digital "virtual chips," represented by an icon that users can drag-and-drop into a design and configure to suit a broad array of application requirements. Blutooth Low Energy Component The Bluetooth Low Energy Component inside PSoC Creator provides a comprehensive GUI-based configuration window that lets you quickly design BLE applications. The Component incorporates a Bluetooth Core Specification v4.1 compliant BLE protocol stack and provides API functions to enable user applications to interface with the underlying Bluetooth Low Energy Sub-System (BLESS) hardware via the stack. EZ-SerialTM BLE Firmware Platform The EZ-Serial Firmware Platform provides a simple way to access the most common hardware and communication features needed in BLE applications. EZ-Serial implements an intuitive API protocol over the UART interface and exposes various status and control signals through the module's GPIOs, making it easy to add BLE functionality quickly to existing designs. Use a simple serial terminal and evaluation kit to begin development without requiring an IDE. Refer to the EZ-Serial webpage for User Manuals and instructions for getting started as well as detailed reference materials. EZ-BLE modules are pre-flashed with the EZ-Serial Firmware Platform. If you do not have EZ-Serial pre-loaded on your module, you can download each EZ-BLE module's firmware images on the EZ-Serial webpage. Technical Support Frequently Asked Questions (FAQs): Learn more about our BLE ECO System. Forum: See if your question is already answered by fellow developers on the PSoC 4 BLE. Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States, you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt. Document Number: 002-00214 Rev. *H Page 2 of 38 CYBLE-222005-00 Contents Overview ............................................................................ 4 Module Description ...................................................... 4 Pad Connection Interface ................................................ 6 Recommended Host PCB Layout ................................... 7 Digital and Analog Capabilities and Connections......... 9 Power Supply Connections and Recommended External Components.................................................................... 10 Connection Options ................................................... 10 External Component Recommendation .................... 10 Critical Components List ........................................... 12 Antenna Design......................................................... 12 Electrical Specification .................................................. 13 GPIO ......................................................................... 15 XRES......................................................................... 17 Digital Peripherals ..................................................... 19 Serial Communication ............................................... 21 Memory ..................................................................... 22 System Resources .................................................... 22 Environmental Specifications ....................................... 28 Environmental Compliance ....................................... 28 RF Certification.......................................................... 28 Safety Certification .................................................... 28 Environmental Conditions ......................................... 28 ESD and EMI Protection ........................................... 28 Document Number: 002-00214 Rev. *H Regulatory Information .................................................. 29 FCC ........................................................................... 29 ISED .......................................................................... 30 European R&TTE Declaration of Conformity ............ 30 MIC Japan ................................................................. 31 KC Korea ................................................................... 31 Packaging ........................................................................ 32 Ordering Information ...................................................... 34 Part Numbering Convention ...................................... 34 Acronyms ........................................................................ 35 Document Conventions ................................................. 35 Units of Measure ....................................................... 35 Document History Page ................................................. 36 Sales, Solutions, and Legal Information ...................... 38 Worldwide Sales and Design Support ....................... 38 Products .................................................................... 38 PSoC(R) Solutions ...................................................... 38 Cypress Developer Community ................................. 38 Technical Support ..................................................... 38 Page 3 of 38 CYBLE-222005-00 Overview Module Description The CYBLE-222005-00 module is a complete module designed to be soldered to the applications main board. Module Dimensions and Drawing Cypress reserves the right to select components (including the appropriate BLE device) from various vendors to achieve the BLE module functionality. Such selections will still guarantee that all height restrictions of the component area are maintained. Designs should be held within the physical dimensions shown in the mechanical drawings in Figure 1. All dimensions are in millimeters (mm). Table 1. Module Design Dimensions Dimension Item Specification Length (X) 10.00 0.15 mm Width (Y) 10.00 0.15 mm Length (X) 7.00 0.15 mm Width (Y) 5.00 0.15 mm PCB thickness Height (H) 0.50 0.10 mm Shield height Height (H) 1.10 0.10 mm Module dimensions Antenna location dimensions Maximum component height Height (H) 1.30-mm typical (chip antenna) Total module thickness (bottom of module to highest component) Height (H) 1.80-mm typical See Figure 1 on page 5 for the mechanical reference drawing for CYBLE-222005-00. Document Number: 002-00214 Rev. *H Page 4 of 38 CYBLE-222005-00 Figure 1. Module Mechanical Drawing Top View (View from Top) Side View Bottom View (Seen from Bottom) Note 1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see "Recommended Host PCB Layout" on page 7. Document Number: 002-00214 Rev. *H Page 5 of 38 CYBLE-222005-00 Pad Connection Interface As shown in the bottom view of Figure 1 on page 5, the CYBLE-222005-00 connects to the host board via solder pads on the back of the module. Table 2 and Figure 2 detail the solder pad length, width, and pitch dimensions of the CYBLE-222005-00 module. Table 2. Solder Pad Connection Description Name SP Connections Connection Type 22 Solder Pads Pad Length Dimension Pad Width Dimension Pad Pitch 0.71 mm 0.41 mm 0.76 mm Figure 2. Solder Pad Dimensions (Seen from Bottom) To maximize RF performance, the host layout should follow these recommendations: 1. The ideal placement of the Cypress BLE module is in a corner of the host board with the chip antenna located at the far corner. This placement minimizes the additional recommended keep out area stated in item 2. Refer to AN96841 for module placement best practices. 2. To maximize RF performance, the area immediately around the Cypress BLE module chip antenna should contain an additional keep out area, where no grounding or signal traces are contained. The keep out area applies to all layers of the host board. The recommended dimensions of the host PCB keep out area are shown in Figure 3 (dimensions are in mm). Figure 3. Recommended Host PCB Keep Out Area Around the CYBLE-222005-00 Chip Antenna Host PCB Keep Out Area Around Chip Antenna Document Number: 002-00214 Rev. *H Page 6 of 38 CYBLE-222005-00 Recommended Host PCB Layout Figure 4, Figure 5, Figure 6, and Table 3 provide details that can be used for the recommended host PCB layout pattern for the CYBLE-222005-00. Dimensions are in millimeters unless otherwise noted. Pad length of 0.91 mm (0.455 mm from center of the pad on either side) shown in Figure 6 is the minimum recommended host pad length. The host PCB layout pattern can be completed using either Figure 4, Figure 5, or Figure 6. It is not necessary to use all figures to complete the host PCB layout pattern. Figure 4. Host Layout Pattern for CYBLE-222005-00 Figure 5. Module Pad Location from Origin Top View (Seen on Host PCB) Top View (Seen on Host PCB) Document Number: 002-00214 Rev. *H Page 7 of 38 CYBLE-222005-00 Table 3 provides the center location for each solder pad on the CYBLE-222005-00. All dimensions are referenced to the center of the solder pad. Refer to Figure 6 for the location of each module solder pad. Table 3. Module Solder Pad Location Figure 6. Solder Pad Reference Location Solder Pad (Center of Pad) Location (X,Y) from Orign (mm) Dimension from Orign (mils) 1 (0.26, 1.64) (10.24, 64.57) 2 (0.26, 2.41) (10.24, 94.88) 3 (0.26, 3.17) (10.24, 124.80) 4 (0.26, 3.93) (10.24, 154.72) 5 (0.26, 4.69) (10.24, 184.65) 6 (0.26, 5.45) (10.24, 214.57) 7 (0.81, 9.74) (31.89, 383.46) 8 (1.57, 9.74) (61.81, 383.46) 9 (2.34, 9.74) (92.13, 383.46) 10 (3.10, 9.74) (122.05, 383.46) 11 (3.86, 9.74) (151.97, 383.46) 12 (4.62, 9.74) (181.89, 383.46) 13 (5.38, 9.74) (211.81, 383.46) 14 (6.15, 9.74) (242.13, 383.46) 15 (6.91, 9.74) (272.05, 383.46) 16 (7.67, 9.74) (301.97, 383.46) 17 (8.43, 9.74) (331.89, 383.46) 18 (9.19, 9.74) (361.81, 383.46) 19 (9.75, 8.50) (383.86, 334.65) 20 (9.75, 7.74) (383.86, 304.72) 21 (9.75, 6.98) (383.86, 274.80) 22 (9.75, 6.22) (383.86, 244.88) Document Number: 002-00214 Rev. *H Top View (Seen on Host PCB) Page 8 of 38 CYBLE-222005-00 Digital and Analog Capabilities and Connections Table 4 details the solder pad connection definitions and available functions for each connection pad. Table 4 lists the solder pads on CYBLE-222005-00, the BLE device port-pin, and denotes whether the function shown is available for each solder pad. Each connection is configurable for a single option shown with a . Table 4. Solder Pad Connection Definitions Solder Pad Number Device Port Pin 1 GND[4] 2 [5] P4.1 3 P5.1 4 P5.0 5 VDDR 6 VREF P1.6 8 P0.7 P0.4 10 P0.5 11 GND 12 P0.6 13 SPI (SCB1_CTS) (SCB1_MISO) P1.7 I2 C TCPWM[2,3] CapSense (TCPWM0_N) (Sensor/ CTANK) (SCB0_RTS) (SCB0_SS0) (SCB0_CTS) (SCB0_SCLK) Voltage Reference Input (Optional) (TCPWM) (Sensor) (TCPWM) (SCB0_RX) (SCB0_MOSI) (SCB0_SDA) (TCPWM) (SCB0_TX) (SCB0_MISO) (SCB0_SCL) (TCPWM) (SCB0_RTS) (SCB0_SS0) (SCB0_CTS) (SCB0_SCLK) (TCPWM) (TCPWM) (Sensor) VDD Digital Power Supply Input (1.71 to 5.5V) XRES External Reset Hardware Connection Input P3.5 P3.4 18 P3.7 19 P1.4 20 P1.5 21 P3.6 22 P4.0[7] GPIO (SCB1_TX) (SCB1_RX) (SCB1_CTS) (SCB0_RX) (SCB0_MOSI) (SCB0_TX) (SCB0_MISO) (SCB1_RTS) (SCB1_RTS) (SCB1_MOSI) (SWDCLK) Ground Connection 14 17 SWD Radio Power Supply (1.9V to 5.5V) 15 16 WCO ECO LCD OUT OUT Ground Connection (SCB1_TX) (SCB1_SCLK) (SCB1_SCL) (TCPWM3_N) (SCB1_RX) (SCB1_SS0) (SCB1_SDA) (TCPWM3_P) [6] 7 9 UART (SCB1_SCL) (TCPWM) (SCB1_SDA) (TCPWM) (TCPWM) (SCB0_SDA) (TCPWM) (SCB0_SCL) (TCPWM) (TCPWM) (TCPWM0_P) (CMOD) (SWDIO) Notes 2. TCPWM stands for timer, counter, and PWM. If supported, the pad can be configured to any of these peripheral functions. 3. TCPWM connections on ports 0, 1, 2, and 3 can be routed through the Digital Signal Interconnect (DSI) to any of the TCPWM blocks and can be either positive or negative polarity. TCPWM connections on ports 4 and 5 are direct and can only be used with the specified TCPWM block and polarity specified above. 4. The main board needs to connect both GND connections (Pad 1 and Pad 10) on the module to the common ground of the system. 5. When using the capacitive sensing functionality, Pad 2 (P4.1) can be connected to a CTANK capacitor (located off of Cypress BLE Module). CTank should be used if implementing a shield layer on the capacitive sensor. If used, this capacitor should be placed as close to the module as possible. 6. Analog block functionality is augmented for the user with the external VREF input. The internal bandgap may be bypassed with a 1-F to 10-F capacitor. 7. When using the capacitive sensing functionality, Pad 22 (P4.0) must be connected to a CMOD capacitor (located off of Cypress BLE Module). The value of this capacitor is 2.2 nF and should be placed as close to the module as possible. 8. If the I2S feature is used in the design, the I2S pins shall be dynamically routed to the appropriate available GPIO by PSoC Creator Document Number: 002-00214 Rev. *H Page 9 of 38 CYBLE-222005-00 Power Supply Connections and Recommended External Components Power Connections External Component Recommendation The CYBLE-222005-00 contains two power supply connections, VDD and VDDR. The VDD connection supplies power for both digital and analog device operation. The VDDR connection supplies power for the device radio. In either connection scenario, it is recommended to place an external ferrite bead between the supply and the module connection. The ferrite bead should be positioned as close as possible to the module pin connection. VDD accepts a supply range of 1.71 V to 5.5 V. VDDR accepts a supply range of 1.9 V to 5.5 V. These specifications can be found in Table 9. The maximum power supply ripple for both power connections on the module is 100 mV, as shown in Table 7. Figure 7 details the recommended host schematic options for a single supply scenario. The use of one or two ferrite beads will depend on the specific application and configuration of the CYBLE-222005-00. The power supply ramp rate of VDD must be equal to or greater than that of VDDR. Connection Options Figure 8 details the recommended host schematic for an independent supply scenario. The recommended ferrite bead value is 330 , 100 MHz. (Murata BLM21PG331SN1D). Two connection options are available for any application: 1. Single supply: Connect VDD and VDDR to the same supply. 2. Independent supply: Power VDD and VDDR separately. Figure 7. Recommended Host Schematic Options for a Single Supply Option Single Ferrite Bead Option (Seen from Bottom) Two Ferrite Bead Option (Seen from Bottom) Figure 8. Recommended Host Schematic for an Independent Supply Option Independent Power Supply Option (Seen from Bottom) Document Number: 002-00214 Rev. *H Page 10 of 38 CYBLE-222005-00 The CYBLE-222005-00 schematic is shown in Figure 9. Figure 9. CYBLE-222005-00 Schematic Diagram Document Number: 002-00214 Rev. *H Page 11 of 38 CYBLE-222005-00 Critical Components List Table 5 details the critical components used in the CYBLE-222005-00 module. Table 5. Critical Component List Component Reference Designator Silicon U1 Description 76-pin WLCSP PSoC 4 BLE Crystal Y1 24.000 MHz, 10PF Crystal Y2 32.768 kHz, 12.5PF Antenna E1 2.4-2.5 GHz chip antenna Antenna Design Table 6 details the chip antenna used in the CYBLE-222005-00 module. The specifications listed are according to the vendor's datasheet. The Cypress module performance improves many of these characteristics. For more information, see Table 8. Table 6. Chip Antenna Specifications Item Description Chip Antenna Manufacturer Johanson Technology Inc. Chip Antenna Part Number 2450AT18B100 Frequency Range 2400-2500 MHz Peak Gain 0.5 dBi typical Average Gain -0.5-dBi typical Return Loss 9.5-dB minimum Document Number: 002-00214 Rev. *H Page 12 of 38 CYBLE-222005-00 Electrical Specification Table 7 details the absolute maximum electrical characteristics for the Cypress BLE module. Table 7. CYBLE-222005-00 Absolute Maximum Ratings Parameter Description Min Typ Max Units Details/Conditions VDDD_ABS Analog, digital, or radio supply relative to VSS (VSSD = VSSA) -0.5 - 6 V Absolute maximum VCCD_ABS Direct digital core voltage input relative to VSSD -0.5 - 1.95 V Absolute maximum VDDD_RIPPLE Maximum power supply ripple for VDD and VDDR input voltage - - 100 mV VGPIO_ABS GPIO voltage -0.5 - VDD +0.5 V Absolute maximum IGPIO_ABS Maximum current per GPIO -25 - 25 mA Absolute maximum IGPIO_injection GPIO injection current: Maximum for VIH > VDD and minimum for VIL < VSS -0.5 - 0.5 mA Absolute maximum current injected per pin LU Pin current for latch up -200 200 mA - 3.0-V supply Ripple frequency of 100 kHz to 750 kHz Table 8 details the RF characteristics for the Cypress BLE module. Table 8. CYBLE-222005-00 RF Performance Characteristics Parameter Description Min Typ Max Units Details/Conditions -18 0 3 dBm Configurable via register settings - -87 - dBm Guaranteed by design simulation RFO RF output power on ANT RXS RF receive sensitivity on ANT FR Module frequency range 2400 - 2480 MHz - GP Peak gain - 0.5 - dBi - GAvg Average gain - -0.5 - dBi - RL Return loss - -10.5 - dB - Table 9 through Table 47 list the module level electrical characteristics for the CYBLE-222005-00. All specifications are valid for -40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. Table 9. CYBLE-222005-00 DC Specifications Parameter Description Min Typ Max Units Details/Conditions VDD1 Power supply input voltage 1.8 - 5.5 V With regulator enabled VDD2 Power supply input voltage unregulated 1.71 1.8 1.89 V Internally unregulated supply VDDR1 Radio supply voltage (radio on) 1.9 - 5.5 V - VDDR2 Radio supply voltage (radio off) 1.71 - 5.5 V - Active Mode, VDD = 1.71 V to 5.5 V T = 25 C, VDD = 3.3 V IDD3 Execute from flash; CPU at 3 MHz - 1.7 - mA IDD4 Execute from flash; CPU at 3 MHz - - - mA T = -40 C to 85 C IDD5 Execute from flash; CPU at 6 MHz - 2.5 - mA T = 25 C, VDD = 3.3 V IDD6 Execute from flash; CPU at 6 MHz - - - mA T = -40 C to 85 C IDD7 Execute from flash; CPU at 12 MHz - 4 - mA T = 25 C, VDD = 3.3 V Document Number: 002-00214 Rev. *H Page 13 of 38 CYBLE-222005-00 Table 9. CYBLE-222005-00 DC Specifications (continued) Parameter IDD8 Description Execute from flash; CPU at 12 MHz Min Typ Max Units Details/Conditions - - - mA T = -40 C to 85 C IDD9 Execute from flash; CPU at 24 MHz - 7.1 - mA T = 25 C, VDD = 3.3 V IDD10 Execute from flash; CPU at 24 MHz - - - mA T = -40 C to 85 C IDD11 Execute from flash; CPU at 48 MHz - 13.4 - mA T = 25 C, VDD = 3.3 V IDD12 Execute from flash; CPU at 48 MHz - - - mA T = -40 C to 85 C - - - mA T = 25 C, VDD = 3.3 V, SYSCLK = 3 MHz - - - mA T = 25 C, VDD = 3.3 V, SYSCLK = 3 MHz Sleep Mode, VDD = 1.8 V to 5.5 V IDD13 IMO on Sleep Mode, VDD and VDDR = 1.9 V to 5.5 V IDD14 ECO on Deep-Sleep Mode, VDD = 1.8 V to 3.6 V IDD15 WDT with WCO on - 1.5 - A T = 25 C, VDD = 3.3 V IDD16 WDT with WCO on - - - A T = -40 C to 85 C IDD17 WDT with WCO on - - - A T = 25 C, VDD = 5 V IDD18 WDT with WCO on - - - A T = -40 C to 85 C Deep-Sleep Mode, VDD = 1.71 V to 1.89 V (Regulator Bypassed) IDD19 WDT with WCO on - - - A T = 25 C IDD20 WDT with WCO on - - - A T = -40 C to 85 C Hibernate Mode, VDD = 1.8 V to 3.6 V IDD27 GPIO and reset active - 150 - nA T = 25 C, VDD = 3.3 V IDD28 GPIO and reset active - - - nA T = -40 C to 85 C Hibernate Mode, VDD = 3.6 V to 5.5 V IDD29 GPIO and reset active - - - nA T = 25 C, VDD = 5 V IDD30 GPIO and reset active - - - nA T = -40 C to 85 C Stop Mode, VDD = 1.8 V to 3.6 V IDD33 Stop-mode current (VDD) - 20 - nA T = 25 C, VDD = 3.3 V IDD34 Stop-mode current (VDDR) - 40 -- nA T = 25 C, VDDR = 3.3 V IDD35 Stop-mode current (VDD) - - - nA T = -40 C to 85 C IDD36 Stop-mode current (VDDR) - - - nA T = -40 C to 85 C, VDDR = 1.9 V to 3.6 V Stop Mode, VDD = 3.6 V to 5.5 V IDD37 Stop-mode current (VDD) - - - nA T = 25 C, VDD = 5 V IDD38 Stop-mode current (VDDR) - - - nA T = 25 C, VDDR = 5 V IDD39 Stop-mode current (VDD) - - - nA T = -40 C to 85 C IDD40 Stop-mode current (VDDR) - - - nA T = -40 C to 85 C Document Number: 002-00214 Rev. *H Page 14 of 38 CYBLE-222005-00 Table 10. AC Specifications Parameter Description Min Typ Max Units DC - 48 MHz Wakeup from Sleep mode - 0 - s Guaranteed by characterization TDEEPSLEEP Wakeup from Deep-Sleep mode - - 25 s 24-MHz IMO. Guaranteed by characterization THIBERNATE Wakeup from Hibernate mode - - 2 ms Guaranteed by characterization TSTOP Wakeup from Stop mode - - 2 ms XRES wakeup Min Typ Max Units FCPU CPU frequency TSLEEP Details/Conditions 1.71 V VDD 5.5 V GPIO Table 11. GPIO DC Specifications Parameter VIH[9] Description Input voltage HIGH threshold 0.7 x VDD - - V LVTTL input, VDD < 2.7 V 0.7 x VDD - - V LVTTL input, VDD >= 2.7 V 2.0 - - V - - 0.3 x VDD V Input voltage LOW threshold VIL VOH VOL Details/Conditions CMOS input - - CMOS input LVTTL input, VDD < 2.7 V - - 0.3x VDD V - LVTTL input, VDD >= 2.7 V - - 0.8 V - Output voltage HIGH level VDD -0.6 - - V IOH = 4 mA at 3.3-V VDD Output voltage HIGH level VDD -0.5 - - V IOH = 1 mA at 1.8-V VDD Output voltage LOW level - - 0.6 V IOL = 8 mA at 3.3-V VDD Output voltage LOW level - - 0.6 V IOL = 4 mA at 1.8-V VDD IOL = 3 mA at 3.3-V VDD - - 0.4 V RPULLUP Output voltage LOW level Pull-up resistor 3.5 5.6 8.5 k RPULLDOWN Pull-down resistor 3.5 5.6 8.5 k IIL Input leakage current (absolute value) - - 2 nA IIL_CTBM Input leakage on CTBm input pins - - 4 nA - CIN Input capacitance - - 7 pF - - - 25 C, VDD = 3.3 V VHYSTTL Input hysteresis LVTTL 25 40 - mV VHYSCMOS Input hysteresis CMOS 0.05 x VDD - - 1 - IDIODE Current through protection diode to VDD/VSS - - 100 A - ITOT_GPIO Maximum total source or sink chip current - - 200 mA - VDD > 2.7 V Note 9. VIH must not exceed VDD + 0.2 V. Document Number: 002-00214 Rev. *H Page 15 of 38 CYBLE-222005-00 Table 12. GPIO AC Specifications Parameter Description Min Typ Max Units Details/Conditions TRISEF Rise time in Fast-Strong mode 2 - 12 ns 3.3-V VDDD, CLOAD = 25 pF TFALLF Fall time in Fast-Strong mode 2 - 12 ns 3.3-V VDDD, CLOAD = 25 pF TRISES Rise time in Slow-Strong mode 10 - 60 ns 3.3-V VDDD, CLOAD = 25 pF TFALLS Fall time in Slow-Strong mode 10 - 60 ns 3.3-V VDDD, CLOAD = 25 pF FGPIOUT1 GPIO FOUT; 3.3 V VDD 5.5 V Fast-Strong mode - - 33 MHz 90/10%, 25-pF load, 60/40 duty cycle FGPIOUT2 GPIO FOUT; 1.7 VVDD 3.3 V Fast-Strong mode - - 16.7 MHz 90/10%, 25-pF load, 60/40 duty cycle FGPIOUT3 GPIO FOUT; 3.3 V VDD 5.5 V Slow-Strong mode - - 7 MHz 90/10%, 25-pF load, 60/40 duty cycle FGPIOUT4 GPIO FOUT; 1.7 V VDD 3.3 V Slow-Strong mode - - 3.5 MHz 90/10%, 25-pF load, 60/40 duty cycle FGPIOIN GPIO input operating frequency 1.71 V VDD 5.5 V - - 48 MHz 90/10% VIO Min Typ Max Units - - 10 A 25C, VDD = 0 V, VIH = 3.0 V - - 0.4 V IOL = 20 mA, VDD > 2.9 V Table 13. OVT GPIO DC Specifications (P5_0 and P5_1 Only) Parameter IIL VOL Description Input leakage (absolute value). VIH > VDD Output voltage LOW level Details/Conditions Table 14. OVT GPIO AC Specifications (P5_0 and P5_1 Only) Description Min Typ Max Units Details/Conditions TRISE_OVFS Parameter Output rise time in Fast-Strong mode 1.5 - 12 ns 25-pF load, 10%-90%, VDD=3.3 V TFALL_OVFS Output fall time in Fast-Strong mode 1.5 - 12 ns 25-pF load, 10%-90%, VDD=3.3 V TRISESS Output rise time in Slow-Strong mode 10 - 60 ns 25-pF load, 10%-90%, VDD = 3.3 V TFALLSS Output fall time in Slow-Strong mode 10 - 60 ns 25-pF load, 10%-90%, VDD = 3.3 V FGPIOUT1 GPIO FOUT; 3.3 V VDD 5.5 V Fast-Strong mode - - 24 MHz 90/10%, 25-pF load, 60/40 duty cycle FGPIOUT2 GPIO FOUT; 1.71 V VDD 3.3 V Fast-Strong mode - - 16 MHz 90/10%, 25-pF load, 60/40 duty cycle Document Number: 002-00214 Rev. *H Page 16 of 38 CYBLE-222005-00 XRES Table 15. XRES DC Specifications Parameter Description Min Typ Max Units Details/Conditions VIH Input voltage HIGH threshold 0.7 x VDDD - - V CMOS input VIL Input voltage LOW threshold - - 0.3 x VDDD V CMOS input RPULLUP Pull-up resistor 3.5 5.6 8.5 k - CIN Input capacitance - 3 - pF - VHYSXRES Input voltage hysteresis - 100 - mV - IDIODE Current through protection diode to VDD/VSS - - 100 A - Min Typ Max Units Details/Conditions 1 - - s - Table 16. XRES AC Specifications Parameter TRESETWIDTH Description Reset pulse width SAR ADC Table 17. SAR ADC DC Specifications Min Typ Max Units A_RES Parameter Resolution Description - - 12 bits A_CHNIS_S Number of channels - single-ended - - 6 6 full-speed[10] A-CHNKS_D Number of channels - differential - - 3 Diff inputs use neighboring I/O[10] A-MONO Monotonicity - - - Yes A_GAINERR Gain error - - 0.1 % With external reference A_OFFSET Input offset voltage - - 2 mV Measured with 1-V VREF A_ISAR Current consumption - - 1 mA A_VINS Input voltage range - single-ended VSS - VDDA V A_VIND Input voltage range - differential VSS - VDDA V A_INRES Input resistance - - 2.2 k A_INCAP Input capacitance - - 10 pF VREFSAR Trimmed internal reference to SAR -1 - 1 % Min Typ Max Units Details/Conditions Percentage of Vbg (1.024 V) Table 18. SAR ADC AC Specifications Parameter Description A_PSRR Power-supply rejection ratio 70 - - dB A_CMRR Common-mode rejection ratio 66 - - dB A_SAMP Sample rate - - 1 Msps Fsarintref SAR operating speed without external ref. bypass - - 100 Ksps Details/ Conditions Measured at 1-V reference 12-bit resolution Note 10. A maximum of six single-ended ADC Channels can be accomplished only if the AMUX Buses are not being used for other functionality (such as CapSense). If the AMUX Buses are being used for other functionality, then the maximum number of single-ended ADC channels is four. Similarly, if the AMUX Buses are being used for other functionality, then the maximum number of differential ADC channels is two. Document Number: 002-00214 Rev. *H Page 17 of 38 CYBLE-222005-00 Table 18. SAR ADC AC Specifications (continued) Parameter Description Min Typ Max Units 65 - - dB Details/ Conditions FIN = 10 kHz A_SNR Signal-to-noise ratio (SNR) A_BW Input bandwidth without aliasing - - A_SAMP/2 kHz A_INL Integral nonlinearity. VDD = 1.71 V to 5.5 V, 1 Msps -1.7 - 2 LSB VREF = 1 V to VDD A_INL Integral nonlinearity. VDDD = 1.71 V to 3.6 V, 1 Msps -1.5 - 1.7 LSB VREF = 1.71 V to VDD A_INL Integral nonlinearity. VDD = 1.71 V to 5.5 V, 500 Ksps -1.5 - 1.7 LSB VREF = 1 V to VDD A_dnl Differential nonlinearity. VDD = 1.71 V to 5.5 V, 1 Msps -1 - 2.2 LSB VREF = 1 V to VDD A_DNL Differential nonlinearity. VDD = 1.71 V to 3.6 V, 1 Msps -1 - 2 LSB VREF = 1.71 V to VDD A_DNL Differential nonlinearity. VDD = 1.71 V to 5.5 V, 500 Ksps -1 - 2.2 LSB VREF = 1 V to VDD A_THD Total harmonic distortion - - -65 dB Description Min Typ Max Units VCSD Voltage range of operation 1.71 - 5.5 V IDAC1 DNL for 8-bit resolution -1 - 1 LSB IDAC1 INL for 8-bit resolution -3 - 3 LSB IDAC2 DNL for 7-bit resolution -1 - 1 LSB IDAC2 INL for 7-bit resolution -3 - 3 LSB SNR Ratio of counts of finger to noise 5 - - Ratio IDAC1_CRT1 Output current of IDAC1 (8 bits) in High range - 612 - A IDAC1_CRT2 Output current of IDAC1 (8 bits) in Low range - 306 - A IDAC2_CRT1 Output current of IDAC2 (7 bits) in High range - 305 - A IDAC2_CRT2 Output current of IDAC2 (7 bits) in Low range - 153 - A FIN = 10 kHz CSD CSD Block Specifications Parameter Document Number: 002-00214 Rev. *H Details/ Conditions Capacitance range of 9 pF to 35 pF, 0.1-pF sensitivity. Radio is not operating during the scan Page 18 of 38 CYBLE-222005-00 Digital Peripherals Timer Table 19. Timer DC Specifications Parameter ITIM1 Description Block current consumption at 3 MHz Min - Typ - Max 42 Units A Details/Conditions 16-bit timer ITIM2 Block current consumption at 12 MHz - - 130 A 16-bit timer ITIM3 Block current consumption at 48 MHz - - 535 A 16-bit timer Min FCLK Typ - Max 48 Units MHz Table 20. Timer AC Specifications Parameter TTIMFREQ Description Operating frequency Details/Conditions TCAPWINT Capture pulse width (internal) 2 x TCLK - - ns TCAPWEXT Capture pulse width (external) 2 x TCLK - - ns TTIMRES Timer resolution TCLK - - ns TTENWIDINT Enable pulse width (internal) 2 x TCLK - - ns TTENWIDEXT Enable pulse width (external) 2 x TCLK - - ns TTIMRESWINT Reset pulse width (internal) 2 x TCLK - - ns TTIMRESEXT Reset pulse width (external) 2 x TCLK - - ns 16-bit counter 16-bit counter Counter Table 21. Counter DC Specifications Parameter ICTR1 Description Block current consumption at 3 MHz Min - Typ - Max 42 ICTR2 Block current consumption at 12 MHz - - 130 Units A A ICTR3 Block current consumption at 48 MHz - - 535 A Details/Conditions 16-bit counter Table 22. Counter AC Specifications Parameter TCTRFREQ Description Operating frequency Min FCLK Typ - Max 48 Units MHz TCTRPWINT Capture pulse width (internal) 2 x TCLK - - ns TCTRPWEXT Capture pulse width (external) 2 x TCLK - - ns TCTRES Counter Resolution TCLK - - ns TCENWIDINT Enable pulse width (internal) 2 x TCLK - - ns TCENWIDEXT Enable pulse width (external) 2 x TCLK - - ns TCTRRESWINT Reset pulse width (internal) 2 x TCLK - - ns TCTRRESWEXT Reset pulse width (external) 2 x TCLK - - ns Details/Conditions Pulse Width Modulation (PWM) Table 23. PWM DC Specifications Parameter Description Min Typ Max Units Details/Conditions IPWM1 Block current consumption at 3 MHz - - 42 A 16-bit PWM IPWM2 Block current consumption at 12 MHz - - 130 A 16-bit PWM IPWM3 Block current consumption at 48 MHz - - 535 A 16-bit PWM Document Number: 002-00214 Rev. *H Page 19 of 38 CYBLE-222005-00 Table 24. PWM AC Specifications Parameter Description Min Typ Max Units TPWMFREQ Operating frequency FCLK - 48 MHz TPWMPWINT Pulse width (internal) 2 x TCLK - - ns TPWMEXT Pulse width (external) 2 x TCLK - - ns TPWMKILLINT Kill pulse width (internal) 2 x TCLK - - ns TPWMKILLEXT Kill pulse width (external) 2 x TCLK - - ns TPWMEINT Enable pulse width (internal) 2 x TCLK - - ns TPWMENEXT Enable pulse width (external) 2 x TCLK - - ns TPWMRESWINT Reset pulse width (internal) 2 x TCLK - - ns TPWMRESWEXT Reset pulse width (external) 2 x TCLK - - ns Details/Conditions LCD Direct Drive Table 25. LCD Direct Drive DC Specifications Spec ID SID228 Parameter ILCDLOW Description Operating current in low-power mode SID229 CLCDCAP LCD capacitance per segment/common driver Long-term segment offset SID230 LCDOFFSET SID231 ILCDOP1 SID232 ILCDOP2 LCD system operating current VBIAS = 5 V LCD system operating current VBIAS = 3.3 V Min - Typ 17.5 Max - Units Details/Conditions A 16 x 4 small segment display at 50 Hz pF - 500 5000 - 20 - mV - 2 - mA - 2 - mA Min 10 Typ 50 Max 150 Units Hz 32 x 4 segments. 50 Hz at 25 C 32 x 4 segments 50 Hz at 25 C Table 26. LCD Direct Drive AC Specifications Spec ID SID233 Parameter FLCD Description LCD frame rate Document Number: 002-00214 Rev. *H Details/Conditions Page 20 of 38 CYBLE-222005-00 Serial Communication Table 27. Fixed I2C DC Specifications Parameter Description Min Typ Max Units Details/Conditions - - 50 A - - - 155 A - - - 390 A - - 1.4 A - Min Typ Max Units Details/Conditions - - 400 kHz II2C1 Block current consumption at 100 kHz II2C2 Block current consumption at 400 kHz II2C3 Block current consumption at 1 Mbps - II2C4 2 I C enabled in Deep-Sleep mode Table 28. Fixed I2C AC Specifications Parameter FI2C1 Description Bit rate Table 29. Fixed UART DC Specifications Min Typ Max Units Details/Conditions IUART1 Parameter Block current consumption at 100 kbps Description - - 55 A - IUART2 Block current consumption at 1000 kbps - - 312 A - Min Typ Max Units Details/Conditions - - 1 Mbps - Table 30. Fixed UART AC Specifications Parameter FUART Description Bit rate Table 31. Fixed SPI DC Specifications Min Typ Max Units Details/Conditions ISPI1 Parameter Block current consumption at 1 Mbps Description - - 360 A - ISPI2 Block current consumption at 4 Mbps - - 560 A - ISPI3 Block current consumption at 8 Mbps - - 600 A - Min - Typ - Max 8 Units MHz Min - Typ - Max 18 Units ns 20 - - ns 0 - - ns Table 32. Fixed SPI AC Specifications Parameter FSPI Description SPI operating frequency (master; 6x over sampling) Details/Conditions - Table 33. Fixed SPI Master Mode AC Specifications Parameter TDSI Description MOSI valid after SCLK driving edge MISO valid before SCLK capturing edge Full clock, late MISO sampling used THMO Previous MOSI data hold time TDMO Details/Conditions - Full clock, late MISO sampling Referred to Slave capturing edge Table 34. Fixed SPI Slave Mode AC Specifications Parameter TDMI Description MOSI valid before SCLK capturing edge TDSO THSO MISO valid after SCLK driving edge MISO Valid after SCLK driving edge in external clock mode. VDD < 3.0 V Previous MISO data hold time TSSELSCK SSEL valid to first SCK valid edge TDSO_ext Document Number: 002-00214 Rev. *H Min 40 Typ - Max - Units ns - - 42 + 3 x TCPU ns - - 50 ns 0 - - ns 100 - - ns Details/Conditions Page 21 of 38 CYBLE-222005-00 Memory Table 35. Flash DC Specifications Parameter Description Min Typ Max Units Details/Conditions 1.71 - 5.5 V - Number of Wait states at 32-48 MHz 2 - - CPU execution from flash Number of Wait states at 16-32 MHz 1 - - CPU execution from flash Number of Wait states for 0-16 MHz 0 - - CPU execution from flash Min Typ Max VPE Erase and program voltage TWS48 TWS32 TWS16 Table 36. Flash AC Specifications Parameter Description Units Details/Conditions TROWWRITE[11] TROWERASE[11] Row (block) write time (erase and program) - - 20 ms Row erase time - - 13 ms - TROWPROGRAM[11] TBULKERASE[11] TDEVPROG[11] Row program time after erase - - 7 ms - FEND Flash endurance FRET FRET2 Row (block) = 256 bytes Bulk erase time (256 KB) - - 35 ms - Total device program time - - 25 seconds - 100 K - - cycles - Flash retention. TA 55 C, 100 K P/E cycles 20 - - years - Flash retention. TA 85 C, 10 K P/E cycles 10 - - years - Min Typ Max Units Details/Conditions System Resources Power-on-Reset (POR) Table 37. POR DC Specifications Parameter Description VRISEIPOR Rising trip voltage 0.80 - 1.45 V - VFALLIPOR Falling trip voltage 0.75 - 1.40 V - VIPORHYST Hysteresis 15 - 200 mV - Min Typ Max Units Details/Conditions - - 1 s - Table 38. POR AC Specifications Parameter TPPOR_TR Description Precision power-on reset (PPOR) response time in Active and Sleep modes Table 39. Brown-Out Detect Description Min Typ Max Units Details/Conditions VFALLPPOR Parameter BOD trip voltage in Active and Sleep modes 1.64 - - V - VFALLDPSLP BOD trip voltage in Deep Sleep 1.4 - - V - Min Typ Max Units Details/Conditions 1.1 - - V - Table 40. Hibernate Reset Parameter VHBRTRIP Description BOD trip voltage in Hibernate Note 11. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated. Document Number: 002-00214 Rev. *H Page 22 of 38 CYBLE-222005-00 Voltage Monitors (LVD) Table 41. Voltage Monitor DC Specifications Parameter VLVI1 Description LVI_A/D_SEL[3:0] = 0000b Min 1.71 Typ 1.75 Max 1.79 Units V Details/Conditions - VLVI2 LVI_A/D_SEL[3:0] = 0001b 1.76 1.80 1.85 V - VLVI3 LVI_A/D_SEL[3:0] = 0010b 1.85 1.90 1.95 V - VLVI4 LVI_A/D_SEL[3:0] = 0011b 1.95 2.00 2.05 V - VLVI5 LVI_A/D_SEL[3:0] = 0100b 2.05 2.10 2.15 V - VLVI6 LVI_A/D_SEL[3:0] = 0101b 2.15 2.20 2.26 V - VLVI7 LVI_A/D_SEL[3:0] = 0110b 2.24 2.30 2.36 V - VLVI8 LVI_A/D_SEL[3:0] = 0111b 2.34 2.40 2.46 V - VLVI9 LVI_A/D_SEL[3:0] = 1000b 2.44 2.50 2.56 V - VLVI10 LVI_A/D_SEL[3:0] = 1001b 2.54 2.60 2.67 V - VLVI11 LVI_A/D_SEL[3:0] = 1010b 2.63 2.70 2.77 V - VLVI12 LVI_A/D_SEL[3:0] = 1011b 2.73 2.80 2.87 V - VLVI13 LVI_A/D_SEL[3:0] = 1100b 2.83 2.90 2.97 V - VLVI14 LVI_A/D_SEL[3:0] = 1101b 2.93 3.00 3.08 V - VLVI15 LVI_A/D_SEL[3:0] = 1110b 3.12 3.20 3.28 V - VLVI16 LVI_A/D_SEL[3:0] = 1111b 4.39 4.50 4.61 V - LVI_IDD Block current - - 100 A - Min Typ Max Units Details/Conditions - - 1 s - Min Typ Max Units Details/Conditions - - 14 MHz SWDCLK 1/3 CPU clock frequency Table 42. Voltage Monitor AC Specifications Parameter TMONTRIP Description Voltage monitor trip time SWD Interface Table 43. SWD Interface Specifications Parameter Description F_SWDCLK1 3.3 V VDD 5.5 V F_SWDCLK2 1.71 V VDD 3.3 V - - 7 MHz SWDCLK 1/3 CPU clock frequency T_SWDI_SETUP T = 1/f SWDCLK 0.25 x T - - ns - T_SWDI_HOLD 0.25 x T - - ns - T_SWDO_VALID T = 1/f SWDCLK T = 1/f SWDCLK - - 0.5 x T ns - T_SWDO_HOLD 1 - - ns - T = 1/f SWDCLK Document Number: 002-00214 Rev. *H Page 23 of 38 CYBLE-222005-00 Internal Main Oscillator Table 44. IMO DC Specifications Parameter Description Min Typ Max Units Details/Conditions IIMO1 IMO operating current at 48 MHz - - 1000 A - IIMO2 IMO operating current at 24 MHz - - 325 A - IIMO3 IMO operating current at 12 MHz - - 225 A - IIMO4 IMO operating current at 6 MHz - - 180 A - IIMO5 IMO operating current at 3 MHz - - 150 A - Table 45. IMO AC Specifications Min Typ Max Units FIMOTOL3 Parameter Frequency variation from 3 to 48 MHz Description - - 2 % Details/Conditions FIMOTOL3 IMO startup time - 12 - s - Min Typ Max Units Details/Conditions - 0.3 1.05 A - With API-called calibration Internal Low-Speed Oscillator Table 46. ILO DC Specifications Parameter Description IILO2 ILO operating current at 32 kHz Table 47. ILO AC Specifications Min Typ Max Units Details/Conditions TSTARTILO1 Parameter ILO startup time Description - - 2 ms - FILOTRIM1 32-kHz trimmed frequency 15 32 50 kHz - Table 48. Recommended ECO Trim Value Parameter ECOTRIM Description 24-MHz trim value (firmware configuration) Value Details/Conditions 0x0000A0A0 Recommended trim value that needs to be loaded to register CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG BLE Subsystem Table 49. BLE Subsystem Parameter Description Details/ Conditions Min Typ Max Units RX sensitivity with idle transmitter - -89 - dBm RX sensitivity with idle transmitter excluding Balun loss - -91 - dBm Guaranteed by design simulation RXS, DIRTY RX sensitivity with dirty transmitter - -87 -70 dBm RF-PHY Specification (RCV-LE/CA/01/C) RXS, HIGHGAIN RX sensitivity in high-gain mode with idle transmitter - -91 - dBm PRXMAX Maximum input power -10 -1 - dBm RF-PHY Specification (RCV-LE/CA/06/C) CI1 Cochannel interference, Wanted signal at -67 dBm and Interferer at FRX - 9 21 dB RF-PHY Specification (RCV-LE/CA/03/C) RF Receiver Specification RXS, IDLE Document Number: 002-00214 Rev. *H Page 24 of 38 CYBLE-222005-00 Table 49. BLE Subsystem (continued) Parameter Details/ Conditions Description Min Typ Max Units CI2 Adjacent channel interference Wanted signal at -67 dBm and Interferer at FRX 1 MHz - 3 15 dB RF-PHY Specification (RCV-LE/CA/03/C) CI3 Adjacent channel interference Wanted signal at -67 dBm and Interferer at FRX 2 MHz - -29 - dB RF-PHY Specification (RCV-LE/CA/03/C) CI4 Adjacent channel interference Wanted signal at -67 dBm and Interferer at FRX 3 MHz - -39 - dB RF-PHY Specification (RCV-LE/CA/03/C) CI5 Adjacent channel interference Wanted Signal at -67 dBm and Interferer at Image frequency (FIMAGE) - -20 - dB RF-PHY Specification (RCV-LE/CA/03/C) CI3 Adjacent channel interference Wanted signal at -67 dBm and Interferer at Image frequency (FIMAGE 1 MHz) - -30 - dB RF-PHY Specification (RCV-LE/CA/03/C) OBB1 Out-of-band blocking, Wanted signal at -67 dBm and Interferer at F = 30-2000 MHz -30 -27 - dBm RF-PHY Specification (RCV-LE/CA/04/C) OBB2 Out-of-band blocking, Wanted signal at -67 dBm and Interferer at F = 2003-2399 MHz -35 -27 - dBm RF-PHY Specification (RCV-LE/CA/04/C) OBB3 Out-of-band blocking, Wanted signal at -67 dBm and Interferer at F = 2484-2997 MHz -35 -27 - dBm RF-PHY Specification (RCV-LE/CA/04/C) OBB4 Out-of-band blocking, Wanted signal a -67 dBm and Interferer at F = 3000-12750 MHz -30 -27 - dBm RF-PHY Specification (RCV-LE/CA/04/C) IMD Intermodulation performance Wanted signal at -64 dBm and 1-Mbps BLE, third, fourth, and fifth offset channel -50 - - dBm RF-PHY Specification (RCV-LE/CA/05/C) RXSE1 Receiver spurious emission 30 MHz to 1.0 GHz - - -57 dBm 100-kHz measurement bandwidth ETSI EN300 328 V1.8.1 RXSE2 Receiver spurious emission 1.0 GHz to 12.75 GHz - - -47 dBm 1-MHz measurement bandwidth ETSI EN300 328 V1.8.1 RF Transmitter Specifications TXP, ACC RF power accuracy - 1 - dB TXP, RANGE RF power control range - 20 - dB TXP, 0dBm Output power, 0-dB Gain setting (PA7) - 0 - dBm TXP, MAX Output power, maximum power setting (PA10) - 3 - dBm TXP, MIN Output power, minimum power setting (PA1) - -18 - dBm F2AVG Average frequency deviation for 10101010 pattern 185 - - kHz Document Number: 002-00214 Rev. *H RF-PHY Specification (TRM-LE/CA/05/C) Page 25 of 38 CYBLE-222005-00 Table 49. BLE Subsystem (continued) Parameter Description Min Typ Max Units kHz Details/ Conditions F1AVG Average frequency deviation for 11110000 pattern 225 250 275 RF-PHY Specification (TRM-LE/CA/05/C) EO Eye opening = F2AVG/F1AVG 0.8 - - FTX, ACC Frequency accuracy -150 - 150 kHz RF-PHY Specification (TRM-LE/CA/06/C) FTX, MAXDR Maximum frequency drift -50 - 50 kHz RF-PHY Specification (TRM-LE/CA/06/C) FTX, INITDR Initial frequency drift -20 - 20 kHz RF-PHY Specification (TRM-LE/CA/06/C) FTX, DR Maximum drift rate -20 - 20 kHz/ 50 s RF-PHY Specification (TRM-LE/CA/06/C) IBSE1 In-band spurious emission at 2-MHz offset - - -20 dBm RF-PHY Specification (TRM-LE/CA/03/C) IBSE2 In-band spurious emission at 3-MHz offset - - -30 dBm RF-PHY Specification (TRM-LE/CA/03/C) TXSE1 Transmitter spurious emissions (average), <1.0 GHz - - -55.5 dBm FCC-15.247 TXSE2 Transmitter spurious emissions (average), >1.0 GHz - - -41.5 dBm FCC-15.247 RF-PHY Specification (TRM-LE/CA/05/C) RF Current Specifications IRX Receive current in normal mode - 18.7 - mA IRX_RF Radio receive current in normal mode - 16.4 - mA IRX, HIGHGAIN Receive current in high-gain mode - 21.5 - mA ITX, 3dBm TX current at 3-dBm setting (PA10) - 20 - mA ITX, 0dBm TX current at 0-dBm setting (PA7) - 16.5 - mA ITX_RF, 0dBm Radio TX current at 0 dBm setting (PA7) - 15.6 - mA Measured at VDDR ITX_RF, 0dBm Radio TX current at 0 dBm excluding Balun loss - 14.2 - mA Guaranteed by design simulation ITX,-3dBm TX current at -3-dBm setting (PA4) - 15.5 - mA ITX,-6dBm TX current at -6-dBm setting (PA3) - 14.5 - mA ITX,-12dBm TX current at -12-dBm setting (PA2) - 13.2 - mA ITX,-18dBm TX current at -18-dBm setting (PA1) - 12.5 - mA Iavg_1sec, 0dBm Average current at 1-second BLE connection interval - 17.1 - A TXP: 0 dBm; 20-ppm master and slave clock accuracy. For empty PDU exchange Iavg_4sec, 0dBm Average current at 4-second BLE connection interval - 6.1 - A TXP: 0 dBm; 20-ppm master and slave clock accuracy. For empty PDU exchange 2400 - 2482 MHz Measured at VDDR General RF Specifications FREQ RF operating frequency Document Number: 002-00214 Rev. *H Page 26 of 38 CYBLE-222005-00 Table 49. BLE Subsystem (continued) Parameter Description Min Typ Max Units CHBW Channel spacing - 2 - MHz DR On-air data rate - 1000 - kbps IDLE2TX BLE.IDLE to BLE. TX transition time - 120 140 s IDLE2RX BLE.IDLE to BLE. RX transition time - 75 120 s RSSI, ACC RSSI accuracy - 5 - dB RSSI, RES RSSI resolution - 1 - dB RSSI, PER RSSI sample period - 6 - s Details/ Conditions RSSI Specifications Document Number: 002-00214 Rev. *H Page 27 of 38 CYBLE-222005-00 Environmental Specifications Environmental Compliance This Cypress BLE module is built in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen Free (HF) directives. The Cypress module and components used to produce this module are RoHS and HF compliant. RF Certification The CYBLE-222005-00 module is certified under the following RF certification standards: FCC: WAP2005 CE IC: 7922A-2005 MIC: 203-JN0495 KC: MSIP-CRM-Cyp-2005 Safety Certification The CYBLE-222005-00 module complies with the following regulations: Underwriters Laboratories, Inc. (UL) - Filing E331901 CSA TUV Environmental Conditions Table 50 describes the operating and storage conditions for the Cypress BLE module. Table 50. Environmental Conditions for CYBLE-222005-00 Description Operating temperature Operating humidity (relative, non-condensation) Thermal ramp rate Storage temperature Minimum Specification Maximum Specification -40 C 85 C 5% 85% - 3 C/minute -40 C 85 C Storage temperature and humidity - 85 C at 85% ESD: Module integrated into system Components[12] - 15-kV Air 2.2-kV Contact ESD and EMI Protection Exposed components require special attention to ESD and electromagnetic interference (EMI). A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability. Note 12. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM. Document Number: 002-00214 Rev. *H Page 28 of 38 CYBLE-222005-00 Regulatory Information FCC FCC NOTICE: The device CYBLE-222005-00, including the antenna 2450AT18B100 from Johanson Technology, complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter approval as detailed in FCC public Notice DA00-1407.transmitter Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. CAUTION: The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by Cypress Semiconductor may void the user's authority to operate the equipment. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions,e may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help LABELING REQUIREMENTS: The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well as the FCC Notice above. The FCC identifier is FCC ID: WAP2005. In any case the end product must be labeled exterior with "Contains FCC ID: WAP2005" ANTENNA WARNING: This device is tested with a standard SMA connector and with the antennas listed below. When integrated in the OEMs product, these fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna not in the following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions. RF EXPOSURE: To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved antenna in the previous. The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antennas in Table 6 on page 12, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal instructions about the integrated radio module is not allowed. The radiated output power of CYBLE-222005-00 with the chip antenna mounted (FCC ID: WAP2005) is far below the FCC radio frequency exposure limits. Nevertheless, use CYBLE-222005-00 in such a manner that minimizes the potential for human contact during normal operation. End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions for satisfying RF exposure compliance. Document Number: 002-00214 Rev. *H Page 29 of 38 CYBLE-222005-00 ISED Innovation, Science and Economic Development Canada (ISED) Certification CYBLE-222005-00 is licensed to meet the regulatory requirements of Innovation, Science and Economic Development Canada (ISED). License: IC: 7922A-2005 Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from www.ic.gc.ca. This device has been designed to operate with the antennas listed in Table 6 on page 12, having a maximum gain of 0.5 dBi. Antennas not included in this list or having a gain greater than 0.5 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. ISED NOTICE: The device CYBLE-222005-00 including the antenna 2450AT18B100 from Johanson technology, complies with Canada RSS-GEN Rules. The device meets the requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. ISED RADIATION EXPOSURE STATEMENT FOR CANADA This device complies with Innovation, Science and Economic Development (ISED) Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Cet appareil est conforme a la norme sur l'innovation, la science et le developpement economique (ISED) norme RSS exempte de licence. L'exploitation est autorisee aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioelectrique subi, meme si le brouillage est susceptible d'en compromettre le fonctionnement. LABELING REQUIREMENTS: The Original Equipment Manufacturer (OEM) must ensure that ISED labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the ISED Notice above. The IC identifier is 7922A-2005. In any case, the end product must be labeled in its exterior with "Contains IC: 7922A-2005". European R&TTE Declaration of Conformity Hereby, Cypress Semiconductor declares that the Bluetooth module CYBLE-222005-00 complies with the essential requirements and other relevant provisions of Directive 1999/5/EC. As a result of the conformity assessment procedure described in Annex III of the Directive 1999/5/EC, the end-customer equipment should be labeled as follows: All versions of the CYBLE-222005-00 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway. Document Number: 002-00214 Rev. *H Page 30 of 38 CYBLE-222005-00 MIC Japan CYBLE-222005-00 is certified as a module with type certification number 203-JN0495. End products that integrate CYBLE-222005-00 do not need additional MIC Japan certification for the end product. End product can display the certification label of the embedded module. KC Korea CYBLE-222005-00 is certified for use in Korea with certificate number MSIP-CRM-Cyp-2005. Document Number: 002-00214 Rev. *H Page 31 of 38 CYBLE-222005-00 Packaging Table 51. Solder Reflow Peak Temperature Module Part Number Package Maximum Peak Temperature Maximum Time at Peak Temperature No. of Cycles CYBLE-222005-00 22-pad SMT 260 C 30 seconds 2 Table 52. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Module Part Number Package MSL CYBLE-222005-00 22-pad SMT MSL 3 The CYBLE-222005-00 is offered in tape and reel packaging. Figure 10 details the tape dimensions used for the CYBLE-222005-00. Figure 10. CYBLE-222005-00 Tape Dimensions Figure 11 details the orientation of the CYBLE-222005-00 in the tape as well as the direction for unreeling. Figure 11. Component Orientation in Tape and Unreeling Direction Document Number: 002-00214 Rev. *H Page 32 of 38 CYBLE-222005-00 Figure 12 details reel dimensions used for the CYBLE-222005-00. Figure 12. Reel Dimensions The CYBLE-222005-00 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The center-of-mass for the CYBLE-222005-00 is detailed in Figure 13. Figure 13. CYBLE-222005-00 Center of Mass Document Number: 002-00214 Rev. *H Page 33 of 38 CYBLE-222005-00 Ordering Information Table 53 lists the CYBLE-222005-00 part number and features. Table 54 lists the reel shipment quantities for the CYBLE-222005-00. Table 53. Ordering Information Part Number CPU Speed (MHz) Flash Size (KB) CapSense SCB TCPWM 12-Bit SAR ADC I2S LCD Drive Package Packing 48 256 Yes 2 4 1 Msps Yes Yes 22-SMT Tape and Reel CYBLE-222005-00 Table 54. Tape and Reel Package Quantity and Minimum Order Amount Description Minimum Reel Quantity Maximum Reel Quantity Reel Quantity 500 500 Minimum Order Quantity (MOQ) 500 - Order Increment (OI) 500 - Comments Ships in 500 unit reel quantities. The CYBLE-222005-00 is offered in tape and reel packaging. The CYBLE-222005-00 ships with a maximum of 500 units/reel. Part Numbering Convention The part numbers are of the form CYBLE-FATT##-SB where the fields are defined as follows. CY BLE - F A T T ## - S B Bluetooth Version: Integration Type: Device Identification Number: Temperature Range: EZ-BLE Module Type: Antenna Type: Flash Size: Marketing Code: Company ID: 0 = BT 4.1, 1 = BT 4.2, 2 = BT 5.0 0 = Full Integration With Shield, 1 = No Shield Unique sequential product number for each module 0 = Industrial, 1 = Extended Industrial 2/4 = PSoC4, 3 = WICED, 4 = PSoC6 0 = No Antenna, 1 = PCB Antenna, 2 = Chip Antenna 0 = 128KB, 2 = 256KB BLE = BLE Product Family CY = Cypress For additional information and a complete list of Cypress Semiconductor BLE products, contact your local Cypress sales representative. To locate the nearest Cypress office, visit our website. U.S. Cypress Headquarters Address U.S. Cypress Headquarter Contact Info Cypress website address Document Number: 002-00214 Rev. *H 198 Champion Court, San Jose, CA 95134 (408) 943-2600 http://www.cypress.com Page 34 of 38 CYBLE-222005-00 Acronyms Acronym Description BLE Bluetooth Low Energy Bluetooth SIG Bluetooth Special Interest Group CE European Conformity CSA Canadian Standards Association EMI electromagnetic interference ESD electrostatic discharge FCC Federal Communications Commission GPIO general-purpose input/output IC Industry Canada IDE integrated design environment KC Korea Certification MIC Ministry of Internal Affairs and Communications (Japan) PCB printed circuit board RX receive QDID qualification design ID SMT surface-mount technology; a method for producing electronic circuitry in which the components are placed directly onto the surface of PCBs TCPWM timer, counter, pulse width modulator (PWM) TUV Germany: Technischer Uberwachungs-Verein (Technical Inspection Association) TX transmit Document Conventions Units of Measure Symbol Unit of Measure C degree Celsius kV kilovolt mA milliamperes mm millimeters mV millivolt A microamperes m micrometers MHz megahertz GHz gigahertz V volt Document Number: 002-00214 Rev. *H Page 35 of 38 CYBLE-222005-00 Document History Page Document Title: CYBLE-222005-00 EZ-BLETM Creator Module Document Number: 002-00214 Revision ECN Orig. of Change Submission Date ** 4953407 DSO 10/08/2015 Preliminary datasheet for CYBLE-222005-00 module. *A 5060713 DSO 01/07/2016 Updated General Description to add reference and link to PSoC BLE silicon datasheet and include Declaration ID number. Added More Information section to the datasheet. Updated Figure 1, Figure 2, Figure 3, and Figure 4 to improve clarity and viewing. Added Figure 5 in Recommended Host PCB Layout section to show solder pad location from module origin. Updated Table 3 and Figure 6 in Recommended Host PCB Layout section to provide the location to the center of each solder pad from the origin (in mm and mils). Added BLE Subsystem section. Added French translation for IC Radiation Exposure Statement For Canada in ISED section on page 30 in accordance with IC requirements. Updated MIC Japan section on page 31 to specify final MIC certification number. Updated KC Korea section on page 31 to specify final KC certification number. Added Table 51 and Table 52 on page 32. *B 5146846 DSO 02/22/2016 Changed status from "Preliminary" to "Final". Update More Information section to add KBA210574 (Certification Test Reports) to reference list. Update General Description to include reference and link for QDID. Updated orientation of module drawings in Figure 1 through Figure 9 and Figure 13 to match orientation in PSoC Creator. Updated Table 4 to add additional information with respect to the functional capabilities for each solder pad. *C 5421877 DSO 09/01/2016 Updated More Information: Added additional Knowledge Base Article references. Updated Electrical Specification: Updated System Resources: Updated Internal Low-Speed Oscillator: Updated Table 48 (Updated details in "Value" column corresponding to ECOTRIM parameter). Updated Ordering Information: No change in part numbers. Added Table 54 (To specify minimum and maximum reel quantities that ship for orders of the CYBLE-222005-00 module). Updated to new template. Completing Sunset Review. *D 5528433 DSO 11/23/2016 Updated More Information: Added EZ-SerialTM BLE Firmware Platform section. Updated Recommended Host PCB Layout: Updated Figure 4, Figure 5, and Figure 6 captions to specify that these as "Seen on Host PCB". Updated Power Supply Connections and Recommended External Components: Updated Figure 7 and Figure 8 to specify that these are "Seen from Bottom". Updated Digital and Analog Capabilities and Connections: Updated Table 4: Updated TCPWM column to add TCPWM capability on Port 2 pins. Added Footnote 3. Updated Document History Page: Remove "," from Document Title. Document Number: 002-00214 Rev. *H Description of Change Page 36 of 38 CYBLE-222005-00 Document History Page Document Title: CYBLE-222005-00 EZ-BLETM Creator Module Document Number: 002-00214 *E 5553544 DSO 12/14/2016 Updated Electrical Specification: Updated SAR ADC: Updated Table 17 to add Note 10 to specify under what conditions the maximum number of ADC channels can be achieved. *F 5709580 GNKK 04/24/2017 Updated the Cypress logo and copyright information. *G 6002363 DSO 12/22/2017 Updated reel dimensions in Figure 10 and Figure 12. *H 6087229 DSO 03/12/2018 Updated document title as "EZ-BLETM Creator Module". Updated "PRoCTM" references to "Creator". Updated the links of QDID and Declaration ID in Module Description section as "https://launchstudio.bluetooth.com/ListingDetails/474" Updated "PRoC BLE" to "PSoC 4 BLE" throughout the document. Updated More Information section. Updated the term "IC" to "ISED". Changed the Heading "Industry Canada (IC) Certification" to "ISED" and added a subtitle "Innovation, Science and Economic Development Canada (ISED) Certification". Updated Part Numbering Convention. Added "Cet appareil est conforme a la norme sur l'innovation, la science et le developpement economique (ISED) norme RSS exempte de licence. L'exploitation est autorisee aux deux conditions suivantes:" in ISED RADIATION EXPOSURE STATEMENT FOR CANADA. Updated the Copyright year. Document Number: 002-00214 Rev. *H Page 37 of 38 CYBLE-222005-00 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC(R) Solutions Products Arm(R) Cortex(R) Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface cypress.com/clocks cypress.com/interface Internet of Things Memory cypress.com/iot cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs Cypress Developer Community Community | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU cypress.com/usb cypress.com/wireless (c) Cypress Semiconductor Corporation, 2015-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach, such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-00214 Rev. *H Revised March 12, 2018 Page 38 of 38