HIP2100EIBT - Intersil - Product.Network

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

HIP2100

100V/2A Peak, Low Cost, High Frequency

Half Bridge Driver

The HIP2100 is a high frequency, 100V Half Bridge

N-Channel power MOSFET driver IC. The low-side and

high-side gate drivers are independently controlled and

matched to 8ns. This gives the user maximum flexibility in

dead-time selection and driver protocol. Undervoltage

protection on both the low-side and high-side supplies force

the outputs low. An on-chip diode eliminates the discrete

diode required with other driver ICs. A new level-shifter

topology yields the low-power benefits of pulsed operation

with the safety of DC operation. Unlike some competitors,

the high-side output returns to its correct state after a

momentary undervoltage of the high-side supply.

Features

• Drives N-Channel MOSFET Half Bridge

• SOIC, EPSOIC, QFN and DFN Package Options

• SOIC, EPSOIC and DFN Packages Compliant with 100V

Conductor Spacing Guidelines of IPC-2221

• Pb-Free Product Available (RoHS Compliant)

• Bootstrap Supply Max Voltage to 114VDC

• On-Chip 1Ω Bootstrap Diode

• Fast Propagation Times for Multi-MHz Circuits

• Drives 1000pF Load with Rise and Fall Times Typ. 10ns

• CMOS Input Thresholds for Improved Noise Immunity

• Independent Inputs for Non-Half Bridge Topologies

• No Start-Up Problems

• Outputs Unaffected by Supply Glitches, HS Ringing Below

Ground, or HS Slewing at High dv/dt

• Low Power Consumption

• Wide Supply Range

• Supply Undervoltage Protection

•3Ω Driver Output Resistance

• QFN/DFN Package:

- Compliant to JEDEC PUB95 MO-220

QFN - Quad Flat No Leads - Package Outline

- Near Chip Scale Package Footprint, which Improves

PCB Efficiency and has a Thinner Profile

Applications

• Telecom Half Bridge Power Supplies

• Avionics DC/DC Converters

• Two-Switch Forward Converters

• Active Clamp Forward Converters

Ordering Information

PART

NUMBER

(Note 1)

PART

MARKING

TEMP.

RANGE

(°C) PACKAGE

PKG.

DWG. #

HIP2100IB 2100 IB -40 to +125 8 Ld SOIC M8.15

HIP2100IBZ

(Note 2)

2100 IBZ -40 to +125 8 Ld SOIC

(Pb-free)

M8.15

HIP2100EIBZ

(Note 2)

2100 EIBZ -40 to +125 8 Ld EPSOIC

(Pb-free)

M8.15C

HIP2100IRZ

(Note 2)

HIP 2100IRZ -40 to +125 16 Ld 5x5 QFN

(Pb-free)

L16.5x5

HIP2100IR4Z

(Note 2)

21 00IR4Z -40 to +125 12 Ld 4x4 DFN

(Pb-free)

L12.4x4A

NOTES:

1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on

reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-

free material sets, molding compounds/die attach materials, and

100% matte tin plate plus anneal (e3 termination finish, which is

RoHS compliant and compatible with both SnPb and Pb-free

soldering operations). Intersil Pb-free products are MSL classified

at Pb-free peak reflow temperatures that meet or exceed the Pb-

free requirements of IPC/JEDEC J STD-020.

Data Sheet April 2, 2010 FN4022.14

2FN4022.14

Application Block Diagram

Pinouts

HIP2100

(8 LD SOIC, EPSOIC)

TOP VIEW

NOTE: EPAD = Exposed PAD.

HIP2100IR4

(12 LD DFN)

TOP VIEW

HIP2100

(16 LD QFN)

TOP VIEW

VDD

VSS

EPAD

VDD

VSS

67HI

EPAD

VDD

16 14 13

6578

VSS

EPAD

SECONDARY

CIRCUIT

+100V

CONTROL

CONTROLLER

PWM

HI HO

VDD

+12V

VSS

HIP2100

REFERENCE

AND

ISOLATION

DRIVE

HIP2100

3FN4022.14

Functional Block Diagram

UNDER

VOLTAGE

VDD

VSS

DRIVER

LEVEL SHIFT

UNDER

VOLTAGE

EPAD (EPSOIC, QFN and DFN PACKAGES ONLY)

*EPAD = Exposed Pad. The EPAD is electrically isolated from all other pins. For best

thermal performance connect the EPAD to the PCB power ground plane.

SECONDARY

HIP2100

ISOLATION

PWM

+48V

+12V

CIRCUIT

FIGURE 1. TWO-SWITCH FORWARD CONVERTER

SECONDARY

CIRCUIT

HIP2100

ISOLATION

PWM

+48V

+12V

FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE CLAMP

HIP2100

4FN4022.14

Absolute Maximum Ratings Thermal Information

Supply Voltage, VDD, VHB-VHS (Notes 3, 4) . . . . . . . . -0.3V to 18V

LI and HI Voltages (Note 4) . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V

Voltage on LO (Note 4) . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V

Voltage on HO (Note 4) . . . . . . . . . . . . . . . VHS -0.3V to VHB +0.3V

Voltage on HS (Continuous) (Note 4) . . . . . . . . . . . . . . -1V to 110V

Voltage on HB (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +118V

Average Current in VDD to HB diode . . . . . . . . . . . . . . . . . . . 100mA

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 (1kV)

Maximum Recommended Operating Conditions

Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . +9V to 14.0VDC

Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V

Voltage on HS. . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V

Voltage on HB . . . VHS +8V to VHS +14.0V and VDD -1V to VDD +100V

HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns

Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)

SOIC (Note 5) . . . . . . . . . . . . . . . . . . . 95 50

EPSOIC (Note 6) . . . . . . . . . . . . . . . . . 40 3.0

QFN (Note 6) . . . . . . . . . . . . . . . . . . . . 37 6.5

DFN (Note 6) . . . . . . . . . . . . . . . . . . . . 40 3.0

Max Power Dissipation at +25°C in Free Air (SOIC, Note 5) . . . . 1.3W

Max Power Dissipation at +25°C in Free Air (EPSOIC, Note 6) . . 3.1W

Max Power Dissipation at +25°C in Free Air (QFN, Note 6) . . . . . 3.3W

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

Junction Temperature Range. . . . . . . . . . . . . . . . . .-55°C to +150°C

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

3. The HIP2100 is capable of derated operation at supply voltages exceeding 14V. Figure 16 shows the high-side voltage derating curve for this

mode of operation.

4. All voltages referenced to VSS unless otherwise specified.

5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θJC, the

“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.

Electrical Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified.

PARAMETERS SYMBOL TEST CONDITIONS

TJ = +25°C TJ = -40°C TO +125°C

UNITSMIN TYP MAX

MIN

(Note 7)

MAX

(Note 7)

SUPPLY CURRENTS

VDD Quiescent Current IDD LI = HI = 0V - 0.1 0.15 - 0.2 mA

VDD Operating Current IDDO f = 500kHz - 1.5 2.5 - 3 mA

Total HB Quiescent Current IHB LI = HI = 0V - 0.1 0.15 - 0.2 mA

Total HB Operating Current IHBO f = 500kHz - 1.5 2.5 - 3 mA

HB to VSS Current, Quiescent IHBS VHS = VHB = 114V - 0.05 1 - 10 µA

HB to VSS Current, Operating IHBSO f = 500kHz - 0.7 - - - mA

INPUT PINS

Low Level Input Voltage Threshold VIL 45.4 - 3 - V

High Level Input Voltage Threshold VIH -5.87 - 8 V

Input Voltage Hysteresis VIHYS -0.4 - - - V

Input Pulldown Resistance RI- 200 - 100 500 kΩ

UNDERVOLTAGE PROTECTION

VDD Rising Threshold VDDR 7 7.3 7.8 6.5 8 V

VDD Threshold Hysteresis VDDH -0.5 - - - V

HB Rising Threshold VHBR 6.5 6.9 7.5 6 8 V

HB Threshold Hysteresis VHBH -0.4 - - - V

HIP2100

5FN4022.14

BOOT STRAP DIODE

Low-Current Forward Voltage VDL IVDD-HB = 100µA - 0.45 0.55 - 0.7 V

High-Current Forward Voltage VDH IVDD-HB = 100mA - 0.7 0.8 - 1 V

Dynamic Resistance RDIVDD-HB = 100mA - 0.8 1 - 1.5 Ω

LO GATE DRIVER

Low Level Output Voltage VOLL ILO = 100mA - 0.25 0.3 - 0.4 V

High Level Output Voltage VOHL ILO = -100mA, VOHL = VDD-VLO - 0.25 0.3 - 0.4 V

Peak Pullup Current IOHL VLO = 0V - 2 - - - A

Peak Pulldown Current IOLL VLO = 12V - 2 - - - A

HO GATE DRIVER

Low Level Output Voltage VOLH IHO = 100mA - 0.25 0.3 - 0.4 V

High Level Output Voltage VOHH IHO = -100mA, VOHH = VHB-VHO - 0.25 0.3 - 0.4 V

Peak Pullup Current IOHH VHO = 0V - 2 - - - A

Peak Pulldown Current IOLH VHO = 12V - 2 - - - A

Electrical Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified. (Continued)

PARAMETERS SYMBOL TEST CONDITIONS

TJ = +25°C TJ = -40°C TO +125°C

UNITSMIN TYP MAX

MIN

(Note 7)

MAX

(Note 7)

Switching Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified.

PARAMETERS SYMBOL

TEST

CONDITIONS

TJ = +25°C TJ = -40°C TO +125°C

UNITSMIN TYP MAX

MIN

(Note 7)

MAX

(Note 7)

Lower Turn-Off Propagation Delay (LI Falling to LO Falling) tLPHL - 20 35 - 45 ns

Upper Turn-Off Propagation Delay (HI Falling to HO Falling) tHPHL - 20 35 - 45 ns

Lower Turn-On Propagation Delay (LI Rising to LO Rising) tLPLH - 20 35 - 45 ns

Upper Turn-On Propagation Delay (HI Rising to HO Rising) tHPLH - 20 35 - 45 ns

Delay Matching: Lower Turn-On and Upper Turn-Off tMON - 2 8 - 10 ns

Delay Matching: Lower Turn-Off and Upper Turn-On tMOFF - 2 8 - 10 ns

Either Output Rise/Fall Time tRC, tFC CL = 1000pF - 10 - - - ns

Either Output Rise/Fall Time (3V to 9V) tR, tFCL = 0.1µF - 0.5 0.6 - 0.8 µs

Either Output Rise Time Driving DMOS tRD CL = IRFR120 - 20 - - - ns

Either Output Fall Time Driving DMOS tFD CL = IRFR120 - 10 - - - ns

Minimum Input Pulse Width that Changes the Output tPW - - - - 50 ns

Bootstrap Diode Turn-On or Turn-Off Time tBS -10 - - - ns

NOTE:

7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

HIP2100

6FN4022.14

Timing Diagrams

Pin Descriptions

SYMBOL DESCRIPTION

VDD Positive Supply to lower gate drivers. De-couple this pin to VSS. Bootstrap diode connected to HB.

HB High-Side Bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin.

Bootstrap diode is on-chip.

HO High-Side Output. Connect to gate of High-Side power MOSFET.

HS High-Side Source connection. Connect to source of High-Side power MOSFET. Connect negative side of bootstrap capacitor to

this pin.

HI High-Side input.

LI Low-Side input.

VSS Chip negative supply, generally will be ground.

LO Low-Side Output. Connect to gate of Low-Side power MOSFET.

EPAD Exposed Pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.

FIGURE 3. FIGURE 4.

tHPLH,

tLPLH

tHPHL,

tLPHL

HI,

HO,

tMON tMOFF

Typical Performance Curves

FIGURE 5. OPERATING CURRENT vs FREQUENCY FIGURE 6. HB TO VSS OPERATING CURRENT vs

FREQUENCY

T = +125°C

T = +25°C

T = -40°C

T = +150°C

10k 100k 1M

0.1

0.01

FREQUENCY (Hz)

IDDO, IHBO (mA)

T = -40°C

T = +125°C

T = +25°C

T = +150°C

0.1

0.01

IHBSO (mA)

10k 100k 1M

FREQUENCY (Hz)

HIP2100

7FN4022.14

FIGURE 7. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE FIGURE 8. LOW LEVEL OUTPUT VOLTAGE vs TEMPERATURE

FIGURE 9. UNDERVOLTAGE LOCKOUT THRESHOLD vs

TEMPERATURE

FIGURE 10. UNDERVOLTAGE LOCKOUT HYSTERESIS vs

TEMPERATURE

FIGURE 11. PROPAGATION DELAYS vs TEMPERATURE FIGURE 12. PEAK PULLUP CURRENT vs OUTPUT VOLTAGE

Typical Performance Curves (Continued)

TEMPERATURE (°C)

VOHL, VOHH (mV)

500

400

300

200

100

-50 0 50 100 150

VHB = VDD = 9V

VHB = VDD = 12V

VHB = VDD = 14V

TEMPERATURE (°C)

VOLL, VOLH (mV)

500

400

300

200

100

-50 0 50 100 150

VHB = VDD = 9V

VHB = VDD = 12V

VHB = VDD = 14V

TEMPERATURE (°C)

-50 0 50 100 150

7.6

7.4

7.2

7.0

6.8

6.6

VDDR

VHBR

VHBR, VDDR (V)

TEMPERATURE (°C)

-50 0 50 100 150

0.54

0.50

0.46

0.42

0.38

0.30

VDDH

VHBH

VHBH, VDDH (mV)

0.34

tHPHL

tHPLH

tLPHL

tLPLH

TEMPERATURE (°C)

-50 0 50 100 150

tLPLH, tLPHL, tHPLH, tHPHL (ns)

2.0

IHO, ILO (A)

12108420

2.5

1.5

1.0

0.5

VHO, VLO (V)

HIP2100

8FN4022.14

FIGURE 13. PEAK PULLDOWN CURRENT vs OUTPUT

VOLTAGE

FIGURE 14. BOOTSTRAP DIODE I-V CHARACTERISTICS

FIGURE 15. QUIESCENT CURRENT vs VOLTAGE FIGURE 16. VHS VOLTAGE vs VDD VOLTAGE

Typical Performance Curves (Continued)

2.0

ILO, IHO (A)

12108420

2.5

1.5

1.0

0.5

VLO, VHO (V)

0.8

1.000

0.100

0.010

0.001

1·10-4

1·10-5

1·10-6 0.70.60.50.40.3

FORWARD VOLTAGE (V)

FORWARD CURRENT (A)

VDD, VHB (V)

051015

IDD, IHB (µA)

IDD vs VDD

IHB vs VHB

120

100

014 15 1612

VHS TO VSS VOLTAGE (V)

VDD TO VSS VOLTAGE (V)

HIP2100

9FN4022.14

HIP2100

Dual Flat No-Lead Plastic Package (DFN)

Micro Lead Frame Plastic Package (MLFP)

TOP VIEW

INDEX

D1/2

D/2

E1/2 E/2

E1 E

0.15

BOTTOM VIEW

SEATING

PLANE

0.10

NX b A1

0.15

AC0.15

AREA

SIDE VIEW

0.08 C

NX b

4X P

0.10 C A

(Nd-1)Xe

REF.

7 8

AREA

INDEX

N-1

D2/2

NX k

E2/2

FOR EVEN TERMINAL/SIDE

TERMINAL TIP

L12.4x4A

12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

SYMBOL

MILLIMETERS

NOTESMIN NOMINAL MAX

A - 0.85 0.90 -

A1 0.00 0.01 0.05 -

A2 - 0.65 0.70 -

A3 0.20 REF -

b 0.18 0.23 0.30 5, 8

D 4.00 BSC -

D1 3.75 BSC -

D2 2.65 2.80 2.95 7, 8

E 4.00 BSC -

E1 3.75 BSC -

E2 1.43 1.58 1.73 7, 8

e 0.50 BSC -

k 0.635 - - -

L 0.30 0.40 0.50 8

N122

Nd 6 3

P 0.24 0.42 0.60 -

θ--12-

Rev. 0 8/03

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.

2. N is the number of terminals.

3. Nd refer to the number of terminals on D.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land Pattern

Design efforts, see Intersil Technical Brief TB389.

9. COMPLIANT TO JEDEC MO-229-VGGD-2 ISSUE C except for

the L dimension.

10 FN4022.14

HIP2100

Quad Flat No-Lead Plastic Package (QFN)

Micro Lead Frame Plastic Package (MLFP)

L16.5x5

16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

(COMPLIANT TO JEDEC MO-220VHHB ISSUE C)

SYMBOL

MILLIMETERS

NOTESMIN NOMINAL MAX

A 0.80 0.90 1.00 -

A1 - - 0.05 -

A2 - - 1.00 9

A3 0.20 REF 9

b 0.28 0.33 0.40 5, 8

D 5.00 BSC -

D1 4.75 BSC 9

D2 2.55 2.70 2.85 7, 8

E 5.00 BSC -

E1 4.75 BSC 9

E2 2.55 2.70 2.85 7, 8

e 0.80 BSC -

k0.25 - - -

L 0.35 0.60 0.75 8

L1 - - 0.15 10

N162

Nd 4 3

Ne 4 4 3

P- -0.609

θ--129

Rev. 2 10/02

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land Pattern

Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when

Anvil singulation method is used and not present for saw

singulation.

10. Depending on the method of lead termination at the edge of the

package, a maximum 0.15mm pull back (L1) maybe present. L

minus L1 to be equal to or greater than 0.3mm.

11 FN4022.14

HIP2100

Small Outline Plastic Packages (SOIC)

INDEX

AREA

123

-B-

0.25(0.010) C AMBS

-A-

-C-

SEATING PLANE

0.10(0.004)

h x 45°

H0.25(0.010) BM M

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9

C 0.0075 0.0098 0.19 0.25 -

D 0.1890 0.1968 4.80 5.00 3

E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5

L 0.016 0.050 0.40 1.27 6

N8 87

α0° 8° 0° 8° -

Rev. 1 6/05

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN4022.14

HIP2100

Small Outline Exposed Pad Plastic Packages (EPSOIC)

INDEX

AREA

123

-B-

0.25(0.010) C AMBS

-A-

-C-

SEATING PLANE

0.10(0.004)

h x 45°

H0.25(0.010) BM M

123

BOTTOM VIEW

TOP VIEW

SIDE VIEW

M8.15C

8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD

PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.056 0.066 1.43 1.68 -

A1 0.001 0.005 0.03 0.13 -

B 0.0138 0.0192 0.35 0.49 9

C 0.0075 0.0098 0.19 0.25 -

D 0.189 0.196 4.80 4.98 3

E 0.150 0.157 3.811 3.99 4

e 0.050 BSC 1.27 BSC -

H 0.230 0.244 5.84 6.20 -

h 0.010 0.016 0.25 0.41 5

L 0.016 0.035 0.41 0.89 6

N8 87

α0° 8° 0° 8° -

P - 0.126 - 3.200 11

P1 - 0.099 - 2.514 11

Rev. 1 6/05

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions.

Interlead flash and protrusions shall not exceed 0.25mm (0.010

inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch

dimensions are not necessarily exact.

11. Dimensions “P” and “P1” are thermal and/or electrical enhanced

variations. Values shown are maximum size of exposed pad

within lead count and body size.