IRF1324S-7PPbF
G D S
Gate Drain Source
Base Part Number Package Type Standard Pack Orderable Part Number
Form Quantity
IRF1324S-7PPbF Tube 50 IRF1324S-7PPbF
Tape and Reel Left 800 IRF1324STRL-7PP
D2Pak 7 Pin
VDSS 24V
RDS(on) typ. 0.8m
max. 1.0m
ID (Silicon Limited) 429A
ID (Package Limited) 240A
Applications
High Efficiency Synchronous Rectification in SMPS
Uninterruptible Power Supply
High Speed Power Switching
Hard Switched and High Frequency Circuits
Benefits
Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
Fully Characterized Capacitance and Avalanche SOA
Enhanced body diode dV/dt and dI/dt Capability
Lead-Free
1 2015-10-15
HEXFET® is a registered trademark of Infineon.
*Qualification standards can be found at www.infineon.com
Absolute Maximum Ratings
Symbol Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited) 429
A
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited) 303
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package Limited) 240
IDM Pulsed Drain Current 1640
PD @TC = 25°C Maximum Power Dissipation 300 W
Linear Derating Factor 2.0 W/°C
VGS Gate-to-Source Voltage ± 20 V
dv/dt Peak Diode Recovery 1.6 V/ns
TJ Operating Junction and -55 to + 175
TSTG Storage Temperature Range °C
Soldering Temperature, for 10 seconds (1.6mm from case) 300
Thermal Resistance
Symbol Parameter Typ. Max. Units
RJC Junction-to-Case ––– 0.50
°C/W
RJA Junction-to-Ambient ––– 40
D2Pak 7 Pin
Avalanche Characteristics
EAS Single Pulse Avalanche Energy (Thermally Limited) 230
mJ
IAR Avalanche Current See Fig.14,15, 18a, 18b A
EAR Repetitive Avalanche Energy mJ
HEXFET® Power MOSFET
IRF1324S-7PPbF
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Notes:
Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 240A. Note that
current limitations arising from heating of the device leads may occur with some lead mounting arrangements. (Refer to AN-1140)
Repetitive rating; pulse width limited by max. junction temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.018mH, RG = 25, IAS = 160A, VGS =10V. Part not recommended for use above
this value.
I
SD 160A, di/dt 600A/µs, VDD V(BR)DSS, TJ 175°C.
Pulse width 400µs; duty cycle 2%.
C
oss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.
C
oss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to
application note #AN-994
R
is measured at TJ approximately 90°C.
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 24 ––– ––– V VGS = 0V, ID = 250µA
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient ––– 0.023 ––– V/°C Reference to 25°C, ID = 5mA
RDS(on) Static Drain-to-Source On-Resistance ––– 0.80 1.0 m VGS = 10V, ID = 160A
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA VDS =24V, VGS = 0V
––– ––– 250 VDS =19V,VGS = 0V,TJ =125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 200 nA VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -200 VGS = -20V
RG Gate Resistance ––– 3.0 –––
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
gfs Forward Trans conductance 190 ––– ––– S VDS = 15V, ID = 160A
Qg Total Gate Charge ––– 180 252 ID = 75A
Qgs Gate-to-Source Charge ––– 47 ––– VDS = 12V
Qgd Gate-to-Drain Charge ––– 58 ––– nCVGS = 10V
Qsync Total Gate Charge Sync. (Qg - Qgd) ––– 122 –––
td(on) Turn-On Delay Time ––– 19 –––
ns
VDD = 16V
tr Rise Time ––– 240 ––– ID = 160A
td(off) Turn-Off Delay Time ––– 86 ––– RG= 2.7
tf Fall Time ––– 93 ––– VGS = 10V
Ciss Input Capacitance ––– 7700 –––
pF
VGS = 0V
Coss Output Capacitance ––– 3380 ––– VDS = 19V
Crss Reverse Transfer Capacitance ––– 1930 ––– ƒ = 1.0MHz, See Fig. 5
Coss eff.(ER) Effective Output Capacitance (Energy Related) ––– 4780 ––– VGS = 0V, VDS = 0V to 19V
Coss eff.(TR) Effective Output Capacitance (Time Related) ––– 4970 ––– VGS = 0V, VDS = 0V to 19V
Diode Characteristics
Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 429
A
MOSFET symbol
(Body Diode) showing the
ISM Pulsed Source Current ––– ––– 1640 integral reverse
(Body Diode) p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C,IS = 160A,VGS = 0V
trr Reverse Recovery Time ––– 71 107 ns TJ = 25°C VDD = 20V
––– 74 110 TJ = 125°C IF = 160A,
Qrr Reverse Recovery Charge ––– 83 120
nC TJ = 25°C di/dt = 100A/µs
––– 92 140 TJ = 125°C
IRRM Reverse Recovery Current ––– 2.0 ––– A TJ = 25°C
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
IRF1324S-7PPbF
3 2015-10-15
Fig. 2 Typical Output Characteristics
Fig. 3 Typical Transfer Characteristics Fig. 4 Normalized On-Resistance vs. Temperature
Fig. 1 Typical Output Characteristics
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
0.1 110 100
VDS , Drain-to-Source Voltage (V)
10
100
1000
ID, Drain-to-Source Current (A)
VGS
TOP 15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
BOTTOM 4.5V
60µs PULSE WIDTH
Tj = 25°C
4.5V
0.1 110 100
VDS , Drain-to-Source Voltage (V)
10
100
1000
ID, Drain-to-Source Current (A)
4.5V
60µs PULSE WIDTH
Tj = 175°C
VGS
TO P 15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
BOTTOM 4.5V
2 3 4 5 6 7 8 9
VGS, Gate-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
TJ = 25°C
TJ = 175°C
VDS = 15V
60µs PULSE WIDTH
-60 -40 -20 020 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
0.6
0.8
1.0
1.2
1.4
1.6
1.8
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 160A
VGS
= 10V
110 100
VDS, Drain-to-Source Voltage (V)
1000
10000
100000
C, Capacitance (pF)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0 50 100 150 200
QG, Total Gate Charge (nC)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
VGS, Gate-to-Source Voltage (V)
VDS= 19V
VDS= 12V
ID= 75A
IRF1324S-7PPbF
4 2015-10-15
Fig 8. Maximum Safe Operating Area
Fig 10. Drain-to-Source Breakdown Voltage
Fig 11. Typical COSS Stored Energy Fig 12. Maximum Avalanche Energy vs. Drain Current
0.0 0.5 1.0 1.5 2.0 2.5
VSD, Source-to-Drain Voltage (V)
1.0
10
100
1000
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
0110100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
OPERATION IN THIS AREA
LIMITED BY RDS(on)
Tc = 25°C
Tj = 175°C
Single Pulse
100µsec
1msec
10msec
DC
25 50 75 100 125 150 175
TC , Case Temperature (°C)
0
50
100
150
200
250
300
350
400
450
ID, Drain Current (A)
Limited By Package
Fig. 7 Typical Source-to-Drain Diode
Forward Voltage
-60 -40 -20 020 40 60 80 100 120 140 160 180
TJ , Temperature ( °C )
24
25
26
27
28
29
30
31
32
V(BR)DSS, Drain-to-Source Breakdown Voltage (V)
Id = 5mA
-5 0 5 10 15 20 25
VDS, Drain-to-Source Voltage (V)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
Energy (µJ)
Fig 9. Maximum Drain Current vs. Case Temperature
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
100
200
300
400
500
600
700
800
900
1000
EAS , Single Pulse Avalanche Energy (mJ)
ID
TOP 45A
80A
BOTTOM 160A
IRF1324S-7PPbF
5 2015-10-15
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 14. Avalanche Current vs. Pulse width
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
Thermal Response ( Z thJC ) °C/W
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Ri (°C/W) I (sec)
0.02070 0.000010
0.08624 0.000070
0.24491 0.001406
0.15005 0.009080
J
J
1
1
2
2
3
3
R
1
R
1
R
2
R
2
R
3
R
3
Ci= iRi
Ci= iRi
C
C
4
4
R
4
R
4
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
1
10
100
1000
Avalanche Current (A)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming j = 25°C and
Tstart = 150°C.
0.01
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 150°C and
Tstart =25°C (Single Pulse)
IRF1324S-7PPbF
6 2015-10-15
Fig 15. Maximum Avalanche Energy vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.infineon.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as Tjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 18a, 18b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 13, 14).
t
av = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
Z
thJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC
Iav = 2T/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
50
100
150
200
250
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 160A
Fig 16. Threshold Voltage vs. Temperature
-75 -50 -25 025 50 75 100 125 150 175 200
TJ , Temperature ( °C )
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VGS(th), Gate threshold Voltage (V)
ID = 250µA
ID = 1.0mA
ID = 1.0A
IRF1324S-7PPbF
7 2015-10-15
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
Fig 18a. Unclamped Inductive Test Circuit Fig 18b. Unclamped Inductive Waveforms
Fig 19a. Switching Time Test Circuit
Fig 20a. Gate Charge Test Circuit Fig 20b. Gate Charge Waveform
R
G
I
AS
0.01
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
tp
V
(BR)DSS
I
AS
Fig 19b. Switching Time Waveforms
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
IRF1324S-7PPbF
8 2015-10-15
D2Pak - 7 Pin Package Outline (Dimensions are shown in millimeters (inches))
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
IRF1324S-7PPbF
9 2015-10-15
D2Pak - 7 Pin Part Marking Information
ASSEMBLY
LOT CODE
INTERNATIONAL
RECTIFIER LOGO
DATE CODE
Y = YEAR
W = WEEK
P = LEADFREE
89
YWWP
17
PART NUMBER
F1324S-7P
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
D2Pak - 7 Pin Tape and Reel
IRF1324S-7PPbF
10 2015-10-15
† Qualification standards can be found at International Rectifier’s web site: http//www.irf.com/
†† Applicable version of JEDEC standard at the time of product release.
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2015
All Rights Reserved.
IMPORTANT NOTICE
The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any
information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and
liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third
party.
In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this
document and any applicable legal requirements, norms and standards concerning customer’s products and any use of
the product of Infineon Technologies in customer’s applications.
The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of
customer’s technical departments to evaluate the suitability of the product for the intended application and the
completeness of the product information given in this document with respect to such application.
For further information on the product, technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies office (www.infineon.com).
WARNINGS
Due to technical requirements products may contain dangerous substances. For information on the types in question
please contact your nearest Infineon Technologies office.
Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized
representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a
failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.
Qualification Information
Qualification Level Industrial††
(per JEDEC JESD47F†† guidelines)
Moisture Sensitivity Level D2-Pak 7 Pin MSL1
(perJEDECJ‐STD‐020D††)
RoHS Compliant Yes
Revision History
Date Comments
10/15/2015
Updated datasheet with corporate template
Updated typo on GFS from “VDD =50V, ID =160A, Min= 270S to “VDD = 15V,ID =160A Min =190S on page 2.
Corrected typo on Fig9 package limited from “160A” to “240A” on page 4.
4/8/2014
Added Ordering information table on page 1
Updated package outline on page 8
Updated part marking on page 9
Added Qualification table on page 10.
Updated data sheet with new IR corporate template.
