Secondary Side Synchronous Rectification Driver for High Efficiency SMPS Topologies NCP4306 The NCP4306 is high performance driver tailored to control a synchronous rectification MOSFET in switch mode power supplies. Thanks to its high performance drivers and versatility, it can be used in various topologies such as DCM or CCM flyback, quasi resonant flyback, forward and half bridge resonant LLC. The combination of externally or fixed adjustable minimum off-time and on-time blanking periods helps to fight the ringing induced by the PCB layout and other parasitic elements. A reliable and noise less operation of the SR system is insured due to the Self Synchronization feature. The NCP4306 also utilizes Kelvin connection of the driver to the MOSFET to achieve high efficiency operation at full load and utilizes a light load detection architecture to achieve high efficiency at light load. The precise turn-off threshold, extremely low turn-off delay time and high sink current capability of the driver allow the maximum synchronous rectification MOSFET conduction time and enables maximum SMPS efficiency. The high accuracy driver and 5 V gate clamp enables the use of GaN MOSFETs. www.onsemi.com 8 1 SOIC-8 NB CASE 751-07 1 Typical Applications * * * * Notebook Adapters High Power Density AC / DC Power Supplies (Cell Phone Chargers) LCD TVs All SMPS with High Efficiency Requirements (c) Semiconductor Components Industries, LLC, 2017 March, 2020 - Rev. 6 1 1 DFN8, 4x4 CASE 488AF DFN8, 2.0x2.2, 0.5P CASE 506BP MARKING DIAGRAMS 8 XXXXXXXX ALYWX * Self-Contained Control of Synchronous Rectifier in CCM, DCM and * * * * * * * * * * * * * * * TSOP-6 CASE 318G-02 8 Features QR for Flyback or LLC Applications Precise True Secondary Zero Current Detection Typically 15 ns Turn off Delay from Current Sense Input to Driver Rugged Current Sense Pin (up to 200 V) Ultrafast Turn-off Trigger Interface / Disable Input (10.5 ns) Adjustable or Fixed Minimum ON-Time Adjustable or Fixed Minimum OFF-Time with Ringing Detection Improved Robust Self Synchronization Capability 7 A / 2 A Peak Current Sink / Source Drive Capability Operating Voltage Range up to VCC = 35 V Automatic Light-load Disable Mode GaN Transistor Driving Capability Low Startup and Disable Current Consumption Maximum Operation Frequency up to 1 MHz TSOP6, SOIC8, DFN8 4x4 and DFN8 2x2.2 Packages This is a Pb-Free Device 1 XXXAYWG G 1 G 1 SOIC-8 NB XXXXXX XXXXXX ALYWG G DFN8, 4x4 TSOP-6 1 XXMG G DFN8, 2.0x2.2, 0.5P See detailed marking information on page 2 of this data sheet. XXXXX A L Y W M G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Date Code = Pb-Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. Publication Order Number: NCP4306/D NCP4306 ORDERING INFORMATION TABLE Table 1. AVAILABLE DEVICES Device Package Shipping SOIC-8 (Pb-Free) 2500 / Tape and Reel TSOP-6 (Pb-Free) 3000 / Tape and Reel DFN-8 4x4 (Pb-Free) 4000 / Tape and Reel DFN-8 2x2.2 (Pb-Free) 3000 / Tape and Reel Package Marking NCP4306AAAZZZADR2G 6AAAZZZA NCP4306AADZZZADR2G 6AADZZZA NCP4306AAHZZZADR2G 6AAHZZZA NCP4306DADZZDASNT1G 6AC NCP4306DAHZZAASNT1G 6AD NCP4306DADZZBASNT1G 6AK NCP4306AAAZZZAMNTWG 4306AAAZZZA NCP4306AADZZZAMNTWG 4306AADZZZA NCP4306AAAZZZAMN1TBG 6A NCP4306AADZZZAMN1TBG 6D For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com. C3 R1 Tr1 M1 RLLD +VBULK MIN_TON LLD RMIN_TON RMIN_TOFF VCC MIN_TOFF NCP4306 +VOUT M3 N2 LLC STAGE CONTROL DRV GND CS TRIG C2 RTN M2 N1 D1 N3 M4 C1 OK1 DRV VCC MIN_TOFF GND CS MIN_TON LLD RLLD RMIN_TON RMIN_TOFF R2 C4 TRIG NCP4306 Figure 1. Typical Application Example - LLC Converter with optional LLD and Trigger Utilization www.onsemi.com 2 NCP4306 +VOUT VBULK TR1 R1 C1 C2 C5 R3 D3 VCC FLYBACK CONTROL CIRCUITRY M2 D4 C3 DRV M1 VCC FB GND C4 CS DRV MIN_TOFF GND OK1 CS TRIG LLD D5 NCP4306 RLLD R2 RMIN_TON RMIN_TOFF MIN_TON Figure 2. Typical Application Example - DCM, CCM or QR Flyback Converter with optional LLD and disabled TRIG +VOUT VBULK C1 TR1 R1 C2 C5 D3 R3 VCC M2 D4 FLYBACK CONTROL CIRCUITRY C3 M1 DRV CS VCC CS LLD NCP4306 RMIN_TOFF GND MIN_TOFF RLLD DRV FB GND C4 D5 OK1 Figure 3. Typical Application Example - DCM, CCM or QR Flyback Converter with NCP4306 in TSOP6 (v Cxxxxxx) www.onsemi.com 3 NCP4306 +VOUT VBULK TR1 R1 C1 C2 R3 C8 R5 D3 VCC C4 C3 DRV C7 M1 GND DRV VCC GND MIN_TOFF COMP CS CS R2 R4 MIN_TON NCP4306 RMIN_TOFF R3 M2 D4 PRIMARY SIDE FLYBACK CONTROLLER RMIN_TON ZCD C5 C6 Figure 4. Typical Application Example - Primary Side Flyback Converter and NCP4306 in TSOP6 PIN FUNCTION DESCRIPTION Table 2. PIN FUNCTION DESCRIPTION TSOP6 Bxxxxxx TSOP6 Cxxxxxx TSOP6 Dxxxxxx TSOP6 Exxxxxx TSOP6 Fxxxxxx TSOP6 Gxxxxxx SOIC8, DFN8 Axxxxxx Pin Name 6 6 6 6 6 6 1 VCC - 5 5 5 - 2 MIN_TOFF Adjust the minimum off time period by connecting resistor to ground 5 - 4 - 5 - 3 MIN_TON Adjust the minimum on time period by connecting resistor to ground 4 4 - - - 4 4 LLD This input modulates the driver clamp level and / or turns the driver off during light load conditions - - - 4 4 5 5 TRIG / DIS Ultrafast turn-off input that can be used to turn off the SR MOSFET in CCM applications in order to improve efficiency. Activates disable mode if pulled-up for more than 100 s 3 3 3 3 3 3 6 CS 2 2 2 2 2 2 7 GND Ground connection for the SR MOSFET driver and VCC decoupling capacitor. Ground connection for minimum tON and tOFF adjust resistors, LLD and trigger inputs. GND pin should be wired directly to the SR MOSFET source terminal / soldering point using Kelvin connection. DFN8 exposed flag should be connected to GND. 1 1 1 1 1 1 8 DRV Driver output for the SR MOSFET www.onsemi.com 4 Description Supply voltage pin Current sense pin detects if the current flows through the SR MOSFET and / or its body diode NCP4306 Exception time generator MIN_TON EN ELAPSED DISABLE Disable detection LLD EXT_ADJ INT_ADJ CS Minimum ON time generator CS detection ELAPSED INT_ADJ EN DRIVER dV/dt CS_ON CS_OFF CS_RESET DRVOUT DRV Control logic VDD RESET MIN_TOFF EXT_ADJ INT_ADJ Minimum OFF time generator ELAPSED EN TRIG DISABLE VCC managment UVLO VCC DISABLE TRIG/DIS Disable detection 10 A VTRIG Figure 5. Internal Circuit Architecture - NCP4306 www.onsemi.com 5 GND NCP4306 ABSOLUTE MAXIMUM RATINGS Table 3. ABSOLUTE MAXIMUM RATINGS Rating Supply Voltage TRIG / DIS, MIN_TON, MIN_TOFF, LLD Input Voltage (Note 3) Symbol Value Unit VCC -0.3 to 37.0 V VTRIG / DIS, VMIN_TON, VMIN_TOFF, VLLD -0.3 to VCC V VDRV -0.3 to 17.0 V Driver Output Voltage Current Sense Input Voltage Current Sense Dynamic Input Voltage (tPW = 200 ns) MIN_TON, MIN_TOFF, LLD, TRIG Input Current VCS -4 to 200 V VCS_DYN -10 to 200 V IMIN_TON, IMIN_TOFF, ILLD, ITRIG -10 to 10 mA DRV Pin Current (tPW = 10 s) IDRV_DYN -3 to 12 A VCC Pin Current (tPW = 10 s) IVCC_DYN 3 A Junction to Air Thermal Resistance, 1 oz 1 in2 Copper Area, SOIC8 RJ-A_SOIC8 200 C / W Junction to Air Thermal Resistance, 1 oz 1 in2 Copper Area TSOP6 RJ-A_TSOP6 250 C / W Junction to Air Thermal Resistance, 1 oz 1 in2 Copper Area DFN8 4x4 RJ-A_DFN8_4x4 80 C / W Junction to Air Thermal Resistance, 1 oz 1 in2 Copper Area DFN8 2x2.2 RJ-A_DFN8_2x2.2 85 C / W Maximum Junction Temperature TJMAX 150 C Storage Temperature TSTG -60 to 150 C ESD Capability, Human Body Model (except pin CS) (Note 1) ESDHBM 2000 V ESD Capability, Human Body Model Pin CS ESDHBM 600 V ESD Capability, Machine Model (Note 1) ESDMM 200 V ESD Capability, Charged Device Model (Note 1) ESDCDM Class C1 - Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. This device series contains ESD protection and exceeds the following tests: Except pin CS: Human Body Model 2000 V per JEDEC Standard JESD22-A114E. All pins: Machine Model Method 200 V per JEDEC Standard JESD22-A115-A Charged Machine Model per JEDEC Standard JESD22-C101F 2. This device meets latchup tests defined by JEDEC Standard JESD78D. 3. If voltage higher than 22 V is connected to pin, pin input current increases. Internal ESD clamp contains 24 V Zener diode with 3 k in series. It is recommended to add serial resistance in case of higher input voltage to limit input pin current. Table 4. RECOMMENDED OPERATING CONDITION Parameter Maximum Operating Voltage Operating Junction Temperature Symbol Min Max 35 V -40 125 C VCC TJ www.onsemi.com 6 Unit NCP4306 ELECTRICAL CHARACTERISTICS Table 5. ELECTRICAL CHARACTERISTICS -40 C TJ 125 C; VCC = 12 V; CDRV = 0 nF; RMIN_TON = RMIN_TOFF = 10 k or internally set values; VLLD = 3.0 V or LLD internally disabled; VTRIG / DIS = 0 V; VCS = 4 V, unless otherwise noted. Typical values are at TJ = +25 C Test Conditions Parameter Symbol Min Typ Max Unit VCCON 3.7 4.0 4.2 V VCCOFF 3.2 3.5 3.7 SUPPLY SECTION VCC UVLO VCC rising VCC falling VCC UVLO Hysteresis Start-up Delay Current Consumption, tMIN_TON = tMIN_TOFF = 1 s, tLLD = 130 s VCC rising from 0 to VCCON + 1 V @ tr = 10 s VCCHYS 0.5 V tSTART_DEL 50 80 s ICC 1.8 2.5 mA CDRV = 0 nF, fCS = 100 kHz xAxxxxx xBxxxxx 1.7 2.4 CDRV = 1 nF, fCS = 100 kHz xAxxxxx 2.8 4.0 xBxxxxx 2.1 3.4 CDRV = 10 nF, fCS = 100 kHz xAxxxxx 12 15 xBxxxxx 6.7 9.0 Current Consumption ICC 1.4 2.2 mA Current Consumption below UVLO VCC = VCCOFF - 0.1 V ICC_UVLO 35 60 A Current Consumption in Disable Mode t > tLLD , VLLD = 0.55 V ICC_DIS 60 100 A VTRIG / DIS = 5 V; VLLD = 0.55 V 60 100 t > tLLD, LLD set internally 37 80 VTRIG / DIS = 5 V, LLD set internally 37 80 DRIVER OUTPUT Output Voltage Rise-Time CDRV = 10 nF, 10 % to 90 % VDRVMAX, VCS = 4 to -1 V tr 60 100 ns Output Voltage Fall-Time CDRV = 10 nF, 90 % to 10 % VDRVMAX, VCS = -1 to 4 V tf 25 45 ns Driver Source Resistance Driver Sink Resistance Output Peak Source Current Output Peak Sink Current Maximum Driver Pulse Length Maximum Driver Output Voltage RDRV_SOURCE 2 RDRV_SINK 0.5 IDRV_SOURCE 2 A IDRV_SINK 7 A tDRV_ON_MAX 4 ms VDRVMAX VCC = 35 V, CDRV > 1 nF, (ver. xAxxxxx) VCC = 35 V, CDRV > 1 nF, (ver. xBxxxxx) Minimum Driver Output Voltage VDRVMIN VCC = VCCOFF + 200 mV, (ver. xAxxxxxx) VCC = VCCOFF + 200 mV, (ver. xBxxxxxx) 9 10 11 4.5 5.0 5.5 3.4 3.7 3.9 3.4 3.7 3.9 V V CS INPUT Total Propagation Delay From CS to DRV Output On VCS goes down from 4 to -1 V, tf_CS <= 5 ns tPD_ON 30 60 ns Total Propagation Delay From CS to DRV Output Off VCS goes up from -1 to 4 V, tr_CS <= 5 ns tPD_OFF 13 23 ns -75 -40 mV 0 mV 0.6 V 500 nA Turn On CS Threshold Voltage Turn Off CS Threshold Voltage Guaranteed by Design Turn Off Timer Reset Threshold Voltage CS Leakage Current VCS = 200 V VTH_CS_ON -120 VTH_CS_OFF -1 VTH_CS_RESET 0.4 0.5 ICS_LEAKAGE dV / dt Detector High Threshold VCS_DVDT_H www.onsemi.com 7 3.0 V NCP4306 Table 5. ELECTRICAL CHARACTERISTICS (continued) -40 C TJ 125 C; VCC = 12 V; CDRV = 0 nF; RMIN_TON = RMIN_TOFF = 10 k or internally set values; VLLD = 3.0 V or LLD internally disabled; VTRIG / DIS = 0 V; VCS = 4 V, unless otherwise noted. Typical values are at TJ = +25 C Parameter Test Conditions Symbol Min Typ Max Unit 37 ns 10 ns CS INPUT dV / dt Detector Low Threshold dV / dt Detector Threshold VCS_DVDT_L (Note 4) ver. xxDxxxx tdV / dt 0.5 13 25 V TRIGGER DISABLE INPUT Minimum Trigger Pulse Duration VTRIG / DIS = 5 V; Shorter pulses may not be proceeded Trigger Threshold Voltage Trigger to DRV Propagation Delay tTRIG_PW_MIN VTRIG_TH VTRIG / DIS goes from 0 to 5 V, tr_TRIG / DIS <= 5 ns Trigger Blank Time After DRV Turn-on VCS drops below VTH_CS_ON Event 1.6 tPD_TRIG 2.0 2.2 V 10.0 16.5 ns tTRIG_BLANK 30 55 80 ns 75 100 125 s 1.5 3.0 s 200 ns 15 A 10 s Delay to Disable Mode VTRIG / DIS goes from 0 to 5 V tDIS_TIM Disable Recovery Timer VTRIG / DIS goes down from 5 to 0 V; tMIN_TOFF = 130 ns tDIS_REC Minimum Pulse Duration to Disable Mode End VTRIG / DIS = 0 V; Shorter pulses may not be proceeded tDIS_END Pull Down Current VTRIG / DIS = 5 V Maximum Transition Time VTRIG / DIS goes from 1 to 3 V or from 3 to 1 V ITRIG / DIS 7 11 tTRIG_TRAN MINIMUM TON AND TOFF ADJUST Minimum tON time RMIN_TON = 0 (ver. xxxZxxx) tON_MIN 55 Minimum tOFF time RMIN_TOFF = 0 (ver. xxxxZxx) tOFF_MIN 70 Minimum tON time RMIN_TON = 10 k (ver. xxxZxxx) tON_MIN 0.90 1.00 1.10 s Minimum tOFF time RMIN_TOFF = 10 k (ver. xxxxZxx) tOFF_MIN 0.90 1.00 1.10 s Minimum tON time RMIN_TON = 50 k (ver. xxxZxxx) tON_MIN 4.50 5.00 5.50 s Minimum tOFF time RMIN_TOFF = 50 k (ver. xxxxZxx) tOFF_MIN 4.40 4.90 5.40 s Internal minimum tON time tON_MIN = 130 ns, (ver. xxxAxxx) tON_MIN -20% tON_MIN +20% ns tON_MIN = 220, 310, 400 ns (ver. xxx[B-D]xxx) tON_MIN -15% tON_MIN +15% ns tON_MIN = 500, 600, 700, 800, 1000, 1200, 1400, 1700, 2000 ns (ver. xxx[E-M]xxx) tON_MIN -10% tON_MIN +10% ns tOFF_MIN = 0.9, 1.0, 1.1, 1.2, 1.4, 1.6, 1.8, 2.0, 2.2, 2.4, 2.6, 2.9, 3.2, 3.5, 3.9 s (ver. xxxx[A-O]xx) tOFF_MIN -10% tOFF_MI +10% s -19 A 0.3 V Internal minimum tOFF time ns ns N LLD ADJUST LLD Pull Up Current LLD Time Selection (ver. xxxxxZx) ILLD IC disabled VLLD -20 tLLD = 68 s 0.40 0.51 0.63 tLLD = 130 s 0.75 0.89 1.03 tLLD = 280 s 1.15 1.32 1.50 tLLD = 540 s 1.68 1.82 1.97 tLLD = 1075 s 2.20 2.50 2.70 LLD function disabled LLD Main Time -21 3.10 VLLD = 0.51 V or ver. xxxxxAx tLLD 53 68 83 VLLD = 0.89 V or ver. xxxxxBx 100 130 160 VLLD = 1.32 V or ver. xxxxxCx 220 280 340 VLLD = 1.82 V or ver. xxxxxDx 420 540 660 VLLD = 2.45 V or ver. xxxxxEx 840 1075 1310 www.onsemi.com 8 s NCP4306 Table 5. ELECTRICAL CHARACTERISTICS (continued) -40 C TJ 125 C; VCC = 12 V; CDRV = 0 nF; RMIN_TON = RMIN_TOFF = 10 k or internally set values; VLLD = 3.0 V or LLD internally disabled; VTRIG / DIS = 0 V; VCS = 4 V, unless otherwise noted. Typical values are at TJ = +25 C Parameter Test Conditions Symbol Min Typ Max Unit LLD ADJUST LLD Reduced Time Disable mode activated LLD Blanking Time Disable Recovery Time tMIN_TOFF = 130 ns tLLD_RED 0.5 x tLLD s tLLD_BLK 0.25 x tLLD s tLLD_DIS_REC 1.5 tEXC 4x tMIN_TON 3.0 s EXCEPTION TIMER Exception Time (ver. xxHxxxx) Exception Timer Ratio Accuracy RatioEXC 4. Test signal: VCS [V] 4.0 VCS_DVDT_H t dV/dt 1.5 VCS_DVDT_L t [ns] -1.0 Figure 6. Test Signal www.onsemi.com 9 -15 s +15 % NCP4306 TYPICAL CHARACTERISTICS 4,2 1,6 4,1 1,4 4,0 1,2 3,8 ICC[mA] VCC[V] 3,9 VCC on 3,7 VCC off 3,6 1,0 0,6 3,5 0,4 3,4 0,2 3,3 -40 -20 0 20 40 TJ[C] 60 80 100 0,0 120 TJ = 125 C TJ = 85 C TJ = 55 C TJ = 25 C TJ = 0 C TJ = -20 C TJ = -40 C 0,8 0 14 3,0 12 2,0 1,5 1,0 0,5 10 15 20 25 30 35 10 TJ = 125 C TJ = 105 C TJ = 85 C TJ = 55 C TJ = 25 C TJ = 0 C TJ = -20 C TJ = -40 C 20 25 30 ICC[mA] ICC[mA] 2,5 5 15 Figure 8. Current Consumption VCS = 4 V 3,5 0 10 VCC[V] Figure 7. VCCON and VCCOFF Levels 0,0 5 CDRV = 0 nF 8 CDRV = 1 nF 6 CDRV = 10 nF 4 2 0 -40 35 -20 0 20 VCC[V] 40 60 80 100 120 TJ[C] Figure 9. Current Consumption, fCS = 100 kHz, CDRV = 1 nF, Ver. xAxxxxx Figure 10. Current Consumption, fCS = 100 kHz, Ver. xAxxxxx 10 2,5 9 8 1,5 1,0 0,5 0,0 7 TJ = 125 C TJ = 105 C TJ = 85 C TJ = 55 C TJ = 25 C TJ = 0 C TJ = -20 C TJ = -40 C 0 5 10 15 20 25 30 ICC[mA] ICC[mA] 2,0 6 5 CDRV = 0 nF 4 CDRV = 1 nF 3 CDRV = 10 nF 2 1 0 -40 35 -20 0 20 40 60 80 100 VCC[V] TJ[C] Figure 12. Current Consumption, fCS = 100 kHz, CDRV = 1 nF, Ver. xBxxxx Figure 11. Current Consumption, fCS = 100 kHz, Ver. xBxxxxx www.onsemi.com 10 120 NCP4306 60 100 90 80 40 ICC_DIS[A] ICC_UVLO[A] 50 30 20 10 70 60 50 40 30 0 -40 -20 0 20 40 60 80 100 20 -40 120 -20 0 20 TJ[C] 100 120 120 90 TJ = 125 C TJ = 105 C TJ = 85 C TJ = 55 C 100 80 70 ICC_DIS[A] ICC_DIS[A] 80 Figure 14. Current Consumption in Disable Mode VCS = 4 V, t > tLLD 100 60 50 40 80 60 TJ = 25 C TJ = 0 C TJ = -20 C TJ = -40 C 40 20 30 20 -40 -20 0 20 40 TJ[C] 60 80 100 0 120 0 0,0 90 -0,1 TJ = 85 C TJ = 55 C TJ = 25 C TJ = 0 C TJ = -20 C TJ = -40 C 60 50 40 30 15 20 -0,3 ICS[mA] 70 10 15 25 30 35 -0,2 TJ = 125 C TJ = 105 C 80 5 10 Figure 16. Current Consumption in Disable Mode, VCS = 4 V, t > tLLD 100 0 5 VCC[V] Figure 15. Current Consumption in Disable Mode, VTRIG/DIS = 5 V ICC_DIS[A] 60 TJ[C] Figure 13. Current Consumption below UVLO, VCC = VCCOFF - 0.1 V 20 40 20 25 30 TJ = 125 C TJ = 105 C TJ = 85 C TJ = 55 C TJ = 25 C TJ = 0 C TJ = -20 C TJ = -40 C -0,4 -0,5 -0,6 -0,7 -0,8 -0,9 35 -1,0 -1 -0,8 -0,6 -0,4 -0,2 VCC[V] 0 0,2 0,4 VCS[V] Figure 17. Current Consumption in Disable Mode, VTRIG/DIS = 5 V Figure 18. CS Input Current www.onsemi.com 11 0,6 0,8 1 2,2 2,0 1,8 1,6 1,4 1,2 1,0 0,8 0,6 0,4 0,2 0,0 -1,0 -0,8 -40 -50 VTH_CS_ON[mV] ICC[mA] NCP4306 TJ = 125 C TJ = 105 C TJ = 85 C TJ = 55 C TJ = 25 C TJ = 0 C TJ = -20 C TJ = -40 C -60 -70 -80 -90 -100 -110 -0,6 -0,4 -0,2 0,0 VCS[V] 0,2 0,4 0,6 -120 0,8 1,0 -40 Figure 19. Supply Current vs. CS Voltage 0 20 40 TJ[C] 60 80 100 120 100 120 100 120 Figure 20. CS Turn-on Threshold 0,60 1,0 VTH_CS_RESET[V] 0,5 VTH_CS_OFF[mV] -20 0,0 -0,5 -1,0 0,55 0,50 0,45 -1,5 -2,0 -40 -20 0 20 40 60 80 100 0,40 -40 120 -20 0 20 TJ[C] tPD_ON[ns] ICS_LEAKAGE[nA] 400 300 200 100 0 20 40 80 Figure 22. CS Reset Threshold 500 -20 60 TJ[C] Figure 21. CS turn-off Threshold 0 -40 40 60 80 100 120 60 55 50 45 40 35 30 25 20 15 10 -40 TJ[C] -20 0 20 40 60 80 TJ[C] Figure 23. CS Input Leakage VCS = 200 V Figure 24. Propagation Delay from CS to DRV Output On www.onsemi.com 12 24 22 20 18 16 14 12 10 8 6 4 -40 2,2 2,0 VTRIG_TH[V] tPD_OFF[ns] NCP4306 TJ = 125 C TJ = 105 C TJ = 85 C TJ = 55 C TJ = 25 C TJ = 0 C TJ = -20 C TJ = -40 C 1,8 1,6 1,4 1,2 -20 0 20 40 60 80 100 1,0 120 0 5 10 15 TJ[C] 20 30 25 35 VCC[V] Figure 25. Propagation Delay from CS to DRV Output Off Figure 26. Trigger Pin Threshold 15 2,3 14 2,2 ITRIG/DIS[A] VTRIG_TH[V] 13 2,1 2,0 1,9 12 11 10 9 1,8 1,7 -40 8 -20 0 20 40 60 80 100 7 -40 120 -20 0 20 TJ[C] Figure 27. Trigger Pin Threshold 60 80 100 120 Figure 28. Trigger Pin Pull Down Current 120 17 115 15 110 13 11 tDIS_TIM[s] tPD_TRIG[ns] 40 TJ[C] 9 7 5 105 100 95 90 85 3 -40 -20 0 20 40 60 80 100 80 -40 120 TJ[C] -20 0 20 40 60 80 100 TJ[C] Figure 29. Propagation Delay from TRIG to DRV Output Off Figure 30. Delay to Disable Mode, VTRIG/DIS = 5 V www.onsemi.com 13 120 1,10 1,08 1,06 1,04 1,02 1,00 0,98 0,96 0,94 0,92 0,90 -40 tMIN_TON[s] tMIN_TON[s] NCP4306 -20 0 20 40 60 80 100 120 5,5 5,4 5,3 5,2 5,1 5,0 4,9 4,8 4,7 4,6 4,5 -40 -20 0 20 TJ[C] 0 20 40 60 80 100 120 tMIN_TOFF[s] 5,4 5,3 5,2 5,1 5,0 4,9 4,8 4,7 4,6 4,5 4,4 -40 -20 0 20 TJ[C] 100 120 40 60 80 100 120 TJ[C] Figure 33. Minimum on Time RMIN_TOFF = 10 kW Figure 34. Minimum on Time RMIN_TOFF = 50 kW -18,0 0,0 TJ = 125 C TJ = 105 C TJ = 85 C TJ = 55 C TJ = 25 C TJ = 0 C TJ = -20 C TJ = -40 C -10,0 -15,0 -18,5 TJ = 125 C TJ = 105 C TJ = 85 C TJ = 55 C -19,0 ILLD[A] -5,0 ILLD[A] 80 Figure 32. Minimum on Time RMIN_TON = 50 kW tMIN_TOFF[s] -20 60 TJ[C] Figure 31. Minimum on Time RMIN_TON = 10 kW 1,10 1,08 1,06 1,04 1,02 1,00 0,98 0,96 0,94 0,92 0,90 -40 40 -19,5 -20,0 TJ = 25 C TJ = 0 C TJ = -20 C TJ = -40 C -20,5 -21,0 -20,0 -21,5 -25,0 0 5 10 15 20 VCC[V] 25 30 35 -22,0 0 5 10 15 20 25 VCC[V] Figure 35. LLD Current, VLLD = 3.0 V Figure 36. LLD current, VLLD = 2.5 V www.onsemi.com 14 30 35 -15.0 640 -16.0 620 -17.0 -18.0 -19.0 600 TJ = 125 C TJ = 105 C TJ = 85 C -20.0 TJ = 55 C TJ = 25 C TJ = 0 C TJ = -20 C TJ = -40 C -21.0 -22.0 -23.0 -24.0 -25.0 580 tLLD[s] ILLD[A] NCP4306 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 560 540 520 500 480 460 440 -40 4.0 -20 0 20 VLLD[V] Figure 37. LLD Current 10,0 5,1 9,8 VDRV[V] VDRV[V] 5,3 VCC = 12 V, CDRV = 0 nF VCC = 12 V, CDRV = 1 nF VCC = 12 V, CDRV = 10 nF VCC = 35 V, CDRV = 0 nF VCC = 35 V, CDRV = 1 nF VCC = 35 V, CDRV = 10 nF 9,6 9,4 9,2 100 120 -20 0 20 40 TJ[C] 60 80 100 VCC = 12 V, CDRV = 0 nF VCC = 12 V, CDRV = 1 nF VCC = 12 V, CDRV = 10 nF VCC = 35 V, CDRV = 0 nF VCC = 35 V, CDRV = 1 nF VCC = 35 V, CDRV = 10 nF 4,9 4,7 4,5 4,3 -40 120 Figure 39. Driver Output Voltage, Ver. xAxxxxx -20 0 20 40 TJ[C] 60 80 100 120 Figure 40. Driver Output Voltage, Ver. xBxxxxx 38 4,6 33 4,4 RatioEXC[-] tdV/dt[ns] 80 5,5 10,2 28 23 18 13 -40 60 Figure 38. LLD Time, VLLD = 1.82 V (or Internal Option) 10,4 9,0 -40 40 TJ[C] 4,2 4,0 3,8 3,6 -20 0 20 40 60 80 100 3,4 -40 120 TJ[C] -20 0 20 40 60 80 100 TJ[C] Figure 41. dV/dt Detector Time Threshold, Ver. xxDxxxx Figure 42. Exception Timer Ratio to tMIN_TON, Ver. xxHxxxx www.onsemi.com 15 120 NCP4306 GENERAL DESCRIPTION The NCP4306 is designed to operate either as a standalone IC or as a companion IC to a primary side controller to help achieve efficient synchronous rectification in switch mode power supplies. This controller features a high current gate driver along with high-speed logic circuitry to provide appropriately timed drive signals to a synchronous rectification MOSFET. With its novel architecture, the NCP4306 has enough versatility to keep the synchronous rectification system efficient under any operating mode. The NCP4306 works from an available voltage with range from 4.0 / 3.5 V to 35 V (typical). The wide VCC range allows direct connection to the SMPS output voltage of most adapters such as notebooks, cell phone chargers and LCD TV adapters. Precise turn-off threshold of the current sense comparator together with an accurate offset current source allows the user to adjust for any required turn-off current threshold of the SR MOSFET switch using a single resistor. Compared to other SR controllers that provide turn-off thresholds in the range of -10 mV to -5 mV, the NCP4306 offers a turn-off threshold of 0 mV. When using a low RDS_ON SR (1 m) MOSFET our competition, with a -10 mV turn off, will turn off with 10 A still flowing through the SR FET, while our 0 mV turn off turns off the FET at 0 A; significantly reducing the turn-off current threshold and improving efficiency. Many of the competitor parts maintain a drain source voltage across the MOSFET causing the SR MOSFET to operate in the linear region to reduce turn-off time. Thanks to the 6 A sink current of the NCP4306 significantly reduces turn off time allowing for a minimal drain source voltage to be utilized and efficiency maximized. To overcome false triggering issues after turn-on and turn-off events, the NCP4306 provides adjustable minimum on-time and off-time blanking periods. Blanking times can be set internally during production or adjusted independently of IC VCC using external resistors connected to GND (internal or external option depends on IC variant). If needed, externally set blanking periods can be modulated using additional components. An extremely fast turn-off comparator, implemented on the current sense pin, allows for NCP4306 implementation in CCM applications without any additional components or external triggering. An ultrafast trigger input offers the possibility to further increase efficiency of synchronous rectification systems operated in CCM mode (for example, CCM flyback or forward). The time delay from trigger input to driver turn off event is tPD_TRIG. Additionally, the trigger input can be used to disable the IC and activate a low consumption standby mode. This feature can be used to decrease standby consumption of an SMPS. If the trigger input is not wanted than the trigger pin can be tied to GND. An output driver features capability to keep SR transistor turned-off even when there is no supply voltage for the NCP4306. SR transistor drain voltage goes up and down during SMPS operation and this is transferred through drain gate capacitance to gate and may open transistor. The NCP4306 keeps DRV pin pulled low even without any supply voltage and thanks to this the risk of turned-on SR transistor before enough VCC is applied to the NCP4306 is eliminated. Finally, the NCP4306 features a Light Load Detection function that can be set internally or externally at LLD pin by resistor connected to ground. This function detects light load or no load conditions and during them between conduction phases it decreases current consumption. This helps to improve SMPS efficiency. If LLD function is not needed pin can be left open. www.onsemi.com 16 NCP4306 SUPPLY SECTION Supply voltage should be connected to VCC pin. Minimum voltage for proper operation is 4.0 / 3.5 V typically and maximum level is 35 V. Decoupling capacitor between VCC and GND pin is needed for proper operation and its recommended value is 1 F. If IC is supplied from SMPS output voltage, few ohm resistor is recommended between SMPS output voltage and VCC pin. Resistor task is to divide decoupling cap from output to avoid closing HF currents through NCP4306 decoupling cap, because these currents may causes drops at GND connection that affects SR transistor sensing and incorrect SR transistor turn-off. SR transistor is usually used in low side configuration (placed in return path), but it may be also used in high side configuration (placed in positive line). It is not possible to use SMPS VOUT for SR supply in high side configuration so it is needed to provide supply differently. One possibility is to use auxiliary winding as shown in Figure 43. Voltage from auxiliary winding is rectified, filtered and use as supply voltage. C5 C4 R6 C1 R2 C2 R7 R8 R9 D4 TR1 NCP4306 D3 M2 VCC FLYBACK CONTROL CIRCUITRY FB D1 C3 DRV CS D2 +VOUT M1 OK1 R1 D5 C1 R3 GND Figure 43. High Side Configuration Supplied from Auxiliary Winding If auxiliary winding is not acceptable, transformer forward voltage can be used as supply source (Figure 44). Forward voltage is regulated by simple voltage regulator to fit NCP4306 VCC restriction. Penalty for this solution is slightly lower efficiency. C4 R6 C5 R7 R8 R9 D4 VBULK R2 C1 D5 C2 NCP4306 M2 D3 FLYBACK CONTROLL FB CS C3 DRV +VOUT D1 D2 C6 M1 OK1 R1 D6 R3 Figure 44. High Side Configuration Supplied from Transformer Forward Voltage www.onsemi.com 17 GND NCP4306 Auxiliary winding or forward voltage can be used as supply source also for low side configuration if VOUT is not high enough (Figure 45). Do not focus just on SR controller UVLO, but also on SR transistor characteristics. Some transistors may be not turned-on enough even at 5 V so in these case SR controller supply voltage should be increased. +VOUT < 5V VBULK R1 C1 R3 D4 C2 C8 R6 R7 D3 C7 VCC ZCD C4 R4 D4 PRIMARY SIDE FLYBACK CONTROLLER C3 DRV M2 M1 R8 D5 GND C9 COMP CS R2 R5 NCP4306 C5 C6 Figure 45. Low Side Configuration Supplied from Transformer Forward Voltage for Low VOUT SMPS Current Sense Input Because of parasitic impedances, significant ringing can occur in the application. To overcome false sudden turn-off due to mentioned ringing, the minimum conduction time of the SR MOSFET is activated. Minimum conduction time can be adjusted using the RMIN_TON resistor or can be chosen from internal fixed values. Figure 46 shows the internal connection of the CS circuitry on the current sense input. When the voltage on the secondary winding of the SMPS reverses, the body diode of M1 starts to conduct current and the voltage of M1's drain drops approximately to -1 V. Once the voltage on the CS pin is lower than VTH_CS_ON threshold, M1 is turned-on. + VOUT + SR MOSFET M1 VTH_CS_ON CS_ON CS_OFF To Internal logic CS_RESET VTH_CS_RESET dV / dt Detector Figure 46. Current Sensing Circuitry Functionality www.onsemi.com 18 High dV / dt NCP4306 The SR MOSFET is turned-off as soon as the voltage on the CS pin is higher than VTH_CS_OFF (typically -0.5 mV). For the same ringing reason, a minimum off-time timer is asserted once the VCS goes above VTH_CS_RESET. The minimum off-time can be externally adjusted using RMIN_TOFF resistor or can be chosen from internally fixed values (depends on version). The minimum off-time generator can be re-triggered by MIN_TOFF reset comparator if some spurious ringing occurs on the CS input after SR MOSFET turn-off event. This feature significantly simplifies SR system implementation in flyback converters. In an LLC converter the SR MOSFET M1 channel conducts while secondary side current is decreasing (refer to Figure 47). Therefore the turn-off current depends on MOSFET RDSON. The -0.5 mV threshold provides an optimum switching period usage while keeping enough time margin for the gate turn-off. To ensure proper switching, the min_tOFF timer is reset, when the VDS of the MOSFET rings and falls down past the VTH_CS_RESET. The minimum off-time needs to expire before another drive pulse can be initiated. Minimum off-time timer is started again when VDS rises above VTH_CS_RESET. VDS = VCS ISEC VTH_CS_RESET VTH_CS_OFF VTH_CS_ON VDRV Turn on delay Min ON-time Turn off delay Min tOFF timer was stopped here because of VCS<VTH_CS_RESET tMIN_TON Min OFF-time tMIN_TOFF Figure 47. CS Input Comparators Thresholds and Blanking Periods Timing in LLC www.onsemi.com 19 NCP4306 VDS = VCS ISEC VTH_CS_RESET VTH_CS_OFF VTH_CS_ON VDRV Turn off delay Turn on delay Min ON-time Min tOFF timer was stopped here because of VCS<VTH_CS_RESET tMIN_TON Min OFF-time tMIN_TOFF Figure 48. CS Input Comparators Thresholds and Blanking Periods Timing in Flyback SR Transistor Selection which was selected with minimum available RDS(ON) resistance requirement only. Sensing VDS drop across the SR transistor, which is ideally product of transistor's RDS(ON) and secondary side current, is affected by voltage drop at parasitic inductance of package (bonding, leads, ...) and PCB layout-(refer to Figure 49). The current that flows through the SR MOSFET experiences a high i(t) / t that induces an error voltage on the SR MOSFET bonds and leads due to their parasitic inductance. This error voltage is proportional to the derivative of the SR MOSFET current; and shifts the CS input voltage to zero when significant current still flows through the MOSFET channel. As a result, the SR MOSFET is turned-off prematurely and the efficiency of the SMPS is not optimized - refer to Figure 50 for a better understanding. An SMPS designer should consider all important SR MOSFET parameters for its optimum selection in given application and not stick only to the lowest RDS(ON) requirement. The lower RDS(ON) device is selected the more significant role the lead parasitic inductances play in turn-of threshold sensing i.e. the more premature turn-off will happen (refer to section below for parasitic inductance impact to VDS sensing). The lower RDS(ON) switch also usually features higher input capacitance that increases driving losses. The higher output capacitance and higher reverse recovery charge of body diode then results in higher drain-to source voltage peaks in CCM applications. Thus the higher RDS(ON) MOSFET can usually provide better or at least same efficiency result when compare to a switch www.onsemi.com 20 NCP4306 VDS a) VL_LAYOUT LLAYOUT VL_DRAIN LDRAIN ISEC VRDS_ON VL_SOURCE VL_LAYOUT LLAYOUT LSOURCE RDS_ON MOSFET equivalent circuit To VCC 1 F 100 nF Decoupling Capacitors NCP4306 VDS ISEC b) VL_LAYOUT LLAYOUT VL_DRAIN LDRAIN VRDS_ON RDS_ON VL_SOURCE LSOURCE VL_LAYOUT LLAYOUT MOSFET equivalent circuit To VCC 1 F 100 nF Decoupling Capacitors NCP4306 Figure 49. SR System Connection Including MOSFET and Layout Parasitic Inductances in a) LLC and b) Flyback Application www.onsemi.com 21 NCP4306 a) b) Figure 50. Waveforms from SR System Implemented in a) LLC and b) Flyback Application and Using MOSFET in TO220 Package With Long Leads - SR MOSFET channel Conduction Time is Reduced current i / t and high operating frequency is to use lead-less SR MOSFET i.e. SR MOSFET in SMT package. The parasitic inductance of a SMT package is negligible causing insignificant CS turn-off threshold shift and thus minimum impact to efficiency (refer to Figure 51). Note that the efficiency impact caused by the error voltage due to the parasitic inductance increases with lower MOSFETs RDS_ON and / or higher operating frequency. It is thus beneficial to minimize SR MOSFET package leads length in order to maximize application efficiency. The optimum solution for applications with high secondary a) b) Figure 51. Waveforms from SR System Implemented in a) LLC b) Flyback Application and Using MOSFET in SMT Package with Minimized Parasitic Inductance - SR MOSFET Channel Conduction Time is Optimized www.onsemi.com 22 NCP4306 resistance. In reality there will be small parasitic impedance on the CS path due to the bonding wires, leads and soldering. To assure the best efficiency results, a Kelvin connection of the SR controller to the power circuitry should be implemented. The GND pin should be connected to the SR MOSFET source soldering point and current sense pin should be connected to the SR MOSFET drain soldering point - refer to Figure 49. Using a Kelvin connection will avoid any impact of PCB layout parasitic elements on the SR controller functionality; SR MOSFET parasitic elements will still play a role in attaining an error voltage. Figure 52 and Figure 53 show examples of SR system layouts using MOSFETs in D2PAK and SO8FL packages. It can be deduced from the above paragraphs on the induced error voltage and parameter tables that turn-off threshold precision is quite critical. If we consider a SR MOSFET with RDS_ON of 1 m, the 1 mV error voltage on the CS pin results in a 1 A turn-off current threshold difference; thus the PCB layout is very critical when implementing the SR system. Note that the CS turn-off comparator is referred to the GND pin. Any parasitic impedance (resistive or inductive - even on the magnitude of m and nH values) can cause a high error voltage that is then evaluated by the CS comparator. Ideally the CS turn-off comparator should detect voltage that is caused by secondary current directly on the SR MOSFET channel Figure 52. Recommended Layout When Using SR MOSFET in D2PAK Package Figure 53. Recommended Layout When Using SR MOSFET in SMT Package SO8 FL Trigger / Disable input advantageous than leaving end of conduction phase on body diode. Reason is body diode has usually longer recovery time and resulting overlap time (simultaneously conduction primary and secondary side switches) is longer. There are several possibilities for transferring the trigger signal from the primary to the secondary side - refer to Figure 68 and Figure 69. The trigger signal is blanked for tTRIG_BLANK after the DRV turn-on process has begun. The blanking technique is used to increase trigger input noise immunity against the parasitic ringing that is present during the turn on process due to the SMPS layout. The trigger input is supersedes the CS input except trigger blanking period. TRIG / DIS signal turns the SR MOSFET off or prohibits its turn-on when the TRIG / DIS pin is pulled above VTRIG_TH. The SR controller enters disable mode when the trigger pin is pulled-up for more than tDIS_TIM. In disable mode the IC consumption is significantly reduced. To recover from disable mode and enter normal operation, the TRIG / DIS pin has to be pulled low at least for tDIS_END. The NCP4306 features an ultrafast trigger input that exhibits a maximum of tPD_TRIG delay from its activation to the start of SR MOSFET turn-off of process. This input can be used in applications operated in deep Continues Conduction Mode (CCM) to further increase efficiency and / or to activate disable mode of the SR driver in which the consumption of the NCP4306 is reduced to maximum of ICC_DIS. NCP4306 is capable to turn-off the SR MOSFET reliably in CCM applications just based on CS pin information only, without using the trigger input. However, natural delay of the ZCD comparator and DRV turn-off delay increase overlap between primary and secondary MOSFETs switching (also known as cross conduction). If one wants to achieve absolutely maximum efficiency with deep CCM applications, then the trigger signal coming from the primary side should be applied to the trigger pin. It is good to set trigger pulse in way there is just short overlap between primary and secondary switches. Short overlap is usually www.onsemi.com 23 NCP4306 VDS = VCS VTH_CS_RESET VTH_CS_OFF VTH_CS_ON VTRIG / DIS VDRV t1 t2 t3 t4 t5 t6 t7 t8 t t9 Figure 54. Trigger Input Functionality Waveforms Using the Trigger to Turn-off and Block the DRV Signal / DIS pin almost immediately turns off the drive to the SR MOSFET, turning off the MOSFET. The DRV is not turned-on in other case (t6) because the trigger pin is high in the time when CS pin signal crosses turn-on threshold. This figure clearly shows that the DRV can be asserted only on falling edge of the CS pin signal in case the trigger input is at low level (t2). Figure 54 shows basic TRIG / DIS input functionality. At t1 the TRIG / DIS pin is pulled low to enter into normal operation. At t2 the CS pin is dropped below the VTH_CS_ON, signaling to the NCP4306 to start to turn the SR MOSFET on. At t3 the NCP4306 begins to drive the MOSFET. At t4, the SR MOSFET is conducting and the TRIG / DIS pin is pulled high. This high signal on the TRIG VDS = VCS VTH_CS_RESET VTH_CS_OFF VTH_CS_ON VTRIG / DIS TRIG / DIS blank tTRIGBLANK Min ON-time VDRV t1 t2 t t3 Figure 55. Trigger Input Functionality Waveforms - Trigger Blanking shortly after time t2. Due to the Trigger blanking clock (tTRIG_BLANK) the Trigger's high signal does not affect the DRV signal until the tTRIG_BLANK timer has expired. At time t3 the TRIG / DIS signal is reevaluated and the DRV In Figure 55 above, at time t1 the CS pin falls below the VTH_CS_ON while the Trigger is low setting in motion the DRV signal that appears at t2. At time t2 the DRV signal and Trigger blanking clock begin. TRIG / DIS signal goes high www.onsemi.com 24 NCP4306 signal is turned off. The TRIG / DIS input is blanked for tTRIG_BLANK after DRV set signal to avoid undesirable behavior during SR MOSFET turn-on event. The blanking time in combination with high threshold voltage (VTRIG_TH) prevent triggering on ringing and spikes that are present on the TRIG / DIS input pin during the SR MOSFET turn-on process. Controller's response to the narrow pulse on the TRIG / DIS pin is depicted in Figure 55 - this short trigger pulse enables to turn the DRV on for tTRIG_BLANK. Note that this case is valid only if device not entered disable mode before. VDS = VCS VTH_CS_RESET VTH_CS_OFF VTH_CS_ON VTRIG / DIS VTRIG_BLANK TRIG / DIS blank MIN ON-TIME VDRV t0 t1 t2 t3 t4 t t5 t6 Figure 56. Trigger Input Functionality Waveforms - Trigger Blanking Acts Like a Filter Figure 56 above shows almost the same situation as in Figure 55 with one main exception; the TRIG / DIS signal was not high after trigger blanking timer expired so the DRV signal remains high. The advantage of the trigger blanking time during DRV turn-on is evident from Figure 56 since it acts like a filter on the TRIG / DIS pin. Rising edge of the DRV signal may cause spikes on the trigger input. If it wasn't for the TRIG / DIS blanking these spikes, in combination with ultra-fast performance of the trigger logic, could turn the SR MOSFET off in an inappropriate time. VDS = VCS VTH_CS_RESET VTH_CS_OFF VTH_CS_ON VTRIG / DIS Min ON-time VDRV t0 t1 t2 t3 t4 t5 t6 t7 t8 t Figure 57. Trigger Input Functionality Waveforms - Trigger over Ride, CS Turn Off and Min On-time www.onsemi.com 25 NCP4306 Figure 57 depicts all possible driver turn-off events in details when correct VCC is applied. Controller driver is disabled based on TRIG / DIS input signal in time t2; the TRIG / DIS input overrides the minimum on-time period. Driver is turned-off according to the CS (VDS) signal (t5 marker) and when minimum on-time period elapsed already. TRIG / DIS signal needs to be low during this event. If the CS (VDS) voltage reaches VTH_CS_OFF threshold before minimum on-time period ends (t7) and the TRIG / DIS pin is low the DRV is turned-off on the falling edge of the minimum on-time period (t8 time marker in Figure 57). This demonstrates the fact that the Trigger over rides the minimum on-time. Minimum on-time has higher priority than the CS signal. In Figure 58 the TRIG / DIS input is low the whole time and the DRV pulses are purely a function of the CS signal and the minimum on-time. The first DRV pulse terminated based on the CS signal and another two DRV pulses are prolonged till the minimum on-time period end despite the CS signal crosses the VTH_CS_OFF threshold earlier. If a minimum on-time is too long the situation that occurs after time marker t6 Figure 58 can occur, is not correct and should be avoided. The minimum tON period should be selected shorter to overcome situation that the SR MOSFET is turned-on for too long time. The secondary current then changes direction and energy flows back to the transformer that result in reduced application efficiency and also in excessive ringing on the primary and secondary MOSFETs. VDS = VCS VTH_CS_RESET VTH_CS_OFF VTH_CS_ON VTRIG / DIS Min ON-time VDRV t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t Figure 58. Minimum On-Time Priority pin voltage goes above VTH_CS_RESET threshold. Next cycle starts in time t6. The TRIG / DIS goes low and enables the DRV before VDS drops below VTH_CS_ON threshold voltage thus the DRV turns-on in time t6. The TRIG / DIS signal rises up to HIGH level at time t7, consequently DRV turns-off and IC waits for high CS voltage to start minimum off-time execution. Figure 59 shows IC behavior in case the trigger signal features two pulses during one cycle of the VDS (CS) signal. The TRIG / DIS goes low enables the DRV just before time t1 and DRV turns-on because the VDS voltage drops under VTH_CS_ON threshold voltage. The TRIG / DIS signal disables driver at time t2. The TRIG / DIS drops down to LOW level in time t3, but IC waits for complete minimum off-time. Minimum off-time execution is blocked until CS www.onsemi.com 26 NCP4306 VDS = VCS VTH_CS_RESET VTH_CS_OFF VTH_CS_ON VTRIG/DIS Min ON-time Min OFF-time VDRV t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t Figure 59. TRIG / DIS Input Functionality Waveforms - Two Pulses at One Cycle VDS = VCS VTH_CS_RESET VTH_CS_OFF VTH_CS_ON VTRIG / DIS tDIS_TIM Min ON-time VDRV Power consumption t0 t1 t2 t3 t4 t Figure 60. Trigger Input Functionality Waveforms - Disable Mode Activation transition to disable mode. Figure 61 shows disable mode transition 2nd case - i.e. when trigger rising edge comes during the trigger blank period. Figure 62 shows entering into disable mode and back to normal sequences. In Figure 60 above, at t2 the CS pin rises to VTH_CS_OFF and the SR MOSFET is turned-off. At t3 the TRIG / DIS signal is held high for more than tDIS_TIM. NCP4306 enters disable mode after tDIS_TIM. Driver output is disabled in disable mode. The DRV stays low (disabled) during www.onsemi.com 27 NCP4306 VDS = VCS VTH_CS_RESET VTH_CS_OFF VTH_CS_ON VTRIG / DIS tDIS_TIM Min ON-time tTRIGBLANK VDRV Power consumption t0 t1 t2 t3 t Figure 61. Trigger Input Functionality Waveforms - Disable Mode Clock Initiation VDS = VCS VTH_CS_RESET VTH_CS_OFF VTH_CS_ON VTRIG / DIS tDIS_TIM tDIS_REC VDRV Min OFF-time Power consumption Disable Mode t0 t1 t2 t3 t4 Figure 62. Trigger Input Functionality Waveforms - Disable and Normal Modes www.onsemi.com 28 t NCP4306 Figure 63 and Figure 64 shows exit from disable mode in detail. NCP4306 requires time up to tDIS_REC to recover all internal circuitry to normal operation mode when recovering from disable mode. The driver is then enabled after complete tMIN_TOFF period when CS (VDS) voltage is over VTH_CS_RESET threshold. Driver turns-on in the next cycle on CS (VDS) falling edge signal only (t5 - Figure 63). The DRV stays low during recovery time period. TRIG / DIS input has to be low at least for tDIS_END time to end disable mode and start with recovery. Trigger can go back high after tDIS_END without recovery interruption. VDS = VCS VTH_CS_RESET VTH_CS_OFF VTH_CS_ON VTRIG / DIS Min ON-time Power consumption Disable Mode VDRV Rec time Waits for complete Normal Mode tMIN_TOFF t t0 t1 t2 t3 t4 t5 t6 t7 t8 Note: Rec Time = Recovery Time Figure 63. Trigger Input Functionality Waveforms - Exit from Disable Mode before the Falling Edge of the CS Signal www.onsemi.com 29 NCP4306 VDS = VCS VTH_CS_RESET VTH_CS_OFF VTH_CS_ON VTRIG / DIS tDIS_END Min OFF-time VDRV Power consumption Waits for complete time tMIN_TOFF Rec Disable Mode t0 t1 t2 t4 t3 Normal Mode t t5 Note: Rec Time = Recovery Time Figure 64. Trigger Input Functionality Waveforms VDS = VCS VTH_CS_RESET VTH_CS_OFF VTH_CS_ON VTRIG / DIS Min OFF-time tMIN_TOFF tDIS_REC VDRV Power consumption Disable Mode Waits for complete tMIN_TOFF Recovery t0 t1 t2 t3 t4 Normal Mode t5 t6 t7 t8 Figure 65. Trigger Input Functionality Waveforms www.onsemi.com 30 tt NCP4306 normal mode doesn't start. VDS voltage goes high again at time t4 and this event starts new minimum off-time timer execution. Next VDS falling edge below VTH_CS_ON level activates driver. Figure 65 shows detail IC behavior after disable mode is ended. The trigger pin voltage goes low at t1 and after tDIS_REC IC leaves disable mode (t2). Time interval between t2 and t3 is too short for complete minimum off-time so VDS = VCS VTH_CS_RESET VTH_CS_OFF VTH_CS_ON VTRIG / DIS tMIN_TOFF Min OFF-time Disable Mode VDRV Power consumption t0 tDIS_REC Waits for complete tMIN_TOFF Recovery t1 t4 t2 t3 Normal Mode t5 t6 t t7 t8 Figure 66. Trigger Input Functionality Waveforms the IC waits to another time when VDS voltage is positive and then is again started the minimum off-time timer. The IC returns into normal mode after whole minimum off-time elapses. Different situation of leaving from disable mode is shown at Figure 66. Minimum off-time execution starts at time t2, but before time elapses VDS voltage falls to negative voltage. This interrupts minimum off-time execution and VDS = VCS VTH_CS_RESET VTH_CS_OFF VTH_CS_ON Min OFF-time Not Complete tMIN_TOFF - IC is not activated tMIN_TOFF Complete tMIN_TOFF - activates IC tMIN_TOFF tMIN_TOFF - is stopped due to VDS drops below VTH_CS_RESET tMIN_TON Min ON-time VDRV VCC VCCON t t1 t3 t2 t4 t5 t7 t6 t8 t9 t10 t11 t13 t14 t12 Figure 67. NCP4306 Operation after Start-Up Event www.onsemi.com 31 NCP4306 Start-up event waveforms are shown at Figure 67. A start-up event is very similar to an exit from disable mode event. The IC waits for a complete minimum off-time event (CS pin voltage is higher than VTH_CS_RESET) until drive pulses can continue. Figure 67 shows how the minimum off-time timer is reset when CS voltage is oscillating through VTH_CS_RESET level. The NCP4306 starts operation at time t1 (time t1 can be seen as a wake-up event from the disable mode through TRIG / DIS or LLD pin). Internal logic waits for one complete minimum off-time period to expire before the NCP4306 can activate the driver after a start-up or wake-up event. The minimum off-time timer starts to run at time t1, because VCS is higher than VTH_CS_RESET. The timer is then reset, before its set minimum off-time period expires, at time t2 thanks to CS voltage lower than VTH_CS_RESET threshold. The aforementioned reset situation can be seen again at time t3, t4, t5 and t6. A complete minimum off-time period elapses between times t7 and t8 allowing the IC to activate a driver output after time t8. Optional primary triggering techniques for CCM flyback application are shown in Figure 68 and Figure 69. NCP4306 can operate properly without triggering in CCM, but use of triggering can reduce the commutation losses and the SR MOSFET drain voltage spike, which results in improved efficiency in CCM. VBULK C1 R3 + VOUT TR1 R4 C3 C6 D2 M2 VCC FLYBACK CONTROL CIRCUITRY FB D3 DRV D1 C2 M1 CS GND C4 R5 R6 R7 R1 D4 NCP4306 R2 C5 OK1 D5 R7 Figure 68. Optional Primary Triggering in Deep CCM Application Using Auxiliary Winding The application shown in Figure 68 is simplest and the most cost effective solution for primary SR triggering. This method uses auxiliary winding made of triple insulated wire placed close to the primary winding section. This auxiliary winding provides information about primary turn-on event to the SR controller before the secondary winding reverses. This is possible thanks to the leakage between primary and secondary windings that creates natural delay in energy transfer. This technique provides approximately 0.5% efficiency improvement when the application is operated in deep CCM and a transformer that has a leakage of 1% of primary inductance is used. www.onsemi.com 32 NCP4306 VBULK C1 TR1 R2 + VOUT R4 C4 D2 VCC FLYBACK CONTROL CIRCUITRY FB CS C7 M2 D3 C3 DRV GND C6 D1 M1 R5 R6 R7 R1 R3 D4 NCP4306 OK1 D5 TR2 R8 C5 Figure 69. Optional Primary Triggering in Deep CCM Application Using Trigger Transformer to assure LPRIMARY = LSECONDARY > 10 H. Proper safety insulation between primary and secondary sides can be easily assured by using triple insulated wire for one or, better, both windings. This primary triggering technique provides approximately 0.5% efficiency improvement when the application is operated in deep CCM and transformer with leakage of 1% of primary inductance is used. It is also possible to use capacitive coupling (use additional capacitor with safety insulation) between the primary and secondary to transmit the trigger signal. We do not recommend this technique as the parasitic capacitive currents between primary and secondary may affect the trigger signal and thus overall system functionality. Application from Figure 69 uses an ultra-small trigger transformer to transfer primary turn-on information directly from the primary controller driver pin to the SR controller trigger input. Because the trigger input is rising edge sensitive, it is not necessary to transmit the entire primary driver pulse to the secondary. The coupling capacitor C5 is used to allow the trigger transformer's core to reset and also to prepare a needle pulse (a pulse with width shorter than 100 ns) to be transmitted to the NCP4306 TRIG / DIS input. The advantage of needle trigger pulse usage is that the required volt-second product of the pulse transformer is very low and that allows the designer to use very small and cheap magnetic. The trigger transformer can even be prepared on a small toroidal ferrite core with outer diameter of 4 mm and four turns for primary and secondary windings www.onsemi.com 33 NCP4306 Minimum tON and tOFF adjustment Fixed versions are defined internally and can't be modified later or changed during operation. The adjustment of minimum tON and tOFF periods are done based on an internal timing capacitance and external resistors connected to the GND pin - refer to Figure 70 for a better understanding. The NCP4306 offers fixed or an adjustable minimum on-time and off-time blanking periods (depends on IC version) that ease the implementation of a synchronous rectification system in any SMPS topology. These timers avoid false triggering on the CS input after the MOSFET is turned on or off. VDD To Internal Logic VREF IR_MIN_TON tMIN_TON MIN_TON Discharge Switch Ct IR_MIN_TON RMIN_TON NCP4306 GND Figure 70. Internal Connection of the MIN_TON Generator (the MIN_TOFF Works in the Same Way) Current through the MIN_TON adjust resistor can be calculated as: I R_MIN_TON + V ref R MIN_TON If the internal current mirror creates the same current through RMIN_TON as used the internal timing capacitor (Ct) charging, then the minimum on-time duration can be calculated using this equation. (eq. 1) t MIN_ON + V t V ref I R_MIN_TON V ref + Ct V ref + Ct R MIN_TON (eq. 2) R MIN_TON the accuracy of equations 7 and 8 when MIN_TON or MIN_TOFF times are selected near to their minimum possible values. Please refer to Figure 71 and Figure 72 for measured minimum on and off time charts. 5,0 5,0 4,5 4,5 4,0 4,0 3,5 3,5 tMIN_TOFF [s] tMIN_TON [s] The internal capacitor size would be too large if IR_MIN_TON was used. The internal current mirror uses a proportional current, given by the internal current mirror ratio. Note that the internal timing comparator delay affects 3,0 2,5 2,0 1,5 1,0 2,5 2,0 1,5 1,0 0,5 0,0 3,0 0,5 0 5 10 15 20 25 30 RMIN_TON [k] 35 40 45 0,0 50 Figure 71. MIN_TON Adjust Characteristic 0 5 10 15 20 25 30 35 RMIN_TOFF [k] 40 45 Figure 72. MIN_TOFF Adjust Characteristic www.onsemi.com 34 50 NCP4306 The total off-time blanking period is prolonged due to the ringing in the application (refer to Figure 47). Some applications may require adaptive minimum on and off time blanking periods. It is possible to modulate blanking periods by using an external NPN transistor - refer to Figure 73. The modulation signal can be derived based on the load current, feedback regulator voltage or other application parameter. The absolute minimum tON duration is internally clamped to 55 ns and minimum tOFF duration to 70 ns in order to prevent any potential issues with the minimum tON and / or tOFF input being shorted to GND. The NCP4306 features dedicated anti-ringing protection system that is implemented with a minimum tOFF blank generator. The minimum off-time one-shoot generator is restarted in the case when the CS pin voltage crosses VTH_CS_RESET threshold and MIN_TOFF period is active. VDD To Internal Logic VREF IR_MIN_TON tMIN_TON MIN_TON RMIN_TON MIN_TON modulation Input RMIN_TON_2 Modulation Current Discharge Switch IR_MIN_TON NCP4306 GND Figure 73. Possible Connection for MIN_TON and MIN_TOFF Modulation dV / dt Detection - Flyback feature primary side switch is turned on and off again so SR controller doesn't turn on SR mosfet. Whole secondary side current flows through body diode that makes power loss. Figure 74 shows situation without dV / dt detection. Here can be seen that without detection next conduction cycle may be not taken through activated SR transistor. Reason is not elapsed minimum off-time blanking interval. The NCP4306 includes optional feature for flyback type converters, which operates with shorter primary on-time than ringing period after demagnetization phase during medium / high loads. These applications are for example USB-PD or Quick Charge adapters. Difficulty with this situation is that minimum off-time doesn't elapse before www.onsemi.com 35 NCP4306 tMIN_TOFF has to be set to longer time length of ringing period tMIN_TOFF VDS = VCS ISEC Primary on-time is very short (shorter than ringing period) for low VOUT VTH_CS_RESET VTH_CS_OFF VTH_CS_ON VDRV tMIN_TOFF timer is stopped here because of VCS< VTH_CS_RESET tMIN_TON tMIN_TOFF Min ON-time Driver is not turned-on because tMIN_TOFF doesn't elapse Turn-on delay Turn-off delay Min OFF-time tMIN_TOFF Figure 74. Situation without dV / dt Detection Feature Figure 75 shows how system with activated dV / dt detection behaves. Min_toff blanking interval is also reset during voltage drops at CS pin, but if high negative dV / dt occurs at CS pin, min_toff interval is shorted and SR controller is ready to detect CS voltage lower than VCS_TH_ON and turn SR transistor on. Negative dV / dt at CS pin after primary switch is turned off is high in compare to slope that comes during ringing after demagnetization. Thanks to this we can safely detect end of primary on-time from ringing. VDS = VCS tMIN_TOFF has to be set to longer time than length of ringing period tMIN_TOFF ISEC VTH_CS_RESET VTH_CS_OFF VTH_CS_ON VDRV Min ON-time Turn-on delay tMIN_TON Min OFF-time Turn-off delay CS voltage drops below VTH_CS_ON but at time when min tOFF doesn't elapse and just low dV / dt is detected so DRV is not activated tMIN_TOFF timer is stopped here because of VCS< VTH_CS_RESET tMIN_TOFF Negative dV / dt detector at CS pin tMIN_TOFF tMIN_TOFF timer doesn't elapse but high dV / dt is detected so DRV is enable Figure 75. Situation with Enabled dV / dt Detection Exception Timer - LLC feature part followed by distorted sine. Examples of current shape is shown in Figure 76. This figure shows different current shapes at different loading. Lower loading makes shape more distorted from ideal sine. Exception timer is special feature for LLC type SMPS. It is mainly targeted to operation under light / medium load, where secondary side SMPS current shape is not sine, but it contains part of capacitive peak optionally with no current www.onsemi.com 36 NCP4306 ISEC t Figure 76. Current Shapes in LLC Examples above VTH_CS_OFF threshold. Turn-off process can be masked by min_ton blanking interval, but in this case is needed to set it at least to 1.5 s that can make issue during very light load where current flows just short time and long min_ton may cause reverse current from output capacitors back to transformer and may change soft switching condition to hard switching at primary side. 3,00 2 2,50 0 2,00 -2 VDS[mV] ISEC[A] Problematic shapes may cause prematurely SR transistor turn-off, because CS voltage may get to zero or to positive voltage (due to low current or high dI / dt and parasitic inductance). Sensed voltage drop can be seen in Figure 77. This situation is valid for SR mosfet with RDSON = 1 m and with package (SMT) parasitic inductance LPACPAR = 0.5 nH. There can be seen that SR transistor should be turned off in time between 0.4 to 1.5 s, because CS voltage is 1,50 -4 1,00 -6 0,50 -8 -10 0,00 0 1 2 3 4 5 6 7 VTH_CS_OFF Drop just at RDSon 0 t[s] 1 2 Drop at RDSon and parasitic inductance 3 4 5 6 7 t[s] Figure 77. Sensed Voltage Drop at SR Transistor in LLC during Light / Medium Load To early SR transistor turn-off is not issue just from efficiency point of view, but also from system stability point of view. When load is decreased, feedback loop asks primary side for lower power that changes secondary side current shape and SR driver can be turned off shortly after min_toff elapses. This causes lower efficiency transfer to secondary side and output voltage starts to decrease. Feedback loop asks for more power, secondary current shape changes and SR driver starts to conduct whole period again that improves energy transfer efficiency and output voltage starts to increase. This has to be again regulated by feedback loop and everything starts from begin and make SMPS oscillations that can be accompany with audible noise. www.onsemi.com 37 NCP4306 Regulation loop decreases transferred power because thanks to SR Regulation loop increases transferred power because thanks to low it is too much voltage at the output SR conduction angle lot of power is lose at body diode ISEC VDS1 VDRV1 MIN_TON VDS2 Bodydiode conducts Bodydiode conducts CS voltage goes above 0 V after min_ton = SR is turned off VDRV2 MIN_TON Bodydiode conducts Bodydiode conducts Figure 78. LLC System Oscillation due to Short SR Transistor Conduction Operation of new feature is shown in Figure 79. Current shape makes drop at SR transistor with 1 m and 0.5 nH shown as VDS that is sensed at CS pin and on and off comparators decide about SR operation based on this voltage. Driver is turned on and exception timer is started when VCS drops below VCS_TH_ON. During minimum on-time blanking interval off comparator is not active. CS pin voltage is above VTH_CS_OFF after minimum on-time elapses so driver is turned-off and because exception timer doesn't elapse, min_ton blanking interval is started. During this time on comparator output is blanked. Reason is to avoid quick driver turning on and off that would just increase consumption. When min_ton blanking interval elapses CS voltage is again below VTH_CS_ON and exception timer is not elapsed, driver can be turned on again simultaneously with minimum on-time interval. Driver is turned off again almost at the end of conduction phase, but this is correct turn off. Min-ton blanking interval doesn't start, because exception timer elapsed before so SR controller waits for VCS > VCS_TH_RESET to start minimum off time blanking timer. Exception timer length is given as multiple of minimum on time interval. It should be not set to longer time than t EXC t 3 1 f SWMAX (eq. 3) where fSWMAX is maximum LLC switching frequency. www.onsemi.com 38 NCP4306 ISEC 2.7 A 0.25 A VDS = VCS VTH_CS_RESET VTH_CS_OFF VTH_CS_ON Body diode drop (not in scale) Min ON-time Min ON-time_2 Driver can be turned on again up to this point Exception timer DRV Min OFF-time Figure 79. Exception Timer Operation Light Load Detection informs about CS voltage lower than zero (body diode or SR transistor conducting), LLD timer with set able nominal time and possibility to reduce it to one half and finally D flip flop with Disable signal output. Nominal time can be set by resistor at LLD pin connected to ground or internally during production. Recommended resistor values are shown in Table 6. In case of very noisy system, capacitor in parallel to LLD resistor may be used. Capacitor value impacts start-up time, because capacitor has to be charged above disable threshold by internal LLD current source. Light load detection feature is feature which task is to decrease SR controller consumption during time when SR transistor switching is not needed. This is usually during no load and light load condition when static SR controller consumption starts to play role. Goal is to disable controller during no switching time to eliminate static consumption and turn-on SR transistor as soon as possible when switching comes. Internal simplified block diagram is shown in Figure 80. Main parts of this system are comparator at CS input that VCSLLD CS Set max Set max to tLLD / 2 to tLLD LLD Timer RESET ELAPSED tim > 1/4 tLLD Figure 80. LLD Internal Block Diagram www.onsemi.com 39 S R Q Disable NCP4306 Table 6. PIN FUNCTION DESCRIPTION LLD setting tLLD [ms] IC disabled 70 130 280 540 1075 LLD disabled RLLD [kW] <12 27 43 68 91 120 >470* *floating pin allowed, small cap for noise robustness improvement recommended and IC starts to wake up (takes tLLD_DIS_REC, system wake up is controlled same as exit from disable mode by TRIG / DIS pin). End of conduction phase (CS voltage goes positive) starts LLD timer. If next conduction phase comes shortly after first (pulses in skip burst) so shortly than tLLD / 4 just LLD timer is reset. LLD timer length is set back to tLLD only when new conduction phase comes after previous in time between tLLD / 4 to tLLD / 2. This situation happens when load is slowly increased and skip bursts come more often. Logic function is also described by bubble diagram in Figure 81. LLD timer is running every time when CS pin voltage is positive (body diode and or transistor not conducting). If conduction doesn't come sooner than LLD timer elapses, DISABLE flag is set (IC is sent into low consumption mode), LLD timer length is changed to tLLD / 2 (this adds some hysteresis in system and helps keeping overall system stable) and timer is also reset. SR controller waits for falling edge at CS pin (begin of new conduction cycle). When CS goes negative, disable mode is deactivated Start LLD TIM is RUNNING LLD_CMP & TIM CNT < 1/4 tLLD Reset TIM DISABLE = 0 LLD_CMP DISABLE = 1 tTIM = 1/2 tLLD Reset TIM Reset TIM DISABLE = 0 tTIM = tLLD Figure 81. LLD Operation Bubble Diagram Example of LLD operation with flyback convertor can be seen in Figure 82. SMPS works under heavy load from point 0 to 1 where switching pulses comes regularly at high frequency that resets LLD timer soon after begin of counting. Load is significantly decreased to light load at point 1 so primary controller turns to skip mode. LLD timer elapses during skip so controller enters disable mode with very low consumption and change LLD timer maximum to tLLD / 2. Switching pulse in skip comes at time 3, this resets LLD timer and starts IC wake-up. Controller is waked up fully before point 4 and turns-on SR transistor. There is again no switching from 4 to 6 and thanks to it, LLD timer elapses at point 5 and controller enters disable mode again. Disable mode is ended at time 6, because new cycle comes. SR controller wakes-up and next pulse in skip burst is conducted via SR transistor. Time between 7 and 8 is delay between skip burst. Time is still less than tLLD / 4, LLD timer interval is not changed. Pulse at time 8 is fully conducted via SR transistor, because controller was not in disable mode before pulse came. No switching period between 9 and 11 is longer than tLLD / 2 that changes LLD timer setting to tLLD. This is because shorter delay between skip burst means higher load. Pulses are transferred via SR transistor at time 11 and 12, because disable mode was not activated. Load is being decreased again between time 12 to 15 so at time 15 SR controller enters disable mode and LLD timer time is reduced again to tLLD / 2. Second pulse in skip burst is again transferred via turned on SR transistor. Disable mode is activated after tLLD / 2 at time 18. Load is sharply changed at time 19 that means LLD timer is reset each pulse and timers time is kept at tLLD / 2. Load is removed at time 20 and disable is activated at time 21. Suitable LLD timer setting for flyback type of SMPS is 540 or 1075 s (for special type 280 s). www.onsemi.com 40 NCP4306 VDS = VCS t1 t2 t4 t2 t1 t2 DRV DIS ICC 0 t4 t1 t2 LLD tim tLLD 1 2 3 4 5 6 7 8 9 101112 13 14 15 16 17 18 19 20 21 22 Figure 82. LLD Operation with Flyback SMPS at time 8 respectively 9. Skip burst ends at time 12, LLD timers elapse at time 13 and 14 (reached tLLD / 2) and SR controllers enter disable mode. Controllers wake up at time 15 and 16 same as was in time 6 and 7. SMPS goes into skip in time 21, but load is connected soon and SMPS starts to operate under higher load from time 22. LLD timers reach time higher than tLLD / 4 but lower than tLLD / 2 so LLD timers maximum is set to tLLD. LLD timer setting for LLC may be set to lower times. Example of LLD operation with LLC convertor can be seen in Figure 83. SMPS works under heavy load from point 0 to 3. Both LLD timers are reset each cycle before LLD timer reaches tLLD / 4 and disable mode is not activated. SMPS load decreases at point 3 and goes into skip. LLD timers elapse during no switching time and change LLD timer time to tLLD / 2. When skip burst comes at time 6 channel 2 starts to wake up, channel 1 starts to wake up at time 7. Both channels are ready to conduct via SR transistor VDS1 = VCS1 VDS2 = VCS2 DRV1 DRV2 DIS1 DIS2 t2 0 1 2 3 t4 t1 LLD tim1 tLLD1 LLD tim2 tLLD1 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Figure 83. LLD Operation with LLC SMPS www.onsemi.com 41 19 20 21 22 23 24 25 26 27 28 NCP4306 Operation flow and dV / dt features are never activated both at same time. Operation starts in bubble start where system comes when VCC is higher than UVLO level and / or disable mode is activated (by LLD or TRIG / DIS pin). Followed bubble diagram at Figure 84 shows overall operation flow. Black bubbles are fundamental parts of system. States for dV / dt feature are colored by blue color and states for LLC feature (exception timer) are in red. LLC Figure 84. Overall Operation Bubble Diagram Power dissipation calculation significantly. Therefore, the MOSFET switch always operates under Zero Voltage Switching (ZVS) conditions when in a synchronous rectification system. The following steps show how to approximately calculate the power dissipation and DIE temperature of the NCP4306 controller. Note that real results can vary due to the effects of the PCB layout on the thermal resistance. It is important to consider the power dissipation in the MOSFET driver of a SR system. If no external gate resistor is used and the internal gate resistance of the MOSFET is very low, nearly all energy losses related to gate charge are dissipated in the driver. Thus it is necessary to check the SR driver power losses in the target application to avoid over temperature and to optimize efficiency. In SR systems the body diode of the SR MOSFET starts conducting before SR MOSFET is turned-on, because there is some delay from VTH_CS_ON detect to turn-on the driver. On the other hand, the SR MOSFET turn off process always starts before the drain to source voltage rises up Step 1 - MOSFET gate to source capacitance: During ZVS operation the gate to drain capacitance does not have a Miller effect like in hard switching systems because the drain to source voltage does not change (or its change is negligible). Figure 85. Typical MOSFET Capacitances Dependency on VDS and VGS Voltages www.onsemi.com 42 NCP4306 C iss + C gs ) C gd (eq. 4) C rss + C gd (eq. 5) C oss + C ds ) C gd (eq. 6) NCP4306 offers both a 5 V gate clamp and a 10 V gate clamp for those MOSFET that require higher gate to source voltage. The total driving loss can be calculated using the selected gate driver clamp voltage and the input capacitance of the MOSFET: Therefore, the input capacitance of a MOSFET operating in ZVS mode is given by the parallel combination of the gate to source and gate to drain capacitances (i.e. Ciss capacitance for given gate to source voltage). The total gate charge, Qg_total, of most MOSFETs on the market is defined for hard switching conditions. In order to accurately calculate the driving losses in a SR system, it is necessary to determine the gate charge of the MOSFET for operation specifically in a ZVS system. Some manufacturers define this parameter as Qg_ZVS. Unfortunately, most datasheets do not provide this data. If the Ciss (or Qg_ZVS) parameter is not available then it will need to be measured. Please note that the input capacitance is not linear (as shown Figure 85) and it needs to be characterized for a given gate voltage clamp level. P DRV_total + V CC - + RDRV_SINK_EQ f SW (eq. 7) The total driving power loss won't only be dissipated in the IC, but also in external resistances like the external gate resistor (if used) and the MOSFET internal gate resistance (Figure 86). Because NCP4306 features a clamped driver, it's high side portion can be modeled as a regular driver switch with equivalent resistance and a series voltage source. The low side driver switch resistance does not drop immediately at turn-off, thus it is necessary to use an equivalent value (RDRV_SIN_EQK) for calculations. This method simplifies power losses calculations and still provides acceptable accuracy. Internal driver power dissipation can then be calculated using equation 8: VCC RDRV_SOURCE_EQ C g_ZVS Where: VCC is the NCP4306 supply voltage VCLAMP is the driver clamp voltage Cg_ZVS is the gate to source capacitance of the MOSFET in ZVS mode fsw is the switching frequency of the target application Step 2 - Gate drive losses calculation: Gate drive losses are affected by the gate driver clamp voltage. Gate driver clamp voltage selection depends on the type of MOSFET used (threshold voltage versus channel resistance). The total power losses (driving loses and conduction losses) should be considered when selecting the gate driver clamp voltage. Most of today's MOSFETs for SR systems feature low RDS_ON for 5 V VGS voltage. The VCC - VCLAMP V CLAMP DRV RG_EXT SR MOSFET RG_INT GND CG_ZVS Figure 86. Equivalent Schematic of Gate Drive Circuitry www.onsemi.com 43 NCP4306 P DRV_IC + 1 2 C g_ZVS V CLAMP ) 1 2 C g_ZVS V CLAMP 2 2 f SW f SW R DRV_SOURCE_EQ V CLAMP f SW (V CC ) V CLAMP) (eq. 8) Step 4 - IC die temperature arise calculation: The die temperature can be calculated now that the total internal power losses have been determined (driver losses plus internal IC consumption losses). The package thermal resistance is specified in the maximum ratings table for a 35 mm thin copper layer with 1 in2 copper area. The die temperature is calculated as: T DIE + (P DRV_IC ) P CC) Step 3 - IC consumption calculation: In this step, power dissipation related to the internal IC consumption is calculated. This power loss is given by the ICC current and the IC supply voltage. The ICC current depends on switching frequency and also on the selected min tON and tOFF periods because there is current flowing out from the MIN_TON and MIN_TOFF pins. The most accurate method for calculating these losses is to measure the ICC current when CLOAD = 0 nF and the IC is switching at the target frequency with given min_tON and min_tOFF adjust resistors. IC consumption losses can be calculated as: I CC ) C g_ZVS R DRV_SOURCE_EQ ) R G_EXT ) R g_int Where: RDRV_SINK_EQ is the NCP4306 driver low side switch equivalent resistance (1.6 ) RDRV_SOURCE_EQ is the NCP4306 driver high side switch equivalent resistance (7 ) RG_EXT is the external gate resistor (if used) Rg_int is the internal gate resistance of the MOSFET P CC + V CC R DRV_SINK_EQ R DRV_SINK_EQ ) R G_EXT ) R g_int R qJ*A ) T A (eq. 10) Where: PDRV_IC is the IC driver internal power dissipation PCC is the IC control internal power dissipation R J-A is the thermal resistance from junction to ambient TA is the ambient temperature (eq. 9) www.onsemi.com 44 NCP4306 OPN coding table NCP4306 OPN is built from prefix of NCP4306 and postfix that consist of seven letters. Meaning of these letters are shown in table 7. Table 7. OPN CODING TABLE NCP4306xxxxxxx Postfix Index Parameter Postfix 1 Pinout A MIN_TON, MIN_TOFF, LLD, TRIG / DIS - 8 pins 2 3 4 5 DRV dV / dt + exception MIN_TON MIN_TOFF Parameter B MIN_TON, LLD C MIN_TOFF, LLD D MIN_TON, MIN_TOFF E MIN_TOFF, TRIG / DIS F MIN_TON, TRIG / DIS G TRIG / DIS, LLD H None A DRV CLMP = 10 V B DRV CLMP = 5 V A None D Flyback (dV / dt) - 100 V / s H LLC exception - multiplier 4 A 130 ns B 220 ns C 310 ns D 400 ns E 500 ns F 600 ns G 700 ns H 800 ns I 1000 ns J 1200 ns K 1400 ns L 1700 ns M 2000 ns Z External A 0.9 s B 1.0 s C 1.1 s D 1.2 s E 1.4 s F 1.6 s G 1.8 s H 2.0 s I 2.2 s J 2.4 s K 2.6 s L 2.9 s M 3.2 s N 3.5 s O 3.9 s Z External www.onsemi.com 45 NCP4306 Table 7. OPN CODING TABLE (continued) NCP4306xxxxxxx Postfix Index Parameter Postfix 6 LLD A 68 s B 130 s C 280 s D 540 s E 1075 s F Disabled Z External A - 7 Reserved www.onsemi.com 46 Parameter MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSOP-6 CASE 318G-02 ISSUE V 1 SCALE 2:1 D H EE EE 6 E1 1 NOTE 5 5 2 L2 4 GAUGE PLANE E 3 L b SEATING PLANE C DETAIL Z e DIM A A1 b c D E E1 e L L2 M c A 0.05 M DATE 12 JUN 2012 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H. 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE. A1 DETAIL Z MIN 0.90 0.01 0.25 0.10 2.90 2.50 1.30 0.85 0.20 0 MILLIMETERS NOM MAX 1.00 1.10 0.06 0.10 0.38 0.50 0.18 0.26 3.00 3.10 2.75 3.00 1.50 1.70 0.95 1.05 0.40 0.60 0.25 BSC 10 - STYLE 1: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN STYLE 2: PIN 1. EMITTER 2 2. BASE 1 3. COLLECTOR 1 4. EMITTER 1 5. BASE 2 6. COLLECTOR 2 STYLE 3: PIN 1. ENABLE 2. N/C 3. R BOOST 4. Vz 5. V in 6. V out STYLE 4: PIN 1. N/C 2. V in 3. NOT USED 4. GROUND 5. ENABLE 6. LOAD STYLE 5: PIN 1. EMITTER 2 2. BASE 2 3. COLLECTOR 1 4. EMITTER 1 5. BASE 1 6. COLLECTOR 2 STYLE 6: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. EMITTER 5. COLLECTOR 6. COLLECTOR STYLE 7: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. N/C 5. COLLECTOR 6. EMITTER STYLE 8: PIN 1. Vbus 2. D(in) 3. D(in)+ 4. D(out)+ 5. D(out) 6. GND STYLE 9: PIN 1. LOW VOLTAGE GATE 2. DRAIN 3. SOURCE 4. DRAIN 5. DRAIN 6. HIGH VOLTAGE GATE STYLE 10: PIN 1. D(OUT)+ 2. GND 3. D(OUT)- 4. D(IN)- 5. VBUS 6. D(IN)+ STYLE 11: PIN 1. SOURCE 1 2. DRAIN 2 3. DRAIN 2 4. SOURCE 2 5. GATE 1 6. DRAIN 1/GATE 2 STYLE 12: PIN 1. I/O 2. GROUND 3. I/O 4. I/O 5. VCC 6. I/O STYLE 13: PIN 1. GATE 1 2. SOURCE 2 3. GATE 2 4. DRAIN 2 5. SOURCE 1 6. DRAIN 1 STYLE 14: PIN 1. ANODE 2. SOURCE 3. GATE 4. CATHODE/DRAIN 5. CATHODE/DRAIN 6. CATHODE/DRAIN STYLE 15: PIN 1. ANODE 2. SOURCE 3. GATE 4. DRAIN 5. N/C 6. CATHODE STYLE 16: PIN 1. ANODE/CATHODE 2. BASE 3. EMITTER 4. COLLECTOR 5. ANODE 6. CATHODE STYLE 17: PIN 1. EMITTER 2. BASE 3. ANODE/CATHODE 4. ANODE 5. CATHODE 6. COLLECTOR GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 6X 0.60 XXXAYWG G 1 6X 3.20 XXX A Y W G 0.95 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98ASB14888C TSOP-6 1 IC 0.95 XXX MG G = Specific Device Code =Assembly Location = Year = Work Week = Pb-Free Package STANDARD XXX = Specific Device Code M = Date Code G = Pb-Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G" or microdot " G", may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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(c) Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN8, 4x4 CASE 488AF-01 ISSUE C 1 SCALE 2:1 A B D PIN ONE REFERENCE 2X 0.15 C 2X 0.15 C 0.10 C 8X EE EE EE 0.08 C DETAIL A E OPTIONAL CONSTRUCTIONS EXPOSED Cu DETAIL B CCCC (A3) A A1 C D2 CCCC e 8X SEATING PLANE EEE EEE CCC A3 A1 ALTERNATE CONSTRUCTIONS 8X MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.25 0.35 4.00 BSC 1.91 2.21 4.00 BSC 2.09 2.39 0.80 BSC 0.20 --- 0.30 0.50 --- 0.15 XXXXXX XXXXXX ALYWG G E2 5 DIM A A1 A3 b D D2 E E2 e K L L1 GENERIC MARKING DIAGRAM* L 4 CCCC 8 MOLD CMPD DETAIL B SIDE VIEW K CCC CCC EEE TOP VIEW 1 NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. DETAILS A AND B SHOW OPTIONAL CONSTRUCTIONS FOR TERMINALS. L L L1 NOTE 4 DETAIL A DATE 15 JAN 2009 b XXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) 0.10 C A B 0.05 C NOTE 3 BOTTOM VIEW SOLDERING FOOTPRINT* 2.21 8X *This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G" or microdot " G", may or may not be present. 0.63 4.30 2.39 PACKAGE OUTLINE 8X 0.35 0.80 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON15232D DFN8, 4X4, 0.8P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. (c) Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN8, 2.0x2.2, 0.5P CASE 506BP-01 ISSUE A 8 DATE 13 JAN 2010 1 SCALE 4:1 A B D PIN ONE REFERENCE 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L L1 EEE EEE EEE DETAIL A E ALTERNATE TERMINAL CONSTRUCTIONS 0.10 C 2X 0.10 C CCC CCC EEE EXPOSED Cu TOP VIEW (A3) DETAIL B 0.05 C DIM A A1 A3 b D D2 E E2 e K L L1 A MOLD CMPD DETAIL B 9X ALTERNATE CONSTRUCTIONS 0.05 C NOTE 4 SIDE VIEW A1 C SEATING PLANE D2 DETAIL A L 1 8 K 5 e 1.43 1.05 0.20 0.25 --- 1 4 E2 8X 0.20 0.10 C A B 8X b 0.10 C A B e/2 BOTTOM VIEW 0.05 C MILLIMETERS TYP MAX --1.00 --0.05 0.20 REF --0.30 2.00 BSC --1.53 2.20 BSC --1.25 0.50 BSC 0.22 0.30 --0.35 --0.15 GENERIC MARKING DIAGRAM* 0.10 C A B 8X MIN 0.80 0.00 NOTE 3 XXMG G XX = Specific Device Code M = Date Code G = Pb-Free Device *This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G" or microdot " G", may or may not be present. SOLDERING FOOTPRINT* 1.63 CC C CC CC CCCCCCC 1.15 CCCCCCC CCCCCCC CCCCCCC 1 0.50 PITCH 8X 0.45 2.50 8X 0.28 DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON38697E DFN8, 2.0X2.2, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. (c) Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC-8 NB CASE 751-07 ISSUE AK 8 1 SCALE 1:1 -X- DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. A 8 5 S B 0.25 (0.010) M Y M 1 4 -Y- K G C N X 45 _ SEATING PLANE -Z- 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb-Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb-Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb-Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G" or microdot "G", may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC-8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. (c) Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC-8 NB CASE 751-07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N-SOURCE 2. N-GATE 3. P-SOURCE 4. P-GATE 5. P-DRAIN 6. P-DRAIN 7. N-DRAIN 8. N-DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC-8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. (c) Semiconductor Components Industries, LLC, 2019 www.onsemi.com ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. 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