70V34S25PFG8 - Integrated Device Technology

JULY 2002

DSC-5624/3

PRELIMINARY

IDT70V35/34S/L

HIGH-SPEED 3.3V

8/4K x 18 DUAL-PORT

STATIC RAM

◆◆

◆IDT70V35/34 easily expands data bus width to 36 bits or

more using the Master/Slave select when cascading more

than one device

◆◆

◆M/S = VIH for BUSY output flag on Master

M/S = VIL for BUSY input on Slave

◆◆

◆BUSY and Interrupt Flag

◆◆

◆On-chip port arbitration logic

◆◆

◆Full on-chip hardware support of semaphore signaling

between ports

◆◆

◆Fully asynchronous operation from either port

◆◆

◆LVTTL-compatible, single 3.3V (±0.3V) power supply

◆◆

◆Available in a 100-pin TQFP

◆◆

◆Industrial temperature range (-40°C to +85°C) is available

for selected speeds

Functional Block Diagram

NOTES:

1. A12 is a NC for IDT70V34.

2. (MASTER): BUSY is output; (SLAVE): BUSY is input.

3. BUSY outputs and INT outputs are non-tri-stated push-pull.

Features

◆◆

◆True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

◆◆

◆High-speed access

– Commercial: 15/20/25ns (max.)

– Industrial: 20ns

◆◆

◆Low-power operation

– IDT70V35/34S

Active: 430mW (typ.)

Standby: 3.3mW (typ.)

– IDT70V35/34L

Active: 415mW (typ.)

Standby: 660

W (typ.)

◆◆

◆Separate upper-byte and lower-byte control for multiplexed

bus compatibility

I/O

Control

Address

Decoder MEMORY

ARRAY

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

Address

Decoder

I/O

Control

R/WL

BUSYL

A12L(1)

A0L

5624 drw 01

UBL

LBL

CEL

OEL

I/O9L-I/O17L

I/O0L-I/O8L

CEL

OEL

R/WL

SEML

INTLM/S

R/WR

BUSYR

UBR

LBR

CER

OER

I/O9R-I/O17R

I/O0R-I/O8R

A12R(1)

A0R

R/WR

SEMR

INTR

CER

OER

(3)

(2,3) (2,3)

(3)

13 13

6.42

IDT70V35/34S/L PRELIMINARY

High-Speed 8/4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Description

The IDT70V35/34 is a high-speed 8/4K x 18 Dual-Port Static RAM.

The IDT70V35/34 is designed to be used as a stand-alone Dual-Port RAM

or as a combination MASTER/SLAVE Dual-Port RAM for 36-bit or wider

memory system applications results in full-speed, error-free operation

without the need for additional discrete logic.

This device provides two independent ports with separate control,

address, and I/O pins that permit independent, asynchronous access for

reads or writes to any location in memory. An automatic power down

feature controlled by CE permits the on-chip circuitry of each port to enter

a very low standby power mode.

Fabricated using IDT’s CMOS high-performance technology, these

devices typically operate on only 430mW of power.

The IDT70V35/34 is packaged in a plastic 100-pin Thin Quad

Flatpack.

Pin Configurations(1,2,3,4)

NOTES:

1. A12 is a NC for IDT70V34.

2. All VCC pins must be connected to power supply.

3. All GND pins must be connected to ground.

4. PN100-1 package body is approximately 14mm x 14mm x 1.4mm.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part marking.

Index

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

IDT70V35/34PF

PN100-1

(5)

100-Pin TQFP

Top View

(6)

N/C

I/O

17L

I/O

11L

I/O

12L

I/O

13L

I/O

14L

GND

I/O

15L

I/O

16L

GND

I/O

17R

N/C

5624 drw 02

N/C

INT

GND

M/S

BUSY

INT

N/C

BUSY

I/O

10L

I/O

GND

I/O

R/W

SEM

11L

10L

I/O

10R

I/O

11R

I/O

12R

I/O

13R

I/O

14R

I/O

15R

GND

I/O

16R

R/W

SEM

GND

11R

10R

12L

(1)

12R

(1)

07/02/02

6.42

IDT70V35/34S/L PRELIMINARY

High-Speed 8/4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Truth Table I: Non-Contention Read/Write Control

Truth Table II: Semaphore Read/Write Control(1)

NOTE:

1. A0L — A12L ≠ A0R — A12R

NOTE:

1. There are eight semaphore flags written to via I/O0 and read from all of the I/O's (I/O0-I/O17). These eight semaphores are addressed by A0-A2.

Inputs(1) Outputs

Mode

CE R/WOE UB LB SEM I/O9-17 I/O0-8

H X X X X H High-Z High-Z Des elec te d: P owe r Down

X X X H H H High-Z Hig h-Z Both By te s Des elec te d

LLXLHHDATA

IN Hig h-Z Write to Up p e r By te Only

L L X H L H High-Z DATAIN W ri te to Lo w e r B yte O nl y

LLXLLHDATA

IN DATAIN Wri te to B o th By te s

LHLLHHDATA

OUT Hig h-Z Re ad Upp e r By te Onl y

LHLHLHHigh-ZDATA

OUT Read Lo we r By te Onl y

LHLLLHDATA

OUT DATAOUT Re ad Both Byte s

X X H X X X High-Z High-Z Outputs Disabled

5 624 t bl 02

Inputs Outputs

Mode

CE R/WOE UB LB SEM I/O9-17 I/O0-8

HHLXXLDATA

OUT DATAOUT Read Data in Semaphore Flag

XHLHHLDATA

OUT DATAOUT Read Data in Semaphore Flag

H↑XXXLDATA

IN DATAIN Wri te I/ O0 into Semaphore Flag

X↑XHHLDATA

IN DATAIN Wri te I/ O0 into Semaphore Flag

LXXLXL ____ ____ No t A llo we d

LXXXLL ____ ____ No t A llo we d

5 624 t bl 03

Pin Names

Left P ort Right Port Names

CELCERChip Enable

R/WLR/WRRe ad /Write Enab le

OELOEROutput Enab le

A0L - A 12L(1) A0R - A 12R(1) Address

I/O0L - I/ O17L I/O0R - I/O17R Data Inp ut/Outp ut

SEMLSEMRSemaphore Enable

UBLUBRUpper B y te Sel ec t

LBLLB

RLower Byte Se lect

INTLINTRInte r rupt Flag

BUSYLBUSYRBusy F lag

M/SMaster or Slave Select

VCC Po we r (3.3V)

GND Gro und (0V)

5624 t b l 01

1. A12 is a NC for IDT70V34.

6.42

IDT70V35/34S/L PRELIMINARY

High-Speed 8/4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Absolute Maximum Ratings(1) Maximum Operating Temperature

and Supply Voltage(1)

Capacitance(1) (TA = +25°C, f = 1.0MHz)

Recommended DC Operating

Conditions

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in

the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. VTERM must not exceed Vcc + 0.3V.

NOTES:

1. This parameter is determined by device characterization but is not production

tested.

2. 3dV references the interpolated capacitance when the input and output

signals switch from 0V to 3V or from 3V to 0V.

NOTE:

1. This is the parameter TA. This is the "instant on" case temperature.

NOTES:

1. VIL > -1.5V for pulse width less than 10ns.

2. VTERM must not exceed Vcc + 0.3V.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)

NOTE:

1. At Vcc < 2.0V leakages are undefined.

Symbol Rating Commercial

& I nd ustr ial Unit

VTERM(2) Terminal Vo ltage

with Re spe ct

to GND

-0.5 to +4.6 V

TBIAS Temperature

Under Bias -55 to + 125 oC

TSTG Storage

Tempe rature -65 to + 150 oC

IOUT DC Output

Current 50 mA

5624 tbl 04

Grade Ambient

Temperature GND Vcc

Commercial 0OC to +70OC0V3.3V

+ 0.3V

Industrial -40OC to +85OC0V 3.3V

+ 0.3V

5624 tbl 05

Symbol Parameter Min. Typ. Max. Unit

VCC Sup pl y Vo ltag e 3.0 3.3 3.6 V

GND Ground 0 0 0 V

VIH Inp ut Hi gh Vo ltag e 2.0 ____ VCC+0.3(2) V

VIL Inp ut Low Vol tag e -0.3(1) ____ 0.8 V

5624 tbl 06

Symbol Parameter Conditions(2) Max. Unit

CIN Inp ut Cap ac itance VIN = 3d V 9 pF

COUT Outp ut Cap ac itanc e V OUT = 3dV 10 pF

5624 tbl 07

Symbol Parameter Test Conditions

70V35/34S 70V35/34L

UnitMin. Max. Min. Max.

|ILI| Input Leakage Curre nt(1) VCC = 3.6V, VIN = 0V to VCC ___ 10 ___ 5µA

|ILO| Output Le ak ag e Curre ntt(1) CE = VIH, VOUT = 0V to V CC ___ 10 ___ 5µA

VOL Output Low Vo ltage IOL = +4mA ___ 0.4 ___ 0.4 V

VOH Outp ut Hig h Voltage IOH = -4mA 2.4 ___ 2.4 ___ V

5624 t bl 0 8

6.42

IDT70V35/34S/L PRELIMINARY

High-Speed 8/4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range(1) (VCC = 3.3V ± 0.3V)

NOTES:

1. 'X' in part number indicates power rating (S or L)

2. VCC = 3.3V, TA = +25°C, and are not production tested. Icc dc = 115mA (typ.)

3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t RC, and using “AC Test Conditions” of input levels of GND

to 3V.

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

70V35/34X15

Com'l Only 70V35/34X20

Com'l

& Ind

70V35/34X25

Com'l Only

Sym bol Param eter Test Condition Version Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Unit

ICC Dy nam ic O p er ating

Current

(Both Po rts Active)

CE = VIL, Outp uts Disabled

SEM = VIH

f = fMAX(3)

COM'L S

L150

140 215

185 140

130 200

175 130

125 190

165 mA

IND S

L____

____

____ 140

130 225

195 ____

____

ISB1 Standby Current

(Bo th Po rts - TTL

Lev el Inp uts)

CER and CEL = VIH

SEMR = SEML = VIH

f = fMAX(3)

COM'L S

L25

20 35

30 20

15 30

25 16

13 30

25 mA

MIL &

IND S

L____

____

____ 20

15 45

40 ____

____

ISB2 Standby Current

(One Po rt - TTL

Lev el Inp uts)

CE"A" = VIL and CE"B" = VIH(5)

Active Po rt Outp uts Disable d,

f=fMAX(3)

SEMR = SEML = VIH

COM'L S

L85

80 120

110 80

75 110

100 75

72 110

95 mA

MIL &

IND S

L____

____

____ 80

75 130

115 ____

____

ISB3 Full Standb y Curre nt

(Bo th Po rts -

CM OS Le ve l Inp uts )

Both Ports CEL and

CER > VCC - 0.2V,

VIN > VCC - 0.2V or

VIN < 0.2V, f = 0(4)

SEMR = SEML > VCC-0.2V

COM'L S

L1.0

0.2 5

2.5 1.0

0.2 5

2.5 1.0

0.2 5

2.5 mA

MIL &

IND S

L____

____

____ 1.0

0.2 15

5____

____

ISB4 Full Standb y Curre nt

(One Po rt -

CM OS Le ve l Inp uts )

CE"A" < 0.2V and

CE"B" > VCC - 0.2V(5)

SEMR = SEML > VCC-0.2V

VIN > VCC - 0.2V o r VIN < 0.2V

Active Po rt Outp uts Disable d,

f = fMAX(3)

COM'L S

L85

80 125

105 80

75 115

100 75

70 105

90 mA

MIL &

IND S

L____

____

____ 80

75 130

115 ____

____

5624 tbl 09

AC Test Conditions

Figure 1. AC Output Test Load

Input Pulse Le vels

Inp ut Ris e/ Fal l Time s

Inp ut Timing Re fere nce Le v els

Outp ut Refe re nce Le v e ls

Output Load

GND to 3.0V

3ns Max .

1.5V

Fi g ure s 1 and 2

5624 tbl 10

Figure 2. Output Test

Load

(For tLZ, tHZ, tWZ, tOW)

*Including scope and jig.

5624 drw 03

590Ω

30pF

435Ω

3.3V

DATAOUT

BUSY

INT

590Ω

5pF*

435Ω

3.3V

DATAOUT

Timing of Power-Up Power-Down

5624 drw 04

tPU

ICC

ISB

tPD

50% 50%

6.42

IDT70V35/34S/L PRELIMINARY

High-Speed 8/4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Waveform of Read Cycles(5)

NOTES:

1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.

2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.

3. tBDD delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations BUSY has no

relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

tRC

R/W

ADDR

tAA

UB,LB

5624 drw 05

(4)

tACE(4)

tAOE(4)

tABE(4)

(1)

tLZ tOH

(2)

tHZ

(3,4)

tBDD

DATAOUT

BUSYOUT

VALID DATA(4)

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(4)

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL.

4. 'X' in part number indicates power rating (S or L).

70V35/34X15

Com'l Only 70V35/34X20

Com'l

& Ind

70V35/34X25

Com'l Only

UnitSymbol Parameter Min.Max.Min.Max.Min.Max.

READ CYCLE

tRC Re ad Cyc le Time 15 ____ 20 ____ 25 ____ ns

tAA Address Access Time ____ 15 ____ 20 ____ 25 ns

tACE Chip Enable Acce ss Time(3) ____ 15 ____ 20 ____ 25 ns

tABE Byte Enable Access Time(3) ____ 15 ____ 20 ____ 25 ns

tAOE Output Enable Access Time(3) ____ 10 ____ 12 ____ 13 ns

tOH Outp ut Ho ld fro m A dd re ss Chang e 3 ____ 3____ 3____ ns

tLZ Output Lo w-Z Time(1,2) 3____ 3____ 3____ ns

tHZ Output Hig h-Z Time (1,2) ____ 10 ____ 12 ____ 15 ns

tPU Chip Enab le to Po we r Up Time (1,2) 0____ 0____ 0____ ns

tPD Chip Dis ab le to P owe r Down Ti me (1,2) ____ 15 ____ 20 ____ 25 ns

tSOP Semaphore Flag Upd ate Pulse (OE or SEM)10

____ 10 ____ 10 ____ ns

tSAA Semaphore Address Access(3) ____ 15 ____ 20 ____ 25 ns

5624 tbl 11

6.42

IDT70V35/34S/L PRELIMINARY

High-Speed 8/4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage (5)

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access SRAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. Either condition must be valid for the entire

tEW time.

4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and t OW values will vary over voltage and

temperature, the actual tDH will always be smaller than the actual tOW.

5. 'X' in part number indicates power rating (S or L).

Symbol Parameter

70V35/34X15

Com'l Only 70V35/34X20

Com'l

& Ind

70V35/34X25

Com'l Only

UnitMin. Max. Min. Max. Min. Max.

WRITE CYCLE

tWC Write Cycle Time 15 ____ 20 ____ 25 ____ ns

tEW Chi p Enable to End -of-Write(3) 12 ____ 15 ____ 20 ____ ns

tAW Address Valid to End-of-Write 12 ____ 15 ____ 20 ____ ns

tAS Ad dress Set-up Time (3) 0____ 0____ 0____ ns

tWP Wri te Pulse Width 12 ____ 15 ____ 20 ____ ns

tWR Write Re covery Time 0 ____ 0____ 0____ ns

tDW Da ta Val id to E nd -o f-W rite 10 ____ 15 ____ 15 ____ ns

tHZ Outp ut Hig h-Z Ti me (1,2) ____ 10 ____ 12 ____ 15 ns

tDH Da ta Hol d Ti me (4) 0____ 0____ 0____ ns

tWZ Write Enable to Output in High-Z(1,2) ____ 10 ____ 12 ____ 15 ns

tOW Output Active from End-of-Write (1,2,4) 0____ 0____ 0____ ns

tSWRD SEM Fl ag Write to Re ad Time 5____ 5____ 5____ ns

tSPS SEM Fl ag Co ntentio n Wi ndo w 5____ 5____ 5____ ns

5624 tbl 12

6.42

IDT70V35/34S/L PRELIMINARY

High-Speed 8/4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)

NOTES:

1. R/W or CE or UB & LB must be HIGH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a LOW UB or LB and a LOW CE and a LOW R/W for memory array writing cycle.

3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end-of-write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition the outputs remain in the HIGH-impedance state.

6. Timing depends on which enable signal is asserted last, CE, R/W, or UB or LB.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with Output Test Load

(Figure 2).

8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be

placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as

the specified tWP.

9. To access SRAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access Semaphore, CE = VIH or UB and LB = VIH, and SEM = V IL. tEW must be met for either condition.

Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)

R/W

tWC

tHZ

tAW

tWR

tAS tWP

DATAOUT

(2)

tWZ

tDW tDH

tOW

ADDRESS

DATAIN

(6)

(4) (4)

(7)

CE or SEM

5624 drw 08

(9)

CE or SEM (9)

(7)

(3)

5624 drw 07

tWC

tAS tWR

tDW tDH

ADDRESS

DATAIN

R/W

tAW

tEW

UB or LB

(3)

(2)

(6)

CE or SEM(9)

(9)

6.42

IDT70V35/34S/L PRELIMINARY

High-Speed 8/4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side(1)

Timing Waveform of Semaphore Write Contention(1,3,4)

NOTES:

1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH.

2. All timing is the same for left and right port. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.

4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag.

NOTES:

1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle).

2. “DATAOUT VALID” represents all I/O's (I/O0-I/O17) equal to the semaphore value.

SEM

5624 drw 08

SOP

I/O

VALID ADDRESS

SAA

R/W

ACE

VALID ADDRESS

DATA

VALID DATA

OUT

SWRD

AOE

Read CycleWrite Cycle

-A

VALID

(2)

SEM"A"

5624 drw 09

tSPS

MATCH

R/W"A"

MATCH

A0"A"-A2"A"

SIDE "A"

(2)

SEM"B"

R/W"B"

A0"B"-A2"B"

SIDE(2) "B"

6.42

IDT70V35/34S/L PRELIMINARY

High-Speed 8/4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

5624 drw 10

tAPS

ADDR"A"

tWC

DATAOUT "B"

MATCH

tWP

R/W"A"

DATAIN "A"

ADDR"B"

tDH

VALID

(1)

MATCH

BUSY"B"

tBDA

VALID

tBDD

tDDD(3)

tWDD

tBAA

tDW

Timing Waveform of Write Port-to-Port Read and BUSY(2,4,5) (M/S = VIH)

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).

2. CEL = CER = VIL.

3. OE = VIL for the reading port.

4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY“A” = VIH and BUSY“B” input is shown above.

5. All timing is the same for both left and right ports. Port “A” may be either the left or right port. Port “B ” is the port opposite from port “A”.

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(6)

NOTES:

1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "TIMING WAVEFORM OF WRITE PORT-TO-PORT READ AND

BUSY (M/S = VIH)".

2. To ensure that the earlier of the two ports wins.

3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited during contention.

5. To ensure that a write cycle is completed after contention.

6. 'X' in part number indicates power rating (S or L).

70V35/34X15

Com'l Ony 70V35/34X20

Com'l

& Ind

70V35/34X25

Com'l Only

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

BUSY TIMING (M/S = VIH)

tBAA BUSY Access Time fro m Addre ss Match ____ 15 ____ 20 ____ 20 ns

tBDA BUSY Di s ab le Tim e from Add re ss No t M atc hed ____ 15 ____ 20 ____ 20 ns

tBAC BUSY Access Time from Chip Enable LOW ____ 15 ____ 20 ____ 20 ns

tBDC BUSY Dis able Time from Chip Enable HIGH ____ 15 ____ 17 ____ 17 ns

tAPS A rb i trati o n P ri o ri ty Set-up Ti me(2) 5____ 5____ 5____ ns

tBDD BUSY Di s ab l e to Val id Data (3) ____ 18 ____ 30 ____ 30 ns

tWH Write Hold After BUSY(5) 12 ____ 15 ____ 17 ____ ns

BUSY TIMING (M/S = VIL)

tWB BUSY Input to Wri te (4) 0____ 0____ 0____ ns

tWH Write Hold After BUSY(5) 12 ____ 15 ____ 17 ____ ns

P ORT -T O-P ORT DE LAY T IMING

tWDD Write P ulse to Data Delay(1) ____ 30 ____ 45 ____ 50 ns

tDDD Write Data Valid to Re ad Data Delay (1) ____ 25 ____ 35 ____ 35 ns

5624 tbl 13

6.42

IDT70V35/34S/L PRELIMINARY

High-Speed 8/4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Write with BUSY

Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)

Waveform of BUSY Arbitration Cycle Controlled by Address Match

Timing(1) (M/S = VIH)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

5624 drw 11

R/W"A"

BUSY"B"

tWP

tWB

R/W"B"

tWH

(2)

(3)

(1)

NOTES:

1. tWH must be met for both master BUSY input (slave) and output (master).

2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.

3. tWB is only for the slave version.

5624 drw 12

ADDR"A"

and "B" ADDRESSES MATCH

CE"A"

CE"B"

BUSY"B"

tAPS

tBAC tBDC

(2)

5624 drw 13

ADDR"A" ADDRESS "N"

ADDR"B"

BUSY"B"

tAPS

tBAA tBDA

(2)

MATCHING ADDRESS "N"

6.42

IDT70V35/34S/L PRELIMINARY

High-Speed 8/4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Waveform of Interrupt Timing(1)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. See Interrupt Flag Truth Table III.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

5624 drw 14

ADDR"A" INTERRUPT SET ADDRESS

CE"A"

R/W"A"

tAS

tWC

tWR

(3) (4)

tINS(3)

INT"B"

(2)

5624 drw 15

ADDR"B" INTERRUPT CLEAR ADDRESS

CE"B"

OE"B"

tAS

tRC

(3)

tINR(3)

INT"B"

(2)

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(1)

NOTES:

1. 'X' in part number indicates power rating (S or L).

70V35/34X15

Com'l Only 70V35/34X20

Com'l

& Ind

70V35/34X25

Com'l Only

Symbol Parameter Min.Max.Min.Max.Min.Max.Unit

INTE RRUP T TIM ING

tAS Address Set-up Time 0 ____ 0____ 0____ ns

tWR Write Re covery Time 0 ____ 0____ 0____ ns

tINS Inte rrup t Se t Ti me ____ 15 ____ 20 ____ 20 ns

tINR Inte rrup t Res et Tim e ____ 15 ____ 20 ____ 20 ns

5624 t bl 1 4

6.42

IDT70V35/34S/L PRELIMINARY

High-Speed 8/4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Truth Table III  Interrupt Flag(1)

NOTES:

1. Assumes BUSYL = BUSYR = VIH.

2. If BUSYL = VIL, then no change.

3. If BUSYR = VIL, then no change.

4. A12 is a NC for IDT70V34, therefore Interrupt Addresses are FFF and FFE.

Left Port Right Port

FunctionR/WLCE

LOELA12L-A0L(4) INTLR/WRCE

ROERA12R-A0R(4) INTR

LLX1FFF

(4) XXXX X L

(2) S et Rig ht INTR Flag

XXXXXXLL1FFF

(4) H(3) Re se t Rig ht INTR Flag

XXX X L

(3) LLX1FFE

(4) XSet Left INTL Flag

XLL1FFE

(4) H(2) X X X X X Re s e t L e ft INTL Flag

5 624 tbl 15

Truth Table V  Example of Semaphore Procurement Sequence(1,2,3)

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V35/34.

2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O17). These eight semaphores are addressed by A0-A2.

3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Tables.

Functions D0 - D17 Left D0 - D17 Right Status

No Action 1 1 Semaphore free

Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token

Rig ht P ort Write s " 0" to Se map hore 0 1 No chang e . Rig ht sid e has no write acc e ss to se map hore

Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token

Le ft Po rt Writes "0" to Se map ho re 1 0 No chang e . Le ft p o rt has no wri te acc es s to se map hore

Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token

Left Port Writes "1" to Semaphore 1 1 Semaphore free

Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token

Right Port Writes "1" to Semaphore 1 1 Semaphore free

Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token

Left Port Writes "1" to Semaphore 1 1 Semaphore free

5624 tbl 17

Truth Table IV  Address BUSY

Arbitration

NOTES:

1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V35/

34 are push pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.

2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. VIH if the inputs to the opposite port became stable after the address

and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored

when BUSYR outputs are driving LOW regardless of actual logic level on the pin.

4. A12 is a NC for IDT70V34. Address comparison will be for A0 - A11.

Inputs Outputs

Function

CELCERA12L-A0L(4)

A12R-A0R BUSYL(1) BUSYR(1)

XXNO MATCHHHNormal

HXMATCHHHNormal

XHMATCHHHNormal

LL MATCH Note

(2) Note(2) Write Inhibit(3)

5624 tbl 16

6.42

IDT70V35/34S/L PRELIMINARY

High-Speed 8/4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V35/34 SRAMs.

programmed by tying the BUSY pins HIGH. If desired, unintended write

operations can be prevented to a port by tying the BUSY pin for that port

LOW.

The BUSY outputs on the IDT 70V35/34 SRAM in master mode, are

push-pull type outputs and do not require pull up resistors to operate. If

these SRAMs are being expanded in depth, then the BUSY indication for

the resulting array requires the use of an external AND gate.

Width Expansion with Busy Logic

Master/Slave Arrays

When expanding an IDT70V35/34 SRAM array in width while using

BUSY logic, one master part is used to decide which side of the SRAM

array will receive a BUSY indication, and to output that indication. Any

number of slaves to be addressed in the same address range as the

master, use the BUSY signal as a write inhibit signal. Thus on the

IDT70V35/34 SRAM the BUSY pin is an output if the part is used as a master

(M/S pin = VIH), and the BUSY pin is an input if the part used as a slave

(M/S pin = VIL) as shown in Figure 3.

If two or more master parts were used when expanding in width, a

split decision could result with one master indicating BUSY on one side

of the array and another master indicating BUSY on one other side of

the array. This would inhibit the write operations from one port for part

of a word and inhibit the write operations from the other port for the

other part of the word.

The BUSY arbitration, on a master, is based on the chip enable and

address signals only. It ignores whether an access is a read or write.

In a master/slave array, both address and chip enable must be valid

long enough for a BUSY flag to be output from the master before the

actual write pulse can be initiated with either the R/W signal or the byte

enables. Failure to observe this timing can result in a glitched internal

write inhibit signal and corrupted data in the slave.

Semaphores

The IDT70V35/34 is an extremely fast Dual-Port 8/4K x 18 CMOS

Static RAM with an additional 8 address locations dedicated to binary

semaphore flags. These flags allow either processor on the left or right

side of the Dual-Port SRAM to claim a privilege over the other

processor for functions defined by the system designer’s software. As

an example, the semaphore can be used by one processor to inhibit the

Functional Description

The IDT70V35/34 provides two ports with separate control, address

and I/O pins that permit independent access for reads or writes to any

location in memory. The IDT70V35/34 has an automatic power down

feature controlled by CE. The CE controls on-chip power down circuitry

that permits the respective port to go into a standby mode when not selected

(CE HIGH). When a port is enabled, access to the entire memory array

is permitted.

Interrupts

If the user chooses the interrupt function, a memory location (mail

box or message center) is assigned to each port. The left port interrupt

flag (INTL) is asserted when the right port writes to memory location

1FFE (HEX), where a write is defined as the CER = R/WR = VIL per

Truth Table III. The left port clears the interrupt by an address location

1FFE access when CEL = OEL = VIL, R/WL is a "don't care". Likewise,

the right port interrupt flag (INTR) is set when the left port writes to

memory location 1FFF (HEX) (FFF for IDT70V34) and to clear the

interrupt flag (INTR), the right port must read the memory location 1FFF.

The message (16 bits) at 1FFE or 1FFF (FFE or FFF for IDT70V34) is

user-defined, since it is an addressable SRAM location. If the interrupt

function is not used, address locations 1FFE and 1FFF (FFE and FFF

for IDT70V34) are not used as mail boxes, but as part of the random access

memory. Refer to Truth Table III for the interrupt operation.

Busy Logic

Busy Logic provides a hardware indication that both ports of the

SRAM have accessed the same location at the same time. It also

allows one of the two accesses to proceed and signals the other side

that the SRAM is “busy”. The BUSY pin can then be used to stall the

access until the operation on the other side is completed. If a write

operation has been attempted from the side that receives a BUSY

indication, the write signal is gated internally to prevent the write from

proceeding.

The use of BUSY logic is not required or desirable for all applica-

tions. In some cases it may be useful to logically OR the BUSY outputs

together and use any BUSY indication as an interrupt source to flag the

event of an illegal or illogical operation. If the write inhibit function of

BUSY logic is not desirable, the BUSY logic can be disabled by placing

the part in slave mode with the M/S pin. Once in slave mode the BUSY

pin operates solely as a write inhibit input pin. Normal operation can be

5624 drw 16

MASTER

Dual Port

SRAM

BUSYLBUSYR

MASTER

Dual Port

SRAM

BUSYLBUSYR

SLAVE

Dual Port

SRAM

BUSYLBUSYR

SLAVE

Dual Port

SRAM

BUSYLBUSYR

DECODER

6.42

IDT70V35/34S/L PRELIMINARY

High-Speed 8/4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

other from accessing a portion of the Dual-Port SRAM or any other shared

resource.

The Dual-Port SRAM features a fast access time, and both ports are

completely independent of each other. This means that the activity on the

left port in no way slows the access time of the right port. Both ports are

identical in function to standard CMOS Static RAM and can be accessed

at the same time with the only possible conflict arising from the simultaneous

writing of, or a simultaneous READ/WRITE of, a non-semaphore location.

Semaphores are protected against such ambiguous situations and may

be used by the system program to avoid any conflicts in the non-

semaphore portion of the Dual-Port SRAM. These devices have an

automatic power-down feature controlled by CE, the Dual-Port SRAM

enable, and SEM, the semaphore enable. The CE and SEM pins control

on-chip power down circuitry that permits the respective port to go into

standby mode when not selected. This is the condition which is shown in

Truth Table I where CE and SEM are both HIGH.

Systems which can best use the IDT70V35/34 contain multiple

processors or controllers and are typically very high-speed systems

which are software controlled or software intensive. These systems

can benefit from a performance increase offered by the IDT70V35/34's

hardware semaphores, which provide a lockout mechanism without

requiring complex programming.

Software handshaking between processors offers the maximum in

system flexibility by permitting shared resources to be allocated in

varying configurations. The IDT70V35/34 does not use its semaphore

flags to control any resources through hardware, thus allowing the system

designer total flexibility in system architecture.

An advantage of using semaphores rather than the more common

methods of hardware arbitration is that wait states are never incurred

in either processor. This can prove to be a major advantage in very

high-speed systems.

How the Semaphore Flags Work

The semaphore logic is a set of eight latches which are indepen-

dent of the Dual-Port SRAM. These latches can be used to pass a flag,

or token, from one port to the other to indicate that a shared resource

is in use. The semaphores provide a hardware assist for a use

assignment method called “Token Passing Allocation.” In this method,

the state of a semaphore latch is used as a token indicating that shared

resource is in use. If the left processor wants to use this resource, it

requests the token by setting the latch. This processor then verifies its

success in setting the latch by reading it. If it was successful, it

proceeds to assume control over the shared resource. If it was not

successful in setting the latch, it determines that the right side

processor has set the latch first, has the token and is using the shared

resource. The left processor can then either repeatedly request that

semaphore’s status or remove its request for that semaphore to

perform another task and occasionally attempt again to gain control of

the token via the set and test sequence. Once the right side has

relinquished the token, the left side should succeed in gaining control.

The semaphore flags are active LOW. A token is requested by

writing a zero into a semaphore latch and is released when the same

side writes a one to that latch.

The eight semaphore flags reside within the IDT70V35/34 in a

separate memory space from the Dual-Port SRAM. This address space

is accessed by placing a LOW input on the SEM pin (which acts as a chip

select for the semaphore flags) and using the other control pins (Address,

OE, and R/W) as they would be used in accessing a standard static RAM.

Each of the flags has a unique address which can be accessed by either

side through address pins A0 – A2. When accessing the semaphores, none

of the other address pins has any effect.

When writing to a semaphore, only data pin D0 is used. If a LOW level

is written into an unused semaphore location, that flag will be set to a zero

on that side and a one on the other side (see Truth Table V). That

semaphore can now only be modified by the side showing the zero. When

a one is written into the same location from the same side, the flag will be

set to a one for both sides (unless a semaphore request from the other side

is pending) and then can be written to by both sides. The fact that the side

which is able to write a zero into a semaphore subsequently locks out writes

from the other side is what makes semaphore flags useful in interprocessor

communications. (A thorough discussion on the use of this feature follows

shortly.) A zero written into the same location from the other side will be

stored in the semaphore request latch for that side until the semaphore is

freed by the first side.

When a semaphore flag is read, its value is spread into all data bits so

that a flag that is a one reads as a one in all data bits and a flag containing

a zero reads as all zeros. The read value is latched into one side’s output

signals go active. This serves to disallow the semaphore from changing

state in the middle of a read cycle due to a write cycle from the other side.

Because of this latch, a repeated read of a semaphore in a test loop must

cause either signal (SEM or OE) to go inactive or the output will never

change.

A sequence WRITE/READ must be used by the semaphore in

order to guarantee that no system level contention will occur. A

processor requests access to shared resources by attempting to write

a zero into a semaphore location. If the semaphore is already in use,

the semaphore request latch will contain a zero, yet the semaphore

flag will appear as one, a fact which the processor will verify by the

subsequent read (see Truth Table V). As an example, assume a

processor writes a zero to the left port at a free semaphore location. On

a subsequent read, the processor will verify that it has written success-

fully to that location and will assume control over the resource in

question. Meanwhile, if a processor on the right side attempts to write

a zero to the same semaphore flag it will fail, as will be verified by the

fact that a one will be read from that semaphore on the right side during

subsequent read. Had a sequence of READ/WRITE been used

instead, system contention problems could have occurred during the

gap between the read and write cycles.

It is important to note that a failed semaphore request must be

followed by either repeated reads or by writing a one into the same

location. The reason for this is easily understood by looking at the

simple logic diagram of the semaphore flag in Figure 4. Two sema-

phore request latches feed into a semaphore flag. Whichever latch is

first to present a zero to the semaphore flag will force its side of the

semaphore flag LOW and the other side HIGH. This condition will

continue until a one is written to the same semaphore request latch.

Should the other side’s semaphore request latch have been written to

a zero in the meantime, the semaphore flag will flip over to the other

side as soon as a one is written into the first side’s request latch. The

second side’s flag will now stay LOW until its semaphore request latch is

written to a one. From this it is easy to understand that, if a semaphore is

6.42

IDT70V35/34S/L PRELIMINARY

High-Speed 8/4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

requested and the processor which requested it no longer needs the

resource, the entire system can hang up until a one is written into that

semaphore request latch.

The critical case of semaphore timing is when both sides request

a single token by attempting to write a zero into it at the same time. The

semaphore logic is specially designed to resolve this problem. If

simultaneous requests are made, the logic guarantees that only one

side receives the token. If one side is earlier than the other in making

the request, the first side to make the request will receive the token. If

both requests arrive at the same time, the assignment will be arbitrarily

made to one port or the other.

One caution that should be noted when using semaphores is that

semaphores alone do not guarantee that access to a resource is

secure. As with any powerful programming technique, if semaphores

are misused or misinterpreted, a software error can easily happen.

Initialization of the semaphores is not automatic and must be

handled via the initialization program at power-up. Since any sema-

phore request flag which contains a zero must be reset to a one, all

semaphores on both sides should have a one written into them at

initialization from both sides to assure that they will be free when

needed.

Using SemaphoresSome Examples

Perhaps the simplest application of semaphores is their applica-

tion as resource markers for the IDT70V35/34’s Dual-Port SRAM. Say

the 8K x 18 SRAM was to be divided into two 4K x 18 blocks which were

to be dedicated at any one time to servicing either the left or right port.

Semaphore 0 could be used to indicate the side which would control

the lower section of memory, and Semaphore 1 could be defined as the

indicator for the upper section of memory.

To take a resource, in this example the lower 4K of Dual-Port

SRAM, the processor on the left port could write and then read a zero

in to Semaphore 0. If this task were successfully completed (a zero

was read back rather than a one), the left processor would assume

control of the lower 4K. Meanwhile the right processor was attempting

to gain control of the resource after the left processor, it would read

back a one in response to the zero it had attempted to write into

Semaphore 0. At this point, the software could choose to try and gain

control of the second 4K section by writing, then reading a zero into

Semaphore 1. If it succeeded in gaining control, it would lock out the

left side.

Once the left side was finished with its task, it would write a one to

Semaphore 0 and may then try to gain access to Semaphore 1. If

Semaphore 1 was still occupied by the right side, the left side could

undo its semaphore request and perform other tasks until it was able

to write, then read a zero into Semaphore 1. If the right processor

performs a similar task with Semaphore 0, this protocol would allow the

two processors to swap 4K blocks of Dual-Port SRAM with each other.

The blocks do not have to be any particular size and can even be

variable, depending upon the complexity of the software using the

semaphore flags. All eight semaphores could be used to divide the

Dual-Port SRAM or other shared resources into eight parts. Sema-

phores can even be assigned different meanings on different sides

rather than being given a common meaning as was shown in the

example above.

Semaphores are a useful form of arbitration in systems like disk

interfaces where the CPU must be locked out of a section of memory

during a transfer and the I/O device cannot tolerate any wait states.

With the use of semaphores, once the two devices has determined

which memory area was “off-limits” to the CPU, both the CPU and the

I/O devices could access their assigned portions of memory continu-

ously without any wait states.

Semaphores are also useful in applications where no memory

“WAIT” state is available on one or both sides. Once a semaphore

handshake has been performed, both processors can access their

assigned RAM segments at full speed.

Another application is in the area of complex data structures. In this

case, block arbitration is very important. For this application one

processor may be responsible for building and updating a data

structure. The other processor then reads and interprets that data

structure. If the interpreting processor reads an incomplete data

structure, a major error condition may exist. Therefore, some sort of

arbitration must be used between the two different processors. The

building processor arbitrates for the block, locks it and then is able to

go in and update the data structure. When the update is completed, the

data structure block is released. This allows the interpreting processor

to come back and read the complete data structure, thereby guaran-

teeing a consistent data structure.

5624 drw 17

0DQ

WRITE D0

QWRITE

SEMAPHORE

REQUEST FLIP FLOP SEMAPHORE

REQUEST FLIP FLOP

LPORT RPORT

SEMAPHORE

READ SEMAPHORE

READ

Figure 4. IDT70V35/34 Semaphore Logic

6.42

IDT70V35/34S/L PRELIMINARY

High-Speed 8/4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Ordering Information(1)

5624 drw 18

Power

999

Speed

Package

Process/

Temperature

Range

Blank

I(1) Commercial (0°Cto+70

°C)

Industrial (-40°Cto+85

°C)

PF 100-pin TQFP (PN100-1)

LStandard Power

Low Power

XXXXX

Device

Type

144K (8K x 18-Bit) 3.3V Dual-Port RAM

72K (4K x 18-Bit) 3.3V Dual-Port RAM

70V35

70V34

IDT

Speed in Nanoseconds

Commercial Only

Commercial & Industrial

Commercial Only

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or 408-727-6116 831-754-4613

Santa Clara, CA 95054 fax: 408-492-8674 DualPortHelp@idt.com

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

Datasheet Document History

6/8/00: Initial Public Offering

8/9/01: Page 1 Corrected I/O numbering

Page 5-7, 10 & 12 Removed Industrial temperature range offering for 25ns from DC & AC Electrical Characteristics

Page 17 Removed Industrial temperature range offering for 25ns speed from the ordering information

Added Industrial temperature offering footnote

7/2/02: Page 2 Added date revision for pin configuration

Added 70V34 to datasheet

NOTES:

1. Contact your local sales office for Industrial temp range for other speeds, packages and powers.

Preliminary Datasheet:

"PRELIMINARY' datasheets contain descriptions for products that are in early release.