QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 794
TRIPLE HIGH SPEED VIDEO BUFFER
1
LT6554
DESCRIPTION
Demonstration Circuit 794 is a Triple High Speed
Video Buffer featuring the LT6554. This circuit is de-
signed to demonstrate DC-coupled performance in
either split- or single-supply operation. Table 1 indi-
cates the performance that is achieved with this
evaluation board.
Design files for this circuit board are available. Call
the LTC factory.
Table 1.
Performance Summary (T
A
= 25°C)
PARAMETER CONDITION VALUE
Split supply operation, Min/Max ±2.3V/±6V
Supply Voltage
Single supply operation, Min/Max +4.5/+12V
Input Impedance, INR, ING, INB 75Ω, dc-coupled to ground
Output Impedance, OUTR, OUTG, OUTB 75Ω, dc-coupled
CAL trace Impedance 75Ω nominal
Outputs terminated into 75Ω -6dB nominal
Gain
Outputs terminated into High impedance 0dB nominal
Bandwidth –3dB, outputs terminated in 75Ω, -13dBm input 450MHz typical
Worst-case All Hostile, 10MHz –75dB typical
Crosstalk
Worst-case All Hostile, 100MHz –50dB typical
±3.3V Split Supply, No Output Clipping, Hi-Z loading ±2.0V
±5.0V Split Supply, No Output Clipping, Hi-Z loading ±3.7V
Input Signal Voltage Range
+9.0V Single Supply, No Output Clipping, Hi-Z loading +1.3 to +7.7V
Logic Low Voltage (Amplifiers ON), DGND = 0V ≤0.8V
On/Off Control Input
Logic High Voltage (Amplifiers OFF), DGND = 0V ≥2.0V (5.5V max)
OPERATING PRINCIPLES
DC794 provides three identical channels of wideband
signal buffering suitable for driving HDTV or high-
resolution RGB video multiplexers or digitizers. Each
buffer section of the LT6554 provides a fixed gain of
1 to a destination load. Each input is terminated to
analog ground to properly load the input signal ca-
bles.
To minimize ingress of external digital ground noise,
the DGND logic reference input is decoupled from
analog ground within the LT6554. DC794 includes a
jumper, JP2, which allows the DGND to be strapped
to the local analog ground (AGND); for example,
when the logic source is floating or none is used dur-
ing the evaluation. DGND may be left uncommitted
with JP2 in the FLOAT position.
Another jumper, JP1, allows the LT6554 to be forced
to an ENABLE condition. If JP1 is left in the EXTernal
position, then enabling the LT6554 is accomplished
by pulling down the EN connection to a level near that
of DGND via connection to E1 or J1. A pull-up resis-
tor internal to the LT6554 will provide a default shut-
down mode of operation if the control input is left
QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 794
TRIPLE HIGH SPEED VIDEO BUFFER
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open-circuit. NOTE: DO NOT open-circuit EN if V+ is
more than 5.5V above DGND; refer to LT6554 data-
sheet for application details in this situation.
A CAL trace is also provided on DC794 to provide a
means of precision calibration for a Network Analyzer
(use the CAL connections when performing the
“THRU” transmission calibration). The CAL trace has
the same electrical performance and delay as the
transmission lines of the three signal channels,
thereby allowing circuit board and connector effects
to be eliminated from the transmission measure-
ments.
JP3 is provided as a convenience to eliminate having
to externally short V– to GND in the case of SINGLE
supply operation. Leave JP3 in the DUAL position
when using split supplies.
Figure 4 shows the material list of the components
used by DC794, and Figure 5 shows the electrical in-
terconnection.
QUICK START PROCEDURE
Demonstration Circuit 794 is easy to set up to evalu-
ate the performance of the LT6554. Refer to Figure 1
for proper measurement equipment setup and follow
the procedure below:
NOTE:
Due to the Ultra High Frequencies (UHF) in-
volved, RF measurement practices are required to
accurately evaluate the performance of the LT6554.
1.
Place jumpers in the following positions:
ENABLE
AGND
DUAL
2.
Prior to connecting the power supply, preset the
output voltages to ±5V, or to the desired level, if
different.
3.
With power off, connect the power supplies to V+,
V–, and GND using banana-plug cables.
4.
Energize the power supply.
5.
For video-signal evaluation, connect a component-
video signal source to the inputs and a high input
impedance video analyzer to the outputs, using
equal-length 75Ω cabling amongst the three video
channels. Figure 3 shows a typical pulse response.
6.
If using a Network Analyzer, perform the THRU
transmission calibration with all cabling, adapters,
impedance converters, etc. in place, and using the
DC794 CAL trace as the reference 0dB path.
7.
Connect a Network Analyzer (if used) to the appro-
priate channels to measure frequency response
and crosstalk as desired. Figure 2 shows a typical
transmission plot for 1k loading. Use of 75Ω load-
ing with the DC794 as shipped will reduce the -3dB
response to about 450MHz (and show a passband
loss of -6dB). If the analyzer has only a low-
impedance input, then the R
L
=1kΩ condition can
be simulated by installing 953Ω resistors in R1,
R2, and R3 and providing a 26.05dB correction to
the 50Ω analyzer reading (or 22.74dB for a 75Ω
instrument).
8.
To evaluate the shutdown mode, disconnect or re-
locate the JP1 jumper to the EXT position (with no
connections made at EN, or if present, a logic high
provided).
JP1
JP2
JP3
QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 794
TRIPLE HIGH SPEED VIDEO BUFFER
3
– COM +
Power Supply
-
--
-
5.00
5.005.00
5.00
+5.00
+5.00+5.00
+5.00
Inputs
Outputs
Figure 1.
Recommended Demo Circuit Setup
Figure 2.
Typical Transmission Frequency Response
QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 794
TRIPLE HIGH SPEED VIDEO BUFFER
4
Figure 3.
Typical Time-Domain Transmission Response
Figure 4.
DC794 Bill of Material
QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 794
TRIPLE HIGH SPEED VIDEO BUFFER
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Figure 5.
DC794 Electrical Schematic Diagram
