September 3rd, 2012 Automotive Grade AUIRS2332J 3-PHASE BRIDGE DRIVER IC Features * * * * * * * * * * * * * * Floating channel designed for bootstrap operation Fully operational to +600 V Tolerant to negative transient voltage - dV/dt immune Gate drive supply range from 10 V to 20 V Undervoltage lockout for all channels Over-current shutdown turns off all six drivers Independent half-bridge drivers Matched propagation delay for all channels 3.3 V logic compatible Outputs out of phase with inputs Cross-conduction prevention logic Integrated Operational Amplifier RoHS Compliant Product Summary 600V VOFFSET VOUT 10 - 20V Io+ & I o- (typical) 250mA & 500mA tON & tOFF (typical) 540ns Deadtime (typical) 850ns Package Options Automotive qualified* Typical Applications * * * Automotive Body electronics 3 phase motor control Pumps and fans Typical Connection Diagram 44-Lead PLCC w/o 12 Leads AUIRS2332J Table of Contents Page Description 3 Qualification Information 4 Absolute Maximum Ratings 5 Recommended Operating Conditions 6 Dynamic Electrical Characteristics 6 Static Electrical Characteristics 7-8 Functional Block Diagram 8 Input/Output Pin Equivalent Circuit Diagram 9 Lead Definitions 10 Lead Assignments 10 Application Information and Additional Details 11 - 25 Parameter Temperature Trends 26 - 29 Package Details 30 - 31 Part Marking Information 32 Ordering Information 32 Important Notice 33 2 AUIRS2332J Description The AUIRS2332J is a high voltage, high speed power MOSFET and IGBT driver with three independent high and low side referenced output channels. Proprietary HVIC technology enables ruggedized monolithic construction. Logic inputs are compatible with CMOS or LSTTL outputs, down to 3.3V logic. A ground-referenced operational amplifier provides analog feedback of bridge current via an external current sense resistor. A current trip function which terminates all six outputs is also derived from this resistor. An open drain FAULT signal indicates if an over-current or undervoltage shutdown has occurred. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use at high frequencies. The floating channel can be used to drive N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts. 3 AUIRS2332J Qualification Information Automotive (per AEC-Q100 ) Comments: This family of ICs has passed an Automotive qualification. IR's Industrial and Consumer qualification level is granted by extension of the higher Automotive level. Qualification Level MSL3 245C (per IPC/JEDEC J-STD-020) Moisture Sensitivity Level Machine Model ESD Human Body Model Charged Device Model IC Latch-Up Test RoHS Compliant Class M2 (Pass +/-200V) (per AEC-Q100-003) Class H1C (Pass +/-1500V) (per AEC-Q100-002) Class C4 (+/-1000V) (per AEC-Q100-011) Class II, Level A (per AEC-Q100-004) Yes Qualification standards can be found at International Rectifier's web site http://www.irf.com/ Exceptions (if any) to AEC-Q100 requirements are noted in the qualification report. Higher MSL ratings may be available for the specific package types listed here. Please contact your International Rectifier sales representative for further information. 4 AUIRS2332J Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which permanent damage to the device may occur. These are stress ratings only, functional operation of the device at these or any other condition beyond those indicated in the "Recommended Operating Condition" is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability. All voltage parameters are absolute voltages referenced to VSO unless otherwise stated in the table. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol VB1,2,3 Definition High Side Floating Supply Voltage Min. Max. -0.3 620 VS1,2,3 High Side Floating Offset Voltage VB1,2,3 - 20 VB1,2,3 + 0.3 VHO1,2,3 High Side Floating Output Voltage VS1,2,3 - 0.3 VB1,2,3 + 0.3 VCC Low Side and Logic Fixed Supply Voltage VSS Logic Ground VLO1,2,3 VIN VFLT VCAO VCA- Low Side Output Voltage _______ ______ Logic Input Voltage ( HIN1,2,3, LIN1,2,3 & ITRIP) FAULT Output Voltage Operational Amplifier Output Voltage Operational Amplifier Inverting Input Voltage -0.3 20 VCC - 20 VCC + 0.3 -0.3 VCC + 0.3 VSS -0.3 (VSS + 15) or (VCC + 0.3) Whichever is lower VSS -0.3 VSS -0.3 VCC +0.3 VCC +0.3 VSS -0.3 VCC +0.3 Units V dVS/dt Allowable Offset Supply Voltage Transient -- 50 V/ns PD Package Power Dissipation @ TA +25 C -- 2.0 W RthJA Thermal Resistance, Junction to Ambient -- 63 C/W RthJC Thermal Resistance, Junction to Case --- 21.95 C/ W TJ Junction Temperature -- 150 TS Storage Temperature -55 150 TL Lead Temperature (soldering, 10 seconds) -- 300 C 5 AUIRS2332J Recommended Operating Conditions The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute voltage referenced to VSO. The VS offset rating is tested with all supplies biased at 15V differential. Symbol Definition VB1,2,3 High Side Floating Supply Voltage Min. Max. VS1,2,3 +10 VS1,2,3 +20 VSO-8 (Note1) 600 -50 (Note2) VS1,2,3 600 VB1,2,3 VS1,2,3 Static High side floating offset voltage VSt1,2,3 VHO1,2,3 Transient High side floating offset voltage VCC Low Side and Logic Fixed Supply Voltage 10 20 VSS Logic Ground -5 5 0 VSS VSS VCC VSS + 5 VCC VLO1,2,3 VIN VFLT High Side Floating Output Voltage Low Side Output Voltage Logic Input Voltage (HIN1,2,3, LIN1,2,3 & ITRIP) FAULT Output Voltage VCAO Operational Amplifier Output Voltage VSS VSS + 5 VCA- Operational Amplifier Inverting Input Voltage VSS VSS + 5 Units V TA Ambient temperature -40 125 C Note 1: Logic operational for VS of (VSO -8 V) to (VSO +600 V). Logic state held for VS of (VSO -8 V) to (VSO - VBS). Note 2: Operational for transient negative VS of VSS - 50 V with a 50 ns pulse width. Guaranteed by design. Refer to the Application Information section of this datasheet for more details. Note 3: CAO input pin is internally clamped with a 5.2 V zener diode. Dynamic Electrical Characteristics Unless otherwise noted, these specifications apply for an operating junction temperature range of -40C Tj 125C with bias conditions VBIAS (VCC, VBS1,2,3) = 15 V, CL = 1000 pF. Symbol Definition Min Typ Max Units ton Turn-on propagation delay 400 540 700 toff Turn-off propagation delay 400 540 700 tr Turn-on rise time -- 80 145 tf Turn-off fall time ITRIP to Output Shutdown Propagation delay ITRIP Blanking Time ITRIP to FAULT Indication Delay Input Filter Time (All Six Inputs) LIN1,2,3 to FAULT Clear Time -- 40 55 400 625 920 -- 350 -- 400 550 325 -- 870 -- 5300 8500 13700 Deadtime: Deadtime matching: 500 -- 850 -- 1100 145 titrip tbl tflt tflt, in tfltclr DT MDT MT Delay matching time (t ON , t OFF) -- -- 50 PM Pulse width distortion -- -- 75 SR+ Operational Amplifier Slew Rate (+) 5 10 -- SR- Operational Amplifier Slew Rate (-) 2.4 3.2 -- Test Conditions VS1,2,3 = 0 V to 600 V VS1,2,3 = 0 V ns VIN = 0 V & 5 V without external deadtime VIN = 0 V & 5 V without external deadtime larger than DT PM input 10 s V/s 1 V input step 1 V input step 6 AUIRS2332J NOTE: For high side PWM, HIN pulse width must be > 1.5 usec Static Electrical Characteristics Unless otherwise noted, these specifications apply for an operating junction temperature range of -40C Tj 125C with bias conditions of VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS . The VIN, VTH and IIN parameters are referenced to VSS and are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3. The VO and IO parameters are referenced to VSO1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3. Symbol Definition VIH Logic "0" input Voltage (OUT = LO) VIL Min Typ Max Units Test Conditions -- -- 2.2 VIT,TH+ Logic "1" input Voltage (OUT = HI) ITRIP Input Positive Going Threshold 0.8 400 -- 490 -- 580 VOH High Level Output Voltage, VBIAS - VO -- -- 1150 VOL Low Level Output Voltage, VO -- -- 400 ILK Offset Supply Leakage Current -- -- 50 IQBS Quiescent VBS Supply Current -- 37 50 IQCC Quiescent VCC Supply Current -- 4.5 6.2 IIN+ IIN- Logic "1" Input Bias Current (OUT =HI) Logic "0" Input Bias Current (OUT = LO) "High" ITRIP Bias Current "LOW" ITRIP Bias Current VBS Supply Undervoltage Positive Going Threshold VBS Supply Undervoltage Negative Going Threshold VCC Supply Undervoltage Positive going Threshold VCC Supply Undervoltage Negative Going Threshold IITRIP+ IITRIPVBSUV+ VBSUVVCCUV+ VCCUV- -450 -300 -100 -350 -220 -100 -- 5 10 -- -- 30 7.5 8.3 9.2 7.1 7.9 8.8 8.3 8.9 9.7 8 8.6 9.4 VCCUVH Hysteresis -- 0.3 -- VBSUVH Hysteresis FAULT Low On-Resistance -- 0.4 -- -- 55 75 IO+ Output High Short Circuit Pulsed Current -- IO- Output Low Short Circuit Pulsed Current 375 500 -- -- -- -- -- 20 100 -- 80 -- Ron, FLT V mV VIN = 5 V, IO = 20 mA VB = VS = 600 V A mA A nA CMRR PSRR VOH,AMP VOL,AMP Operational Amplifier Input Offset Voltage CA- Input Bias Current Operational Amplifier Common Mode Rejection Ratio Operational Amplifier Power Supply Rejection Ratio Operational Amplifier High Level Output Voltage Operational Amplifier Low Level Output Voltage mV nA -- 75 -- 4.8 5.2 5.6 V -- -- 40 mV -- -7 -4 ISNK,AMP Operational Amplifier Output Sink Current 1 2.1 -- VIN = 0 V VIN = 4 V ITRIP = 4 V ITRIP = 0 V VO = 0 V, VIN = 0 V PW 10 us VO = 15 V, VIN = 5 V PW 10 us VSO = 0.2 V VCA- = 1 V VSO = 0.1 V & 5 V dB Operational Amplifier Output Source Current VIN = 0 V -250 -180 ISRC,AMP VIN = 0 V or 4 V V mA VOS ICA- VIN = 0 V, IO = 20 mA mA VSO = 0.2 V VCC = 9.7 V & 20 V VCA- = 0 V, VSO =1 V VCA- = 1 V, VSO =0 V VCA- = 0 V, VSO =1 V VCAO = 4 V VCA- = 1 V, VSO =0 V VCAO = 2 V 7 AUIRS2332J IO+,AMP IO-,AMP Operational Amplifier Output High Short Circuit Current Operational Amplifier Output Low Short Circuit Current -30 -10 -- -- 4 -- VCA- = 0 V, VSO =5 V VCAO = 0 V VCA- = 5 V, VSO =0 V VCAO = 5 V Functional Block Diagram 8 AUIRS2332J Input/Output Pin Equivalent Circuit Diagram: VCC ESD Diode HIN123 , LIN123 50 KOhm 250 Ohm 20V ESD Diode 5V VSS VCC ESD Diode 250 Ohm ITRIP ESD Diode 5V 1 MOhm VSS 9 AUIRS2332J VB123 ESD Diode 20V HO123 ESD Diode VS123 10 AUIRS2332J Lead Definitions Symbol HIN1,2,3 LIN1,2,3 FAULT VCC Description Logic input for high side gate driver outputs (HO1,2,3), out of phase Logic input for low side gate driver output (LO1,2,3), out of phase Indicates over-current or undervoltage lockout (low side) has occurred, negative logic Low side and logic fixed supply ITRIP Input for over-current shutdown CAO Output of current amplifier CA- Negative input of current amplifier VSS VB1,2,3 HO1,2,3 VS1,2,3 Logic Ground High side floating supply High side gate drive output High side floating supply return LO1,2,3 Low side gate drive output VSO Low side return and positive input of current amplifier #Leas7, #11, #13, #15, #17, #20, #21 are N.C. Lead Assignments Leads num. 7, 11, 13, 15, 17, 20 and 21 are N.C. 11 AUIRS2332J Application Information and Additional Details Information regarding the following topics are included as subsections within this section of the datasheet. * * * * * * * * * * * * * * * * * * * * IGBT/MOSFET Gate Drive Switching and Timing Relationships Deadtime Matched Propagation Delays Input Logic Compatibility Undervoltage Lockout Protection Shoot-Through Protection Fault Reporting Over-Current Protection Over-Temperature Shutdown Protection Truth Table: Undervoltage lockout, ITRIP Advanced Input Filter Short-Pulse / Noise Rejection Integrated Bootstrap Functionality Bootstrap Power Supply Design Separate Logic and Power Grounds Negative VS Transient SOA DC- bus Current Sensing PCB Layout Tips Additional Documentation IGBT/MOSFET Gate Drive The AUIRS2332J HVIC is designed to drive up to six MOSFET or IGBT power devices. Figures 1 and 2 illustrate several parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC, used to drive the gate of the power switch, is defined as IO. The voltage that drives the gate of the external power switch is defined as VHO for the high-side power switch and VLO for the low-side power switch; this parameter is sometimes generically called VOUT and in this case does not differentiate between the high-side or low-side output voltage. VB (or VCC) VB (or VCC) IO+ HO (or LO) + HO (or LO) IO- VHO (or VLO) VS (or COM) - Figure 1: HVIC sourcing current VS (or COM) Figure 2: HVIC sinking current 12 AUIRS2332J Switching and Timing Relationships The relationship between the input and output signals of the AUIRS2332J are illustrated below in Figures 3. From these figures, we can see the definitions of several timing parameters (i.e., PW IN, PW OUT, tON, tOFF, tR, and tF) associated with this device. LINx (or HINx) 50% 50% PWIN tON tOFF tR 90% LOx (or HOx) tF PWOUT 10% 90% 10% Figure 3: Switching time waveforms The following two figures illustrate the timing relationships of some of the functionalities of the AUIRS2332J. These functionalities are described in further detail later in this document. During interval A of Figure 4, the HVIC has received the command to turn-on both the high- and low-side switches at the same time; as a result, the shoot-through protection of the HVIC has prevented this condition and both the high- and low-side output are held in the off state. Interval B of Figures 4 shows that the signal on the ITRIP input pin has gone from a low to a high state; as a result, all of the gate drive outputs have been disabled (i.e., see that HOx has returned to the low state; LOx is also held low) and a fault is reported by the FAULT output transitioning to the low state. Once the ITRIP input has returned to the low state, the fault condition is latched until the all LINx become high. HIN1,2,3 A B LIN1, 2, 3 ITRIP FAULT HO1, 2, 3 LO1,2, 3 Figure 4: Input/output timing diagram 13 AUIRS2332J Deadtime This HVIC features integrated deadtime protection circuitry. The deadtime for this IC is fixed; other ICs within IR's HVIC portfolio feature programmable deadtime for greater design flexibility. The deadtime feature inserts a time period (a minimum deadtime) in which both the high- and low-side power switches are held off; this is done to ensure that the power switch being turned off has fully turned off before the second power switch is turned on. This minimum deadtime is automatically inserted whenever the external deadtime is shorter than DT; external deadtimes larger than DT are not modified by the gate driver. Figure 5 illustrates the deadtime period and the relationship between the output gate signals. The deadtime circuitry of the AUIRS2332J is matched with respect to the high- and low-side outputs of a given channel; additionally, the deadtimes of each of the three channels are matched. Figure 5: Illustration of deadtime Matched Propagation Delays The AUIRS2332J HVIC is designed with propagation delay matching circuitry. With this feature, the IC's response at the output to a signal at the input requires approximately the same time duration (i.e., tON, tOFF) for both the low-side channels and the high-side channels. Additionally, the propagation delay for each low-side channel is matched when compared to the other low-side channels and the propagation delays of the high-side channels are matched with each other. The propagation turn-on delay (tON) of the AUIRS2332J is matched to the propagation turn-on delay (tOFF). Input Logic Compatibility The inputs of this IC are compatible with standard CMOS and TTL outputs. The AUIRS2332J has been designed to be compatible with 3.3 V and 5 V logic-level signals. The AUIRS2332J features an integrated 5.2 V Zener clamp on the HIN, LIN, and ITRIP pins. Figure 6 illustrates an input signal to the AUIRS2332J, its input threshold values, and the logic state of the IC as a result of the input signal. 14 AUIRS2332J Figure 6: HIN & LIN input thresholds Undervoltage Lockout Protection This IC provides undervoltage lockout protection on both the VCC (logic and low-side circuitry) power supply and the VBS (high-side circuitry) power supply. Figure 7 is used to illustrate this concept; VCC (or VBS) is plotted over time and as the waveform crosses the UVLO threshold (VCCUV+/- or VBSUV+/-) the undervoltage protection is enabled or disabled. Upon power-up, should the VCC voltage fail to reach the VCCUV+ threshold, the IC will not turn-on. Additionally, if the VCC voltage decreases below the VCCUV- threshold during operation, the undervoltage lockout circuitry will recognize a fault condition and shutdown the high- and low-side gate drive outputs, and the FAULT pin will transition to the low state to inform the controller of the fault condition. Upon power-up, should the VBS voltage fail to reach the VBSUV threshold, the IC will not turn-on. Additionally, if the VBS voltage decreases below the VBSUV threshold during operation, the undervoltage lockout circuitry will recognize a fault condition, and shutdown the high-side gate drive outputs of the IC. The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is sufficient to fully enhance the power devices. Without this feature, the gates of the external power switch could be driven with a low voltage, resulting in the power switch conducting current while the channel impedance is high; this could result in very high conduction losses within the power device and could lead to power device failure. Figure 7: UVLO protection Shoot-Through Protection 15 AUIRS2332J The AUIRS2332J is equipped with shoot-through protection circuitry (also known as cross-conduction prevention circuitry). Figure 8 shows how this protection circuitry prevents both the high- and low-side switches from conducting at the same time. Table 1 illustrates the input/output relationship of the devices in the form of a truth table. Note that the AUIRS2332J has inverting inputs (the output is out-of-phase with its respective input). Figure 8: Illustration of shoot-through protection circuitry AUIRS2332J HIN LIN HO LO 0 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 Table 1: Input/output truth table Fault Reporting The AUIRS2332J provides an integrated fault reporting output. There are two situations that would cause the HVIC to report a fault via the FAULT pin. The first is an undervoltage condition of VCC and the second is if the ITRIP pin recognizes a fault. Once the fault condition occurs, the FAULT pin is internally pulled to VSS and the fault condition is latched. The fault output stays in the low state until the fault condition has been removed by all LINx set to high state. Once the fault is removed, the voltage on the FAULT pin will return to VCC. Over-Current Protection The AUIRS2332J HVICs are equipped with an ITRIP input pin. This functionality can be used to detect over-current events in the DC- bus. Once the HVIC detects an over-current event through the ITRIP pin, the outputs are shutdown, a fault is reported through the FAULT pin. The level of current at which the over-current protection is initiated is determined by the resistor network (i.e., R0, R1, and R2) connected to ITRIP as shown in Figure 9, and the ITRIP threshold (VIT,TH+). The circuit designer will need to determine the maximum allowable level of current in the DC- bus and select R0, R1, and R2 such that the voltage at node VX reaches the over-current threshold (VIT,TH+) at that current level. VIT,TH+ = R0IDC-(R1/(R1+R2)) 16 AUIRS2332J Vcc A U I R S 2 3 3 2 J HIN(x3) LIN(x3) FAULT ITRIP VSS R1 VB (x3) HO( x3) VS (x3) LO(x3) COM R2 R0 IDC- Figure 9: Programming the over-current protection For example, a typical value for resistor R0 could be 50 m. The voltage of the ITRIP pin should not be allowed to exceed 5 V; if necessary, an external voltage clamp may be used. Over-Temperature Shutdown Protection The ITRIP input of the AUIRS2332J can also be used to detect over-temperature events in the system and initiate a shutdown of the HVIC (and power switches) at that time. In order to use this functionality, the circuit designer will need to design the resistor network as shown in Figure 10 and select the maximum allowable temperature. This network consists of a thermistor and two standard resistors R3 and R4. As the temperature changes, the resistance of the thermistor will change; this will result in a change of voltage at node VX. The resistor values should be selected such the voltage VX should reach the threshold voltage (VIT,TH+) of the ITRIP functionality by the time that the maximum allowable temperature is reached. The voltage of the ITRIP pin should not be allowed to exceed 5 V. When using both the over-current protection and over-temperature protection with the ITRIP input, OR-ing diodes (e.g., DL4148) can be used. This network is shown in Figure 11; the OR-ing diodes have been labeled D1 and D2. Figure 10: Programming over-temperature protection Figure 11: Using over-current protection and over-temperature protection Truth Table: Undervoltage lockout and ITRIP 17 AUIRS2332J Table 2 provides the truth table for the AUIRS2332J. The first line shows that the UVLO for VCC has been tripped; the FAULT output has gone low and the gate drive outputs have been disabled. VCCUV is not latched in this case and when VCC is greater than VCCUV, the FAULT output returns to the high impedance state. The second case shows that the UVLO for VBS has been tripped and that the high-side gate drive outputs have been disabled. After VBS exceeds the VBSUV threshold, HO will stay low until the HVIC input receives a new falling transition of HIN. The third case shows the normal operation of the HVIC. The fourth case illustrates that the ITRIP trip threshold has been reached and that the gate drive outputs have been disabled and a fault has been reported through the fault pin. The fault output stays in the low state until the fault condition has been removed by all LINx set to high state. Once the fault is removed, the voltage on the FAULT pin will return to VCC. UVLO VCC UVLO VBS Normal operation ITRIP fault VCC <VCCUV 15 V 15 V 15 V VBS --<VBSUV 15 V 15 V ITRIP --0V 0V >VITRIP FAULT 0 High impedance High impedance 0 LO 0 LIN LIN 0 HO 0 0 HIN 0 Table 2: AUIRS2332J UVLO, ITRIP & FAULT truth table Advanced Input Filter The advanced input filter allows an improvement in the input/output pulse symmetry of the HVIC and helps to reject noise spikes and short pulses. This input filter has been applied to the HIN and LIN. The working principle of the new filter is shown in Figures 12 and 13. Figure 12 shows a typical input filter and the asymmetry of the input and output. The upper pair of waveforms (Example 1) shows an input signal with a duration much longer then tFIL,IN; the resulting output is approximately the difference between the input signal and tFIL,IN. The lower pair of waveforms (Example 2) show an input signal with a duration slightly longer then tFIL,IN; the resulting output is approximately the difference between the input signal and tFIL,IN. Figure 13 shows the advanced input filter and the symmetry between the input and output. The upper pair of waveforms (Example 1) show an input signal with a duration much longer then tFIL,IN; the resulting output is approximately the same duration as the input signal. The lower pair of waveforms (Example 2) show an input signal with a duration slightly longer then tFIL,IN; the resulting output is approximately the same duration as the input signal. Figure 12: Typical input filter Figure 13: Advanced input filter Short-Pulse / Noise Rejection 18 AUIRS2332J Example 2 Example 1 This device's input filter provides protection against short-pulses (e.g., noise) on the input lines. If the duration of the input signal is less than tFIL,IN, the output will not change states. Example 1 of Figure 14 shows the input and output in the low state with positive noise spikes of durations less than tFIL,IN; the output does not change states. Example 2 of Figure 19 shows the input and output in the high state with negative noise spikes of durations less than tFIL,IN; the output does not change states. Figure 14: Noise rejecting input filters Figures 15 and 16 present lab data that illustrates the characteristics of the input filters while receiving ON and OFF pulses. The input filter characteristic is shown in Figure 15; the left side illustrates the narrow pulse ON (short positive pulse) characteristic while the left shows the narrow pulse OFF (short negative pulse) characteristic. The x-axis of Figure 20 shows the duration of PW IN, while the y-axis shows the resulting PW OUT duration. It can be seen that for a PW IN duration less than tFIL,IN, that the resulting PW OUT duration is zero (e.g., the filter rejects the input signal/noise). We also see that once the PW IN duration exceed tFIL,IN, that the PW OUT durations mimic the PW IN durations very well over this interval with the symmetry improving as the duration increases. To ensure proper operation of the HVIC, it is suggested that the input pulse width for the high-side inputs be 500 ns. Time (ns) The difference between the PW OUT and PW IN signals of both the narrow ON and narrow OFF cases is shown in Figure 16; the careful reader will note the scale of the y-axis. The x-axis of Figure 21 shows the duration of PW IN, while the y-axis shows the resulting PW OUT-PW IN duration. This data illustrates the performance and near symmetry of this input filter. Figure 15: AUIRS2332J input filter characteristic 19 AUIRS2332J Figure 16: Difference between the input pulse and the output pulse Separate Logic and Power Grounds The AUIRS2332J has separate logic and power ground pin (VSS and VSO respectively) to eliminate some of the noise problems that can occur in power conversion applications. Current sensing shunts are commonly used in many applications for power inverter protection (i.e., over-current protection), and in the case of motor drive applications, for motor current measurements. In these situations, it is often beneficial to separate the logic and power grounds. Figure 19 shows a HVIC with separate VSS and VSO pins and how these two grounds are used in the system. The VSS is used as the reference point for the logic and over-current circuitry; VX in the figure is the voltage between the ITRIP pin and the VSS pin. Alternatively, the VSO pin is the reference point for the low-side gate drive circuitry. The output voltage used to drive the low-side gate is VLO-VSO; the gate-emitter voltage (VGE) of the low-side switch is the output voltage of the driver minus the drop across RG,LO. DC+ BUS DBS VB (x3) VCC CBS HO (x3) HVIC ITRIP RG,HO VS (x3) LO (x3) VS1 VS3 RG,LO + + VSS VS2 VGE1 COM + VGE2 - - VGE3 - R2 R0 + VX R1 - DC- BUS Figure 19: Separate VSS and VSO (COM) pins Negative VS Transient SOA 20 AUIRS2332J A common problem in today's high-power switching converters is the transient response of the switch node's voltage as the power switches transition on and off quickly while carrying a large current. A typical 3-phase inverter circuit is shown in Figure 20; here we define the power switches and diodes of the inverter. If the high-side switch (e.g., the IGBT Q1 in Figures 21 and 22) switches off, while the U phase current is flowing to an inductive load, a current commutation occurs from high-side switch (Q1) to the diode (D2) in parallel with the low-side switch of the same inverter leg. At the same instance, the voltage node VS1, swings from the positive DC bus voltage to the negative DC bus voltage. Figure 20: Three phase inverter DC+ BUS Q1 ON IU VS1 Q2 OFF D2 DC- BUS Figure 21: Q1 conducting Figure 22: D2 conducting Also when the V phase current flows from the inductive load back to the inverter (see Figures 23 and 24), and Q4 IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, VS2, swings from the positive DC bus voltage to the negative DC bus voltage. 21 AUIRS2332J Figure 23: D3 conducting Figure 24: Q4 conducting However, in a real inverter circuit, the VS voltage swing does not stop at the level of the negative DC bus, rather it swings below the level of the negative DC bus. This undershoot voltage is called "negative VS transient". The circuit shown in Figure 25 depicts one leg of the three phase inverter; Figures 26 and 27 show a simplified illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit from the die bonding to the PCB tracks are lumped together in LC and LE for each IGBT. When the high-side switch is on, VS1 is below the DC+ voltage by the voltage drops associated with the power switch and the parasitic elements of the circuit. When the high-side power switch turns off, the load current momentarily flows in the low-side freewheeling diode due to the inductive load connected to VS1 (the load is not shown in these figures). This current flows from the DC- bus (which is connected to the VSO pin of the HVIC) to the load and a negative voltage between VS1 and the DC- Bus is induced (i.e., the VSO pin of the HVIC is at a higher potential than the VS pin). Figure 25: Parasitic Elements Figure 26: VS positive Figure 27: VS negative In a typical motor drive system, dV/dt is typically designed to be in the range of 3-5 V/ns. The negative VS transient voltage can exceed this range during some events such as short circuit and over-current shutdown, when di/dt is greater than in normal operation. International Rectifier's HVICs have been designed for the robustness required in many of today's demanding applications. An indication of the AUIRS2332J's robustness can be seen in Figure 28, where there is represented the AUIRS2332J Safe Operating Area at VBS=15V based on repetitive negative VS spikes. A negative VS transient voltage falling in the grey area (outside SOA) may lead to IC permanent damage; viceversa unwanted functional anomalies or permanent damage to the IC do not appear if negative Vs transients fall inside SOA. At VBS=15V in case of -VS transients greater than -16.5 V for a period of time greater than 50 ns; the HVIC will hold by design the high-side outputs in the off state for 4.5 s. 22 AUIRS2332J Figure 28: Negative VS transient SOA for AUIRS2332J Even though the AUIRS2332J has been shown able to handle these large negative VS transient conditions, it is highly recommended that the circuit designer always limit the negative VS transients as much as possible by careful PCB layout and component use. DC- bus Current Sensing A ground referenced current signal amplifier has been included so that the current in the return leg of the DC bus may be monitored. A typical circuit configuration is provided in Fig.29. The signal coming from the shunt resistor is amplified by the ratio (R1+R2)/R2. Additional details can be found on Design Tip DT 92-6. This design tip is available at www.irf.com. Figure 29: Current amplifier typical configuration In the following Figures 30, 31, 32, 33 the configurations used to measure the operational amplifier characteristics are shown. 23 AUIRS2332J 15V VCC 1V CA- 0V CAO VSS VSO T1 1V 50pF T2 90% V 0V 10% V T1 SR+ V T2 SR - Figure 30: Operational Amplifier Slew rate measurement Figure 31: Operational Amplifier Input Offset Voltage measurement 15V VCC CA CAO VSO VSS Measure VCAO1 at VSO = 0.1V VCAO2 at VSO =1.1V CMRR= -20*LOG (VCAO1 -0.1V)-(VCAO2-1.1V) (dB) 1V Figure 32: Operational Amplifier Common mode rejection measurement Figure 33: Operational Amplifier Power supply rejection measurement PCB Layout Tips Distance between high and low voltage components: It's strongly recommended to place the components tied to the floating voltage pins (VB and VS) near the respective high voltage portions of the device. The AUIRS2332J in the PLCC44 package has had some unused pins removed in order to maximize the distance between the high voltage and low voltage pins. Please see the Case Outline PLCC44 information in this datasheet for the details. Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high voltage floating side. Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure 34). In order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive loops must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the IGBT collector-to-gate parasitic 24 AUIRS2332J capacitance. The parasitic auto-inductance of the gate loop contributes to developing a voltage across the gate-emitter, thus increasing the possibility of a self turn-on effect. Figure 34: Antenna Loops Supply Capacitor: It is recommended to place a bypass capacitor (CIN) between the VCC and VSS pins. This connection is shown in Figure 35. A ceramic 1 F ceramic capacitor is suitable for most applications. This component should be placed as close as possible to the pins in order to reduce parasitic elements. Vcc HIN(x3) VB (x3) LIN(x3) HO( x3) FAULT VS (x3) LO(x3) ITRIP COM VSS R1 R2 R0 IDC- Figure 35: Supply capacitor Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients at the switch node; it is recommended to limit the phase voltage negative transients. In order to avoid such conditions, it is recommended to 1) minimize the high-side emitter to low-side collector distance, and 2) minimize the low-side emitter to negative bus rail stray inductance. However, where negative VS spikes remain excessive, further steps may be taken to reduce the spike. This includes placing a resistor (5 or less) between the VS pin and the switch node (see Figure 36), and in some cases using a clamping diode between VSS and VS (see Figure 37). See DT04-4 at www.irf.com for more detailed information. 25 AUIRS2332J Figure 36: VS resistor Figure 37: VS clamping diode Additional Documentation Several technical documents related to the use of HVICs are available at www.irf.com; use the Site Search function and the document number to quickly locate them. Below is a short list of some of these documents. DT97-3: Managing Transients in Control IC Driven Power Stages AN-1123: Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality DT04-4: Using Monolithic High Voltage Gate Drivers AN-978: HV Floating MOS-Gate Driver ICs 26 AUIRS2332J Parameter Temperature Trends Figures illustrated in this chapter provide information on the experimental performance of the AUIRS2332J HVIC. The line plotted in each figure is generated from actual lab data. A large number of individual samples were tested at three temperatures (-40 C, 25 C, and 125 C) in order to generate the experimental curve. The line consists of three data points (one data point at each of the tested temperatures) that have been connected together to illustrate the understood trend. The individual data points on the Typ. curve were determined by calculating the averaged experimental value of the parameter (for a given temperature). Figure 38. Turn-on propagation delay vs. temperature Figure 40. Turn-on rise time vs. temperature Figure 39. Turn-off propagation delay vs. temperature Figure 41. Turn-off fall time vs. temperature 27 AUIRS2332J Figure 42. ITRIP to output shutdown propagation delay vs. temperature Figure 43. ITRIP to FAULT' indication delay vs. temperature Figure 44. Dead time vs. temperature Figure 45. Offset supply leakage current vs. temperature Figure 46. Quiescent VCC supply current vs. temperature Figure 47. Quiescent VBS supply current vs. temperature 28 AUIRS2332J Figure 48. High level output voltage vs. temperature Figure 49. Low level output voltage vs. temperature Figure 50. VCC supply undervoltage positive going threshold vs. temperature Figure 51. VCC supply undervoltage negative going threshold vs. temperature Figure 52. VBS supply undervoltage positive going threshold vs. temperature Figure 53. VBS supply undervoltage negative going threshold vs. temperature 29 AUIRS2332J Figure 54. ITRIP input positive going threshold vs. temperature Figure 55. Op-amp input offset voltage vs. temperature Figure 56. Op-amp high level output voltage vs. temperature 30 AUIRS2332J Case Outlines 31 AUIRS2332J Package Land Pattern 32 AUIRS2332J Tape and Reel Details: PLCC44 LOADED TAPE FEED DIRECTION A B H D F C NOTE : CONTROLLING DIM ENSION IN M M E G CARRIER TAPE DIMENSION FOR Metric Code Min Max A 23.90 24.10 B 3.90 4.10 C 31.70 32.30 D 14.10 14.30 E 17.90 18.10 F 17.90 18.10 G 2.00 n/a H 1.50 1.60 44PLCC Imperial Min Max 0.94 0.948 0.153 0.161 1.248 1.271 0.555 0.562 0.704 0.712 0.704 0.712 0.078 n/a 0.059 0.062 F D C B A E G H REEL DIMENSIONS FOR 44PLCC Metric Code Min Max A 329.60 330.25 B 20.95 21.45 C 12.80 13.20 D 1.95 2.45 E 98.00 102.00 F n/a 38.4 G 34.7 35.8 H 32.6 33.1 Imperial Min Max 12.976 13.001 0.824 0.844 0.503 0.519 0.767 0.096 3.858 4.015 n/a 1.511 1.366 1.409 1.283 1.303 33 AUIRS2332J Part Marking Information Ordering Information Standard Pack Base Part Number AUIRS2332J Package Type PLCC44 Complete Part Number Form Quantity Tube/Bulk 27 AUIRS2332J Tape and Reel 500 AUIRS2332JTR 34 AUIRS2332J IMPORTANT NOTICE Unless specifically designated for the automotive market, International Rectifier Corporation and its subsidiaries (IR) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or services without notice. Part numbers designated with the "AU" prefix follow automotive industry and / or customer specific requirements with regards to product discontinuance and process change notification. All products are sold subject to IR's terms and conditions of sale supplied at the time of order acknowledgment. IR warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with IR's standard warranty. Testing and other quality control techniques are used to the extent IR deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. IR assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using IR components. To minimize the risks with customer products and applications, customers should provide adequate design and operating safeguards. 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For technical support, please contact IR's Technical Assistance Center http://www.irf.com/technical-info/ WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245 Tel: (310) 252-7105 35 Revision History Date Jul. 7, 2010 July 28, 2010 May 6, 2011 May 11, 2011 May 11, 2011 Comment Converted from industrial datasheet Typ Application section updated in front page. Logic block diagram modified because UVVcc is not latched. Added Input Output equivalent circuit diagram Added tri-temp graphs; updated qual info page and table of contents. Formated to AU DS format Ton and toff typ values changed from 500ns to 540ns.Tf typ from 35ns to 40ns DT typ from 700ns to 850ns.Iqbs typ from 30uA to 37uA; Iqcc typ from 4.0uA to 4.5uA. ITRIP to Output Shutdown Propagation delay typ from 660ns to 625ns. VOH max from 1V to 1.1V. VCCUV+ typ from 9V to 8.9V; VCCUV- from 8.7V to 8.6V. VBSUV+ typ from 8.35V to 8.3V; VCCUV- from 7.95V to 7.9V. Iin+ min changed from -400 to -450; Iin- min changed from -300 to -350; Io- min changed from 420 to 375; Tr max changed from 125 to 145; MDT max change from 140 to 145; VOH max changed from 1.1 to 1.15. Changed formula in Figure 31 Updated CDM class Added RthJC Updated disclaimer May 13, 2011 May 17, 2011 June 7, 2011 June 24, 2011 August 30th, Updated Case Outline (more readable) and added Package Land Pattern 2012 rd September, 3 , Added NC (not connected) in lead assignment figure and text. 2012 Package Land Pattern updated * Qualification standards can be found on IR's web site www.irf.com (c) 2010 International Rectifier Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: International Rectifier: AUIRS2332J AUIRS2332JTR