Description
The HCPL-7840 isolation ampli er family was designed
for current sensing in electronic motor drives. In a typical
implementation, motor currents  ow through an external
resistor and the resulting analog voltage drop is sensed by
the HCPL-7840. A di erential output voltage is created on
the other side of the HCPL-7840 optical isolation barrier.
This di erential output voltage is proportional to the
motor current and can be converted to a single-ended
signal by using an op-amp as shown in the recommended
application circuit. Since common-mode voltage swings
of several hundred volts in tens of nanoseconds are
common in modern switching inverter motor drives, the
HCPL-7840 was designed to ignore very high common-
mode transient slew rates (of at least 10 kV/µs).
The high CMR capability of the HCPL-7840 isolation
ampli er provides the precision and stability needed to
accurately monitor motor current in high noise motor
control environ-ments, providing for smoother control
(less “torque ripple”) in various types of motor control
applications.
The product can also be used for general analog signal
isolation applications requiring high accuracy, stability,
and linearity under similarly severe noise con-ditions. For
general applications, we recommend the HCPL-7840 (gain
tolerance of ± 5%). The HCPL-7840 utilizes sigma delta
(∑-∆) analog-to-digital converter technology, chopper
stabilized ampli ers, and a fully di erential circuit topol-
ogy fabricated using Avago’s 0.8 µm CMOS IC process.
Together, these features deliver unequaled isolation-
mode noise rejection, as well as excellent o set and gain
accuracy and stability over time and temperature. This
performance is delivered in a compact, auto-insertable,
industry standard 8-pin DIP package that meets world-
wide regulatory safety standards. (A gull-wing surface
mount option #300 is also available).
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
1
2
3
4
8
7
6
5
IDD1
VDD1
VIN+
VIN–
GND1
IDD2
VDD2
VOUT+
VOUT–
GND2
+
–
+
–
SHIELD
HCPL-7840
Isolation Ampli er
Data Sheet
Features
15 kV/µs common-mode rejection at VCM = 1000 V
Compact, auto-insertable standard 8-pin DIP package
0.00025 V/V/°C gain drift vs. temperature
0.3 mV input o set voltage
100 kHz bandwidth
0.004% nonlinearity
Worldwide safety approval:
UL 1577 (3750 Vrms/1 min.)
and CSA, IEC/EN/DIN EN 60747-5-2
Advanced Sigma-Delta (∑-∆) A/D converter technol-
ogy
Fully di erential circuit topology
0.8 µm CMOS IC technology
Applications
Motor phase and rail current sensing
Inverter current sensing
Switched mode power supply signal isolation
General purpose current sensing and monitoring
General purpose analog signal isolation
Functional Diagram
A 0.1 µF bypass capacitor must be connected
between pins 1 and 4 and between pins 5 and 8.
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
2
Ordering Information
HCPL-7840 is UL Recognized with 3750 Vrms for 1 minute per UL1577.
Option
Part RoHS non RoHS Surface Gull Tape IEC/EN/DIN
Number Compliant Compliant Package Mount Wing & Reel EN 60747-5-2 Quantity
-000E no option X 50 per tube
-300E #300 X X X 50 per tube
HCPL-7840 -500E #500 300 mil DIP-8 X X X X 1000 per reel
-060E #060 X 50 per tube
-360E #360 X X X 50 per tube
-560E #560 X X X X 1000 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
HCPL-7840-560E to order product of Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN
EN 60747-5-2 Safety Approval and RoHS compliant.
Example 2:
HCPL-7840 to order product of 300 mil DIP package in Tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since July 15, 2001 and
RoHS compliant will use ‘–XXXE.’
3
Note: Initial or continued variation in the color of the HCPL-7840’s white mold compound is normal and does not a ect device performance or
reliability.
Package Outline Drawings
Standard DIP Package
9.80 ± 0.25
(0.386 ± 0.010)
1.78 (0.070) MAX.
1.19 (0.047) MAX.
A 7840
YYWW
DATE CODE
1.080 ± 0.320
(0.043 ± 0.013) 2.54 ± 0.25
(0.100 ± 0.010)
0.51 (0.020) MIN.
0.65 (0.025) MAX.
4.70 (0.185) MAX.
2.92 (0.115) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.
5678
4321
5° TYP. 0.20 (0.008)
0.33 (0.013)
7.62 ± 0.25
(0.300 ± 0.010)
6.35 ± 0.25
(0.250 ± 0.010)
3.56 ± 0.13
(0.140 ± 0.005)
4
Gull Wing Surface Mount Option 300
0.635 ± 0.25
(0.025 ± 0.010) 12° NOM.
9.65 ± 0.25
(0.380 ± 0.010)
0.635 ± 0.130
(0.025 ± 0.005)
7.62 ± 0.25
(0.300 ± 0.010)
5
6
7
8
4
3
2
1
9.80 ± 0.25
(0.386 ± 0.010)
6.350 ± 0.25
(0.250 ± 0.010)
1.016 (0.040)
1.27 (0.050)
10.9 (0.430)
2.0 (0.080)
LAND PATTERN RECOMMENDATION
1.080 ± 0.320
(0.043 ± 0.013)
3.56 ± 0.13
(0.140 ± 0.005)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
2.54
(0.100)
BSC
NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.
DIMENSIONS IN MILLIMETERS (INCHES).
TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01
xx.xxx = 0.005
A 7840
YYWW
LEAD COPLANARITY
MAXIMUM: 0.102 (0.004)
0.20 (0.008)
0.33 (0.013)
5
Solder Re ow Temperature Pro le
Recommended Pb-Free IR Pro le
0
TIME (SECONDS)
TEMPERATURE (°C)
200
100
50 150100 200 250
300
0
30
SEC.
50 SEC.
30
SEC.
160°C
140°C
150°C
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C
PEAK
TEMP.
230°C
SOLDERING
TIME
200°C
PREHEATING TIME
150°C, 90 + 30 SEC.
2.5°C ± 0.5°C/SEC.
3°C + 1°C/–0.5°C
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
217 °C
RAMP-DOWN
6 °C/SEC. MAX.
RAMP-UP
3 °C/SEC. MAX.
150 - 200 °C
260 +0/-5 °C
t 25 °C to PEAK
60 to 150 SEC.
20-40 SEC.
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
t
p
t
s
PREHEAT
60 to 180 SEC.
t
L
T
L
T
smax
T
smin
25
T
p
TIME
TEMPERATURE
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
T
smax
= 200 °C, T
smin
= 150 °C
Note: Non-halide  ux should be used..
Note: Non-halide  ux should be used.
6
Regulatory Information
The HCPL-7840 has been approved by the following organizations:
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884
Teil 2):2003-01.
UL
Approval under UL 1577, com-
ponent recognition program up to
VISO = 3750 Vrms.
CSA
Approved under CSA Component Ac-
ceptance Notice #5, File CA 88324.
IEC/EN/DIN EN 60747-5-2 Insulation Characteristics*
Description Symbol Characteristic Unit
Installation classi cation per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤300 Vrms I-IV
for rated mains voltage ≤600 Vrms I-III
Climatic Classi cation 55/100/21
Pollution Degree (DIN VDE 0110/1.89) 2
Maximum Working Insulation Voltage VIORM 891 VPEAK
Input to Output Test Voltage, Method b**
VIORM x 1.875 = VPR, 100% Production Test with VPR 1670 VPEAK
tm = 1 sec, Partial discharge < 5 pC
Input to Output Test Voltage, Method a**
VIORM x 1.5 = VPR, Type and Sample Test, VPR 1336 VPEAK
tm = 60 sec, Partial discharge < 5 pC
Highest Allowable Overvoltage VIOTM 8000 VPEAK
(Transient Overvoltage tini = 10 sec)
Safety-limiting values—maximum values
allowed in the event of a failure.
Case Temperature TS 175 °C
Input Current*** IS,INPUT 400 mA
Output Power*** PS,OUTPUT 600 mW
Insulation Resistance at TS, VIO = 500 V RS >109
*Insulation characteristics are guaranteed only within the safety maximum ratings which must
be ensured by protective circuits within the application. Surface Mount Classi cation is Class A
in accordance with CECC00802.
**Refer to the optocoupler section of the Isolation and Control Components Designer’s Cata-
log, under Product Safety Regulations section, IEC/EN/DIN EN 60747-5-2, for a detailed descrip-
tion of Method a and Method b partial discharge test pro les.
***Refer to the following  gure for dependence of PS and IS on ambient temperature.
OUTPUT POWER - P S, INPUT CURRENT - IS
0
0
TA - CASE TEMPERATURE - oC
20050
400
12525 75 100 150
600
800
200
100
300
500
700
175
PS (mW)
IS (mA)
7
Insulation and Safety Related Speci cations
Parameter Symbol Value Unit Conditions
Minimum External Air Gap
(Clearance)
L(101) 7.4 mm Measured from input terminals to output
terminals, shortest distance through air.
Minimum External Tracking
(Creepage)
L(102) 8.0 mm Measured from input terminals to output
terminals, shortest distance path along body.
Minimum Internal Plastic Gap
(Internal Clearance)
0.5 mm Through insulation distance conductor to
conductor, usually the straight line distance
thickness between the emitter and detector.
Tracking Resistance
(Comparative Tracking Index)
CTI >175 Volts DIN IEC 112/VDE 0303 Part 1
Isolation Group III a Material Group
(DIN VDE 0110, 1/89, Table 1)
Absolute Maximum Ratings
Parameter Symbol Min. Max. Unit Note
Storage Temperature TS-55 125 °C
Operating Temperature TA- 40 100
Supply Voltage VDD1, VDD2 0 5.5 V
Steady-State Input Voltage
2 Second Transient Input Voltage
VIN+, VIN- -2.0 VDD1 +0.5
-6.0 VDD1 +0.5
Output Voltage VOUT -0.5 VDD2 +0.5
Solder Re ow Temperature Pro le See Solder Re ow Temperature Pro le Section
Recommended Operating Conditions
Parameter Symbol Min. Max. Unit Note
Ambient Operating Temperature TA-40 85 °C
Supply Voltage VDD1, VDD2 4.5 5.5 V
Input Voltage (accurate and linear) VIN+, VIN- -200 200 mV 1
Input Voltage (functional) VIN+, VIN- -2 2 V
8
DC Electrical Speci cations
Unless otherwise noted, all typicals and  gures are at the nominal operating conditions of VIN+ = 0, VIN- = 0 V, VDD1 = VDD2
= 5 V and TA = 25°C; all Min./Max. speci cations are within the Recommended Operating Conditions.
Parameter Symbol Min. Typ. Max. Unit Test Conditions Fig. Note
Input O set Voltage VOS -2.0 0.3 2.0 mV TA = 25°C 1,2
-3.0 3.0 mV TA = -40°C to +85°C 1,2
Magnitude of Input
O set Change vs.
Temperature
|∆VOS/∆TA| 3.0 10.0 µV/°C 3 2
Gain (± 5% Tol.) G 7.60 8.00 8.40 V/V -200 mV < VIN+ < 200 mV,
TA = 25°C
4,5,6 3
Magnitude of VOUT
Gain Change vs.
Temperature
|∆G/∆TA| 0.00025 V/V/°C 4
VOUT 200 mV Nonlinearity NL200 0.0037 0.35 % -200 mV < VIN+ < 200 mV 7,8 5
Magnitude of VOUT 200 mV
Nonlinearity Change
vs. Temperature
|dNL200/dT| 0.0002 % / °C
VOUT 100 mV Nonlinearity NL100 0.0027 0.2 % -100 mV < VIN+ < 100 mV 6
Maximum Input
Voltage before
VOUT Clipping
|VIN+|MAX 308.0 mV 9
Input Supply Current IDD1 10.86 15.5 mA VIN+ = 400 mV 10 7
Output Supply Current IDD2 11.56 15.5 VIN+ = -400 mV 8
Input Current IIN+ -0.5 5.0 µA 11 9
Magnitude of Input
Bias Current vs.
Temperature
Coe cient
|dIIN/dT| +0.45 nA/°C 11
Output Low Voltage VOL 1.29 V 10
Output High Voltage VOH 3.80 V 10
Output Common-Mode
Voltage
VOCM 2.2 2.545 2.8 V
Output Short-Circuit
Current
|IOSC| 18.6 mA 11
Equivalent Input Impedance RIN 500 k
VOUT Output Resistance ROUT 15
Input DC Common-Mode
Rejection Ratio
CMRRIN 76.1 dB 12
9
AC Electrical Speci cations
Unless otherwise noted, all typicals and  gures are at the nominal operating conditions of VIN+ = 0, VIN- = 0 V, VDD1 =
VDD2 = 5 V and TA = 25°C; all Min./Max. speci cations are within the Recommended Operating Conditions.
Parameter Symbol Min. Typ. Max. Unit Test Conditions Fig. Note
VOUT Bandwidth (-3 dB) BW 50 100 kHz VIN+ = 200 mVpk-pk
sine wave.
12,13
VOUT Noise NOUT 31.5 mVrms VIN+ = 0.0 V 13
VIN to VOUT Signal Delay
(50 – 10%)
tPD10 2.03 3.3 µs Measured at output of
MC34081 on Figure 15.
VIN+ = 0 mV to 150 mV
step.
14,15
VIN to VOUT Signal Delay
(50 – 50%)
tPD50 3.47 5.6
VIN to VOUT Signal Delay
(50 – 90%)
tPD90 4.99 9.9
VOUT Rise/Fall Time
(10 – 90%)
tR/F 2.96 6.6
Common Mode Transient
Immunity
CMTI 10.0 15.0 kV/µs VCM = 1 kV, TA = 25°C 16 14
Power Supply Rejection PSR 170 mVrms With recommended
application circuit.
15
Package Characteristics
Parameter Symbol Min. Typ. Max. Unit Test Conditions Fig. Note
Input-Output Momentary
Withstand Voltage
VISO 3750 Vrms RH < 50%, t = 1 min.,
TA = 25°C
16,17
Resistance
(Input-Output)
RI-O >109V
I-O = 500 VDC 18
Capacitance
(Input-Output)
CI-O 1.2 pF F = 1 MHz 18
10
Notes:
General Note: Typical values represent the mean value of all characteriza-
tion units at the nominal operating conditions. Typical drift speci ca-
tions are determined by calculating the rate of change of the speci ed
parameter versus the drift pa-rameter (at nominal operating conditions)
for each characterization unit, and then averaging the individual unit
rates. The corresponding drift  gures are normalized to the nominal
operating conditions and show how much drift occurs as the par-ticular
drift parameter is varied from its nominal value, with all other param-
eters held at their nominal operating values. Note that the typical drift
speci cations in the tables below may di er from the slopes of the mean
curves shown in the corresponding  gures.
1. Avago recommends operation with VIN- = 0 V (tied to GND1).
Limiting VIN+ to 100 mV will improve DC nonlinearity and nonlinear-
ity drift. If VIN- is brought above VDD1 – 2 V, an internal test mode may
be activated. This test mode is for testing LED coupling and is not
intended for customer use.
2. This is the Absolute Value of Input O set Change vs. Temperature.
3. Gain is de ned as the slope of the best- t line of di erential output
voltage (VOUT+–VOUT- ) vs. di erential input voltage (VIN+–VIN-)
over the speci ed input range.
4. This is the Absolute Value of Gain Change vs. Temperature.
5. Nonlinearity is de ned as half of the peak-to-peak output deviation
from the best- t gain line, expressed as a percentage of the full-scale
di erential output voltage.
6. NL100 is the nonlinearity speci ed over an input voltage range of
±100 mV.
7. The input supply current decreases as the di erential input voltage
(VIN+–VIN-) decreases.
8. The maximum speci ed output supply current occurs when the
di erential input voltage (VIN+–VIN-) = -200 mV, the maximum rec-
ommended operat-ing input voltage. However, the out-put supply
current will continue to rise for di erential input voltages up to
approximately -300 mV, beyond which the output supply current
remains constant.
9. Because of the switched-capacitor nature of the input sigma-delta
con-verter, time-averaged values are shown.
10. When the di erential input signal exceeds approximately 308 mV,
the outputs will limit at the typical values shown.
11. Short circuit current is the amount of output current generated
when either output is shorted to VDD2 or ground.
12. CMRR is defined as the ratio of the differential signal
gain (signal applied differentially between pins 2 and 3)
to the common-mode gain (input pins tied together and the signal
applied to both inputs at the same time), expressed in dB.
13. Output noise comes from two primary sources: chopper noise
and sigma-delta quantization noise. Chopper noise results from
chopper stabilization of the output op-amps. It occurs at a speci c
frequency (typically 400 kHz at room temperature), and is not at-
tenuated by the internal output  lter. A  lter circuit can be easily
added to the external post-ampli er to reduce the total rms output
noise. The internal output  lter does eliminate most, but not
all, of the sigma-delta quantization noise. The magnitude of the
output quantization noise is very small at lower frequencies (below
10 kHz) and increases with increasing frequency.
14. CMTI (Common Mode Transient Immunity or CMR, Common Mode
Rejection) is tested by applying an exponentially rising/falling
voltage step on pin 4 (GND1) with respect to pin 5 (GND2). The rise
time of the test waveform is set to approximately 50 ns. The ampli-
tude of the step is adjusted until the di erential output (VOUT+–VOUT-)
exhibits more than a 200 mV deviation from the average output
voltage for more than 1µs. The HCPL-7840 will continue to func-tion
if more than 10 kV/µs common mode slopes are applied, as
long as the breakdown voltage limitations are observed.
15. Data sheet value is the di erential amplitude of the transient at the
output of the HCPL-7840 when a 1 Vpk-pk, 1 MHz square wave with
40 ns rise and fall times is applied to both VDD1 and VDD2.
16. In accordance with UL 1577, each optocoupler is proof tested by ap-
plying an insulation test voltage ≥4500 Vrms for 1 second (leakage
detection current limit, II-O ≤ 5 µA). This test is performed before the
100% production test for partial discharge (method b) shown in
IEC/EN/DIN EN 60747-5-2 Insulation Characteristic Table.
17. The Input-Output Momentary With stand Voltage is a dielectric
voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer
to the VDE 0884 insula tion characteristics table and your equipment
level safety speci cation.
18. This is a two-terminal measurement: pins 1–4 are shorted together
and pins 5–8 are shorted together.
11
Figure 3. Input o set vs. supply. Figure 4. Gain vs. temperature.
Figure 1. Input o set voltage test circuit.
Figure 2. Input o set voltage vs. temperature.
Figure 5. Gain and nonlinearity test circuit.
0.1 µF
V
DD2
V
OUT
8
7
6
1
3
HCPL-7840
5
2
4
0.1 µF
10 K
10 K
V
DD1
+15 V
0.1 µF
0.1 µF
-15 V
+
–AD624CD
GAIN = 100
0.47
µF
0.47
µF
0.1 µF
V
DD2
8
7
6
1
3
HCPL-7840
5
2
4
0.01 µF
10 K
10 K
+15 V
0.1 µF
0.1 µF
-15 V
+
–AD624CD
GAIN = 4
0.47
µF
0.47
µF
V
DD1
13.2
404
V
IN
V
OUT
+15 V
0.1 µF
0.1 µF
-15 V
+
–AD624CD
GAIN = 10
10 K
0.47
µF
0.1 µF
VOLTAGE
TA – TEMPERATURE – °C
0.6
0.5
0.3
-25
0.8
35 95
0.2
0.7
-55 125
0.4
565
INPUT OFFSET
VDD – SUPPLY VOLTAGE – V
0.37
0.36
0.39
4.75 5.0
0.33
vs. VDD1
4.5 5.55.25
vs. VDD2
0.34
0.38
0.35
GAIN
TA – TEMPERATURE – °C
8.025
8.02
8.015
-35
8.035
25 85
8.01
8.03
-55 1255 45 105
-15 65
12
GAIN
VDD – SUPPLY VOLTAGE – V
8.028
8.032
4.75 5.0
8.024
4.5 5.55.25
8.03
8.026
vs. VDD1
vs. VDD2
NONLINEARITY
TA – TEMPERATURE – °C
0.02
0.015
0.005
-25
0.03
35 95
0
0.025
-55 125
0.01
565
PROPAGATION DELAY
TA – TEMPERATURE – °C
3.1
-25
5.5
56595
1.5
4.7
-55 125
3.9
2.3
35
Tpd 10
Tpd 50
Tpd 90
Tpd rise
VO – OUTPUT VOLTAGE – V
VIN – INPUT VOLTAGE – V
2.6
1.8
-0.3
4.2
-0.1 0.1 0.3
VOP
VOR
1.0
3.4
-0.5 0.5
NONLINEARITY
VDD – SUPPLY VOLTAGE – V
0.005
4.75 5.0
0.002
4.5 5.55.25
0.004
0.003
vs. VDD1
vs. VDD2
SUPPLY CURRENT
VIN – INPUT VOLTAGE – V
7
-0.3
13
-0.1 0.1 0.3
4
10
-0.5 0.5
IDD1
IDD2
INPUT CURRENT
VIN – INPUT VOLTAGE – V
-3
-0.4
0
-0.2 0.2 0.4
-5
-1
-0.6 0.6
-2
-4
0
GAIN - dB
FREQUENCY (Hz)
-2
1
-4
0
10 100000
-1
-3
1000
100 10000
PHASE - DEGREES
FREQUENCY (Hz)
-100
50
-300
0
10 100000
-50
-150
1000
-200
-250
100 10000
Figure 12. Gain vs. frequency. Figure 13. Phase vs. frequency. Figure 14. Propagation delay vs. temperature.
Figure 6. Gain vs. supply. Figure 7. Nonlinearity vs. temperature. Figure 8. Nonlinearity vs. supply.
Figure 9. Output voltage vs. input voltage. Figure 10. Supply current vs. input voltage. Figure 11. Input current vs. input voltage.
13
Figure 16. CMTI test circuits.
Figure 15. Propagation delay test circuits.
0.1 µF
V
DD2
V
OUT
8
7
6
1
3
HCPL-7840
5
2
4
2 K
2 K
+15 V
0.1 µF
0.1 µF
-15 V
–
+MC34081
0.1 µF
10 K
10 K
0.01 µF
V
DD1
V
IN
V
IN
IMPEDANCE LESS THAN 10 Ω.
0.1 µF
V
DD2
V
OUT
8
7
6
1
3
HCPL-7840
5
2
4
2 K
2 K
78L05
+15 V
0.1 µF
0.1 µF
-15 V
–
+MC34081
150
pF
IN OUT
0.1
µF
0.1
µF
9 V
PULSE GEN.
V
CM
+–
10 K
10 K
150 pF
14
Application Information
Power Supplies and Bypassing
The recommended supply con-nections are shown
in Figure 17. A  oating power supply (which in many
applications could be the same supply that is used to
drive the high-side power transistor) is regulated to 5
V using a simple zener diode (D1); the value of resistor
R4 should be chosen to supply su cient current from
the existing  oating supply. The voltage from the current
sensing resistor (Rsense) is applied to the input of the
HCPL-7840 through an RC anti-aliasing  lter (R2 and C2).
Although the application circuit is relatively simple, a few
recommendations should be followed to ensure optimal
performance.
The power supply for the HCPL -7840 is most often ob-
tained from the same supply used to power the power
transistor gate drive circuit. If a dedicated supply is re-
quired, in many cases it is possible to add an additional
winding on an existing transformer. Otherwise, some
sort of simple isolated supply can be used, such as a
line powered transformer or a high-frequency DC-DC
converter.
An inexpensive 78L05 three-terminal regulator can also
be used to reduce the  oating supply voltage to 5 V. To
help attenuate high-frequency power supply noise or
ripple, a resistor or inductor can be used in series with
the input of the regulator to form a low-pass  lter with
the regulator’s input bypass capacitor.
Figure 17. Recommended supply and sense resistor connections.
HCPL-7840
C1
0.1 µF
R2
39 Ω
GATE DRIVE
CIRCUIT
FLOATING
POWER
SUPPLY
• • •
HV+
• • •
HV–
• • • –+
RSENSE
MOTOR
C2
0.01 µF
D1
5.1 V
–
+
R1
15
As shown in Figure 18, 0.1 µF bypass capacitors (C1, C2)
should be located as close as possible to the pins of the
HCPL-7840. The bypass capacitors are required because
of the high-speed digital nature of the signals inside the
HCPL-7840. A 0.01 µF bypass capacitor (C2) is also rec-
ommended at the input due to the switched-capacitor
also forms part of the anti-aliasing  lter, which is recom-
mended to prevent high-frequency noise from aliasing
down to lower frequencies and interfering with the input
signal. The input  lter also performs an important reliabil-
ity function—it reduces transient spikes from ESD events
owing through the current sensing resistor.
Figure 18: Recommended application circuit.
PC Board Layout
The design of the printed circuit board (PCB) should follow
good layout practices, such as keeping bypass capacitors
close to the supply pins, keeping output signals away
from input signals, the use of ground and power planes,
etc. In addition, the layout of the PCB can also a ect the
isolation transient immunity (CMTI) of the HCPL-7840,
due primarily to stray capacitive coupling between the
input and the output circuits. To obtain optimal CMTI
performance, the layout of the PC board should minimize
any stray coupling by maintaining the maximum possible
distance between the input and output sides of the circuit
and ensuring that any ground or power plane on the PC
board does not pass directly below or extend much wider
than the body of the HCPL-7840.
Figure 19. Example printed circuit board layout.
C3
C2 C4
R5
TO R
SENSE+
TO R
SENSE–
TO V
DD1
TO V
DD2
V
OUT+
V
OUT–
16
Figure 20. Motor output horsepower vs. motor
phase current and supply voltage.
the output voltage across the resistor is also reduced,
which means that the o set and noise, which are  xed,
become a larger percentage of the signal amplitude. The
selected value of the sense resistor will fall somewhere
between the minimum and maximum values, depending
on the particular requirements of a speci c design.
When sensing currents large enough to cause signi cant
heating of the sense resistor, the temperature coe cient
(tempco) of the resistor can introduce nonlinearity due
to the signal dependent temperature rise of the resistor.
The e ect increases as the resistor-to-ambient ther-mal
resistance increases. This e ect can be minimized by
reducing the thermal resistance of the current sensing
resistor or by using a resistor with a lower tempco. Lower-
ing the thermal resistance can be accomplished by repo-
sitioning the current sensing resistor on the PC board, by
using larger PC board traces to carry away more heat, or
by using a heat sink.
For a two-terminal current sensing resistor, as the value
of resistance decreases, the re-sistance of the leads
become a signi cant percentage of the total resistance.
This has two primary e ects on resistor accuracy. First,
the e ective resistance of the sense resistor can become
dependent on factors such as how long the leads are, how
they are bent, how far they are inserted into the board,
and how far solder wicks up the leads during assembly
(these issues will be discussed in more detail shortly).
Second, the leads are typically made from a material, such
as copper, which has a much higher tempco than the
material from which the resistive element itself is made,
resulting in a higher tempco overall.
Both of these e ects are eliminated when a four-terminal
current sensing resistor is used. A four-terminal resistor
has two additional terminals that are Kelvin-connected
directly across the resistive element itself; these two ter-
minals are used to monitor the voltage across the resistive
element while the other two terminals are used to carry
the load current. Because of the Kelvin connection, any
voltage drops across the leads carrying the load current
should have no impact on the measured voltage.
When laying out a PC board for the current
sensing resistors, a couple of points should be kept
in mind. The Kelvin connections to the resistor should
be brought together under the body of the resistor
and then run very close to each other to the input of
the HCPL-7840; this minimizes the loop area of the
connection and reduces the possibility of stray mag-
netic  elds from interfering with the measured signal. If
the sense resistor is not located on the same PC board as
the HCPL-7840 circuit, a tightly twisted pair of wires can
accomplish the same thing.
Current Sensing Resistors
The current sensing resistor should have low resistance
(to minimize power dissipation), low inductance (to
minimize di/dt induced voltage spikes which could
adversely a ect operation), and reasonable tolerance
(to maintain overall circuit accuracy). Choosing a par-
ticular value for the resistor is usually a compro-mise
between minimizing power dissipation and maximiz-
ing accu-racy. Smaller sense resistance decreases
power dissipation, while larger sense resistance
can improve circuit accuracy by utilizing the full input
range of the HCPL -7840.
The  rst step in selecting a sense resistor is determining
how much current the resistor will be sensing. The graph
in Figure 20 shows the RMS current in each phase of a
three-phase induction motor as a function of average
motor output power (in horse-power, hp) and motor
drive supply voltage. The maximum value of the sense
re-sistor is determined by the current being measured
and the maxi-mum recommended input voltage of the
isolation ampli er. The maximum sense resistance can
be calculated by taking the maxi-mum recommended
input voltage and dividing by the peak current that the
sense resistor should see during normal operation. For
example, if a motor will have a maximum RMS current
of 10 A and can experience up to 50% overloads during
normal op-eration, then the peak current is 21.1 A (=10 x
1.414 x 1.5). Assuming a maximum input voltage of 200
mV, the maximum value of sense resistance in this case
would be about 10 mΩ.
The maximum average power dissipation in the sense
resistor can also be easily calculated by multiplying the
sense resistance times the square of the maximum RMS
current, which is about 1 W in the previous example. If
the power dissipation in the sense resistor is too high, the
resistance can be decreased below the maximum value to
decrease power dissipation. The minimum value of the
sense resistor is limited by precision and accuracy require-
ments of the design. As the resistance value is reduced,
MOTOR PHASE CURRENT – A (rms)
15
5
40
10 25 30
0
35
035
25
10
20
440 V
380 V
220 V
120 V
30
20
5
15
17
Also, multiple layers of the PC board can be used to
increase current carrying capacity. Numerous plated-
through vias should surround each non-Kelvin terminal of
the sense resistor to help distribute the current between
the layers of the PC board. The PC board should use 2 or
4 oz. copper for the layers, resulting in a current carrying
capacity in excess of 20 A. Making the current carrying
traces on the PC board fairly large can also improve the
sense resistor’s power dissipation capability by acting as a
heat sink. Liberal use of vias where the load current enters
and exits the PC board is also recommended.
Sense Resistor Connections
The recommended method for connecting the HCPL-7840
to the current sensing resistor is shown in Figure 18. VIN+
(pin 2 of the HPCL-7840) is connected to the positive
terminal of the sense resistor resistor, while VIN- (pin 3) is
shorted to GND1 (pin 4), with the power-supply return
path functioning as the sense line to the negative termi-
nal of the current sense resistor. This allows a single pair
of wires or PC board traces to connect the HCPL-7840
circuit to the sense resistor. By referencing the input
circuit to the negative side of the sense resistor, any load
current induced noise transients on the resistor are seen
as a common-mode signal and will not interfere with the
current-sense signal. This is important because the large
load currents  owing through the motor drive, along with
the parasitic inductances inherent in the wiring of the
circuit, can generate both noise spikes and o sets that are
relatively large compared to the small voltages that are
being measured across the current sensing resistor.
If the same power supply is used both for the gate drive
circuit and for the current sensing circuit, it is very impor-
tant that the connection from GND1 of the HCPL-7840
to the sense resistor be the only return path for supply
current to the gate drive power supply in order to elimi-
nate potential ground loop problems. The only direct
connection between the HCPL-7840 circuit and the gate
drive circuit should be the positive power supply line.
Output Side
The op-amp used in the external post-ampli er circuit
should be of su ciently high precision so that it does not
contribute a signi cant amount of o set or o set drift
relative to the contribution from the isolation ampli er.
Generally, op-amps with bipolar input stages exhibit
better o set performance than op-amps with JFET or
MOSFET input stages.
In addition, the op-amp should also have enough
bandwidth and slew rate so that it does not adversely
a ect the response speed of the overall circuit. The
post-ampli er circuit includes a pair of capacitors (C5
and C6) that form a single-pole low-pass  lter; these
capacitors allow the bandwidth of the post-amp to
be adjusted independently of the gain and are useful for
reducing the output noise from the isola-tion ampli er.
Many di erent op-amps could be used in the circuit,
including: MC34082A (Motorola), TLO32A, TLO52A, and
TLC277 (Texas Instruments), LF412A (National Semicon-
ductor).
The gain-setting resistors in the post-amp should have a
tolerance of 1% or better to ensure adequate CMRR and
adequate gain toler-ance for the overall circuit. Resistor
networks can be used that have much better ratio toler-
ances than can be achieved using discrete resistors. A
resistor network also reduces the total number of com-
ponents for the circuit as well as the required board space.
Please refer to Avago Applications Note 1078 for addi-
tional information on using Isolation Ampli ers.
18
FREQUENTLY ASKED QUESTIONS ABOUT THE HCPL-7840
1. THE BASICS
1.1: Why should I use the HCPL-7840 for sensing current when Hall-e ect sensors are available which don’t need an
isolated supply voltage?
Available in an auto-insertable, 8-pin DIP package, the HCPL-7840 is smaller than and has better linearity, o set vs.
temperature and Common Mode Rejection (CMR) performance than most Hall-e ect sensors. Additionally, often
the required input-side power supply can be derived from the same supply that powers the gate-drive optocoupler.
2. SENSE RESISTOR AND INPUT FILTER
2.1: Where do I get 10 mΩ resistors? I have never seen one that low.
Although less common than values above 10 Ω, there are quite a few manufacturers of resistors suitable for
measuring currents up to 50 A when combined with the HCPL- 7840.
Example product information may be found at Dale’s web site (http://www.vishay.com/vishay/dale) and Isotek’s
web site (http://www.isotekcorp.com).
2.2: Should I connect both inputs across the sense resistor instead of grounding VIN- directly to pin 4?
This is not necessary, but it will work. If you do, be sure to use an RC  lter on both pin 2 (VIN+) and pin 3 (VIN-) to
limit the input voltage at both pads.
2.3: Do I really need an RC  lter on the input? What is it for? Are other values of R and C okay?
The input anti-aliasing  lter (R=39 Ω, C=0.01 µF) shown in the typical application circuit is recommended for  l-
tering fast switching voltage transients from the input signal. (This helps to attenuate higher signal frequencies
which could otherwise alias with the input sampling rate and cause higher input o set voltage.)
Some issues to keep in mind using di erent lter resistors or capacitors are:
1. (Filter resistor:) Input bias current for pins 2 and 3: This is on the order of 500 nA. If you are using a single  lter
resistor in series with pin 2 but not pin 3 the IxR drop across this resistor will add to the o set error of the device.
As long as this IR drop is small compared to the input o set voltage there should not be a problem. If larger-
valued resistors are used in series, it is better to put half of the resistance in series with pin 2 and half the resistance
in series with pin 3. In this case, the o set voltage is due mainly to resistor mismatch (typically less than 1% of
the resistance design value) multiplied by the input bias.
2. (Filter resistor:) The equivalent input resistance for -7840 is around 500 kΩ. It is therefore best to ensure
that the  lter resistance is not a signi cant percentage of this value; otherwise the o set voltage will
be increased through the resistor divider e ect. [As an example, if R lt = 5.5 kΩ, then VOS = (Vin * 1%) =
2 mV for a maximum 200 mV input and VOS will vary with respect with Vin.]
3. The input bandwidth is changed as a result of this di erent R-C  lter con guration. In fact this is one of the main
reasons for changing the input- lter R-C time constant.
4. (Filter capacitance:) The input capacitance of the -78XX is approximately 1.5 pF. For proper operation the switch-
ing input-side sampling capacitors must be charged from a relatively  xed (low impedance) voltage source.
Therefore, if a  lter capacitor is used it is best for this capacitor to be a few orders of magnitude greater than the
CINPUT (A value of at least 100 pF works well.)
2.4: How do I ensure that the HCPL-7840 is not destroyed as a result of short circuit conditions which cause voltage
drops across the sense resistor that exceed the ratings of the HCPL-7840’s inputs?
Select the sense resistor so that it will have less than 5 V drop when short circuits occur. The only other require-
ment is to shut down the drive before the sense resistor is damaged or its solder joints melt. This ensures that the
input of the HCPL-7840 can not be damaged by sense resistors going open-circuit.
For product information and a complete list of distributors, please go to our website: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. Obsoletes AV01-0569EN
AV02-1289EN - July 9, 2012
3. ISOLATION AND INSULATION
3.1: How many volts will the HCPL-7840 withstand?
The momentary (1 minute) withstand voltage is 3750 V rms per UL 1577 and CSA Component Acceptance
Notice #5.
4. ACCURACY
4.1: Can the signal to noise ratio be improved?
Yes. Some noise energy exists beyond the 100 kHz bandwidth of the HCPL-7800(A). Additional  ltering using dif-
ferent  lter R,C values in the post-ampli er application circuit can be used to improve the signal to noise ratio. For
example, by using values of R3 = R4 = 10 kΩ, C5 = C6 = 470 pF in the application circuit the rms output noise will
be cut roughly by a factor of 2. In applications needing only a few kHz bandwidth even better noise performance
can be obtained. The noise spectral density is roughly 500 nV/√ Hz below 20 kHz (input referred).
4.2: I need 1% tolerance on gain. Does Avago sell a more precise version?
The HCPL-7800A is gain-trimmed and matched to within ±1% tolerance (at room temperature.)
4.3: Does the gain change if the internal LED light output degrades with time?
No. The LED is used only to transmit a digital pattern. Avago has accounted for LED degradation in the design
of the product to ensure long life.
5. POWER SUPPLIES AND START-UP
5.1: What are the output voltages before the input side power supply is turned on?
V
O+ is close to 1.29 V and VO- is close to 3.80 V. This is equivalent to the output response at the condition that LED
is completely o .
5.2: How long does the HCPL-7840 take to begin working properly after power-up?
Within 1 ms after VDD1 and VDD2 powered the device starts to work. But it takes longer time for output to settle down
completely. In case of the o set measurement while both inputs are tied to ground there is initially VOS adjustment
(about 60 ms). The output completely settles down in 100 ms after device powering up.
6. MISCELLANEOUS
6.1: How does the HCPL-7840 measure negative signals with only a +5 V supply?
The inputs have a series resistor for protection against large negative inputs. Normal signals are no more than 200
mV in amplitude. Such signals do not forward bias any junctions su ciently to interfere with accurate operation
of the switched capacitor input circuit.