DATA SH EET
Product specification
File under Integrated Circuits, IC04 January 1995
INTEGRATED CIRCUITS
HEF4066B
gates
Quadruple bilateral switches
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995 2
Philips Semiconductors Product specification
Quadruple bilateral switches HEF4066B
gates
DESCRIPTION
The HEF4066B has four independent bilateral analogue
switches (transmission gates). Each switch has two
input/output terminals (Y/Z) and an active HIGH enable
input (E). When E is connected to VDD a low impedance
bidirectional path between Y and Z is established (ON
condition). When E is connected to VSS the switch is
disabled and a high impedance between Y and Z is
established (OFF condition).
The HEF4066B is pin compatible with the HEF4016B but
exhibits a much lower ON resistance. In addition the ON
resistance is relatively constant over the full input signal
range.
Fig.1 Functional diagram. Fig.2 Pinning diagram.
HEF4066BP(N): 14-lead DIL; plastic (SOT27-1)
HEF4066BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73))
HEF4066BT(D): 14-lead SO; plastic (SOT108-1)
( ): Package Designator North America
PINNING
APPLICATION INFORMATION
An example of application for the HEF4066B is:
•Analogue and digital switching
E0to E3enable inputs
Y0to Y3input/output terminals
Z0to Z3input/output terminals
Fig.3 Schematic diagram (one switch).
January 1995 3
Philips Semiconductors Product specification
Quadruple bilateral switches HEF4066B
gates
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
DC CHARACTERISTICS
Tamb =25°C
Power dissipation per switch P max. 100 mW
For other RATINGS see Family Specifications
VDD
VSYMBOL MIN. TYP. MAX. CONDITIONS
ON resistance 5RON
−350 2500 ΩEnat VDD
10 −80 245 ΩVis =V
SS to VDD
15 −60 175 Ωsee Fig.4
ON resistance 5RON
−115 340 ΩEnat VDD
10 −50 160 ΩVis =V
SS
15 −40 115 Ωsee Fig.4
ON resistance 5RON
−120 365 ΩEnat VDD
10 −65 200 ΩVis =V
DD
15 −50 155 Ωsee Fig.4
‘∆’ ON resistance 5 ∆RON
−25 −Ω E
n
at VDD
between any two 10 −10 −Ω V
is =V
SS to VDD
channels 15 −5−Ω see Fig.4
OFF state leakage 5 IOZ
−−−nA Enat VSS
current, any 10 −−−nA
channel OFF 15 −−200 nA
Eninput voltage 5 VIL
−2,25 1 V Iis =10µA
see Fig.9
LOW 10 −4,50 2 V
15 −6,75 2 V
VDD
VSYMBOL Tamb (°c) CONDITIONS
−40 +25 +85
MAX. MAX. MAX.
Quiescent device 5 IDD
1,0 1,0 7,5 µAV
SS = 0; all valid
current 10 2,0 2,0 15,0 µA input combinations;
15 4,0 4,0 30,0 µAV
I
=V
SS or VDD
Input leakage current at En15 ±IIN −300 1000 nA Enat VSS or VDD
January 1995 4
Philips Semiconductors Product specification
Quadruple bilateral switches HEF4066B
gates
NOTE
To avoid drawing VDD current out of terminal Z, when switch current flows into terminals Y, the voltage drop across the
bidirectional switch must not exceed 0,4 V. If the switch current flows into terminal Z, no VDD current will flow out of
terminals Y, in this case there is no limit for the voltage drop across the switch, but the voltages at Y and Z may not
exceed VDD or VSS.
Fig.4 Test set-up for measuring RON.
Fig.5 Typical RON as a function of input voltage.
Enat VDD
Iis = 200 µA
VSS =0V
January 1995 5
Philips Semiconductors Product specification
Quadruple bilateral switches HEF4066B
gates
AC CHARACTERISTICS (1),(2)
VSS =0V; T
amb =25°C; input transition times ≤20 ns
VDD
VSYMBOL TYP. MAX.
Propagation delays
Vis →Vos 51020ns
note 3HIGH to LOW 10 tPHL 510ns
15 5 10 ns
51020ns
note 3LOW to HIGH 10 tPLH 510ns
15 5 10 ns
Output disable times
En→Vos 5 80 160 ns note 4HIGH 10 tPHZ 65 130 ns
15 60 120 ns
5 80 160 ns note 4LOW 10 tPLZ 70 140 ns
15 70 140 ns
Output enable times
En→Vos 54080ns
note 4HIGH 10 tPZH 20 40 ns
15 15 30 ns
54590ns
note 4LOW 10 tPZL 20 40 ns
15 15 30 ns
Distortion, sine-wave 5 0,25 % note 5response 10 0,04 %
15 0,04 %
Crosstalk between 5 −MHz note 6any two channels 10 1 MHz
15 −MHz
Crosstalk; enable 5 −mV note 7input to output 10 50 mV
15 −mV
OFF-state 5 −MHz note 8feed-through 10 1 MHz
15 −MHz
ON-state frequency 5 −MHz note 9response 10 90 MHz
15 −MHz
January 1995 6
Philips Semiconductors Product specification
Quadruple bilateral switches HEF4066B
gates
Notes
1. Vis is the input voltage at a Y or Z terminal, whichever is assigned as input.
2. Vos is the output voltage at a Y or Z terminal, whichever is assigned as output.
3. RL=10kΩto VSS; CL= 50 pF to VSS; En=V
DD;V
is =V
DD (square-wave); see Figs 6 and 10.
4. RL=10kΩ;C
L= 50 pF to VSS; En=V
DD (square-wave);
Vis =V
DD and RLto VSS for tPHZ and tPZH;
Vis =V
SS and RLto VDD for tPLZ and tPZL; see Figs 6 and 11.
5. RL=10kΩ; CL= 15 pF; En=V
DD; Vis =1⁄2VDD(p-p) (sine-wave, symmetrical about 1⁄2VDD); fis = 1 kHz; see Fig.7.
6. RL=1kΩ; Vis =1⁄2VDD(p-p) (sine-wave, symmetrical about 1⁄2VDD);
7. RL=10kΩto VSS; CL= 15 pF to VSS; En=V
DD (square-wave); crosstalk is Vos (peak value); see Fig.6.
8. RL=1kΩ; CL= 5 pF; En=V
SS; Vis =1⁄2VDD(p-p) (sine-wave, symmetrical about 1⁄2VDD);
9. RL=1kΩ; CL= 5 pF; En=V
DD; Vis =1⁄2VDD(p-p) (sine-wave, symmetrical about 1⁄2VDD);
VDD
VTYPICAL FORMULA FOR P (µW)
Dynamic power 5 800 fi+∑(foCL)×VDD 2where
dissipation per 10 3 500 fi+∑(foCL)×VDD 2fi= input freq. (MHz)
package (P) 15 10 100 fi+∑(foCL)×VDD 2fo= output freq. (MHz)
CL= load capacitance (pF)
∑(foCL) = sum of outputs
VDD = supply voltage (V)
20 log Vos(B)
Vis A()
------------------- -50 dB; En(A) VSS E;nB() V
DD; see Fig. 8.===
20 log Vos
Vis
--------- -50 dB; see Fig. 7.=
20 log Vos
Vis
--------- -3 dB; see Fig. 7.=
Fig.6 Fig.7
January 1995 7
Philips Semiconductors Product specification
Quadruple bilateral switches HEF4066B
gates
Fig.8
Fig.9
January 1995 8
Philips Semiconductors Product specification
Quadruple bilateral switches HEF4066B
gates
Fig.10 Waveforms showing propagation delays from Vis to Vos.
Fig.11 Waveforms showing output disable and enable times.
(1) Vis at VDD
(2) Vis at VSS.
