February 1989
Revised January 1999
74ACT2708 64 x 9 First-In, First-Out Memory
© 1999 Fairchild Semicond uctor Corpor ation DS010144.prf www.fairchildsemi.com
74ACT2708
64 x 9 Fir st-In, First-Out Memory
General Descript ion
The ACT2708 is an expandable first-in, first-out memory
organized as 64 words by 9 bits. An 85 MHz shift-in and 60
MHz shift-out typical data rate makes it ideal for high-speed
applications. It uses a dual port RAM architecture with
pointer logic to achieve the hig h speed with ne gligible fall-
through time.
Separate Sh ift-I n (SI) an d S hift -Ou t (SO) clocks cont rol the
use of synchronous or asynchronous write or read. Other
controls include a Master Reset (MR) and Output Enable
(OE) for initializing the internal registers and allowing the
data outpu ts to be 3-STATE. Input Ready (IR) and Outp ut
Ready (OR) signal when the FIFO is ready for I/O opera-
tions. The status flags HF and FULL indicate when the
FIFO is full, empty or half full.
The FIFO can be expanded to provide different word
lengths by tying off unused data inputs.
Features
■64-words by 9-bit dual port RAM organization
■85 MHz shift-in, 60 MHz shift-out data rate, typical
■Expandable in word width only
■TTL-compatible inputs
■Asynchronous or synchronous operation
■Asynchronous master reset
■Outputs source/sink 8 mA
■3-STATE outputs
■Full ESD pro tection
■Input and output pins directly in l ine for easy boar d lay-
out
■TRW 1030 work-alike operation
Applications
• High-speed disk or tape controllers
• A/D output buffers
• High-speed graphics pixel buffer
• Video time base correction
• Digital filtering
Ordering Code:
Device also available in Tape and Reel. Specify by app ending suff ix let te r “X” to the ordering code.
Connection Diagram
Pin Assignment for DIP
Pin Descriptions
FACT is a tradem ark of Fairchild S em ic onductor C orp orat ion.
Order Number Package Number Package Description
74ACT2708PC N28B 28-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600” Wide
Pin Names Description
D0–D8 Data Inputs
MR Master Reset
OE Output Enable Input
SI Shift-In
SO Shift-Out
IR Input Ready
OR Output Ready
HF Half Full Flag
FULL Full Flag
O0–O8 Data Outputs
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74ACT2708
Logic Symbol
Block Diagram
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74ACT2708
Functional Description
INPUTS
Data Inputs (D0–D8)
Data inputs for 9-bit wide data are TTL-compatible. Word
width can be reduced by trying unused inputs to ground
and leaving the corresponding outputs open.
Reset (MR)
Reset is accom plished by pulsing th e MR input LOW. Du r-
ing nor mal operation MR is HIGH. A re set is re quired after
power up to guarantee correct operation. On reset, the
data outputs go LOW, IR goes HIGH, OR goes LOW, FH
and FULL go LOW. During reset, both internal read and
write pointers are set to the first location in the array.
Shift-In (SI)
Data is written into the FIFO by pulsing SI HIGH. When
Shift-In go es HIGH, the data is l oad ed in to an i nte r n al da ta
latch. Data setup and hold times need to be adhered to
with respect to the falling edge of SI. The write cycle is
complete after the falling edge of SI. The shift-in is inde-
pendent of any ongoing shift-out operation. After the first
word has been writte n into the F IFO, the falling edge of SI
makes HF go HIGH, indicating a non-empty FIFO. The first
data word appears at the output after the falling edge of SI.
After half the memory is filled, the next rising edge of SI
makes FULL go HIGH indicating a half-full FIFO. When the
FIFO is full, any further shift-ins are disabled.
When th e FIFO is em pty and OE is LOW, the falling edge
of the first SI will cause the first data word just shifted-in to
appear at the output, even though SO may be LOW.
Shift-Out (SO)
Data is read from the FIFO by the Shift-Out signal provided
the FIFO is not empty. SO going HIGH causes OR to go
LOW indicating that output stage is busy. On the falling
edge of SO, new data reaches the output after propagation
delay tD. If the la st data has bee n shifted-o ut of the mem -
ory, OR continues to remain LOW, and the last word
shifted-out remains on the output pins.
Output Enable (OE)
OE LOW enables the 3-S TATE output buffers. When OE is
HIGH, the outputs are in a 3-STATE mode.
OUTPUTS
Data Outputs (O0–O8)
Data outputs are enabled when OE is LOW and in the 3-
STATE condition when OE is HIGH.
Input Ready (IR)
IR HIGH indicates data can be shifted-in. When SI goes
HIGH, IR goes LOW, indicating input stage is busy. IR
stays LOW when the FIFO is full and goes HIGH after the
f alling edge of the first shift-out.
Output Ready (OR)
OR HIGH i ndica tes dat a can be sh ifted -out f rom t he FI FO.
When SO goes HIGH, OR goes LOW, indicating output
stage is busy. OR is L OW when t he F IF O is r ese t or em pty
and goes HIGH after the falling edge of the first shift-in.
Half-Full (HF)
This status flag along with the FULL status flag indicates
the degree o f fullne ss of the F IFO. On reset, HF is LOW; it
rises on the falling edg e of the first SI. The rising edge of
the SI pulse that fills up the FIFO makes HF go LOW.
Going from the empty to the full state with SO LOW, the
falling edge of the first SI causes HF to go HIGH, the rising
edge o f the 33 rd SI causes FU LL t o go HIGH , and the ris-
ing edge of the 64th SI causes HF to go LOW.
When the FIFO is full, HF is LOW and the falling edge of
the first shift- out causes HF to g o HIGH indicating a “n on-
full” FIFO.
Full Flag (FULL)
This statu s flag alo ng with the HF status flag indicates the
degree of fullness of the FIFO. On reset, FULL is LOW.
When half the memory is filled, on the rising edge of the
next SI, the FULL flag goes HIGH. It remains set until the
difference between the write pointer and the read pointer is
less than or equal to one-half of the total memory of the
device. The FULL flag then goes LO W on the rising edge of
the next SO.
Status Flags Truth Table
H = HIGH Voltage Level
L = LOW Volt age Level
Reset Truth Table
H = HIGH Voltage Level
L = LOW Volt age Level
X = Immate r ial
HF FULL Status Flag Condition
L L Empty
L H Full
H L <32 Locations Filled
H H ≥32 Locations Filled
Inputs Outputs
MR SI SO IR OR HF FULL O0–O8
H X X X X X X X
L X X H L L L L
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74ACT2708
MODES OF OPERATION
Mode 1: Shift in Sequence f or FIFO Empty to Full
Sequence of Operation
1. Input Ready is initially HIGH; HF and FULL flags are
LOW. The FIFO is empty and prepared for valid data.
OR is LOW indicating that the FIFO is not yet ready to
output data .
2. S hift-In is s et HIGH, and dat a is loaded i nto the FIFO.
Data has to be settled ts before the falling edge of SI
and held th after.
3. I npu t Ready (IR) go es LOW propagati on delay tIR afte r
SI goes HIGH: input stage is busy.
4. S hift-In is set LOW; IR go es HIGH indicating the FIFO
is ready for ad ditional data. Data just shifted -in arrives
at output propagation delay tOD5 after SI falls. OR goes
HIGH propagation delay tIOR after SI goes LOW, indi-
cating th e FIFO has valid data on its outputs. H F goes
HIGH propagation delay tIEafter SI falls, indicating the
FIFO is no longer empty.
5. The process is repeated through the 64th data word.
On the rising edge of the 33rd SI, FULL flag goes HIGH
propagation delay tIHF after SI, indicating a half-full
FIFO. HF goes L OW propag ati o n de l ay tIF after the r is-
ing edge of the 64th pulse indicating that the FIFO is
full. Any further shift-ins are disabled.
Note: SO and O E are LOW; MR is HIGH. FIGURE 1. Modes of Operation Mode 1
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74ACT2708
Mode 2: Master Reset
Sequence of Operation
1. Input and Output Ready, HF and FULL can be in any
state before the reset sequence with Master Reset
(MR) HIGH.
2. Master Reset goes LOW and clears the FIFO, setting
up all essential internal states. Master Reset must be
LOW pulse width tMRW before rising again.
3. Master Reset rises.
4. IR r ises ( if not HI GH alrea dy) to indica te read y to wr ite
state rec overy time tMRIRH after the falling edge of MR.
Both HF and FULL will go LOW indicating an empty
FIFO, occurring re cover y times tMRE and tMRO respec-
tively after the falling edge of MR. OR falls recovery
time tMRORL afte r MR falls. Data at ou tputs g oes LOW
recovery time tMRONL after MR goes LOW.
5. Shift-In can be taken HIGH after a minimum recovery
time tMRSIH after MR goes HIGH.
FIGURE 2. Mode of Operation Mode 2
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74ACT2708
Mode 3: With FIFO Full, Shift-In is Held HIGH
in Anticipation of an Empty Location
Sequence of Operation
1. T he FIFO is initially full a nd Shift-In goes HIGH. O R is
initially HIGH. Shift-Out is LOW. IR is LOW.
2. Shift-Out is pulsed HIGH, Shift-Out pulse propagates
and the first d ata word is lat ched o n the ri sing edge of
SO. OR falls on this edge. On the falling edge of SO,
the sec ond d ata word a ppears afte r propag ation delay
tD. New data is written into the FIFO after SO goes
LOW.
3. Input Ready goes HIGH one fall-through time, tFT, after
the falling edge of SO. Also, HF goes HIGH one tOF
after SO falls, indicating that the FIFO is no longer full.
4. IR ret urns LOW puls e width t IP after rising and shifting
new data in. Also, HF returns LOW pulse width t3F after
rising, indicating the FIFO is once more full.
5. Shift-In is brought LOW to complete the shift-in process
and maintain normal operation.
Note: MR and FULL are HIG H; OE is LOW. FIGURE 3. Modes of Operation Mode 3
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74ACT2708
Mode 4: Shift-Out Sequence, FIFO Full to Empty
Sequence of Operation
1. FIFO is initially full and OR is HIGH, indicating valid
data is at the output. IR is LOW.
2. SO goes HI G H, re sul ting i n OR goi n g LOW on e pr op a-
gation delay, tOR, after SO rises. OR LOW indicates
output stage is busy.
3. SO goes L OW, new data rea ches outpu t one p ropag a-
tion delay, tD, after SO falls; OR goes HIGH one propa-
gation delay, tOR, after SO falls and HF rises one
propaga tion de lay, tOF, after SO falls. IR rises on e fall-
through time, tFT, after SO falls.
4. Repeat pro cess through the 6 4th SO pulse. FULL fl ag
goes LOW one propag ation del ay, t OHF, afte r t he r i sing
edge of 33rd SO, indicating that the FIFO is less than
half full. On the falling edge of the 64th SO, HF goes
LOW one propagation delay, tOE, after SO, indicating
the FIFO is empty. The SO pulse may rise and fall
again with an attempt to unload an empty FIFO. This
results in no change in the data on the outputs as the
64th word stays latched.
Note: SI and OE are L OW; MR is HIGH; D0–D8 are immate rial.
FIGURE 4. Modes of Operation Mode 4
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74ACT2708
Mode 5: With FIFO Empty, Shift-Out is Held HIGH
in Anticipation of Data
Sequence of Operation
1. FIFO is initially empty; Shift-Out goes HIGH.
2. S hift-In p ulse load s data into the F IFO and IR falls. HF
rises propagation delay tX1 after the falling edge of SI.
3. OR rises a fall-through time of tFTO after the falling
edge o f S h ift-I n, i ndica ti ng th at new da ta i s r ead y t o b e
output.
4. Data arrives at output one propagation delay, tOD5,
after the falling edge of Shift-In.
5. OR goes LOW pulse width tOP after rising and HF
goes LOW pulse width tX3 after rising, indicating that
the FIFO is empty once more.
6. Shift-Out goes LOW, necessary to complet e the Shift-
Out process.
Note: FULL is LOW; MRis HIGH; OE is LOW; tDOF = tFTO − tOD5. Da ta output transition—valid d ata arrives at output stage tDOF after OR is HIGH.
FIGURE 5. Modes of Operation Mode 5
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74ACT2708
FIFO Expansion
Word W idth Expansion
Word width can be increas ed by connecting the corr esp ond i ng inp ut con tro l sig nals of mult iple devices. Flags can be m on-
itored to obtain a composite signal by ANDing the corresponding flags.
Note: AND the correspon ding flags to obtain a com posite signal.
FIGURE 6. Word Width Expansion—64 x 18 FIFO
Vmi = 50 % VDD for AC/ACQ devices; 1.5V for ACT/ACTQ devices
Vmo = 50% VDD for AC/ACT, ACQ/ACTQ devi ces
FIGURE 7. 3-STATE Output Low Enable and
Disable Times for AC/ACT, ACQ/ACTQ
Vmi = 50% VDD for AC/ACQ devices; 1.5V for ACT/ACTQ devices
Vmo = 50% VDD for A C/ACT, ACQ/A CTQ de vi ce s
FIGURE 8. 3-STATE Output High Enable and
Disable Times for AC/ACT, ACQ/ACTQ
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74ACT2708
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maxim um ratings are tho s e value s beyond wh ic h dam age
to the device m ay occur. The databo ok spe cification s shou ld be me t, with-
out exception, to ensure that the system design is reliable over its power
supply, t emperature, and ou tput/input loading var iables. Fair child does not
recomm end ope rat ion of FACT circ uit s out s ide databo ok s pecifications.
DC Electrical Characteristics
Note 2: All output s loaded; thresholds on input associated w it h output un der test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: Test load 50 pF, 500Ω to ground
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (IIK)
VI = −0.5V −20 mA
VI = VCC + 0.5V +20 mA
DC Input Voltage (VI) −0.5V to VCC + 0.5V
DC Output Diode Current (IOK)
VO = −0.5V −20 mA
VO = VCC + 0.5V +20 mA
DC Output Voltage (VO) −0.5V to VCC + 0.5V
DC Output Source
or Sink Current (IO) ±32 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND) ±32 mA
Storage Temperature (TSTG) −65°C to +150°C
Junction Temperature (TJ)
PDIP 140°C
Supply Voltage (VCC) 4.5V to 5.5V
Input Voltage (VI) 0V to VCC
Output Voltage (VO) 0V to VCC
Operating Temperature (TA)−40°C to +85°C
Minimum Input Edge Rate (∆V/∆t) 125 mV/ns
V
IN from 0.8V to 2.0V
V
CC @ 4.5V, 5.5V
Sym bo l Pa ra me t er VCC TA = 25°CT
A = −40° to +85°C Units Condi tions
(V) Typ Guaranteed Limits
VIH Minimum High Level 4.5 1.5 2.0 2.0 V VOUT = 0.1V
Input Voltage 5.5 1.5 2.0 2.0 or VCC −0.1V
VIL Maximum Low Level 4.5 1.5 0.8 0.8 VOUT = 0.1V
Input Voltage 5.5 1.5 0.8 0.8 or VCC −0.1V
VOH Minimum High Level 4.5 4.49 4.4 4.4 V IOUT = −50 µA
5.5 5.49 5.4 5.4 VIN = VIL or VIH
4.5 3.86 3.76 V IOH = −8 mA
5.5 4.86 4.76 I OH = −8 mA (Note 2)
VOL Maximum Low Level 4.5 0.001 0.1 0.1 V IOUT = 50 µA
Output Voltag e 5.5 0.001 0.1 0.1 VIN = VIL or VIH
4.5 0.36 0.44 V IOL = 8 mA
5.5 0.36 0.44 IOL = 8 mA (Note 2)
IIN Maximum Input 5.5 ±0.1 ±1.0 µAV
I = VCC, GND
IOZ Maximum 5.5 ±0.5 ±5.0 µAV
I = VIL, VIH
3-STATE Current VO = VCC, GND
ICCT Maximum ICC/Input 5.5 0.6 1.0 1.5 mA VI = VCC −2.1V
IOLD Maximum Dynamic 5.5 32 mA VOLD = 1.65V
IOHD Output Current (Note 3) 5.5 −32 mA VOHD = 3.85V
ICC Maximum Quiescent 5.5 8.0 80 µAV
IN = VCC
Supply Current or GND
ICCD Supply Current 5.5 125 150 150 mA f = 20 MHz
20 MHz Loaded (Note 4)
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74ACT2708
AC Electrical Characteristics
VCC TA = +25°CT
A = −40°C to +85°C
Symbol Parameter (V) CL = 50 pF CL = 50 pF Units
(Note 5) Min Typ Max Min Max
tPLH Propagation Delay, tIR 5.0 2.0 6.5 11.0 1.5 12.5 ns
SI to IR
tPHL Propagation Delay, tIR 5.0 2.0 6.5 11.0 1.5 12.0 ns
SI to IR
tPLH Propagation Delay, tIHF 5.0 4.0 10.5 17.0 4.0 19.5 ns
SI to > HF
tPHL Propagation Delay, tIF 5.0 4.5 10.5 16.5 4.5 19.5 ns
SI to Full Condition
tPLH Propagation Delay, tIE 5.0 4.0 10.0 15.5 4.0 17.5 ns
SI to Not Empty
tPLH Propagation Delay, tIOR 5.0 4.0 13.5 16.5 4.0 19.0 ns
SI to OR
tPLH Propagation Delay tMRIRH 5.0 3.0 8.5 13.5 3.0 15.5 ns
MR to IR
tPHL Propagation Delay, tMRORL 5.0 7.0 16.5 25.5 7.0 29.0 ns
MR to OR
tPHL Propagation Delay, tMRO 5.0 3.5 9.0 14.0 3.5 16.0 ns
MR to Full Flag
tPHL Propagation Delay, tMRE 5.0 8.0 17.5 27.5 8.0 30.5 ns
MR to HF Flag
tPHL Propagation Delay, tMRONL 5.0 3.0 9.0 15.0 3.0 17.0 ns
MR to On, LO W
tPLH Propagation Delay, tD 5.0 6.5 18.5 27.0 6.5 31.0 ns
SO to Data Out
tPHL Propagation Delay, tD 5.0 6.5 18.5 29.5 6.5 34.5 ns
SO to Data Out
tPHL Propagation Delay, tOHF 5.0 3.5 8.5 13.5 3.5 15.5 ns
SO to < HF
tPLH Propagation Delay, tOF 5.0 5.0 12.5 19.5 5.0 22.0 ns
SO to Not Full
tPLH, tPHL Propagation Delay, tOR 5.0 2.5 7.0 11.5 2.5 13.5 ns
SO to OR
tPHL Propagation Delay, tOE 5.0 3.5 9.5 15.5 3.0 17.5 ns
SO to Empty
tPLH Propagation Delay, tOD5 5.0 7.0 19.0 30.5 6.0 35.5 ns
SI to New Data Out
tPHL Propagation Delay, tOD5 5.0 7.0 19.0 29.5 6.0 34.5 ns
SI to New Data Out
tPLH Propagation Delay, tX1 5.0 3.5 10.0 16.0 2.5 18.0 ns
SI to HF
tPLH Fall-Through Time, tFTO 5.0 3.5 13.5 21.0 1.5 24.0 ns
SI to OR
tW R Pulse Width, tOP 5.0 12.5 17.0 26.0 12.5 30.5 ns
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74ACT2708
AC Electrical Character istics (Continued)
Note 5: Voltage Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements
Note 6: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
VCC TA = +25°CT
A = −40°C to +85°C
Symb ol Pa ra me t er (V) CL = 50 pF CL = 50 pF Units
(Note 5) Min Typ Max Min Max
tWHF Pulse Width, tX3 5.0 14.5 20.5 30.5 14.5 36.5 ns
tWIR Pulse Width, tIP 5.0 16.5 28.0 43.0 16.5 51.5 ns
tWHF Pulse Width, t3F 5.0 17.5 30.0 46.5 17.5 56.0 ns
tPLH Fall-Through Times, tFT 5.0 6.0 15.0 23.5 2.5 28.0 ns
SO to IR
tPZL Output Enable 5.0 2.0 6.5 11.0 1.5 12.0 ns
OE to On
tPLZ Output Disable 5.0 1.5 5.0 8.5 1.5 9.5 ns
OE to On
tPZH Output Enable 5.0 2.0 7.0 12.0 1.5 13.0 ns
OE to On
tPHZ Output Disable 5.0 1.5 7.0 12.0 1.5 13.0 ns
OE to On
fSI Maximum S I 5.0 55 85 45 MHz
Clock Frequency
fSO Maximum S O 5.0 42 60 35 MHz
Clock Frequency
VCC TA = +25°C T
A = −40°C to +85°C
Symbol Paramet er (V) CL = 50 pF CL = 50 pF Units
(Note 6) Typ Guaranteed Minimum
tW(H) SI Pulse Width, tSIH 5.0 3.5 6.5 7.5 ns
tW(L) SI Pulse Width, tSIL 5.0 6.0 10.0 12.0 ns
tSSetup Time, HIGH or 5.0 1.0 3.5 4.5 ns
LOW, Dn to SI
tHHold Time, HIGH or 5.0 1.5 3.5 4.5 ns
LOW, Dn to SI
tWMR Pulse Width, tMRW 5.0 13.0 20.0 24.5 ns
trec Recovery Time, tMRSIH 5.0 4.5 7.5 8.5 ns
MR to SI
tW(H) SO Pulse Width, tSOH 5.0 7.5 6.5 8.0 ns
tW(L) SO Pulse Width, tSOL 5.0 9.0 14.0 17.0 ns
Symbol Parameter Typ Units Conditions
CIN Input Capacitance 4.5 pF VCC = OPEN
CPD Power Dissipation Capacitance 20.0 pF VCC = 5.0V
F airchild does not assum e any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time w ithout notice to change said circuitry and specifications.
74ACT2708 64 x 9 First-In, First-Out Memory
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or s ystem s a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instr uct ions for use provi de d in the label in g, can be re a-
sonably expected to result in a significant injury to the
user.
2. A critic al com ponen t in any com ponen t of a l ife support
device or system whose failure to perform can be rea-
sonably expected to ca use the failure of the life support
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted
28-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600” Wide
Package Number N28B
