SILICON-EXPLORER II - Microsemi

Si licon E xplorer II

User’s Guide

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Silicon Explorer II User's Guide

Silicon Explorer II User's Guide 2

Table of Conte n ts

Getting Started ............................................................................................... 5

About Si licon Explor er (SE ) .................................................................................................. 5

Connecting to the PC............................................................................................................ 6

Connecting Silicon Explorer ......................................................................... 7

Powering Silic on Explorer II .................................................................................................. 7

Connector Types .................................................................................................................. 7

Sil ic on Explor er Target Connections ................................................................................... 10

Sil ic on Explor er P C Connection .......................................................................................... 12

Devi c e S etti ngs .................................................................................................................. 13

Act 1 and A 40M X Connect ion .............................................................................................. 14

Act 2/XL/A c t3/DX/A42M X Connect ions ................................................................................ 14

SX/SX-A/eX/RTSX/RTSX-S Connections ........................................................................... 15

Axcelerator Connect ion ...................................................................................................... 15

External Logic Analyzer Pinout Table .................................................................................. 16

Using the Software ...................................................................................... 18

Software Settings ............................................................................................................... 18

Sil ic on Explorer S oft ware .................................................................................................... 18

Using the Com m and M ode ................................................................................................. 19

Using the A naly z e Modul e .................................................................................................. 21

Main GUI ....................................................................................................... 23

Silicon Explorer Tool Bar .................................................................................................... 23

Main Window ...................................................................................................................... 24

Shortcuts ............................................................................................................................ 25

Data Display ................................................................................................. 27

Bussed Si gnals ................................................................................................................... 27

Rearrange Channels........................................................................................................... 29

Pattern ............................................................................................................................... 29

Find .................................................................................................................................... 30

Highlight ............................................................................................................................. 31

Data Fi les ........................................................................................................................... 31

Copy Di spl ay Data .............................................................................................................. 31

Readback Dat a ................................................................................................................... 31

Logic Analyzer Concepts ............................................................................ 33

Asynchronous Sampling ..................................................................................................... 35

Understandi ng Trigger ing ................................................................................................... 37

Trigger................................................................................................................................ 37

Auto-Trigger ....................................................................................................................... 37

Triggering ........................................................................................................................... 38

Table of Contents

Silicon Explorer II User's Guide 3

Triggeri ng Sil ic on Explorer .................................................................................................. 38

Analyz er Co ntrols ........................................................................................ 40

Probe I nstr ument ................................................................................................................ 40

Run Controls ...................................................................................................................... 42

Sampling ............................................................................................................................ 42

Troubleshooting Silicon Explorer .............................................................. 43

Troubleshooting E r r or s ....................................................................................................... 43

Troubleshooting General .................................................................................................... 45

Troubleshooting S oft ware ................................................................................................... 45

Troubleshooting Har dware .................................................................................................. 46

Debug ging AX/eX/SX/SX-A Devices Using Silicon Explorer II ................. 48

Internal Probing Feature for Antifuse Families ..................................................................... 51

SDO Pin Locations....................................................................................... 53

ACT2 and 1200XL Fam ilies ................................................................................................ 53

ACT3 Family SDO Pin Locations ........................................................................................ 54

A3200 Fam ily SDO Pin Locations ....................................................................................... 55

A42MX SDO Pi n Loc ations ................................................................................................. 56

RT SDO Pin Loc ations ........................................................................................................ 57

Specifications .............................................................................................. 59

Sil ic on Explorer S pecific ations ............................................................................................ 59

Accessories .................................................................................................. 60

Glossary of Terms ....................................................................................... 62

Product Support........................................................................................... 65

Contacting the Customer Technic al S uppor t Cent er ............................................................ 65

Non-Technical Customer Service ........................................................................................ 65

Silicon Ex plorer II User's Guide 5

Gett ing Started

About S il icon Explorer (SE)

The Silic on Explorer™ Logic Analysis software is designed to support logic instrum ents such as a timing

analyzer, a state a nalyzer, and a p rob e pi lot. E ach of these ins truments prov id es specif ic capabi li t ies for

acquiring and or view ing data .

Microsemi has previously offered Silicon Explorer (SE) II Lite, SE Lite and SE I (all now discontinued).

SE full-version has a built in logic analyzer f unctionality. SE has a 22-pin (18 channe ls , a clock, VCC, GND,

and clock GND) and a 16-pin connector for controlling the Action Probe circuitry and reading the design

c hecksum. It als o has a 26-pin connector for programming ProASIC devices. The Silicon Explorer II logic-

analysis system is enhanced to support an external power supply, which permits internal probing of 5. 0V,

3.3V, and 2.5V FPGAs. Ot her features include four-levels of tr ig ger in g, d ecomp res s io n on dow nlo ad to

speed up response tim e and system acquisiti on rates up to 100MHz.

Silicon Explorer II enables control of the Action Probe circuitry, a patented architectur al f eatu re built i nto all

of Ac tel’s ant i fu se devices t hat allo w s access to a ny intern al no de from selected external pins. S E II

int egrates two diagnostic tools, the Comm and module and the Analyze m odule, into a single diagnostic and

logic analysis device th at attac hes to a P C ’s sta ndard COM po rt. Th e Command modu le of the Explore

s of tware lists all t he observ able n ets in the FPGA. Selec t th e desired net in t he li st and cli ck t he PR A or PR B

button to display the signal on the Analyze m odule. The Command module also reads back the design's

checksum. Also, it is possible to read back the CHECKSUM of a device after it has been secured. You can

use th e design’ s checksum to verify that you pro gr ammed t he cor rec t desig n in the FPGA. The A naly z e

module is an 18-channel logic analyzer t hat automatically displays the signals for both probe outputs (and

up to 16 additional signals) on the target system. You may sample data asynchronously at 66 MHz. Channel

1 and 2 of the logic analyzer connect to the PRA and PRB signals on the FPGA automatically. Sili con

Explor er II uses the rem aining 16 channels of the logic analyzer to exami ne other signals on the board.

Sil ic on Explorer has no memor y devic es. File dat a cannot be stored on any of the non-volatile memor y

components.

Device Support

Silicon Explorer supports all antif use devices.

System Requirements

The system req ui rements for Si li con Explo rer I I ar e:

• D esig ner R1-2000 or later

• Pentium-133 or equivalent

• Microsoft® W indows 98 or NT™ 4.0 SP6, 2000, XP

• 8 MB R AM (minimum) ; 16 M B recommended

Kit Contents

The Silic on Explorer kit contains the following:

Table 1 · Silicon E xplorer Kit C onten ts

Hardware/Software

Part N umbe r

Silicon Explorer II

SILICON-EXPL ORER II

Silicon Explorer User’s G uid e

5029134

Product Support

6 Silicon Explorer II User's Guide

Hardware/Software

Part N umbe r

Rib bon C able A ssembly

RIBBO N & BREAKOUT CABLES

Quic k Pro Clips

1630073

Accessory Bag

1630078

Power Supply

SE II PW R SUPPLY

Flyin g Lead C able Ass embly

SI-EX-TCA

CD Con taining S il ic on Explorer Softw are

LIB-CD-PACK-PC

Conn ecti ng to the PC

Silicon Explorer II connects to a standard serial port using an 8250 or 16550 UART. Establish

communica t ion via the 9-Pin D -Sub connector.

Powering Silicon Explorer II

Silicon Explorer II User's Guide 7

Connect in g Sili con Ex plorer

Power ing Silicon Explor er II

SE I I dr aws pow er fr om the extern al power supply (provided) or by connecting the VIO pin to a power source

(such as might exist on a PCB). You must connect VIO to a reference voltage when using the external

power supply. Microsemi recommends using the ext ernal power supply when the target sys tem cannot

supply enough current to run SE II. The table below lists possible power configurations.

Table 2 · Power Configurations for Silicon Explorer II

I/O P o we r Sup pl y

External SE II Power Supply

VIO

2.5V

Required

2.5V

3.3V

Optiona l ( see note)

3.3V

5.0V

Optional

5.0V

Note: N ote : If your curre nt system is limite d, you must use the ex te rnal powe r supply and use VIO as the

r eference voltage.

W hen you apply power, the yellow “heartbeat” LED on Silicon Explor er II begins to blink. Microsemi

designed Silicon Explor er II hard w are to w ith sta nd abuse normally f ound i n a l ab environment. How ever,

long ter m exp osure to out-of-r ange conditions can cause failure. In parti cular, long term connection to

reverse- or over-voltage power conditions can cause thermal failure.

Curr ent Consumption

Silicon Explorer II is a CMOS device and exhibits very low current consumption when idle. Current

consumption rises rapidly to several hundred milliamps during acquisiti on. If your power supply is unable to

supply the nece ssary curre nt, SE II or your target may reset. The tab le below is a guide to typical current

consumption based on an acquisition rate at 5V — current will be proportionately higher at 3V.

Table 3 · Typical Current Consumption

Acquisition Rate

Current@5V

IDLE

75 mA

10 MHZ

300 mA

20 MHz

400 mA

50 MHz

500 mA

100 MHz

700 mA

Connector Types

Silicon Explorer II has a 22-pin (18 channels, a clock, VIO, GND, and clock GND), a 26-pin, and a 16-pin

connector for controlling the Action Probe circuitry and reading the design checksum.

Table 4 · Connector Types

Product Support

8 Silicon Explorer II User's Guide

Connector Type

Mode

22-pin

Logic Analysis

16-pin

Action Probe Control

26-pin

Not Us ed

The pins are assigned according to the table below.

Source

PRC

Pin 6

PRD

Pin 7

GND

Pin 1, 21

VIO

Pin 2

Logic Analysis

Microsemi Silic o n Explorer II ships with a replaceable target cable assem bly (SI-EX-TCA) that interfaces

Silicon Explorer II with your target system. To connect Silicon Explorer II, align the short red wire on the SI-

EX-TCA with no dot on the case and fully insert the 2 mm header (Digi-Key MHD16K -ND). The contacts on

the S I -EX-TCA accept standard 0.025" round or square test accessori es.

Connect any of Silicon Explor er IIs 18-channel leads to the desired target signals using standard test

accessories.

The Silic on Explorer unit s come with cabl es that are terminated wit h a connector so you can insert a post on

the board. A bag of clips that attach to these connectors to clip onto a post or pin of the device, or another

cable is also included.

Probe Leads

Conne ct the probe leads by attaching one of two supplied cable assemblies. One 16-pin cable as sembly

terminates in individual 0.025 connectors that connect to 0.025 headers or microclips according to the labels

on the wires. The other assembly interfaces directly to the target board with a 16-pin header when you install

the targ et ac cor ding t o th e pin-out shown in the figure and listed in the table below.

Connector Types

Silicon Explorer II User's Guide 9

Figure 1 · Silicon Explorer II Probe Connector Pin-Out

Table 5 · Matching Probe Pins to Device Pins 1

Probe

ACT1,40MX

ACT2, 42 MX, 3200DX

SX/SX-A/eX

Mode

Not Us ed

GND

SDI/TDI

SDI

TDO

DCLK/TCK

DCLK

TCK

SDO/TDO

PRA

SDO

TDO

TMS

Not Us ed

TMS

VIO

VCCI

PRA

PRB

Ch3

PRC

Ch4

PRD

1 ERRORn, CO Nn, M2, M1, M0 pins are n ot req uired f or use with Sil icon E xplorer II .

Product Support

10 Silicon Explorer II User's Guide

2 You can connect any or all GND pins. For best results, connect all GND pins.

3 These are used with AX/RTAXS devices.

Note: Note: Chan 16/QO, Chan 17/Q2, and Chan 0/CH0/TRIG refers to a feature in a previous product and

is not available in Silic on Explorer.

Sili con Explorer Target C onnections

Signal Connectio ns

Sil ic on Explorer inclu des a rep lac eable TCA cable which interface s to your target system. The T CA c ontains

flying leads for input signals, clock, power and ground. Each wire is identified by a printed label.

To connect Silicon Explorer to the target signals:

1. Insert the TCA 2 mm header into Silicon Explorer. The connector is keyed and will only go in one way.

2. Connect the leads to the circuit under test using the .025" contac ts, or test accessor ies such as probe

clips, or clip-over adapters.

To avoid dif fic ult y :

• Be sure the TCA is firmly seated in the mating connector.

• Remember that the ground lead is also the signal return. Make a good connection directly to the

ground plane or a ground point near the highest frequency signal that you will be acquiring. If possible

connect all of the ground leads to the target board for best signal quality.

External Clock

Synchronous acquisiti ons are made by connecting the Clock input leads of the target cable assembly (TCA)

to the clock signal on the circuit under test. Silic on Explorer is specifi ed to sampl e using an external clock to

66 MHz.

To connect to an external clock:

1. Insert the TCA 2 mm header into Silicon Explorer. The connector is keyed and will only go in one way.

2. Connect the external clock input lead of the target cable assembly, labeled CKLIN, to the clock signal

on the target board.

3. Connect the clock ground wire to the ground plane or a ground point physicall y clos e to the clock

signal.

To avoid dif fic ult y :

• The clock ground wire should be connected for best signal integri t y.

• Be s ure the T CA is f irmly seated i n t he Silic on Explorer mating connector.

See Also

Sampling

Underst anding Synchronous Sam pling

Power Silic on Explorer is powered by +3V to +5V, which is supplied by the target board, the supplied power

adapter (Silicon Explorer II only), or an external power supply. To determine if a power adapter or external

supply is needed, see the current consumption section.

Caution: Although Silicon Explorer is desi gned to withstand the abuse normally found in a lab envir onment,

long term exposure to out of range conditions can cause failure. In particular long term connection to reverse

or ov er-voltage power conditions can cause thermal failure.

Silicon Explorer Target Connections

Silicon Explorer II User's Guide 11

Target Power

Power and ground leads are provided on the target cable assembly (TCA) for conne ction to a +3V to +5V

source. Two micro-grabber test cli ps are used for connecti on to power test points on the target board.

1. Insert the target cable assembly (TCA) 2 mm header into Silicon Explorer. The connector is keyed and

will only go in one way.

2. With power removed from the target circuit, connect the TCA power and ground leads to the power

(+3V to +5V) and ground test points on the target board. The TCA power lead is labeled +5V but can

be connected to any voltage between +3V and +5V on the target.

3. Apply power to the target circuit.

Note: Note: The amount of current drawn by Sili con Explorer depends on the sample rate selected and

number of active input channels and ranges from 125mA to 750mA with a 5V supply.

Power Adapter

The supplied power adapter (Silicon Explorer II) is a compact switching power supply that provides +5V at 1

A for applications where target power is not availabl e or insufficient. The power supply is plugged into the

power j ack located on the Silicon Explor er II next to the serial cable.

1. With the power adaptor disconnected from any wall outlet, insert the power adaptor's plug into the

power j ack on the Silicon Explorer II.

2. Connect the Silicon Explorer II ground leads to the target .

3. Plug the power adaptor into a wall outlet.

External Power Supply

An external +5V power supply may be used to power Silic on Explor er when target power in insuffici ent.

Power and ground leads are provided on the target cable assembly (TCA) for connection to the +5V source.

Tw o micro-grabber test clips can be used for connecti on to ground test points on the target board.

1. Insert the target cable assembly (TCA) 2mm header into Silicon Expl orer. The connector is keyed and

will only go in one way.

2. With the external power supply turned off, connect the Silicon Explor er and external power supply

ground leads to the ground plane of the circuit under test.

3. Connect the Silicon Explorer and external power supply +5V leads together.

4. Swit ch on the external supply.

Current Cons um ption

Silicon Explorer is a CMOS device and exhibits very low current consumption at idle, rising rapidly to several

hundred milliamps during acquisiti on. The amount of current required depends on the sample rate and

number of active channels. If your power supply is unable to supply the inrush current, Silicon Explorer or

your target may reset. The following lists the minimum and maximum current requirements at 5V. Current

will be proporti onately higher at 3V:

Idle

125 mA

M in imum A c q uisitio n

350 mA

Maxim um Ac quisition

750 mA

Debug Port You can connect the probe leads by attaching one of two supplied cable assem bli es. One cable assembly

terminates in individual 0.025 receptacles that can connect to 0.025 headers or micro-clip s accordin g to the

labels on the wires - the other assembly interfac es direct ly to t he target b oard when a 1 6-pin header is

installed on the target according to the pin-out show n on t he bottom of t he S il ic on Explorer.

Product Support

12 Silicon Explorer II User's Guide

The Probe A and B pins on the probe connector may be selected as the source for logic analyzer channels 1

and 2 respectively, by clicking on the # field in the Waveform wi ndow and selecting PRA or PRB as the

source. Selecting the probe pins as the source disables the CH1 and/or CH2 inputs from the target cable

assembly.

See Also

• Probing

Sili con Explorer P C Connecti on

Devic e Settin gs

Hardware Connection

See Also

Target Connections

Troubleshooting

Device Settings

Silicon Explorer II User's Guide 13

Connecting Silicon Explorer

The Silic on Explorer PO D i s connected to y our PC with a 9 pi n Serial Por t cab le t hat is per man ently

atta che d to the POD. The Silicon Explorer POD is connected to the target by two cables. The f irst ca ble i s a

16 pin ribbon cable that contains the control signals for addressing the PRA, PRB, PRC*, and PRD* Action

Probes (tm) within the Microsemi FPGAs. The second cable is a 22 pin flying-lead cable for connecting the

logic analyzer channels to the target and optionally an external clock. (*Action Probes (tm) PRC and PRD

are only available for Axcelerator devic es and need be connected to the Channel 3 and Channel 4 leads by

the u ser.)

Figure 2 · Connecting E x plorer POD t o PC

Note: Note: The Silic on Explorer units c ome wi th cables that are terminated with a connecto r i nto which a

post on the board can be insert ed. Clips which can be attached to these connectors and used to clip

onto a post or pin of the device, or another cable are also included.

Device S ett ings

The Silic on Explorer c onnects to a st andard RS-232 serial port using either an 8250 or 16550 UART.

Although 16550 UARTs are not required for hi-speed operations some serial ports do not use

dri ver/receivers that are rated f or th e f ull 115,2 00 baud data rate used by the Pod and may not work with

extension cables.

To att ach Silicon Explorer to your PC, connect the Silicon Explorer 9-Pin D-Sub connector to a serial port

(COM 1 through 4) on your PC

Note: Note: I f you wi sh t o use a serial ex tension cable w i th y our Sil icon Explorer c hoose a shielded cable o f

good quality. RTS and CTS are required as well as Transmit, Receive, and Gr ound. DSR is

connected to DTR but is not required for operation.

You can select a serial port (COM1 through 4) from the m enu bar. The Silicon Explorer application polls the

Silicon Explorer continuously for activity. Setting the port to Demo mode prevents the application from

opening any COM ports on your system.

To select the COM port:

On the Device menu, click Port, then click the appropriate COM port.

Select Demo to view data files without Silicon Explorer connected.

The Silic on Explorer software defaults to 115,200 baud at this speed data transfer will be less than 20

seconds for th e ent ire buffer . On some slow s ystems ( 486-33 or less) particularl y those with 8250 UARTs,

better performance may occur at 57,600 baud due to the need to retry blocks at high speed.

Product Support

14 Silicon Explorer II User's Guide

To change the baud rate:

On the Devic e menu , click Baud.

Click the appropriate baud rate.

Ver ify Communication

The Silic on Explorer s of tware reports commu nication status on the status bar. When t he Si lic on E x plorer

has been properly connected, configured and powered, the status will show IDLE. If the status bar reports

POLL or N/C (not connected) then the link has not been established. See the troubleshooting page for

assistance.

Ac t1 and A40MX Connection

The fi gure below shows the connection of Silicon Explorer II to the Act1 and A40MX families of devices. The

Act1 and A40MX families of devices have two probe outputs, PRA & PRB, that connect to the Sili con

Explor er's 16 pin connector.

Figure 3 · Silicon Explorer II Connection to Act1 and A40MX D evi ces

Ac t2/XL/ Act3/DX/A42MX Connecti ons

The fi gure below shows the connection of Silicon Explorer II to the Act2, Act3, XL, DX, and A42MX families

of d ev ic es. All of th ese fami lies of d evi ces have t w o pro be out puts, P RA & P RB, t hat co nnect to the Si l icon

Explor er's 16 pin connector.

SX/SX-A/eX/RTSX/RTSX-S Connections

Silicon Explorer II User's Guide 15

Figure 4 · Silicon Explorer II connection to Act, XL, DX, and A42MX Devices

Note: Note: Desi gner R398 or later is required for probe file creation.

SX/SX-A/eX/RTSX/RTSX-S Connecti ons

The fi gure below shows the connection of Silicon Explorer II to the SX, SX-A, RTSX, RTSX-S, and eX

families of devi ces. All of these families of devices have two probe outputs, PRA & PRB, that connect to the

Sil ic on Explorer's 16 pin c onnector.

The probing of an SX-A, RTSX-S , or eX devic e m ay req uire specia l setu p. Microsemi rec ommends tha t you

use a series 70 ohm termination on all the probe connectors (TDI, TDO, TCK, TMS, PRA, PRB). The 70

ohm series termination prevents data transmission corruption during probing and reading checksum.

Figure 5 · Silicon Explorer Connection

Note: Note: Desi gner R398

A xcelerator Connecti on

The fi gure below shows the connection of Silicon Explorer II to the Axcelerator family of devices. The

Axcel erator family of devices has four probe outputs unlike earlier devi ce fami l ies. Each member of the

Product Support

16 Silicon Explorer II User's Guide

Axcel erator family has four external pads: PRA, PRB, PRC, and PRD. These can be used to bring out four

probe signals from the Axcelerator device (note that the AX125 only has two probe signals that can be

observe d: PRA and PRB). Each core tile has up to two probe signals.

Shown in this figure are the 70 ohm series termination resistors needed on TDI, TCK, TMS, TDO, PRA and

PRB. Probe outputs PRC and PRD do not need termi nation resist ors on the board because resistors are

built i nto the C H3 an d CH 4 lea ds. T he 70 ohm s eries t er minat io n prev ents data tra nsmission corr upt ion

during probing and read ing che cksu m.

Note: Note: Signals in Axcelerator devices can only be probed for speeds of 28 MHz or less.

Figure 6 · Silicon Explorer II Connection t o Axcelerator Devic e

Note: Note: D esigner R1-2003 SP3 or l ater is required for A xcelerator pro be f i le creation.

E xternal Logic Analyzer P inout Table

Table 6 · External Logic Analyzer Pinout Table

Pin Number

Function

GND

+V5

CH0/TRIG

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CH8

CH9

CH10

External Logic Analyzer Pinout Table

Silicon Explorer II User's Guide 17

Pin Number

Function

CH11

CH12

CH13

CH14

CH15

CH16/Q0

CH17/Q1

GND (CLK ground)

CLKIN (for synchron ous sa mpling )

Product Support

18 Silicon Explorer II User's Guide

Using the S oft ware

Software Sett ings

Sil ic on Explorer I I sets i ts elf to Demo mode on instal la t ion. F rom t he D evice menu, cho ose Silicon Explorer

II or Sili con Explorer, depending on your version of the hardware.

Choose the desired port (COM1 through COM4) fro m the Port drop-down list in the Device menu. The

software continuousl y polls the hardware for activity. Setting the port to the Demo mode prevents t he

application from opening any COM ports on your system. The serial port saves information in the analyze.i ni

fi le found i n your Wi ndow s directory. The defa ul t da ta tra nsfer speed is 115,200 baud. At this speed data

transfer f or the entire buf fer i s les s than 15 seconds.

Note: Note: M any noteb ook computers share the external CO M por t with a buil t-i n infrared (IR) port. You

may have to enter your CMOS setup m enu to enable the external COM port.

Sili con Explorer S oftware

The Explorer software consists of two components, the Command module and the Analyze module. The

Comma nd m odule o f th e Explore sof tware lists al l t he observable n ets i n t he FP GA. Us e th e Comman d

m odule to ver ify t hat you pro grammed t he correct desig n in the F PGA. The A nalyze module i s an 18-

channel logic analyzer t hat automatically displays the signals for both probe outputs (and up to 16 additional

signals) on the target system. PRC and PRD are not displayed for other device fami lies. T he f igure belo w

s how s t he Si lic on E x plorer wi th a n A x celerato r probe f ile loaded.

Figure 7 · Silicon Explorer Window with an AX Probe File

Using the Command Mode

Silicon Explorer II User's Guide 19

Us ing the Comm and M ode

The Command module is the interface used to select internal nodes in the Microsemi FPGA family. Th e

Comma nd m odule list s al l t he observable n ets in the F PGA. Yo u can selec t the desired net in th e li st and

click the PRA or PRB button to display the signal on the Analyze module. The Command module also reads

back the design's checksu m. You can sti ll read back the CHECKSUM of a device after it has been secured

and you can use the design’s checksum to verify that you programmed the correct design in the FPGA.

Figure 8 · Command Module

To open a probe file:

1. From the Start menu, choose Programs > Designer > Silicon Explorer to launch Silicon Explorer.

2. From the File menu choose Open. Choose (*.prb) as the File type and double-click the desired probe

fi le. You c an als o open a probe f ile in S il ic on Explorer by double-clicking the Open Actel Probe File

icon.

Explor e uses a PRB file exported from Designer during analysis. The exported file contains device

information, net names, and node location information. After the PRB file opens, verify the inform ation

displayed in th e t ree s tructure i n t he Analy ze window.

To export a probe file from Designer:

1. Launch Designer.

2. Open your design file

3. Go to File > Export to view the Export dialog box.

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20 Silicon Explorer II User's Guide

Figure 9 · Opening the Export Debugging Dialog Box

4. Select Auxiliary File from the File Type pull-down menu.

5. Select Probe from the Type pull-down menu.

6. Select OK to continue and then save the Probe file.

You can also generate a AFM or probe file using the Generate Programming Files: Fuse Files dialog box.

See the figure below. Note that the Gen erate Pro be Fi le Also box is checked.

Figure 10 · Genera te Pro gramming Files Dialog B ox

To verify checksum:

1. Make sure that the SDO/TDO is connected.

2. Click the Checksum button.

3. Once you open a Probe file and make a device connection, read the checksum of th e t arg et devic e

and comp are it to the checksum in th e Probe file by double-clicking the Checksum button. The table

below lists and explains the error m essages.

Using the Analyze Module

Silicon Explorer II User's Guide 21

Note: Note: When reading an FPGA checksum with Silicon Explorer, the Acquire/AutoRun button and the

Stop button may randomly toggle. If this happens, click the Acquire button and then the Stop

button. This returns th e sof tware to nor mal state.

Table 7 · Checksum Error Messages

Error Message

Explanation

Checksum:

383A vs ????

Che cksu m is not readable because the probe is disconnected or not

powered.

Checksum:

383A vs 0000 Checksum does not match the file or The SDO/TDO probe-side pin is

not properly connecte d to the device. Connector Types c ontains a

listing of the proper connections.

To pro be a node:

1. Select the desig ned sig nal from t he t ree b y cli ckin g th e net name. U se th e filter bo x t o searc h nets

quickly, and use th e m ultiple wi ldcard chara cters ( " *") to rest r ict y our searc h.

2. Click the PRA or PRB button. Silicon Explorer I I rou tes t he selec ted node to the probe pin a nd

switches the corresponding analyzer i nput to the probe connector.

Us ing the Analyze Module

To use the Analyze Module:

1. Open Silicon Explorer II and check the status in the lower right corner of the display. If you have

properly selected the COM port and powered up Silicon Explorer II, then the status is IDLE. The

Analyze module captures 64K samples of each channel and uploads them to the host over the serial

port.

Figure 11 · Analy ze Module

2. Set acquisit ion parameters from the tool bar or t he pul l-down menus .

Figure 12 · Acqui sition Parameters

Acquisition

Speed

10 Khz to 100 MHz asynchronous

Trigger

Position

25%

50%

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22 Silicon Explorer II User's Guide

75%

Trigger

Pattern Click on individual signals in the Px Column to specify don't care, low,

high, rising, fallin

g, or either edge. The rigger patterns is the logical AND

of the 18 patterns.

3. Once you set th e acquisi t io n par ameters, cl ick th e R un button ( red t riangle) to begin a cquisi tion. The

analyzer begins capturing data until Silicon Explorer II recognizes the t rigger pattern o r you press t he

stop button (black square). During the capture period, the status window displays “PRE” for the pre-

trigger state (alth ough you m ay not s ee i t if the t rigger p attern m atches qui ckly).

Next, Silic on Explorer II enters th e POS T state an d samples d ata a f ter t he t rigger p attern (or st op but to n)

until it fulfills the post trigger requirement. Then, it uploads the data to the host (READ State with progress

indicator). The entire upload process takes less than 15 seconds, although yo u may z oom in an d v iew data

immediately because the buffer uploads as a background task.

Silicon Explorer Tool Bar

Silicon Explorer II User's Guide 23

Main GUI

Menu Bar The Menu Bar provides pull-dow n men u access to all Silic on Explo rer set tings, cont ro l s and display

functions.

Figure 13 · Menu Bar

Keyboard shortcuts are also ind icated i n th e men u choic e.

Sili con Explorer Tool B ar

The Tools Bars contain button-style controls which are grouped together int o individual tool bars. The

grouped too l bars can be viewed, hi dden or rearranged.

Figure 14 · Tool Bar

Table 8 · Tool Bar Icons and Descripti on

Icon

Gr oup Description

Show/Hide Probe window.

Crea te new project, op en crea ted project, and save

project.

These are run control icons used with the analyzer

instrument. Use t hem to acquire, autorun /a uto tr ig ger,

and halt an acquisition. The auto-trigger mode will

continually trigger , capture, and re-arm for the next

run capture.

Use this pull down me n u to choose synch ronou s or

asynchronous cl ocks. See Synchronous and

Asynchronous .

Select th e t r igg er p osit io n from the pull-down menu

Use these icons to create or undefine signal busses.

Change the resolution of the timing analyzer display

by zooming in or out.

Displays acquisition data as a timing view or a state

list. Timing view is displayed horizontally as a graph

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Icon

Gr oup Description

and t he state l ist is dis pla yed ver ti cal ly as a table.

Main Window

Figure 15 · Sili con Explorer Main Window

The Silic on Explorer software presents information in rows and columns just like a spreadsheet. In the

Timing Analyzer each row represents a channel or, in the case of bussed signals, group of channels. Each

column contains specific information about that channel, such as the acquire d da ta, trigger cond ition, signal

activity indicator, etc. These col umns may be m oved and resized as desired.

Pattern Column

The Pattern column conta ins logic levels and o r ed ge conditions for each channel and can be nam ed. These

logic conditions are logically added together composing a pattern which can be used to trigger the analyze r,

locate (find) s i mila r p attern s within the data , or hig hl ight s i milar ( or dissi milar) patterns

See Pattern f or info r matio n on crea t in g or ren aming a pattern.

Wire Numbe r

The Wire Number column provides a reference between the signal name and the physical target cable

assem bly wire. In the case of bussed signals, this column contains the li st (in order) of all channels included

in the bus. This column can be moved or resized as needed.

C1 and C2 (Level at cursor n)

The C1 and C2 c ol umns dis play t he log ic l evels of all visible channels at th e t i me sample b egin ning wi th

cursor 1 and cursor 2 respectively. For example, if you place cursor 1 on a logic transition, the C1 column

will display the logic level immediately to the right of cur sor 1. Th is column can be moved or res ized a s

needed.

Activity Indicator

The Activity Indicator column provides a real ti me indi cat ion of t he state of ea ch channel . Th e states

displayed are Constant HIGH level, Constant LOW level, and TOGGLI NG. In the case of bussed signals, the

state of the last channel in the bus is displayed. This column can be moved or resized as needed.

Note: Note: R esizin g this column is done b y dr aggin g the rig ht ed ge of t he column to the right and can only

be done when it is not the last column on the right.

Readout Bar

Cursor measurem ents are display ed in the Readout Bar located near the bottom of the screen.

Figure 16 · Readout Bar

Shortcuts

Silicon Explorer II User's Guide 25

C1 - Ti me (o r n umb er of cl ocks) from t he t rigger to curs or 1

C2 - Ti me (o r n umb er of cl ocks) from t he t rigger to curs or 2

dT - Time (or number of clocks) between cursor 1 and cursor 2

Time measurem ents appear on the readout bar automatically after cursors are placed in the data.

Figure 17 · C2 to trigger / C 1 to trigger / C 2 to C1

Shortcuts

Keyboard Shortcuts Table 9 · Keyboard Shortcuts

Action

Shortcut Key

Run Control

Run

Auto Trigger

Stop

Zoom (t i ming displa y)

Zoom in

Up arrow

Zoom o ut

Down arrow

Full sc reen

Spacebar

Pan Controls

Next Screen

Page down

Prev io us S creen

Page up

Timing

Forward

Right arr ow

Backward

Left arrow

Goto

Trigger

Home

Cursor 1

Cursor 2

Find cursor

Beginning or end

End

Find

Ctrl+F

Ctrl+Shift+F

Cursors

Nudge cursor 1 forward

Ctrl+right arrow

Nudge cursor 1

backward

Ctrl+ left arrow

Nudge Cursor 2 forward

Ct rl+ S hift+right arro w

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26 Silicon Explorer II User's Guide

Action

Shortcut Key

Set cur sor 1

Ctrl+1

Set cur sor 2

Ctrl+2

Edit Co ntrols

Undo

Ctrl+Z

Cut

Ctrl+X

Copy

Ctrl+C

Paste

Ctrl+V

Delete

Del

Select all

Ctrl+A

Deselec t all

Esc

Rename

Enter

Wiggle Stick s : Pl ace cur sor in data

area

Course Control

Alt (move mouse)

Fine Control Sh ift+ Alt (move

mouse)

Context Me nu Sho r tcut

Context-sensitive menus are provided via the right mouse button. They are available for the rows and

columns of the logic analyzer window.

Bussed Signa ls

Silicon Explorer II User's Guide 27

Data Dis play

The Silic on Explorer software contains an array of tools to format and view acquired data. These topic s

explain what the tools are, and how t o use them.

• Bussed Signals

• Multiple Document Interface

• Timeline

• Rearrange Channels

Bus sed Signal s

Channels may be grouped together as a bus, with their combined numeric value display ed in hex, decimal,

ASCII or analog radix.

Creating a Bus

Channels can be grouped together as a bus, with their com bined numeric val ue displayed in hex, decimal,

ASCII or analog radix.

Signal busses can be created by grouping similar channels together (such as data lines, address li nes, etc.).

Once created they can be undefi ned and viewed as individual channels again.

To create a bus:

1. Click in the channel's wire number c olumn to highlight t he bus.

2. Click and drag the cursor to highlight the remaining channels.

3. Click the MAKE BUS icon on t he to ol bar.

Unde fini ng a Bus

To undefine a bus:

1. Click the buses wir e number column to highlight it

2. Click the Undefine Bus icon.

Collapsing a Bus

Expanding a bus shows the individual channels without losing the bus structure that happens

when the bus is Undefined. Collapsing the bus has the opposite affect, displaying the signals as a

single bus once more.

To Expand a bus:

1. Highlight the bus by clicking on the bus' wire number column.

2. Click the Expand Bus icon.

Expanding a Bus

To Collapse an Expanded bus:

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28 Silicon Explorer II User's Guide

1. Highlight the bus by clicking on the bus' wire number column.

2. Click the Collapse Bus icon.

See Also

Radix

Bus Ordering

Radix The com bined num eric values of bussed si gnals can be displayed in one of several radixes such as

hexadecimal, binary, decimal, ASCII, analog and user mnemoni cs.

To select a radix:

1. Highlight th e bus by clic king i n t he bus' w i re n umb er c olumn.

2. Select Bus from the menu bar.

3. Click on the desired radix.

Figure 18 · S electing Radix

Note: Note: The bus values will be incorrect if the order of the channels is backwards (MSB is in the LSB

position). See B us Orde ring to correct the proble m.

Bus Ordering

Bus ord ering refers to the order in whic h channels are s elected when a bus is defined.

Problems with bus ordering become apparent after a bus is created and data is captured. If the bus order is

backwards, the data will also be backwards and may be unintelli gible. Silicon Explorer software provides a

way to specify the bit order, even after the bus has been defi ned.

To set the bus order:

1. Highlight th e bus by clic king o n t he bus' wire n umb er column.

2. Cli ck th e appro priate b us ord er icon.

See Also

Radix

Multiple Document Interface

The M ultiple Document Interface lets users open several logic analyzer windows within the Silicon Explorer

application. Each window is a unique analyzer session, containing its own trigger settings, channel labels,

Rearrange Channels

Silicon Explorer II User's Guide 29

data, etc. A window can also be a clone of another, containing t he same d ata a nd settin gs, but with a

dif ferent v iew (p an, zoom, etc.) of the data.

The active window has access to the logic analyzer hardware and is the only one that can capture

acquisition data.

To crea te a copy of th e cur ren t windo w, from the men u bar, select Window > New Window.

To crea te a new analyzer inst rument, f rom t he men u bar, selec t Fi le >New, then click on the instrum ent

desired.

To arrange the analyzer windows, from the menu bar, select Window, then Cascade or Tile.

To switch between analyzer windo ws :

Click withi n the desir ed analyzer window

From the menu bar, select Window, then click on the desired window name.

Timeline A tim eline is displayed along the top of the data display providing a tim e reference for acquired data. This

reference can be presented in time units (seconds) or in sampl es. Additionally, vertical reference dots can

be tur ned on (or off) providing a grid in the data display making time relationships between channels much

easier to see.

To display the tim e lin e in seconds:

1. From the menu bar, select Vie w > Time lin e.

2. Click Time U nits t o pla ce a check next to it.

To displa y the t imelin e in samples:

1. From the menu bar, select Vie w > Tim el in e .

2. Click S amples (Hex) or Samples (Decimal) to pla ce a check nex t to the desired settin g.

To enable or disable the reference dots:

1. From the menu bar, select View.

2. Click S ample D ots to pla ce a check next to it.

Rear range Channel s

Channe ls can be re arrange d so that related signal s are displa ye d next to one another. Channel rearr ange is

also useful before grouping channels together as a bus.

To move a channel:

1. Press and hold the Alt key.

2. Position the cursor over the channel to be moved. A hand displays.

3. Click and drag the channel to the desired location.

Pattern P attern is a generic name describing a user defi ned template of logic conditions used for comparison with

real data. Patterns may include any or all input channels, and are used for trigge ring, loca ting data and

highlighting occurrences of data patterns.

To create a new pattern:

• From the Pattern menu choose N ew Pattern.

• Press the letter P on the keyboard.

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30 Silicon Explorer II User's Guide

To modify the logic conditions:

1. Place t he mo use curso r over the P attern column for the input channel(s) of intere st.

2. Cli ck th e m ouse button t o cyc le through t he list of choic es.

Right-clic k to displa y a list of choic es and select an option from t he dr op-down menu.

Figure 19 ·

Figure 20 · P attern Col umn

To re na me a pa ttern:

1. Cli ck th e pattern to hig hli ght t he pat tern of interes t.

2. Press Enter .

3. Ty pe th e new name an d press Enter.

Find Pat t erns can be used as to locate occurrences of specific logic conditions within the acquisiti on data. Once

the logic conditions of interest are entered into the pat tern, the fin d operation can t ake pla ce.

Locating data using patt er ns:

1. Crea te a pattern containing the data conditions of interest.

2. Right-click th e pat tern name to select i t.

3. Cli ck Fin d Next o r Fi nd Previous . ( You can also use the keyboard short cuts Ctrl+F to Find and

Ctrl+ S hif t+F to Find Previous. )

See Also

Pattern

Trigger

Highlight

Keyboard Shortcuts

Highlight

Silicon Explorer II User's Guide 31

Highlight Silicon E x plorer Patterns can be used t o visually hig hlig ht the occur rence( s) of specified data pattern s within

acquisition memory .

To highlight data that matches a pattern:

1. Crea te a pattern containing the data conditions of interest.

2. Clck the pattern heading (name) to highlight it.

3. For m the Pattern choose Highlight.

4. Ac quisi tion samp les t hat matc h th e data p attern are highl ighted.

See Also

Find

Trigger

Keyboard Shortcuts

Data F il es

Previously acquired data files can be opened for viewing and analysis. When saved, the files are given a

".bce" extensi on.

To open a file:

• From the File choose Open.

• Select P od-A-L yz er Files ( * .bce) i n th e Files of Type box

• Click t he desi red f ile

• Click File Op en icon

To close a file, f rom the File choose Close.

Acquisition data and setup information, such as the trigger condition, channel labels, etc., are stored

together when saved to a fil e. This way, the analyzer display always looks the same as when it was last

used.

To save a data file, from the File menu choose Save or click the Save icon.

Use th e Print command to print an active window in Si lic on Explo rer.

Copy Di splay Data

State list display data may be copied, then pasted into an ASCII file in a tab-delimited format.

To copy state list data:

1. Place t he mo use curso r over the w i re n umb er of t he f i rs t column of d ata to b e selected.

2. Cli ck and dra g t he mo use to highlight al l the data c olumns .

3. From the Edit choose Copy.

Read back Data

Data captured by an analyzer device is automatically t r ansferred to th e PC. I t i s someti mes u seful t o rea d

that data again.

To readback data:

From the Instrument menu choose Readback Data.Instrument and then choose Readback Data.

See Also

• Run Controls

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32 Silicon Explorer II User's Guide

• Multiple Document Interface

Readback Data

Silicon Explorer II User's Guide 33

Logic Analyzer Conce pts

Product Support

34 Silicon Explorer II User's Guide

Synchronous Sampling

Synchronous sampling is supported only on Silicon Explorer I. Silicon Explorer II does not support

synchronous sampling. Synchronous sampling uses a sample clock that is external to the logic analyzer -

usu al ly the clock from th e sy stem under t est. This mode of opera tion i s often referr ed t o as State acquisit ion

s in ce t he analy z er is capturing t he sta te of al l sign al s on every clock. The target clock must be connected to

the w i re labeled CLKIN. The clock ground wire must be connected for best signal int egrity at high clock

rates ( > 20MHz ). The Silicon Explorer does not require the cloc k to be an oscillator. However, it does

require a continuous series of edges for operation.

State Display is a tabular display of logic activity, usually captured synchronously to an external clock. The

data displayed on each horizontal line represents one recorded sam ple. The analyzer can display the

recorded data in a variety of radixes ( num erical formats) including binary, decimal, hexadecimal, analog, etc.

Clock Qualifier

State# Si gnal Names

Acquired Data

The Clock Qualifer is an external signal that acts as a gate for the acquisition clock. When the external

signal is false, the acquisition clock is not allowed to load acquir ed data into acquisition memory.

The Clock Qualif ier is usefu l w hen you wa nt to observ e signal activity tak ing pla ce only w hen a particular

c hip is s elec ted . F or exa mple, i f the system under test has three devic es of th e same type connected t o a

common bus, one of which appears to be defective, you might want to record signal activity on the bus only

when the suspect device is selected.

If the logic a naly z er's Cloc k Q uali fier input w ere c onnected to the chip select lin e of the devic e we w ere

int erested in, the analyzer would record data only when the chip's select line was active. The Clock Qualifier

allows us to filter out irre levant data by only clocking data of interest into the sample buffer.

To set up for Synchronous acquisition:

1. Connect the clock leads of the Target Cable Assembly to the target circuit clock signal.

2. From the Instrument menu, choose Clock > Clock Edge and click either Rising or Falling

depending on which edge is appropriate.

Asynchronous Sampling

Silicon Explorer II User's Guide 35

As ynchronous Sampli ng

An acquisition that is made using a clock signal generated internally by the analyzer. This clock is unrelated

to the clock in the target system , and can be set by you.

Timing Display

Timing display is a graphic representation of the timing relationships between input signals, displaying the

r eco rded signal ac t ivity i n t iming dia gram for mat. The s creen fragmen t belo w sho ws a t ypi ca l timin g disp lay

in which multi ple signals are displayed one on top of another. This type of display is ideal for understanding

the "logic level vs. t ime" r elationships between mult iple channels a t a sin gle g la nce. Measur in g th e t ime

between signal events is usually accomplished with the use of cursors.

Table 10 · Timing Display

Sig nal N ame Time > >

Waveforms

(l ow vs. high)

Sample Rate

Sample rate is t he speed at whic h t he in put sig nals are s ampled, o f ten expres sed in meg a-samples per

s econd (M Sa/s ) . Selec ting t he pro per sample rate is impo r ta nt to ensure that signals are displayed

accurately, and completely.

Figure 21 · Signal with Narrow Pulse

The example above shows a signal containing a narrow pulse at the end. In the case above, it is being

sampled fast enough to capture th e pulse. If th e sam ple rate wer e slow ed dow n, how ever, i t w ould b e

possible to miss the narrow pulse entirely, as shown below.

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36 Silicon Explorer II User's Guide

Figure 22 · Signal with Slowed Rate

To get ad equate sam ple resolution, a goo d "rule of thumb" is t o m ake sure the a nalyzer s amples 4 t o 10

times faster than the fastest signal being captured.

For exampl e, if you wanted to capture a 40 nanosecond (ns) pulse, you would want the analyzer to sampl e

at least 4 ti mes faster ( 40ns/4 = 10ns ). S ampli ng 10 t imes faster may not b e prac tical since i t w ould requi re

an analyzer tha t samples every .4n s, or 2.5 g i ga-samples per second (GSa/s).

Capturing the entire signal

Logic analyzer sample buffers usually have a "fixed" size. This means that the faster memory is filled (the

faster th e sam ple rate), the shorter the overall acquisition time will be.

If you need to capture a burst of data that lasts 5 ms. Let's also assume the sample buffer can store 64K

samples (actually 65536 samples since 64K is really 2^16). Simply divide 5ms by 65536 which resul ts in

76.3 n s . In other words, w i th a 64K sample b uffer and th e analy zer s amp lin g at 76 ns, i t wi ll capture 5 m s

wor th of signal act iv it y.

In realit y the analyzer probably has fixed sample rate steps (such as 200 ns, 100 ns, 50 ns, 20 ns, etc.). To

comply with th e r equiremen ts in t he example above, w e woul d not be able to sample f aster th an 76.3 ns and

still captur e 5 ms worth of data. The closest alternative would be 100 ns, which would result in 6.6 ms worth

of data (65536 samples x 100 ns). Assuming 100 ns is fast enough to sample the input 4 times faster than

the fastest s ig nal (100 ns * 4 = 400 ns puls e) , we wi ll m eet o ur o bject iv es f or sample res olution an d

acquisition length.

Sample Resolution

Sampli ng R esolut io n i s the interval (in seconds) between samples, deter mined by the freque ncy of the

sample clock. Suppose, for exam ple, that the sample clock was running at 100 MHz, and we were sam pling

on the rising edge as shown below. The sample resolution would be 1/100 MHz, or 10 ns.

Figure 23 · S ample R esolu tio n

Wh en th e t i ming analy z er s amples an i nput l ine, it is either hig h or low. I f t he line is at on e state (hig h or low )

on one sample and the opposite state on the next sample, the analyzer "knows" that the input signal

transitioned sometime in between the two samples. It doesn't know when, so it places the transition point at

the last sample, as show n belo w.

Figure 24 · S ample U ncertainty

This presents som e uncertainty as to when the transition actually occurred and when it is displayed by the

analyzer. W orst case for t his u ncertainty is one sample p eri od, ass uming t hat the t ransition occurred

immediately af ter t he previous sample point.

Understanding Triggering

Silicon Explorer II User's Guide 37

Understanding Triggering

Triggering is the process of halting the l ogic analyzer after a sp ecific event h as occurred. The event is

typically called a trigger pattern and is the logical and of logic conditions on one or more channels. In multi-

level triggering, sev era l logic events m ay be required t o occur befo re the anal yzer tr ig gers.

It is helpful to understand how acquisition m emor y applies to the trigger process:

Conceptuall y, the acquisition memory acts as a circular buffer. Once the analyzer is started, samples are

stored in sequence . If the analyzer fills memory befo re a trigger occurs, it will continue to acquire d ata with

the n ewest data o ver-writin g th e old est. O nce a trigg er oc curs, th e analyzer wi ll either:

1. Stop immediately - acquisition m emory contains waveform data of signal activity leading up to the

trigger onl y (also called p re-trigger data).

2. Fill t h e entire memory once more - acquisition m emory contains waveform data of signal activity that

occurred after the trigge r (also called post-trigger data).

3. Fill only a por tion of mem ory - acquisition me mo ry contains both pre-trigger and post trigger

information.

Trigger By default , the Silic on E x plorer s of tware c ontains a t rigger p at tern, id ent ified b y a red f ont. O th er pat terns,

however, ca n be selected for use as t he t r igg er p at tern.

Selecting a pattern to trigge r the analyzer:

1. Cli ck th e pattern o f in terest to highli ght i t.

2. From the Pattern choose Use as Trigg er . The pattern name is displayed in a red font signifying that

this is now the trigger pattern.

See Also

Pattern

Find

Highlight

Auto-Trigger

Auto-t r ig ger lets you view th e captured d ata dynamicall y. Acquisitio ns are mad e, the display updated and

the a nalyzer s tarted f or the next c apt ure a utomat ic ally. The rate at which the display is updated depends

upon the amount of data being viewed and the frequency of the trigger event. The fastest update is about

once every second.

To start auto-trigger:

• Toolbar: C lick the AUTO TRIGGER icon.

• From the Instrument menu choose Run Auto Trigger.

• Keyboard: Press the letter A.

To halt auto-trigger:

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38 Silicon Explorer II User's Guide

• Toolbar: C lick the HALT icon.

• From the Instrumentmenu choose Stop.

• Keyboard: Press the letter S.

See Also

Underst anding Triggering

Triggering

The Silic on Explorer software supports both single-level and multi-level triggering depending on whether you

are c onnected t o a Silicon E xplorer or a Silic on E x plorer II. S elect th e device you are u sing f rom the l ist in

the device menu.

Triggering Si licon Explorer

The Silic on Explorer has a single-level trigger seq uence with a selec ta ble trigger p osi tion. S i lic on Explorer I I

has up to four-levels in its trigger sequence.

Trigger Pattern

A trigger pattern is the logical AND of the trigger conditions set on all 18 channels. Each channel may be set

to one of the foll owing trigger conditions:

• Don't Care

• High

• Low

• Rising Edge

• Falling Edge

• Either Edge

To set the trigger condition for a single channel:

Right-click the trigger pattern column of the desired channel and choose the trigger condition.

To set the trigger patter n for a group of bussed signals:

1. Click the Trigger Pattern column of the channel bus.

2. Enter the pattern using the keyboard, using the same radix as the bus.

To select a pattern to trigger the analyzer:

1. Click to select the pattern of interest.

2. From the Pattern men u choose Use as Trigger.The pattern name is displayed in a red font, indicating

that this is now the trigger pattern.

Trigger Position

The Tri gger Position controls determi nes how much of the captured data came befor e the trigger and how

m uch came after. There are three poss ib le s ettings:

• Early (25% pre, 75% post)

• Cen ter (50% pre, 50% post)

• Late (75% pre, 25% post)

To set the tri gger pos i tion fr om the m enu bar:

1. On the Instrument menu select Trigger Position

2. Cli ck on t he desired position (Early, C enter, or Late)

Triggering Silicon Explorer

Silicon Explorer II User's Guide 39

See Also

Underst anding Triggering

Product Support

40 Silicon Explorer II User's Guide

Analyzer Controls

Probe Instr um ent

Pro be f iles are g enera ted f rom D esig ner softw are a nd contain devic e informat io n, net names, and node

location i nfo r matio n. This i nformat ion i s display ed in a tree s tructure for v er if ic at ion. For Axcelerator devices,

the net name is prefixed by the tile number the m odule is on. e.g. net <0,1>ALU_test_mod_d is .on tile 0,1.

Once a *.prb file is opened and a device connection has been made then the checksum of the target device

can be read and compared against the checksum in the file. This ensures that the selected probe file

m atches t he targ et d evice.

Figure 25 · Display for non-Axcelerator D evi ces

Probe Instrument

Silicon Explorer II User's Guide 41

Figure 26 · D is play for A xcelerator devic es

Open a Probe File

Note: Note: D esigner R39 8 or later is require d. (De signer R1-2002 SP2 or later is required for Axce le rator)

To open a file:

1. From the File menu choose Open > Files of type (*.prb).

2. Double click the desired probe file.

Assign a Probe

To ass i gn a nod e to a probe :

1. Click the node to sele ct it.

2. Click the PRA or PRB button. (PRA, PRB, PRC, or PRD for Axcel erator devices)

The selected node is routed to the probe pin and the corresponding analyzer input switched to the debug

connector. The net name will also appear in the waveform window .

Note: Note: For Axcelerator devices, only the Probe A and Probe B pins will be automatically switched to

the corresponding analyzer input. You must connect the Probe C and Probe D pins to CH3 and CH4

r esp ectively. The net names for P ro be C a nd Pr obe D automatically appear in the current waveform

window for CH3 and CH4 unless you have alr eady typed a nam e for the channel.

Display Features

The tree cont rol l ists t he nets or pins i n th e design . T o forma t t he di splay, r ig ht-c l ick t he N ets bra nch. Use

the F IL TE R f ield to fil ter the lis t . Wi ldcards (* ?) are s uppor ted .

A history is maintained on the probe and filter lists (PRA, PRB, PRC, PRD, and FILTER) accessible from the

pull-down button.

Product Support

42 Silicon Explorer II User's Guide

Run Cont rol s

Severa l c ontrols a re provid ed t o start and sto p th e analy z er instrument , i nclu din g an auto -trigger mode

which continua lly triggers, capture s and re -arms for the next capture. Facility is also provided to readback

data from th e ins t rument whic h is very usefu l when u s in g multiple analyzer windows.

To start a n acquisi tion:

• Tool bar: Click the RUN icon

• From the Instrument choose Run

• Keyboard: Press the letter R

To halt an acquisi tion:

• Tool bar: Click the HALT icon

• From the Instrument menu choose Stop

• Keyboard: Press the letter S

See Also

Auto-Trigger

Readback Data

Sampling S ignals may be sampled synch ronou sly , using an external clock, or asynchronously, using the logic

analyzer's intern al cl ock. S ample rate s pecificat io ns ar e listed in the specifications section of the online help.

To set u p for synchr onous acquisiti on:

1. Connect the clock leads of the Target Cable Assembly to the tar get circuit clock signal.

2. From the Instrument menu, choose Clock > Clock Edge and click either Rising or Falling depending

on which edge is appropriate.

To set the asynchronous sample rate from the tool bar:

1. From the Instrument menu , choose Clock.

2. Scroll down the list of sample rates until the desired rate is selected, then click the left mouse button.

To set the asynchronous sample rate from the menu bar:

1. From the Instrumentmenu, choose Clock.

2. Scroll down the list of sample rates until the desired rate is selected, then click select it.

See Also

Underst anding Synchronous Sam pling

Underst anding Asynchronous Sampling

Troubleshooting Errors

Silicon Explorer II User's Guide 43

Trou bleshooting S il icon Expl orer

Troubleshooti ng E rror s

Q&A

I've connected Silicon Explorer and the waveform window display reads POLL.

Look on the top of the Silicon Explorer for the flashing yellow "heartbeat", if it is not

flashi ng then make sure you have properly connected an adequate power supply .

It 's flashing but still POLL.

A2 T here are a numb er of thing s t hat ca n prev ent c om mu nic ation f rom being

established. The following are the most common:

Wrong COM por t. T ry al l four COM ports even though you ar e sure that your

mouse is on COM 1.

No power to the analyze r.

Desktop systems external COM connector not connected to the COM port

internally.

Laptop systems external COM connector disabled (IR Port Overr i de?). Use your

PC's CMO S setup program to enable the COM port.

COM port IRQ reassigned for DOS program, control panel not updated.

Multiple mo use dr iv ers in system.ini.

Third-party serial port "enhancers" not conforming to windows API.

Q3 I've got the IDLE message but when I cl i ck RUN, the Waveform window flashes an

error message and returns to IDLE.

A3 If the targe t power is incapable of supp lying the necessary current, then the

Wav efo r m wind ow resets an d return s to ID LE. M any current -limiting sup pli es will

trip when set too close to the operating current.

The Wavefo rm wind ow acquires data a nd then indic ates error s on readback.

A4 The Waveform window bursts data back in blocks at high spe e d, with built-in retry

for a bad block (both checksum and byte count are used). Some third-party serial

programs block all interrupts forcing the analyzer i nto a retry loop.

Some laptops power down the UART and drop a few characters. Try disabli ng

"Power Saving" in the CMOS setup m enu.

W hen the Waveform window is open, my other W indo ws programs r un slo wl y.

Product Support

44 Silicon Explorer II User's Guide

A5 If the Waveform window is open but it is not connected or powered up, then the

syste m is constantly timing out looking for a response . Eithe r close the Waveform

window or change the COM port to DEMO.

The Analyze module acquires data and then indicates errors on read-back . Why?

A1 The Analyze module bursts data back in blocks at high speeds, with built-in retry

for a bad block (it uses both checksum and byte count). Some third-par ty s erial

programs block all interrupts, forcing the analyze r into a retry loop. So me laptops

power down the UART and drop a few characters. Try disabling “Power Saving” in

the C M OS setu p menu .

W hen the Explore window is open, my other W indows programs run slowly. Why?

A If the Explore w indo w is open but not connected or powered up, then the system is

constantly timing out looking for a response. Either close the SE II window or

change the COM port to DEMO.

Q I get a message “Device Timed out” when I try to assign a particular signal to the

Probe pins. Why?

A This message giv es us an indication that the power is not sufficient for the Silicon

Explor er and as a soluti on you would have to add a separate power source for the

Sil ic on Explorer. R efer to Pow ering Silicon Explore r II for more information .

I have assigned an internal signal to PRA and PRB but the PRA and PRB li ght is not

blinking on the Probe Pilot. Is this normal?

A The PRA and the PRB light on the Probe Pilot are just an i ndication of the logic lev el

of tha t assigne d internal signal. If the assigned internal net is at permane nt logi c 0,

the light on the Probe Pilot for the corresponding probe will not glow.

Wh ere ar e m y TM S and S DO pin s?

A Your ca ble will not ha ve th e T MS and th e S DO pins if it was bought befor e the SX

probing capability was introduced. To order a new cable (Si-Ex-Ribbons), contact

Actel customer serv ice at C ustomer .Serv ice@ac tel.com.

Is the Silicon Explorer displaying an incorrect signal?

A Make sure th at th e signal i s s ampled at a sufficien t ly hi gh f requency. T he samplin g

r ate s hould b e at l east twice the frequency of th e f astes t cha nging sig nal. The

m ax i mum f req uency at whic h t he signal ca n be sampled i s 100 M H z w hich l i mits the

frequency of the devic e t o 50 M Hz. If a hi gher s amplin g frequency is required t han

the PRA and the PRB pins can be connected to a logic analyzer to view the signals.

Troubleshooting General

Silicon Explorer II User's Guide 45

Why can't I find the net I wish to probe?

A Sil ic on Explorer li st s only t he sign al s that are a ctu all y pres ent o n t he devic e. There

is a possibility t hat the net whic h you wis h to probe h as been o pt imized in Design er.

Plea se check th e li st of the nets comb in ed in the c ombiner f il e (* .cob) whic h i s

ex ported from Design er File > E xport > A uxil lary Fi le w i th file type *.c ob

W hat are the lim itations in probing devices using Sili con Explorer?

A Probing limitations are described in the table below. Note that -- in dicates t hat t he

feature is unavailab le , and * indicates tha t the fe ature only applies to devices tha t

have Qclock.

Figure 27 · Probing Limitations

Family

Probe Capable

Input

Clock

Hclock

Qclock

ACT1/40MX

ACT2/XL/42MX

ACT3

DX/42MX

SX/SX-A/eX

Troubleshooti ng G eneral

The foll owing is a list of frequently asked questions.

Does Silic on Explorer support ProASIC programming and debugging?

A No. As of today Sili con Explorer does not support either ProASIC programm ing or

debugging.

Q Can we use Silicon Explorer to debug devices which have their security fuses

programmed?

A As a part of the FPGA security featur e the Silicon Explor er cannot be used on

devices w hich have their secur ity fuse programmed.

Troubleshooti ng Software

How do I set up triggering?

Product Support

46 Silicon Explorer II User's Guide

A You have an option of setting trigger either EARLY that displays the values in the

ratio of (25% 75%), where the first % represents the % of data sampled before the

trigger point and the lat er % represent % sampled after the trigger point. The other

options available are CENTER(50% 50%) and LATE(75% 25%). You can select the

trigger position from Instr um ent -> Tri gger Position and then selecting the required

Trigger position.

What is the recommended sampling rate?

A For an accurat e reading, the sampling rat e for a particular signal should be at least

twice the rate at which the signal is changing (According to the Nyquist theorem).

For example, a cl ock operat ing at 25 M H z should b e sampled at l east 50 M Hz

frequency. Be aware that sampling at higher frequencies causes the Silicon

Ex plorer to consume more power.

Wha t is the best way to find nets ?

A The best way to find the nets in the Silicon E xplorer is to u se the F il ter o ptio n

ava i la ble in the sof tware. Y ou can searc h f or t he net y ou req uire by usin g t he

* par tial_name* in the f ilter, whic h w oul d r etu rn all the signals having that

partial_name of the net. If you are using an HDL flow, it may be difficult to recognize

the n et n ames y ou need to o bserv e. Microsemi r ecommend s t hat you use a

synthesis tool that can gene rate a gate-level schematic of your synthesized netlist

so that during probing, you can easily trace through the schematic and obtain the

net n ames from i t .

Troubleshooti ng H ardware

How do I probe an SX-A devi ce?

A The probing of an SX-A device requir es special setup because it requires a 70 ohm

termination on all the probe connectors (TDI, TDO, TCK, TMS, PRA, PRB). The 70

ohm series termination is used to prevent data transmission corruption during

probing.

How do I tie the TRST pin during the probing using Silicon Explor er?

A TRST is an active low input. During JTAG mode and Silicon Explor er debugging

m ode, JT AG state machi ne's reset must not be a ct ive, otherwise probe circuit ry is

disabled. The recommendation for TRST pin in JTAG and Silicon Explorer is listed

below:

RTSX Rev0 - No TRS T pin RTSX R ev1 - You must tie TRST pin high when doing

J TA G and Si l icon E xplorer.

RTSX Rev2 - You can leave the TRST pin floating (or drive it high - it must not be

driven low) when running JTAG or Silicon Explorer if “Reserve JTAG TRST” was

s elec ted in D esign er.

SXA - You can leave the TRST pin floating when running JTAG or Silicon Explorer

Troubleshooting Hardware

Silicon Explorer II User's Guide 47

Q Wha t are the differ ent o pt ions that I have to connect a d evice t o Si licon Explo rer

Probe Pilot?

A You can connect the Silicon Explorer to the device by either implement in g a prob e

connector on the board for use with the ribbon connector or by connecting the

device to the P r obe-Pilot using the flying lead connector. If you choose the second

alt ernative, you can either use posts on your board or the clips provided with the Si

Explor er to connect directly to the probe pins.

Wh ere ca n I find th e pin layout of t he Silicon E xplorer?

A The pin layout for the Silicon Explorer is found on the back of the Silicon Explorer

c ase. There is a notc h on one sid e of th e pin c onnect or tha t determines t he positio n

of Pin 1.

How is t he checksum of the device read?

A The checksu m of most devices is read through the TD O/SD O pin. Refe r to the SDO

pin locations sections for informati on about the location of SDO pins in all Microsemi

Devices. ACT1 and the 40MX pins do not have an SDO pin. In order to read the

checksum from ACT1/40MX devices the PRA on the device must be connected to

the S D O pin of the Silicon E xplorer.

Wha t are the p ower r equiremen t s f or Silicon E xplorer II?

A Silicon Explorer II must be connected to a power supply of 5V for 5V tolerant

devices, 3.3V for 3.3V tolerant devices, and 2.5V for 2.5V tolerant devices.

Product Support

48 Silicon Explorer II User's Guide

Debugging AX/eX/SX/SX-A Devices Using

Si licon Ex plorer II

AX, eX, SX, and SX-A d evices may require additional attention when debugging. You must control probing

on AX, eX, SX and SX-A devices through the IEEE 1149.1 pins. You may configure the IEEE 1149.1 pins as

dedicated ( JTAG only) or fl exible ( J TAG or I/ O ). This s ectio n assists you w ith these an d oth er

considerations when debugging SX, SX-A , or eX devices.

Probe Circuit Control Pins

The Silic on Explorer II t ool uses t he IE E E 1149.1 pins (TDI, TC K, TM S an d TDO) to select th e desired nets

for debugging. Assign the selected internal nets to the PRA/PRB pins for observation. The figures below

show the connections between Silicon Explorer II and the SX/SX-A/eX FPGA required for you to perform in-

circuit debugging and the Axcelerat or Silicon Explorer II Setup.

Figure 28 · eX/SX/SX-A Setup

Figure 29 · Explorer Setup

Diagnostic Pin Consideration

To place the IEEE 1149.1 ( JTAG) and probe pins (TDI, TCK, TMS, TDO, PRA and PRB) in the desired

mode, select the appropriate check boxes in the “Device Variations” dialog box. This dialog box is

acc essible through t he D esign Setup Wizard under the Option menu in Designer.

Troubleshooting Hardware

Silicon Explorer II User's Guide 49

Figure 30 · Diagnostic Pins Configuration

To access the Device Variations dialog box in Designer:

1. Launch Designer.

2. Open your design.

3. From the Options m enu choose Device Setup. The Device Selecti ons dialog box appears.

4. Click Next. The Device Variations dialog box appears.

Dedicated JTAG Mode

Wh en you selec t the “Reserv e JTAG Pin ” box, you place the F PGA i n Dedic ated JTAG m ode, whic h

configures TDI, TCK, and TDO pins for JTAG boundary scan or in-cir c uit debug wit h Silicon Explorer II.

Also, you enable an internal pull-up resistor on both the TMS and TDI pins (see fi gure below). In addition, by

checking the “Reserve JTAG Pin” box, TDI, TCK and TDO are not available for pin assignment in the Pin

Editor.

Product Support

50 Silicon Explorer II User's Guide

Figure 31 · Dedicated JTAG Mode

You do not need to specify an internal pull-up r esistor ; S E II au tomat ical ly co nfi gures TM S and T DI w ith

inter nal pull-up res istors.

Flexible JTAG Mode

Wh en you do not select th e “ R eserv e JTAG Pin” box, y ou place the FP GA in Flexible JT AG mode, where

TDI, TCK and TDO pins may function as user I/Os or JTAG pins. When you select Flexible JTAG mode, you

disable the i nternal pull-up res istors o n th e TM S and T DI pin s. Note that you req ui re a n external 10K Ohm

pull-up re sistor on the TMS pin in this mode (fi gure below). Silicon Explorer II transforms TDI, TCK and TDO

pins from user I/Os into JTAG diagnostic pins when a rising edge at TCK is detected while TMS is at logical

low . The JTAG pi ns r evert t o user I/ Os w hen t he JTAG state ma chin e is i n th e Test-Logi c res et state.

Figure 32 · F lexib le J TAG Mod e with 10K P ullup R esistor

The table below shows the possible configurations of the diagnostic pins.

Table 11 · Diagnostic Pin Configuration

Dedicated JTAG Mode

Flexible JTAG Mode

TCK, TDI, and TDO are dedicated

diagnostic pins.

Use TCK, TDI and TDO as I/O's. You need a 10K

pull-u p r esist or on the TM S Pin.

Probe Pins

Wh en you selec t the R eser ve Pro be P in b ox , yo u di rec t th e layout too l t o r eserv e th e PR A a nd PR B pin s as

diagnostic pins. This option is merely a guideline. If the Lay out tool requires that the PRA and PRB pins be

Internal Probing Feature for Antifuse Families

Silicon Explorer II User's Guide 51

user I/O’s to achieve successful layout, then the tool will use these pins as user I/Os. If you assign user I/Os

to the PRA and PRB pins and select the Reserve Probe Pin option, the Layout tool overrides the “Reserv e

Probe Pin” option.

Design Considerations

Avoid u s in g th e TDI, TC K, TDO , PRA, and P RB pins as inp ut or bidirect io nal p orts. S inc e th ese pins are

active during probing, critical input signals through these pins are not available. In addition, do not program

the S ecurity F use. Pr ogramming t he S ecurity F use disables t he Probe C ircuit . How ever, you can still read

the checksum.

Internal P robi ng F eature f or Antif use F am il ies

Depending on the status of the MODE pin and whether or not the security fuse w as pro grammed, th e I / O

capability of the probe pins varies. The probe pins are the PRA, PRB, SDI, and DCLK pins and are used by

the S i li con Explo rer for internal signal probing. C onsul t the Pi n Editor or th e I /O At trib ute Editor to d etermine

the pin numbers for these pins in the device you are using. The following tables show the I/O capability of

the probe pins for all the MODE/Security combinati ons.

Table 12 · AC T 1 and 40 M X D evices

Mode

Program

Probe

PRA, P RB

SDI, DCL K

Low

User Defined I / O

User Defined Inp ut

Low

Yes

User Defined I / O

User Defined Inp ut

Low

Yes

User Defined I / O

Low

Yes

User Defined I / O

High

Probe Circuit Output s

Probe Circuit Inputs

High

Yes

Pro be C ircuit D i sa bled

Pro b e Circ ui t Disa bl ed

High

Yes

Probe Circuit Output s

Probe Circuit Inputs

High

Yes

Pro be C ircuit D i sa bled

Pro be C ircuit Di sabled

Table 13 · ACT, 1200XL, 3200DX, ACT 3, 42MX

Mode or TMS

Security

PRA, P RB

SDI/TDI, DCLK/TCK

Low

User Defined I / O

High

Probe Circuit Outputs

Probe Circuits Inpu ts

High

Yes

Pro be C ircuit D i sa bled

Pro be C ircuit Di sabled

Table 14 · SX, eX, SX-A, AX

TMS

Security

PRA, P RB, (PRC, PRD) 1

TDI , TCK

Low

User Defined I / O

High

Probe Circuit Output s

Probe Circuit Inputs

Product Support

52 Silicon Explorer II User's Guide

TMS

Security

PRA, P RB, (PRC, PRD) 1

TDI , TCK

High

Yes

Pro be C ircuit D i sa bled

Pro be C ircuit Di sabled

1 The Axcelerator family, with the exception of AX125, has PRA, PRB, PRC, and PRD pins. AX125 only

has PRA and PRB pins.

ACT2 and 1200XL Families

Silicon Explorer II User's Guide 53

SDO Pi n Locations

ACT2 and 1200XL Famili es

The tables below show SDO pin numbers for ACT2 and 1200XL families.

Note: Note: If the SDO pin is configured as an input, do not use Silicon Explorer.

Figure 33 · A1225A/A1225XL

Package

SDO Pin N umber

PLCC8452

CPGA100

PQFP100

VQFP100

Figure 34 · A1240A/A1240XL

Package

SDO Pin N umber

PLCC84

PQFP100

CPGA132

N12

PQFP144

TPFP176

Figure 35 · A1280A/a1280XL

Package

SDO Pin Numbe r

PLCC84

PQFP160

CFP172

CPGA176

P13

TFP176

PQFP208

103

Product Support

54 Silicon Explorer II User's Guide

ACT3 Family SDO Pin Locat ions

The ta bles b elow show SDO pin n umb ers for AC T3 families .

Note: Note: If the SDO pin is configured as an input, do not use Silicon Explorer.

Note: Figure 36 · A1415

Package

SDO Pin N umber

PLCC84

CPGA100

PQFP100

VQFP100

Figure 37 · A1425

Package

SDO Pin N umber

PLCC84

PQFP100

VQFP100

CPGA132

CPGA133

M11

PQFP160

Figure 38 · A1440

Package

SD0 P in Numb er

PLCC84

VQFP100

PQFP160

CPGA175

N12

FQFP176

Figure 39 · A1460

Package

SDO Pin N umber

PQFP160

TQFP176

A3200 Family SDO Pin Locations

Silicon Explorer II User's Guide 55

Package

SDO Pin N umber

CQFP196

CPGA207

P15

PQFP208

103

BGA225

N13

Figure 40 · A14100

Package

SDO Pin N umber

RQFP208

103

CQFP256

126

CPGA257

R17

BGA313

AE23

A320 0 Family SDO P in Locat ions

The tables below show SDO pin numbers for A3200 Family pin locations.

Note: Note: If the SDO pin is configured as an input, do not use Silicon Explorer.

Figure 41 · A3265DX

Package

SDO Pin N umber

PLCC84

PQFP100

PQFP160

TQFP176

Figure 42 · A32100DX

Package

SDO Pin N umber

CQFP84

PLCC84

PQFP160

TQFP176

PQFP208

103

Figure 43 · A32140DX

Product Support

56 Silicon Explorer II User's Guide

Package

SDO Pin N umber

PLCC84

PQFP160

TQFP176

PQFP208

103

CQFP256

Figure 44 · A32200DX

Package

SDO Pin N umber

CQFP208

103

PQFP208

103

RQFP208

106

RQFP240

123

CQFP256

Figure 45 · A32300DX

Package

SDO Pin N umber

RQFP208

106

RQFP240

123

CQFP256

A42MX SDO P in Locat ions

The ta bles b elow show SDO pin n umb ers for A2 MX f amilies .

Note: Note: If the SDO pin is configured as an input, do not use Silic on Explorer.

Figure 46 · A42MX09

Package

SDO Pin N umber

PLCC84

PQFP100

VQFP100

PQFP160

TQFP176

RT SDO Pin Locations

Silicon Explorer II User's Guide 57

Figure 47 · A42MX16

Package

SDO Pin N umber

PLCC84

PQFP100

VQFP100

PQFP160

TQFP176

PQFP208

103

Figure 48 · A1440

Package

SD0 P in N umber

PLCC84

VQFP100

PQFP160

CPGA175

N12

FQFP176

RT SDO Pi n Locati ons

The ta bles b elow show SDO pin n umb ers for R T f amilies .

Note: Note: If the SDO pin is configured as an input, do not use Silicon Explorer.

Figure 49 · RT1280A/RH1280

Package

SDO Pin N umber

CQFP

Figure 50 · RT1425A

Package

SDO Pin N umber

CQFP132

Figure 51 · RT1460A

Package

SDO Pin N umber

CQFP196

Product Support

58 Silicon Explorer II User's Guide

Figure 52 · RT14100A

Package

SDO Pin N umber

CQFP256 126

Note: Note: AC T1 a nd 40M X devic e fami lies do not co nta in SDO pins. PR A f rom the devi ce m us t be

connected to SDO input of Silicon Expl orer. Devi ces not listed ( i.e. 42M X 24/A 42M X 36, S X, eX, S X-A,

RTSX, RTSX-S, and A X) , conta i n a TDO pin. Plea se check t he "P ackage Pin D escriptio n" sect ion of

the appropriate datasheet at http://www.actel.com/techdocs/ds/default.aspx.

Silicon Explorer Specifications

Silicon Explorer II User's Guide 59

Specifications

Sili con Explorer S pecif ications

Table 15 · Specifications

Input

Channels

18 plus external clock

Sample R ate

1kSa/s to 100 MSa/s

Minimum Pulse

Width

7 nsec

Buffer

64K samples per channel

Setup/Hold

2.1 nsec / 0 n sec

Impedance

220k ohm, 10pf typic al

Input Voltage

+7V to -3V max

Clock

Asynchronous

1kSa/s to 100 MSa/s

Synchronous

0 to 66MHz

Trigger 18 channel word recognition

High, low and don't care levels on all channels

Built-in edge detec tion for rising, falling or either edge

Sil ic on Explorer: 1 level of t r ig ger

Silicon Explorer II: 4 levels of trigger

Operating Environm ents

Temperature

0° to 30° Celsius

Power

+3V to +5.5V @ 1.25A maximum

Compliance

System

Requirements

See th e latest Silicon Expl orer R elea se Notes on w w w.ac tel.com

for System Requirem ents.

Product Support

60 Silicon Explorer II User's Guide

Accessories

The fo l lowing accessories are a vaila ble for Silicon E x plorer.

Quick Probe Clips

The Quick Probe Clips kit contains 10 micrograbbers for connecting the target cable assembly to test points

on the target board.

Figure 53 · Quick Probe C lip s

TCA Cable The TC A cable k i t contains a replacement logic analysis cable for connecting the 18 channel inputs to the

target board.

Figure 54 · TCA Ca ble

Ribbon and Breakout Cables

The Ribbon and Breakout cables accessory kit contai ns replacem ent cables for connecting the JTAG control

port of the Silicon Explorer to the target board. The Ribbon cable mates with a standard 16 pin header on

the target board. The Breakout cable has individual contacts on the target end to mate with individual test

points on the target board. The Breakout cable can also be used wit h the Quick Probe Clips to make

connection to the target board.

Silicon Explorer Specifications

Silicon Explorer II User's Guide 61

Figure 55 · Ribbon and Breakout Cables

Product Support

62 Silicon Explorer II User's Guide

Glossary of Term s

A B C D E F G,H I J,K,L M,N,O,P Q R S T U,V W,X,Y,Z

Acquisition - The sampling of data from a system under test. Data is stored in acquisition memory so it can

be dis played in different formats or compar ed to other acquired data.

Acquisition Clock - The clo ck t hat d etermines t he rate at whic h th e l ogic analy zer s amp les data. The clo ck

can be an internal analyzer clock with user-s electa ble s ample rate (asyn chronous) , or it can be an external

c lo ck with t he samplin g r ate d eter mined by the system under test (synchronous).

From these sample points, a list of ones and zeros is generated that represents a one-bit picture of the input

wavefo r m. A s far as t he analy z er is concern ed, the w avefo r m i s eit her high or low , no inter mediate steps.

This list is stored in memory and is also used to reconstruct a one-bit picture of the input waveform, as

shown above.

The sample clo ck c an be generated intern ally by the log ic analy zer. This is of ten referred to as

Asynchronous s amplin g, since the sampling is not synchrono us to any signal in the circuit under test. This

m ode is also r eferred to a s Timing Mode since th e displa y show s the timing relationships between input

signals. To get accurate timing informa tion it is nece ssary that the sample rate of th e clo c k i s faster th an t he

rate at which the signals change.

An external signal may also be used as the sample clock. This sampli ng m ode and i s referred to as

Synchronous s ampling sinc e i t i s synchron ous to a n external signal , usua lly from the syste m under test. It is

also referred to as State Mode sinc e th e dis play show s t he state of the input signals at the mom ents when

the cl ock occurred. S ee also external clock and internal clock.

Acquisition Memo ry - The memory in whic h data acquired by t he lo gic a nalyzer is stored. L ogic a naly z ers

typic ally have m emory to store s evera l t housand samp les p er channel.

Conceptuall y, the acquisition memory acts as a circula r buffer. Once t he analyzer is sta r ted , samp les are

stor ed in sequence. If the analy zer fill s memory before a trigger occurs, it will continue to acquire data with

the n ewest data o ver-writin g th e old est. O nce a trigg er oc curs, th e analyzer wi ll either:

1. Stop im m edi a t el y - acquisition memory cont ains wavefor m dat a of signal activity leading up to t he t rigger only (also cal led pre-trigger data).

2. Fill the enti r e memor y once m or e - acquisition mem or y cont ains wavefor m dat a of signal activity t hat occur r ed aft er the trigger ( also called post-trigger data).

3. Fill onl y a porti on of mem or y - acquisition memory cont ains both pre-trigger and post tri gger infor mat ion.

Silicon Explorer Specifications

Silicon Explorer II User's Guide 63

Aliasing - The condition that occurs w hen data from the t ar get s ystem is sampled a t a rate s low er than the

rate at which data changes. When this happens, meaningless data is displayed because the analyzer

m isses t he changes i n dat a t hat oc curred between sample points.

ASCII - stands for American Standard Code for Informati on Interchange. ASCII is an ei ght bit numeric c ode

tha t repres ents text chara cters.

Asynchronous Acquisition - An acquisition that is made using a clock signal generated internally by the

analyzer. This clock is unrelated to the clock in the target system , and can be set by the user.

Bus - See Channel Bus

Channel - An input signal line used by the logic analyzer to acquire data.

Channel Bus - A user -defi ned group of input channels whose com bined num eric value is displayed in a

user sp ecified radix.

Clock - The reg ular sign al pulse t hat deter mines th e sam pling rate for th e logic analy zer. See als o

acquis ition c lock, external clock, and interna l clock.

Clock Qualifier - An external signal that acts as a gate for the acquisition clock. When the external signal is

false, the acquisition cloc k is not allowed to load acquir ed data into acquisition memory.

The Clock Qualifier is handy when we only want to o bserv e s i gnal acti vi ty taking pla ce w hen a partic ular

c hip is s elec ted . F or exa mple, i f the system under test has three devic es of th e same type connected t o a

common bus, one of which appears to be defective, we mi ght want to record signal activity on the bus only

when the suspect d evice i s s elec ted .

If the logic a naly z er's Cloc k Q uali fier input w ere c onnected to the chip select lin e of the devic e w e were

int erested in, the analyzer would record data only when the chip's select line was active. The C lock Q ual ifier

allows us to filter out irrelevant data by only clocking data of interest into the sample buffer. See also

acquis ition memory.

Collapse Bus - The process of retur ning a channel bus from its expanded view to i ts b us v iew. S ee expand

bus.

Condition - A value or event which the logic analy zer can recognize. A condition can be a transition on a

single channel, a com bination of logic highs and lows across multiple channels, a certain number of clock

c ycles, etc. See als o pattern.

Cursor - A v ertic al line repres enting a specific l ocation on t he log ic analy zer displa y .

Def ine Bus - The process of grouping a set of related signals together as a single, composite signal whose

v alu e i s the numeri c combinat io n of signals it contains . See undef ine bus.

Don't Care - A symbol indicating that the channel(s) associated with the symbol may be any logic logic

value and the trigger, find or hig hl ig ht p attern wi ll s til l match. (see find, highlight, and trigger)

Download - The process of transferri ng acquisition memory contents from the Pod to the host computer.

Edge - A signal tr ansiti on from low to high or from high to low.

Edge Triggering - The method of triggering on a low-to-hig h or high-to-low transition instead of on a low or

high voltage thres hold.

Expand Bus - The process of displaying the individual signal which make up a bus, wit hout undefining the

gro up. S ee collapse bus.

Exte rnal Clock - A clock signal external t o the logic analyzer and usually synchronous with the system

under test. See a lso acquisition c lock and internal clock.

Exter nal Clocki ng - A clock mode in which the sampling of the input signals is synchronous with the

exte rnal clock signal .

Find Pattern - A pattern used to locate a specific data pattern within acquisition memory.

G, H

Product Support

64 Silicon Explorer II User's Guide

Highlight - Identific ation all occurrences of a specific data pattern by changing the background color of the

data d ispl ay at all points w here the data pattern exists.

Int ernal Cloc k - The internal logic analyzer clock used to determi ne the rate at which the input signals are

s ampled. See also acquis ition c lock and external clock.

J, K, L

Level - Refers to the reference made of a s ig nal as being a logic high or low based on the signal's voltage at

that instant.

M, N, O, P

Pattern - A set of logic conditions (high, low, rising edge, falling edge either edge or don't care) for each

channel of the logic analyzer. Patterns define the criteria for triggeri ng the analyzer, locating data and

highlighting data.

Post-Trigger D ata - D ata th at o cc urred after the trig ger event.

Pre-Trigger Data - Data the occurred before the trigger event.

Probing - Refers to c ont ro l lin g the Pro be P ilot function of Silicon Explorer which enables the dynamic routi ng

of two internal n odes to two d edicated pins of Actel devices.

Qualifier - See c lock qualifier

Radix - The alphanumeri c base in which the data is displayed. For example, logic a naly z ers typi cal ly dis play

data in hexadecimal, binary, integer, ASCII, analog, etc.

Resolution - See sample resolution

Risi ng Edge - A signal trans ition from logic low to logic high.

Sample Cloc k - See acquisition clock

Sampl e Rate - The speed at which the in put sig nals a re s am pled , often expres sed in mega-samples per

second (M S a/s). S elec ting the p ro per sample rate is impo r ta nt in ensuring t he sign als are displa yed

acc urately, and completely. See Understanding Asynchronous Sampling

Sample Resoluti on - The interval (in seconds) between samples, determined by the frequency of the

s ample clo ck. S ee Understanding Asynchronous Sampling

State Display - A di splay m ode in whic h acquisitio n data is pr esented verti cally in ti me as a column of

samples.

Synchronous Acquisition - An acquisition m ode in w hic h an external signa l is used to clock acquisi tion

data into the anal yz er.

Timing Display - A display mode in which acquisition data is displayed as horizontally in time as signal

waveforms.

Trigger - An event or conditi on that determines the end of the acquisition cycle. When started, the analyzer

continuously acquir es data from the systems under test until the trigger occurs. After triggering, the analyzer

continues to load data until the post-fill requiremen t is met. See als o post-trigger data and pre-trigger data.

Tri gger Patter n - A trigger pattern is a t r ig ger co nditio n com prised of logic l evels and/or ed ges on one or

more channels.

Tri gger Positi on - The location of the trigger event in m emory. The trigger can be at the beginning, middle

or end of acquisition m emory, letting the user vi ew pre and post-t rigger data . See als o post-trigger data and

pre-trigger data.

U, V

Undefi ne Bus - The pro cess of u n-grouping a channel bus so the individual signals are display ed.

W, X, Y, Z

Waveform Display - See timing display.

Silicon Ex plorer II User's Guide 65

Product Sup port

The Microsemi SoC Products Group backs its products with various support s ervices inclu din g a C ustomer

Techni cal Support Center and Non-Tec hnical Customer S ervi ce. This append ix contains infor ma t io n about

contacting the SoC Products Group and using these support services.

Contacti ng the Customer Tec hnical S upport Center

Microsemi staffs its Custom er Technical Support Center with highly skilled engineers who can help answer

your hardware, software, and design questions. The Customer Technical Support Center spends a great

deal of tim e creati ng application notes and answers to FAQs. So , b efore you conta ct us , please visit our

online resources. It is very likely we have already answered your questi ons.

Technical Support

Microsemi customers can receive technical support on Microsemi SoC products by calling Technical

Support Hotline anytime Monday through Friday. Custom ers also have the option to interactively submit and

track cases online at My Cases or submit questions through email anytime during the week.

Web : ww w . actel .c om/my cases

Phone (North America): 1.800.262.1060

Phone (International): +1 650.318.4460

E mail: soc_ te ch@ mi cr osemi.com

ITAR Technical Support

Microsemi customers can receive ITAR technical support on Microsemi SoC products by calling ITAR

Techni cal Support Hotline: Monday thr ough Friday, from 9 AM to 6 PM Pacifi c Time. C ustomers also have

the option to interactively submit and track cases online at My Cases or submit questions through em ail

anyti me dur ing the week.

Web : ww w . actel .c om/my cases

Phone (North America): 1.888.988.ITAR

Phone (I nternati onal): +1 650.318.4900

E mail: soc_tech_itar@ mic rosemi.co m

Non-Technical C ustomer Servi ce

Contact Customer Service for non-technical product suppor t, such as product pricing, produc t upgrades,

update inf ormation, order status, and authorization.

Microsemi ’s customer service representatives are available Monday through Friday, from 8 AM to 5 PM

Pacific Tim e, to answer non-technical questions.

Phone: +1 650.318.2470

5-029134-2/05.12

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