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FEATURES DESCRIPTION
BLOCK DIAGRAM
11
A/B
Vcc 7 12
5 9
GROUND
4 7
RT/CT
2 3
VFB
1 1COMP
3 5
CURRENT
SENSE
34 V
2.50 V
OSC
UVLO
S/R 5 V
REF
VREF
Good
Logic
Internal
BIAS
Error
Amp 2R
R1 V CURRENT
SENSE
COMPARATOR
PWM
LATCH
S
R
T
8 14
VREF
5 V
50 mA
7
VC
106
OUTPUT
85
POWER
GROUND
Note 1:
Note 2: A = DIL−8 Pin Number. B = SO−14 and CFP−14 Pin Number.
Toggle flip flop used only in 1844 and 1845.
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
SLUS223C – APRIL 1997 – REVISED JUNE 2007
CURRENT MODE PWM CONTROLLER
•Optimized For Off-line and DC-to-DC
The UC1842/3/4/5 family of control devices providesConverters
the necessary features to implement off-line ordc-to-dc fixed frequency current mode control•Low Start-Up Current (<1 mA)
schemes with a minimal external parts count.•Automatic Feed Forward Compensation
Internally implemented circuits include under-voltage•Pulse-by-Pulse Current Limiting
lockout featuring start up current less than 1 mA, aprecision reference trimmed for accuracy at the error•Enhanced Load Response Characteristics
amp input, logic to insure latched operation, a PWM•Under-Voltage Lockout With Hysteresis
comparator which also provides current limit control,•Double Pulse Suppression
and a totem pole output stage designed to source orsink high peak current. The output stage, suitable for•High Current Totem Pole Output
driving N-Channel MOSFETs, is low in the off state.•Internally Trimmed Bandgap Reference
Differences between members of this family are the•500-kHz Operation
under-voltage lockout thresholds and maximum duty•Low R
O
Error Amp
cycle ranges. The UC1842 and UC1844 have UVLOthresholds of 16 V
ON
and 10 V
OFF
, ideally suited tooff-line applications. The corresponding thresholdsfor the UC1843 and UC1845 are 8.4 V and 7.6 V.The UC1842 and UC1843 can operate to duty cyclesapproaching 100%. A range of zero to 50% isobtained by the UC1844 and UC1845 by the additionof an internal toggle flip flop which blanks the outputoff every other clock cycle.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1997–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
(1)
CONNECTION DIAGRAMS
1
2
3
4
8
7
6
5
COMP
VFB
ISENSE
RT/CT
VREF
VCC
OUTPUT
GROUND
DIL-8, SOIC-8
N or J PACKAGE, D8 PACKAGE
(TOP VIEW)
NC − No internal connection
1
2
3
4
5
6
7
14
13
12
11
10
9
8
COMP
NC
VFB
NC
ISENSE
NC
RT/CT
SOIC-14, CFP-14
D or W PACKAGE
(TOP VIEW)
VREF
NC
VCC
VC
OUTPUT
GROUND
PWR GND
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
VCC
VC
NC
OUTPUT
NC
NC
VFB
NC
ISENSE
NC
PLCC-20
Q PACKAGE
(TOP VIEW)
NC
COMP
NC
PWR GND
GROUND NC
NC
NC
RT/CT
VREF
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
SLUS223C – APRIL 1997 – REVISED JUNE 2007
UNIT
Low impedance source 30 VSupply voltage
I
CC
< 30 mA Self LimitingOutput current ±1 AOutput energy (capacitive load) 5 µJAnalog inputs (Pins 2, 3) –0.3 V to 6.3 VError amp output sink current 10 mAT
A
≤25 °C (DIL-8) 1 WPower dissipation T
A
≤25 °C (SOIC-14) 725 mWT
A
≤25 °C (SOIC-8) 650 mWStorage temperature range –65 °C to 150 °CJunction temperature range –55 °C to 150 °CLead temperature (soldering, 10 seconds) 300 °C
(1) All voltages are with respect to Pin 5. All currents are positive into the specified terminal. Consult Packaging Section of Databook forthermal limitations and considerations of packages.
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Temp Stability +VREF(max)*VREF (min)
TJ(max)*TJ (min)
V
REF(max)
and V
REF(min)
are the maximum and minimum reference voltages measured over
THERMAL CHARACTERISTICS
DISSIPATION RATINGS
ELECTRICAL CHARACTERISTICS
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
SLUS223C – APRIL 1997 – REVISED JUNE 2007
over operating free-air temperature range (unless otherwise noted)
PACKAGE θ
JC
θ
JA
DIL-8 J 28
(1)
125-160N 25 110
(2)
SOIC-8 D8 42 84-160
(2)
SOIC-14 D14 35 50-120
(2)
CFP-14 W 5.49 °C/W 175.4C/WPLCC-20 Q 34 43-75
(2)
(1) θ
JC
data values stated were derived from MIL-STD-1835B.(2) Specified θ
JA
(junction to ambient) is for devices mounted to 5 in
2
FR4 PC board with one ounce copper where noted. When resistancerange is given, lower values are for 5 in
2
. Test PWB was 0.062 in thick and typically used 0.635-mm trace widths for power packagesand 1.3-mm trace widths for non-power packages with 100 x 100-mil probe land area at the end of each trace.
T
A
≤25 °C DERATING FACTOR T
A
≤70 °C T
A
≤85 °CPO T
A
≤125 °CPACKAGE
POWER RATING ABOVE T
A
≤25 °C POWER RATING WER RATING POWER RATING
W 700 mW 5.5 mW/ °C 452 mW 370 mW 150 mW
Unless otherwise stated, these specifications apply for –55 °C≤T
A
≤125 °C for the UC184X; –40 °C≤T
A
≤85 °C for theUC284X; 0 °C≤T
A
≤70 °C for the 384X; V
CC
= 15 V
(1)
; R
T
= 10 k Ω; C
T
= 3.3 nF, T
A
= T
J
.
UC1842/3/4/5
UC3842/3/4/5UC2842/3/4/5PARAMETER TEST CONDITIONS UNITMIN TYP MAX MIN TYP MAX
REFERENCE SECTION
Output Voltage T
J
= 25 °C, I
O
= 1 mA 4.95 5.00 5.05 4.90 5.00 5.10 VLine Regulation 12 ≤V
IN
≤25 V 6 20 6 20
mVLoad Regulation 1 ≤I
0
≤20 mA 6 25 6 25Temp. Stability See
(2) (3)
0.2 0.4 0.2 0.4 mV/ °CTotal Output Variation Line, load, tempature
(2)
4.9 5.1 4.82 5.18 VOutput Noise Voltage 10 Hz ≤f≤10 kHz, T
J
= 25 °C
(2)
50 50 µVLong Term Stability T
A
= 125 °C, 1000 Hrs
(2)
5 25 5 25 mVOutput Short Circuit –30 –100 –180 –30 –100 –180 mA
OSCILLATOR SECTION
Initial Accuracy T
J
= 25 °C
(4)
47 52 57 47 52 57 kHzVoltage Stability 12 ≤V
CC
≤25 V 0.2% 1% 0.2% 1%Temp. Stability T
MIN
≤T
A
≤T
MAX
(2)
5% 5%Amplitude V
PIN
4 peak-to-peak
(2)
1.7 1.7 V
(1) Adjust V
CC
above the start threshold before setting at 15 V.(2) These parameters, although specified, are not 100% tested in production.(3) Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation:
the appropriate temperature range. Note that the extremes in voltage do not necessarily occur at the extremes in temperature.(4) Output frequency equals oscillator frequency for the UC1842 and UC1843.Output frequency is one half oscillator frequency for the UC1844 and UC1845.
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(7) Gain defined as:
A+DVPIN 1
DVPIN 3, 0 vVPIN 3 v0.8 V
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
SLUS223C – APRIL 1997 – REVISED JUNE 2007
ELECTRICAL CHARACTERISTICS (continued)Unless otherwise stated, these specifications apply for –55 °C≤T
A
≤125 °C for the UC184X; –40 °C≤T
A
≤85 °C for theUC284X; 0 °C≤T
A
≤70 °C for the 384X; V
CC
= 15 V ; R
T
= 10 k Ω; C
T
= 3.3 nF, T
A
= T
J
.
UC1842/3/4/5
UC3842/3/4/5UC2842/3/4/5PARAMETER TEST CONDITIONS UNITMIN TYP MAX MIN TYP MAX
ERROR AMP SECTION
Input Voltage V
PIN 1
= 2.5 V 2.45 2.50 2.55 2.42 2.50 2.58 VInput Bias Current –0.3 –1 –0.3 –2 µAA
VOL
2≤V
O
≤4 V 65 90 65 90 dBUnity Gain Bandwidth T
J
= 25 °C
(5)
0.7 1 0.7 1 MHzPSRR 12 ≤V
CC
≤25 V 60 70 60 70 dBOutput Sink Current V
PIN 2
= 2.7 V, V
PIN 1
= 1.1 V 2 6 2 6
mAOutput Source Current V
PIN 2
= 2.3 V, V
PIN 1
= 5 V –0.5 –0.8 –0.5 –0.8V
OUT
High V
PIN 2
= 2.3 V, R
L
= 15 k Ωto ground 5 6 5 6
VV
OUT
Low V
PIN 2
= 2.7 V, R
L
= 15 k Ωto Pin 8 0.7 1.1 0.7 1.1
CURRENT SENSE SECTION
Gain See
(6) (7)
2.85 3 3.15 2.85 3 3.15 V/VMaximum Input Signal V
PIN 1
= 5 V
(6)
0.9 1 1.1 0.9 1 1.1 VPSRR 12 ≤V
CC
≤25 V
(5) (6)
70 70 dBInput Bias Current –2 –10 –2 –10 µADelay to Output V
PIN 3
= 0 V to 2 V
(5)
150 300 150 300 ns
OUTPUT SECTION
I
SINK
= 20 mA 0.1 0.4 0.1 0.4Output Low Level
I
SINK
= 200 mA 1.5 2.2 1.5 2.2
VI
SOURCE
= 20 mA 13 13.5 13 13.5Output High Level
I
SOURCE
= 200 mA 12 13.5 12 13.5Rise Time T
J
= 25°C, C
L
= 1 nF
(5)
50 150 50 150
nsFall Time T
J
= 25 °C, C
L
= 1nF
(5)
50 150 50 150
UNDER-VOLTAGE LOCKOUT SECTION
X842/4 15 16 17 14.5 16 17.5Start Threshold
X843/5 7.8 8.4 9.0 7.8 8.4 9.0
VX842/4 9 10 11 8.5 10 11.5Min. Operating Voltage AfterTurn On
X843/5 7.0 7.6 8.2 7.0 7.6 8.2
PWM SECTION
X842/3 95% 97% 100% 95% 97% 100%Maximum Duty Cycle
X844/5 46% 48% 50% 47% 48% 50%Minimum Duty Cycle 0% 0%
TOTAL STANDBY CURRENT
Start-Up Current 0.5 1 0.5 1
mAOperating Supply Current V
PIN 2
= V
PIN 3
= 0 V 11 17 11 17V
CC
Zener Voltager I
CC
= 25 mA 30 34 30 34 V
(5) These parameters, although specified, are not 100% tested in production.(6) Parameter measured at trip point of latch with V
PIN 2
= 0.
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ERROR AMP CONFIGURATION
_
+
2.5 V
2
1
VFB
COMP
ZF
ZI
0.5 mA
UNDER-VOLTAGE LOCKOUT
VCC
<17 mA
<1 mA
VOFF VON
VCC
7
VCC ON/OFF Command
to REST of IC
UC1842
UC1844 UC1843
UC1845
VON
VOFF
16 V
10 V
8.4 V
7.6 V
CURRENT SENSE CIRCUIT
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
SLUS223C – APRIL 1997 – REVISED JUNE 2007
Error amp can source or sink up to 0.5 mA.
During under-voltage lock-out, the output drive is biased to sink minor amounts of current. Pin 6 should beshunted to ground with a bleeder resistor to prevent activating the power switch with extraneous leakagecurrents.
A small RC filter may be required to suppress switch transients.
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OSCILLATOR SECTION
8
4
5
VREF
RT/CT
GROUND
RT
CT
For RT> 5 K f ~1.72
RTCT
30
10
3
1
0.3
td− ms
1 2.2 4.7 10 22 47 100
CT − nF
Deadtime vs CT (RT >5 kW)
RT− (k )W
100
30
10
3100 1 k 10 k 100 k 1 M
f − Frequency − Hz
Timing Resistance vs Frequency
OUTPUT SATURATION CHARACTERISTICS
4
3
2
1
0.01 .02 .03 .04 .05 .07 .1 .2 .3 .4 .5 .7 1
SINK SAT (VOL)
SOURCE SAT
(VCC − VOH)
VCC = 15 V
TA = 25°C
TA = −55°C
Output Current, Source or Sink − A
Saturation Voltage − V
ERROR AMPLIFIER OPEN-LOOP FREQUENCY RESPONSE
80
60
40
20
0
0
−45
−90
−135
−180
Voltage Gain − dB
Phase Margin − °
Av
θ
10 100 1 k 10 k 100 k 1 M 10 M
f − Frequency − Hz
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
SLUS223C – APRIL 1997 – REVISED JUNE 2007
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OPEN-LOOP LABORATORY FIXTURE
4.7 kW
1 kW
ERROR AMP
ADJUST
4.7 kW
5 kW
ISENSE
ADJUST
2N2222
100 kW
R1
1
2
3
4
8
7
6
5
COMP
UC1842
VFB
ISENSE
RT / CT
CT
0.1 mF
0.1 mF
A
1 kW1 W
VREF
VCC
OUTPUT
GROUND
VREF
VCC
OUTPUT
GROUND
SHUTDOWN TECHNIQUES
8
3
1 kW
330 W
SHUTDOWN
500 W
To Current
SENSE RESISTOR
VREF
ISENSE
1
SHUTDOWN
COMP
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
SLUS223C – APRIL 1997 – REVISED JUNE 2007
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypascapacitors should be conected close to pin 5 in a single point ground. The transistor and 5k potentiometer areused to sample the oscillator waveform and apply an adjustable ramp to pin 3.
Shutdown of the UC1842 can be accomplished by two methods; either raise pin 3 above 1 V or pull pin 1 belowa voltage two diode drops above ground. Either method causses the output of the PWM comparator to be high(refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clockcycle after the shutdown condition at pin 1 and/or 3 is removed. In one example, an externally latched shutdownmay be accomplished by adding an SCR which will be reset by cycling V
CC
below the lower UVLO threshold. Atthis pint the reference turns off, allowing the SCR to reset.
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OFFLINE FLYBACK REGULATOR
R1
5 Ω 1 W
117 VAC VARO
VM 68 C1
250 µF
250 V R2
56 kΩ
2 W
R12
4.7 kΩ
2 W
C9
3300 pF
600 V NP
D4
1N3613
D2
1N3612 D3
1N3612
NC
R3
20 kΩ
R4
4.7 kΩ
C4
47 µF
25 V
R9
68 Ω
3 W
C3
22 µF
C2
100 µF
25 V
7
2
1
8
453
6
UC3844
R5 150 kΩ
C14
100 pF
R6
10 kΩ
C5
0.01 µFC6
0.0022 µF
USD1120
R7
22 Ω
R8
1 kΩ
C7
470 pF R13
20 kΩR10
0.55 Ω
1 W
Q1
UFN833
T1 D6
U9D946 L1
N5 C10
4700 µF
10 V
C11
4700 µF
10 V
+6 V
COM
+12 V
±12 V COM
−12 V
D7
UF81002
N12
N12
C12
2200 µF
16 V
C13
2200 µF
16 V
D8
UES1002
C8
680 pF
600 V
D8
1N3613 R11
2.7 kΩ
2 W
Power Supply Specifications
SLOPE COMPENSATION
8
4
3
VREF
RT / CT
ISENSE
UC1842/3
0.1 mFRT
CT
R1 R2
C
ISENSE
RSENSE
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
SLUS223C – APRIL 1997 – REVISED JUNE 2007
1. Input Voltagesa. 5VAC to 130VA (50 Hz/60 Hz)2. Line Isolation: 3750 V3. Switchng Frequency: 40 kHz4. Efficiency at Full Load 70%5. Output Voltage:a. +5 V, ±5%; 1A to 4A loadRipple voltage: 50 mV P-P Maxb. +12 V, ±3%; 0.1A to 0.3A loadRipple voltage: 100 mV P-P Maxc. –12 V, ±3%; 0.1A to 0.3A loadRipple voltage: 100 mV P-P Max
A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slopecompensation for converters requiring duty cycles over 50%.
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-8670401PA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 8670401PA
UC1842
5962-8670401XA ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
8670401XA
UC1842L/
883B
5962-8670402PA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 8670402PA
UC1843
5962-8670402XA ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
8670402XA
UC1843L/
883B
5962-8670403PA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 8670403PA
UC1844
5962-8670403XA ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
8670403XA
UC1844L/
883B
5962-8670404DA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type 5962-8670404DA
UC1845W/883B
5962-8670404PA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 8670404PA
UC1845
5962-8670404XA ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
8670404XA
UC1845L/
883B
UC1842J ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 UC1842J
UC1842J883B ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 8670401PA
UC1842
UC1842L883B ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
8670401XA
UC1842L/
883B
UC1842W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 UC1842W
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
UC1843J ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 UC1843J
UC1843J883B ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 8670402PA
UC1843
UC1843L ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 UC1843L
UC1843L883B ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
8670402XA
UC1843L/
883B
UC1843W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 UC1843W
UC1844J ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 UC1844J
UC1844J883B ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 8670403PA
UC1844
UC1844L883B ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
8670403XA
UC1844L/
883B
UC1845J ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 UC1845J
UC1845J883B ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 8670404PA
UC1845
UC1845L ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 UC1845L
UC1845L883B ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
8670404XA
UC1845L/
883B
UC1845W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 UC1845W
UC1845W883B ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type 5962-8670404DA
UC1845W/883B
UC2842D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2842D
UC2842D8 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2842
D8
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 3
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
UC2842D8G4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2842
D8
UC2842D8TR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2842
D8
UC2842D8TRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2842
D8
UC2842DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2842D
UC2842DTR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2842D
UC2842DTRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2842D
UC2842J OBSOLETE CDIP JG 8 TBD Call TI Call TI -40 to 85
UC2842N ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 UC2842N
UC2842NG4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 UC2842N
UC2843D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2843D
UC2843D8 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2843
D8
UC2843D8G4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2843
D8
UC2843D8TR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2843
D8
UC2843D8TRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2843
D8
UC2843DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2843D
UC2843DTR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2843D
UC2843DTRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2843D
UC2843J OBSOLETE CDIP JG 8 TBD Call TI Call TI -40 to 85
UC2843N ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 UC2843N
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 4
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
UC2843NG4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 UC2843N
UC2844D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2844D
UC2844D8 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2844
D8
UC2844D8G4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2844
D8
UC2844D8TR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2844
D8
UC2844D8TRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2844
D8
UC2844DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2844D
UC2844DTR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2844D
UC2844DTRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2844D
UC2844N ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 UC2844N
UC2844NG4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 UC2844N
UC2845D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2845D
UC2845D8 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2845
D8
UC2845D8G4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2845
D8
UC2845D8TR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2845
D8
UC2845D8TRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2845
D8
UC2845DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2845D
UC2845DTR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2845D
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 5
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
UC2845DTRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 UC2845D
UC2845J OBSOLETE CDIP JG 8 TBD Call TI Call TI -40 to 85
UC2845N ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 UC2845N
UC2845NG4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 UC2845N
UC3842D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3842D
UC3842D8 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3842
D8
UC3842D8G4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3842
D8
UC3842D8TR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3842
D8
UC3842D8TRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3842
D8
UC3842DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3842D
UC3842DTR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3842D
UC3842DTRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3842D
UC3842N ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 UC3842N
UC3842NG4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 UC3842N
UC3843D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3843D
UC3843D8 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3843
D8
UC3843D8G4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3843
D8
UC3843D8TR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3843
D8
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 6
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
UC3843D8TRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3843
D8
UC3843DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3843D
UC3843DTR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3843D
UC3843DTRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3843D
UC3843N ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 UC3843N
UC3843NG4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 UC3843N
UC3843QTR OBSOLETE PLCC FN 20 TBD Call TI Call TI 0 to 70
UC3844D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3844D
UC3844D8 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3844
D8
UC3844D8G4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3844
D8
UC3844D8TR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3844
D8
UC3844D8TRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3844
D8
UC3844DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3844D
UC3844DTR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3844D
UC3844DTRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3844D
UC3844N ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 UC3844N
UC3844NG4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 UC3844N
UC3845AJ ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type 0 to 70 UC3845AJ
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 7
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
UC3845D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3845D
UC3845D8 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3845
D8
UC3845D8G4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3845
D8
UC3845D8TR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3845
D8
UC3845D8TRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3845
D8
UC3845DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3845D
UC3845DTR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3845D
UC3845DTRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 UC3845D
UC3845N ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 UC3845N
UC3845NG4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 UC3845N
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 8
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UC1842, UC1843, UC1844, UC1845, UC3842, UC3843, UC3844, UC3845, UC3845AM :
•Catalog: UC3842, UC3843, UC3844, UC3845, UC3842M, UC3845A
•Military: UC1842, UC1843, UC1844, UC1845
•Space: UC1842-SP, UC1843-SP, UC1844-SP, UC1845-SP
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
UC2842D8TR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UC2842DTR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
UC2843D8TR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UC2843DTR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
UC2844D8TR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UC2844DTR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
UC2845D8TR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UC2845DTR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
UC3842D8TR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UC3842DTR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
UC3843D8TR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UC3843DTR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
UC3844D8TR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UC3844DTR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
UC3845D8TR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UC3845DTR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UC2842D8TR SOIC D 8 2500 340.5 338.1 20.6
UC2842DTR SOIC D 14 2500 333.2 345.9 28.6
UC2843D8TR SOIC D 8 2500 340.5 338.1 20.6
UC2843DTR SOIC D 14 2500 333.2 345.9 28.6
UC2844D8TR SOIC D 8 2500 340.5 338.1 20.6
UC2844DTR SOIC D 14 2500 333.2 345.9 28.6
UC2845D8TR SOIC D 8 2500 340.5 338.1 20.6
UC2845DTR SOIC D 14 2500 333.2 345.9 28.6
UC3842D8TR SOIC D 8 2500 340.5 338.1 20.6
UC3842DTR SOIC D 14 2500 333.2 345.9 28.6
UC3843D8TR SOIC D 8 2500 340.5 338.1 20.6
UC3843DTR SOIC D 14 2500 333.2 345.9 28.6
UC3844D8TR SOIC D 8 2500 340.5 338.1 20.6
UC3844DTR SOIC D 14 2500 333.2 345.9 28.6
UC3845D8TR SOIC D 8 2500 340.5 338.1 20.6
UC3845DTR SOIC D 14 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUAR Y 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,16)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
MECHANICAL DATA
MPLC004A – OCTOBER 1994
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER
4040005/B 03/95
20 PIN SHOWN
0.026 (0,66)
0.032 (0,81)
D2/E2
0.020 (0,51) MIN
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D2/E2
0.013 (0,33)
0.021 (0,53)
Seating Plane
MAX
D2/E2
0.219 (5,56)
0.169 (4,29)
0.319 (8,10)
0.469 (11,91)
0.569 (14,45)
0.369 (9,37)
MAX
0.356 (9,04)
0.456 (11,58)
0.656 (16,66)
0.008 (0,20) NOM
1.158 (29,41)
0.958 (24,33)
0.756 (19,20)
0.191 (4,85)
0.141 (3,58)
MIN
0.441 (11,20)
0.541 (13,74)
0.291 (7,39)
0.341 (8,66)
18
19
14
13
D
D1
13
9
E1E
4
8
MINMAXMIN
PINS
**
20
28
44
0.385 (9,78)
0.485 (12,32)
0.685 (17,40)
52
68
84 1.185 (30,10)
0.985 (25,02)
0.785 (19,94)
D/E
0.395 (10,03)
0.495 (12,57)
1.195 (30,35)
0.995 (25,27)
0.695 (17,65)
0.795 (20,19)
NO. OF D1/E1
0.350 (8,89)
0.450 (11,43)
1.150 (29,21)
0.950 (24,13)
0.650 (16,51)
0.750 (19,05)
0.004 (0,10)
M
0.007 (0,18)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
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