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confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
MOS I NTEGRATED CIRCUIT
MC-4R128FKE8D
Direct Rambus DRAM RIMMTM Module
128M-BYTE (64M-WORD x 18-BIT)
DATA
SHEET
Elpida Mem ory, Inc. 2001-2002
NEC Corporation. 2000
El
p
ida Memor
y
, Inc. is a
j
oint venture DRA M c om
p
an
y
of NEC Cor
p
oration and Hit achi, Ltd.
Document No. E0078N20 (Ver 2.0)
Date Published May 2002 (K) Japan
URL: http://www.elpida.com
Description
The Direct Rambus RIMM module is a general-purpose high-performance memory module subsystem suitable for
use in a broad range of applications including computer memory, personal computers, workstations, and other
applications where high bandwidth and low latency are required.
MC-4R128FKE8D modules consists of four 288M Direct Rambus DRAM (Direct RDRAM) devices (
µ
PD488588).
These are extremely high-speed CMOS DRAMs organized as 16M words by 18 bits. The use of Rambus Signaling
Level (RSL) technology permits 600MHz, 711MHz or 800MHz transfer rates while using conventional system and
board design technologies.
Direct RDRAM devices are capable of sustained data trans fers at 1.25 ns per two bytes (10 ns per sixteen bytes).
The architecture of the Direct RDRAM enables the highest sustained bandwidth for multiple, simultaneous,
randomly addressed memory transactions. The separate control and data buses with independent row and column
control yield over 95 % bus efficiency. The Direct RDRAM's 32 banks support up to four simultaneous transactions
per device.
Features
• 184 edge connector pads with 1mm pad spacing
• 128 MB Direct RDRAM storage
• Each RDRAM has 32 banks, for 128 banks total on module
• Gold plated contacts
• RDRAMs use Chip Scale Package (CSP)
• Serial Presence Detect support
• Operates from a 2.5 V supply
• Powerdown self refresh modes
• Separate Row and Column buses for higher efficiency
• Over Drive Factor (ODF) support
Data Sheet E0078N20 (Ver 2.0)
2
MC-4R128FKE8D
Order infor m ation
Part number Organization I/O Freq.
MHz
RAS access time
ns
Package Mounted devices
MC-4R128FKE8D - 845 64M x 18 800 45 184 edge connect or pads RIMM 4 pieces of
MC-4R128FKE8D - 745 711 45 with heat spreader
µ
PD488588FF
MC-4R128FKE8D - 653 600 53 Edge connector : Gold plated FBGA (
µ
BGA) package
Data Sheet E0078N20 (Ver 2.0) 3
MC-4R128FKE8D
Module Pad Configuration
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
GND
LDQA8
GND
LDQA6
GND
LDQA4
GND
LDQA2
GND
LDQA0
GND
LCTMN
GND
LCTM
GND
NC
GND
LROW1
GND
LCOL4
GND
LCOL2
GND
LCOL0
GND
LDQB1
GND
LDQB3
GND
LDQB5
GND
LDQB7
GND
LSCK
V
CMOS
SOUT
V
CMOS
NC
GND
NC
V
DD
V
DD
NC
NC
NC
NC
GND
LDQA7
GND
LDQA5
GND
LDQA3
GND
LDQA1
GND
LCFM
GND
LCFMN
GND
NC
GND
LROW2
GND
LROW0
GND
LCOL3
GND
LCOL1
GND
LDQB0
GND
LDQB2
GND
LDQB4
GND
LDQB6
GND
LDQB8
GND
LCMD
V
CMOS
SIN
V
CMOS
NC
GND
NC
V
DD
V
DD
NC
NC
NC
NC
NC
NC
NC
NC
V
REF
GND
SCL
V
DD
SDA
SV
DD
SWP
V
DD
RSCK
GND
RDQB7
GND
RDQB5
GND
RDQB3
GND
RDQB1
GND
RCOL0
GND
RCOL2
GND
RCOL4
GND
RROW1
GND
NC
GND
RCTM
GND
RCTMN
GND
RDQA0
GND
RDQA2
GND
RDQA4
GND
RDQA6
GND
RDQA8
GND
NC
NC
NC
NC
V
REF
GND
SA0
V
DD
SA1
SV
DD
SA2
V
DD
RCMD
GND
RDQB8
GND
RDQB6
GND
RDQB4
GND
RDQB2
GND
RDQB0
GND
RCOL1
GND
RCOL3
GND
RROW0
GND
RROW2
GND
NC
GND
RCFMN
GND
RCFM
GND
RDQA1
GND
RDQA3
GND
RDQA5
GND
RDQA7
GND
Side B Side A
LCFM, LCFMN,
RCFM, RCFMN : Clock from master
LCTM, LCTMN,
RCTM, RCTMN : Clock to master
LCMD, RCMD : Serial Command Pad
LROW2 - LROW0,
RROW2 - RROW0 : Row bus
LCOL4 - LCOL0,
RCOL4 - RCOL0 : Column bus
LDQA8 - LDQA0,
RDQA8 - RDQA0 : Data bus A
LDQB8 - LDQB0,
RDQB8 - RDQB0 : Data bus B
LSCK, RSCK : Clock input
SA0 - SA2 : Serial Presence Detect Address
SCL, SDA : Serial Presence Detect Clock
SIN, SOUT : Serial I/O
SVDD : SPD Voltage
SWP : Serial Presence Detect Write Protect
VCMOS : Supply voltage for serial pads
VDD : Supply voltage
VREF : Logic threshold
GND : Ground reference
NC : These pads are not connected
Data Sheet E0078N20 (Ver 2.0)
4
MC-4R128FKE8D
Module Pad Names
Pad Signal Name Pad Signal Name Pad Signal Name Pad Signal Nam e
A1 GND B1 GND A47 NC B47 NC
A2 LDQA8 B2 LDQA7 A48 NC B48 NC
A3 GND B3 GND A49 NC B49 NC
A4 LDQA6 B4 LDQA5 A50 NC B50 NC
A5 GND B5 GND A51 VREF B51 VREF
A6 LDQA4 B6 LDQA3 A52 GND B52 GND
A7 GND B7 GND A53 SCL B53 SA0
A8 LDQA2 B8 LDQA1 A54 VDD B54 VDD
A9 GND B9 GND A55 SDA B55 SA1
A10 LDQA0 B10 LCFM A56 SVDD B56 SVDD
A11 GND B11 GND A57 SWP B57 SA2
A12 LCTMN B12 LCFMN A58 VDD B58 VDD
A13 GND B13 GND A59 RSCK B59 RCMD
A14 LCTM B14 NC A60 GND B60 GND
A15 GND B15 GND A61 RDQB7 B61 RDQB8
A16 NC B16 LROW2 A62 GND B62 GND
A17 GND B17 GND A63 RDQB5 B63 RDQB6
A18 LROW1 B18 LROW0 A64 GND B64 GND
A19 GND B19 GND A65 RDQB3 B65 RDQB4
A20 LCOL4 B20 LCOL3 A66 GND B66 GND
A21 GND B21 GND A67 RDQB1 B67 RDQB2
A22 LCOL2 B22 LCOL1 A68 GND B68 GND
A23 GND B23 GND A69 RCOL0 B69 RDQB0
A24 LCOL0 B24 LDQB0 A70 GND B70 GND
A25 GND B25 GND A71 RCOL2 B71 RCOL1
A26 LDQB1 B26 LDQB2 A72 GND B72 GND
A27 GND B27 GND A73 RCOL4 B73 RCOL3
A28 LDQB3 B28 LDQB4 A74 GND B74 GND
A29 GND B29 GND A75 RROW1 B75 RROW0
A30 LDQB5 B30 LDQB6 A76 GND B76 GND
A31 GND B31 GND A77 NC B77 RROW2
A32 LDQB7 B32 LDQB8 A78 GND B78 GND
A33 GND B33 GND A79 RCTM B79 NC
A34 LSCK B34 LCMD A80 GND B80 GND
A35 VCMOS B35 VCMOS A81 RCTMN B81 RCFMN
A36 SOUT B36 SIN A82 GND B82 GND
A37 VCMOS B37 VCMOS A83 RDQA0 B83 RCFM
A38 NC B38 NC A84 GND B84 GND
A39 GND B39 GND A85 RDQA2 B85 RDQA1
A40 NC B40 NC A86 GND B86 GND
A41 VDD B41 VDD A87 RDQA4 B87 RDQA3
A42 VDD B42 VDD A88 GND B88 GND
A43 NC B43 NC A89 RDQA6 B89 RDQA5
A44 NC B44 NC A90 GND B90 GND
A45 NC B45 NC A91 RDQA8 B91 RDQA7
A46 NC B46 NC A92 GND B92 GND
Data Sheet E0078N20 (Ver 2.0) 5
MC-4R128FKE8D
Module Connector Pad Description (1/2)
Signal I/O Type Description
GND – – Ground ref erence for RDRAM core and interface. 72 PCB connector pads.
LCFM I RSL Clock from master. Interface cloc k used for rec ei ving RSL signals f rom the
Channel. Positive polari ty.
LCFMN I RSL Clock from master. Interface cloc k used for rec ei ving RSL signals f rom the
Channel. Negati ve polari ty.
LCMD I VCMOS Serial Command us ed to read from and write t o the control registers. Also used
for power management.
LCOL4..LCOL0 I RSL Column bus. 5-bi t bus contai ni ng control and address inform ation for column
accesses.
LCTM I RSL Clock to master. Interface clock used for transmitt i ng RS L signals t o the
Channel. Positive polari ty.
LCTMN I RSL Clock to master. Interface clock used for transmitt i ng RS L signals t o the
Channel. Negati ve polari ty.
LDQA8..LDQA0 I/O RSL Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. LDQA8 i s non-funct i onal on modules with x16 RDRAM devices .
LDQB8..LDQB0 I/O RSL Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. LDQB8 i s non-funct i onal on modules with x16 RDRAM devices .
LROW2..LROW0 I RSL Row bus. 3-bit bus contai ni ng control and address inform ation for row accesses.
LSCK I VCMOS Serial c l ock input. Cl ock sourc e used to read from and write to the RDRAM
control regi sters.
NC – – These pads are not connected. These 24 connector pads are reserved for future
use.
RCFM I RSL Clock from master. Interface cloc k used for rec ei ving RSL signals f rom the
Channel. Positive polari ty.
RCFMN I RSL Clock from mas t er. Interface clock used for recei vi ng RS L signals f rom the
Channel. Negati ve polari ty.
RCMD I VCMOS Serial Command I nput used to read from and write to the control registers. Als o
used for power management.
RCOL4..RCOL0 I RSL Column bus. 5-bi t bus contai ni ng control and address inform ation for column
accesses.
RCTM I RSL Clock to master. Interface clock used for transmitt i ng RS L signals t o the
Channel. Positive polari ty.
RCTMN I RSL Clock to master. Interface clock used for transmitt i ng RSL signals t o t he
Channel. Negati ve polari ty.
RDQA8..RDQA 0 I/O RSL Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. RDQA8 i s non-funct i onal on modules with x16 RDRAM devices.
RDQB8..RDQB 0 I/O RSL Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. RDQB8 i s non-funct i onal on modules with x16 RDRAM devices.
RROW2..RROW0 I RSL Row bus. 3-bit bus contai ni ng control and address inform ation for row accesses.
Data Sheet E0078N20 (Ver 2.0)
6
MC-4R128FKE8D
(2/2)
Signal I/O Type Description
RSCK I VCMOS Serial c l ock input. Cl ock sourc e used to read from and write to the RDRAM
control regi sters.
SA0 I SVDD Seri al P resence Detec t Address 0.
SA1 I SVDD Seri al P resence Detec t Address 1.
SA2 I SVDD Seri al P resence Detec t Address 2.
SCL I SVDD Serial Presence Detec t Clock.
SDA I/O SVDD Seri al Presence Detect Data (Open Collector I/O).
SIN I/O VCMOS Serial I/O for reading from and writi ng t o the control regi sters. A ttaches to SIO0
of the fi rst RDRAM on the module.
SOUT I/O VCMOS Serial I/O for reading from and writi ng to the control regi sters. A ttaches to SIO1
of the last RDRAM on the module.
SVDD — — SPD Volt age. Used for si gnal s SCL, SDA, SWP, SA 0, SA1 and SA2.
SWP I SVDD Seri al P resence Detec t Write Prot ect (acti ve high). When low, the SPD can be
written as well as read.
VCMOS — — CMOS I/O Vol t age. Used for si gnal s CMD, SCK, S I N, SOUT.
VDD — — Supply voltage for the RDRAM core and int erface logic .
VREF — — Logic threshold reference voltage for RSL signal s.
Data Sheet E0078N20 (Ver 2.0) 7
MC-4R128FKE8D
Block Diagram
SERIAL PD
LDQA 8
LDQA 7
LDQA 6
LDQA 5
LDQA 4
LDQA 3
LDQA 2
LDQA 1
LDQA 0
LCFM
LCFMN
LCTM
LCTMN
LROW 2
LROW 1
LROW 0
LCOL 4
LCOL 3
LCOL 2
LCOL 1
LCOL 0
LDQB 0
LDQB 1
LDQB 2
LDQB 3
LDQB 4
LDQB 5
LDQB 6
LDQB 7
LDQB 8
RDQA 8
RDQA 7
RDQA 6
RDQA 5
RDQA 4
RDQA 3
RDQA 2
RDQA 1
RDQA 0
RCFM
RCFMN
RCTM
RCTMN
RROW 2
RROW 1
RROW 0
RCOL 4
RCOL 3
RCOL 2
RCOL 1
RCOL 0
RDQB 0
RDQB 1
RDQB 2
RDQB 3
RDQB 4
RDQB 5
RDQB 6
RDQB 7
RDQB 8
DQA 8
DQA 7
DQA 6
DQA 5
DQA 4
DQA 3
DQA 2
DQA 1
DQA 0
CFM
CFMN
CTM
CTMN
ROW 2
ROW 1
ROW 0
COL 4
COL 3
COL 2
COL 1
COL 0
DQB 0
DQB 1
DQB 2
DQB 3
DQB 4
DQB 5
DQB 6
DQB 7
DQB 8
SIO 0
SIO 1
SCK
CMD
V
REF
SIO 0
SIO 1
SCK
CMD
V
REF
DQA 8
DQA 7
DQA 6
DQA 5
DQA 4
DQA 3
DQA 2
DQA 1
DQA 0
CFM
CFMN
CTM
CTMN
ROW 2
ROW 1
ROW 0
COL 4
COL 3
COL 2
COL 1
COL 0
DQB 0
DQB 1
DQB 2
DQB 3
DQB 4
DQB 5
DQB 6
DQB 7
DQB 8
SIO 0
SIO 1
SCK
CMD
V
REF
DQA 8
DQA 7
DQA 6
DQA 5
DQA 4
DQA 3
DQA 2
DQA 1
DQA 0
CFM
CFMN
CTM
CTMN
ROW 2
ROW 1
ROW 0
COL 4
COL 3
COL 2
COL 1
COL 0
DQB 0
DQB 1
DQB 2
DQB 3
DQB 4
DQB 5
DQB 6
DQB 7
DQB 8
SIO 0
SIO 1
SCK
CMD
V
REF
SIN
LSCK
LCMD
V
REF
SOUT
RSCK
RCMD
U1
U2
U3
U4
DQA 8
DQA 7
DQA 6
DQA 5
DQA 4
DQA 3
DQA 2
DQA 1
DQA 0
CFM
CFMN
CTM
CTMN
ROW 2
ROW 1
ROW 0
COL 4
COL 3
COL 2
COL 1
COL 0
DQB 0
DQB 1
DQB 2
DQB 3
DQB 4
DQB 5
DQB 6
DQB 7
DQB 8
V
DD
V
CMOS
SCL SDA
A0 A1 A2
SA0 SA1 SA2
SWP
V
CC
SDA
SCL
WP
SV
DD
U0
47
kΩ
Remarks 1. Rambus Channel signals form a loop through the RIMM module, with the exception of the SIO chain.
2. See Serial Presence Detection Specification for information on the SPD device and its contents.
Data Sheet E0078N20 (Ver 2.0)
8
MC-4R128FKE8D
Electrical Specification
Absolute Maximum Ratings
Symbol Parameter MIN. MAX. Unit
VI,ABS Voltage applied to any RSL or CMOS si gnal pad with respect to GND −0.3 VDD + 0.3 V
VDD,ABS Voltage on V DD with respect to GND −0.5 VDD + 1.0 V
TSTORE Storage temperature −50 +100 °C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
DC Recommended Electrical Conditions
Symbol Param et er and conditions MIN. MAX. Unit
VDD Supply voltage 2.50 − 0.13 2.50 + 0.13 V
VCMOS CMOS I/O power supply at pad 2.5V controllers 2.5 − 0.13 2.5 + 0.25 V
1.8V controllers 1.8 − 0.1 1.8 + 0.2
VREF Reference voltage 1.4 − 0.2 1.4 + 0.2 V
VIL RSL i nput low voltage VREF − 0. 5 V REF − 0.2 V
VIH RSL input high voltage VREF + 0.2 VREF + 0.5 V
VIL,CMOS CMOS input low voltage −0.3 0.5VCMOS − 0.25 V
VIH,CMOS CMOS input high voltage 0.5VCMOS+0.25 VCMOS + 0.3 V
VOL,CMOS CMOS output low voltage, IOL,CMOS = 1 mA — 0.3 V
VOH,CMOS CMOS output high volt age, IOH,CMOS = −0.25 mA VCMOS − 0.3 — V
IREF V
REF current , VREF,MAX −40.0 +40.0
µ
A
ISCK,CMD CMOS input leakage current, (0 ≤ VCMOS ≤ VDD) −40.0 +40.0
µ
A
ISIN,SOUT CMOS input leakage current, (0 ≤ VCMOS ≤ VDD) −10.0 +10.0
µ
A
Data Sheet E0078N20 (Ver 2.0) 9
MC-4R128FKE8D
AC Electrical Specifications
Symbol Param et er and Condi tions MIN. TYP. MAX. Unit
Z Module Impedance of RSL si gnals 25.2 28.0 30.8 Ω
Module Impedance of SCK and CMD si gnal s 23.8 28.0 32.2
TPD Average clock del ay from finger to finger of all RS L clock nets 1.28 ns
(CTM, CTMN,CFM, and CFM N)
∆TPD Propagation delay variation of RSL s i gnal s with respect to TPD Note1,2 −21 +21 ps
∆TPD-CMOS Propagation delay variat i on of SCK signal with respect to an average clock
delay Note1
−250 +250 ps
∆TPD- SCK,CMD Propagation delay variation of CMD signal with respect t o S CK signal −200 +200 ps
Vα/VIN Attenuation Limit -845 12.0 %
-745 12.0
-653 10.5
VXF/VIN Forward cross talk coef ficient -845 2.0 %
(300ps input ri se time 20% - 80%) -745 2.0
-653 2.0
VXB/VIN Backward crosstal k coeffi cient -845 1.5 %
(300ps input ri se time 20% - 80%) -745 1.5
-653 1.5
RDC DC Resistance Limit -845 0.6 Ω
-745 0.6
-653 0.6
Notes 1. TPD or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM,
CTMN, CFM, and CFMN).
2. If the RIMM module meets the following specification, then it is compliant to the specification.
If the RIMM module does not meet these specifications, then the specification can be adjusted by the
“Adjusted ∆TPD Specification” table.
Adjusted ∆
∆∆
∆TPD Specification
Symbol Param et er and conditions Adjusted MIN./MAX. Absolute Unit
MIN. MAX.
∆TPD Propagat i on del ay vari ation of RSL s i gnal s with respect to TPD +/− [17+(18*N*∆Z0)] Note −30 +30 ps
Note N = Number of RDRAM devices installed on the RIMM module.
∆Z0 = delta Z0% = (MAX. Z0 − MIN. Z0) / (MIN. Z0)
(MAX. Z0 and MIN. Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers
on the module.)
Data Sheet E0078N20 (Ver 2.0)
10
MC-4R128FKE8D
RIMM Module Current Profile
IDD RIMM module power condit i ons Note1 MAX. Unit
IDD1 One RDRAM in Read Note2, balanc e i n NA P mode -845 642.6 mA
-745 592.6
-653 532.6
IDD2 One RDRAM in Read Note2, balanc e i n S tandby mode -845 900 mA
-745 820
-653 730
IDD3 One RDRAM in Read Note2, balanc e i n A ctive mode -845 1035 mA
-745 955
-653 865
IDD4 One RDRAM in Write, balance in NAP mode -845 732.6 mA
-745 682.6
-653 632.6
IDD5 One RDRAM in Write, bal ance in Standby mode -845 990 mA
-745 910
-653 830
IDD6 One RDRAM in Write, balance in Ac tive mode -845 1125 mA
-745 1045
-653 965
Notes 1. Actual power will depend on individual RDRAM component specifications, memory controller and usage
patterns. Power does not include Refresh Current.
2. I/O current is a function of the % of 1’s, to add I/O power for 50 % 1’s for a x16 need to add 257 mA or 290
mA for x18 ECC module for the following : VDD = 2.5 V, VTERM = 1.8 V, VREF = 1.4 V and VDIL = VREF − 0.5 V.
Data Sheet E0078N20 (Ver 2.0) 11
MC-4R128FKE8D
Package Drawings
184 EDGE CONNECTOR PADS RIMM (SOCKET TYPE) (1/2)
R
G
A
T
B
B
C
A (AREA B)
A1 (AREA A)
J
ITEM MILLIMETERS
Z
A
A1
B
C
C1
D
E
G
H
I
J
K
L
N
P
Q
R
S
T
W
X
Y
S
FDE
H
B1
F
O
M
I
KL
133.35 TYP.
133.35±0.13
55.175
1.00±0.10
11.50
3.00±0.10
45.00
32.00
45.00
5.675
47.625
25.40
47.625
6.35
1.00 TYP.
34.925±0.13
15.145
19.78
29.21
17.78
4.00±0.10
R 2.00
3.00±0.10
2.44
1.27±0.10
0.80±0.05
2.99
0.30
2.00±0.10
P
ON M
φ
M1
M2
Q
M2 (AREA A)
M1 (AREA B)
288 M Direct RDRAM
EEPROM
detail of A part
X
Y
detail of B part
WC1
B1
Z
R1.00
R1.00
ECA-TS2-0012-02
Data Sheet E0078N20 (Ver 2.0)
12
MC-4R128FKE8D
184 EDGE CONNECTOR PADS RIMM (SOCKET TYPE) (2/2)
A
G
H
F
C C
D
B
E
Pad A1 Pad A92
DESCRIPTION
PCB length
PCB height
Center-center pad width from pad A1 to A46,
A47 to A92, B1 to B46 or B47 to B92
Spacing from PCB left edge to connector key notch
Spacing from contact pad PCB edge
to side edge retainer notch
PCB thickness
Heat spreader thickness from PCB surface (one side) to
heat spreader top surface
RIMM thickness
ITEM
A
B
C
D
E
F
G
H
MIN.
133.22
34.795
44.95
-
-
1.17
-
-
TYP.
133.35
34.925
45.00
55.175
17.78
1.27
-
-
MAX.
133.48
35.055
45.05
-
-
1.37
3.09
4.46
UNIT
mm
mm
mm
mm
mm
mm
mm
mm
ECA-TS2-0012-02
Data Sheet E0078N20 (Ver 2.0) 13
MC-4R128FKE8D
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on
these components to prevent damaging them.
In particular, do not push module cover or drop the modules in order to protect from mechanical defects,
which would be electrical defects.
When re-packing memory modules, be sure the modules are not touching each other.
Modules in contact with other modules may cause excessive mechanical stress, which may damage the
modules.
MDE0202
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to V
DD
or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
14 Data Sheet E0078N20 (Ver 2.0)
MC-4R128FKE8D
M01E0107
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
Rambus, RDRAM and the Rambus logo are registered trademarks of Rambus Inc.
RIMM, SO-RIMM, RaSer and QRSL are trademarks of Rambus Inc.
µ
µµ
µ
BGA is a registered trademark of Tessera, Inc.
