TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A DSP Controllers Silicon Errata SPRZ002E July 2001 Revised July 2004 Copyright 2004, Texas Instruments Incorporated LF2407A/LF2406A/LF2403A/LF2402A Silicon Errata SPRZ002E Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Quality and Reliability Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMX Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMP Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3 3 3 4 2 Known Design Marginality / Exceptions to Functional Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LPM1 Mode With an External Crysta l / Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC - ADC Sequencer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAN - CAN Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAN - Method to Service Multiple Interrupts Through the Existing Two-Interrupt Structure . . . . . . . . . . . . . . . . . . . . . EV - CAPn Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EV - PDPINTx Pin Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EV - QEP Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phantom Interrupts While Using the Real-Time Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI - SPISTE Timing Anomaly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 5 6 6 6 7 7 7 8 8 Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 LF2407A/LF2406A/LF2403A/LF2402A Silicon Errata 1 SPRZ002E Introduction This document describes the silicon updates to the functional specifications for the TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, and TMS320LF2402A DSP Controllers, silicon revision 1.1. The updates are applicable to: 1.1 * TMS320LF2407A (144-pin LQFP, PGE suffix) * TMS320LF2406A (100-pin LQFP, PZ suffix) * TMS320LF2403A (64-pin TQFP, PAG suffix) * TMS320LF2402A (64-pin QFP, PG suffix) Quality and Reliability Conditions TMX Definition Texas Instruments (TI) does not warranty either (1) electrical performance to specification, or (2) product reliability for products classified as "TMX." By definition, the product has not completed data sheet verification or reliability performance qualification according to TI Quality Systems Specifications. The mere fact that a "TMX" device was tested over a particular temperature range and voltage range should not, in any way, be construed as a warranty of performance. TMP Definition TI does not warranty product reliability for products classified as "TMP." By definition, the product has not completed reliability performance qualification according to TI Quality Systems Specifications; however, products are tested to a published electrical and mechanical specification. TMS Definition Fully-qualified production device All trademarks are the property of their respective owners. 3 LF2407A/LF2406A/LF2403A/LF2402A Silicon Errata 1.2 SPRZ002E Revision Identification The device revision can be determined by the lot trace code marked on the top of the package. The location of the lot trace code for the PGE package is shown in Figure 1. DSP TMS 320LF2407APGE CA-YMLLLLW Lot trace code with second letter as A (A indicates Revision 1.1) Figure 1. Example, Lot Trace Code for TMS320LF2407A (PGE) Second Letter in Prefix of Lot Trace Code A (second letter in prefix is an "A") Silicon Revision Indicates Revision 1.1 Comments This silicon revision is available as TMS. 4 LF2407A/LF2406A/LF2403A/LF2402A Silicon Errata 2 SPRZ002E Known Design Marginality/Exceptions to Functional Specifications Table 1. Summary of Exceptions Revision(s) Affected Page LPM1 Mode With and External Crystal/Resonator Description 1.1 5 Internal Oscillator 1.1 6 ADC - ADC Sequencer Operation 1.1 6 CAN - CAN Bit Timing 1.1 6 CAN - Method to Service Multiple Interrupts Through the Existing Two-Interrupt Structure 1.1 6 EV - CAPn Input 1.1 7 EV - PDPINTx Pin Operation 1.1 7 EV - QEP Circuit 1.1 7 Phantom Interrupts While Using the Real-Time Monitor 1.1 8 SPI - SPISTE Timing Anomaly 1.1 8 Advisory LPM1 Mode With an External Crysta l / Resonator Revision(s) Affected: 1.1 Details: The device does not come out of LPM1 mode when the internal oscillator (in conjunction with an external crystal/resonator) is used. This is not an issue if an external oscillator is used. Workaround: Do not use LPM1 if using the internal oscillator. Advisory Internal Oscillator Revision(s) Affected: 1.1 Details: The internal oscillator of the 240xA device has a design marginality that may prevent the internal oscillator from starting upon power-up under certain conditions pertaining to board layout, ground bounce, and power-supply ramp rate. This is a concern only when the internal oscillator is used in conjunction with an external quartz crystal/ceramic resonator and not with an external oscillator. Workaround: Use of a 1M- resistor in parallel with the crystal across the XTAL1 and XTAL2 pins removes this condition. 5 LF2407A/LF2406A/LF2403A/LF2402A Silicon Errata Advisory SPRZ002E ADC - ADC Sequencer Operation Revision(s) Affected: 1.1 Details: The ADC sequencer operation has an issue when CPS = 1 and ACQ_Prescaler = 0. When an ADC sequence is started, the sequence stops after performing the first conversion. For example, if there are five conversions programmed for a sequence, the sequencer may stop after performing the first conversion. When CPS = 0, all the conversions are performed. The issue surfaces only when CPS = 1 and ACQ_Prescaler = 0. CPS can be 1 for any other ACQ_Prescaler value. Workaround: ACQ_Prescaler = 0 should not be used in conjunction with CPS = 1. Advisory CAN - CAN Bit Timing Revision(s) Affected: 1.1 Details: When the SBG bit (bit 10 of the BCR1 register) is set to 1, the "high" bit may be one TQ shorter/longer than it should be. Workaround: Set SBG = 0. Advisory CAN - Method to Service Multiple Interrupts Through the Existing Two-Interrupt Structure Revision(s) Affected: 1.1 Details: A CAN module interrupt will not assert a core-level interrupt if a CAN_IFR bit (set by any previous CAN interrupt) still remains set at the time of occurence of the new interrupt. For example, when a new CAN interrupt is asserted before the processor has had a chance to clear the CAN_IFR bit that caused the interrupt to happen, the CAN module does not assert a core-level CPU interrupt (INTn) for the new interrupt and may "lose" interrupts. However, the occurence of any interrupt-causing event will always set the appropriate flag bit in the CAN_IFR register. Workaround: The CAN_IFR bit that causes an interrupt must be cleared as early as possible within the ISR. This can be done by copying the CAN_IFR register to a memory variable and then clearing the set bit. The memory variable can then be examined to determine which interrupt was asserted. If all CAN_IFR bits are cleared (i.e., zero) when a "new" interrupt is asserted, the "new" interrupt will be recognized and serviced by the core. 6 LF2407A/LF2406A/LF2403A/LF2402A Silicon Errata Advisory SPRZ002E EV - CAPn Input Revision(s) Affected: 1.1 Details: If a CAPn input is high while the capture units are being enabled, it triggers spurious captures. The CAPFIFO status bits would indicate that there are two words in the FIFO, when in reality, no capture was triggered. If the capture interrupt is enabled, it will trigger the capture interrupt as well. Workaround: Initialize the CAPFIFO status bits (and enable the capture interrupt) after configuring the capture units. Advisory EV - PDPINTx Pin Operation Revision(s) Affected: 1.1 Details: If the PDPINTx pin is active during a device reset, it prevents the recognition of valid PDPINTx interrupts in the future. Workaround: To overcome this problem, bit PIRQR0.0 (for PDPINTA) and bit PIRQR2.0 (for PDPINTB) need to be cleared to zero. This can be achieved by writing a zero to these bits or by writing a one to the corresponding PIACKRn.0 bits. In addition to this, the EVAIFRA.0 bit (or EVBIFRA.0 bit) should be cleared as appropriate. The PIRQRn and PIACKRn registers are not intended to be used in user applications. The workaround mentioned herein is a special case during the initialization of the device. After initialization, these registers should not be used by the user code. Advisory EV - QEP Circuit Revision(s) Affected: 1.1 Details: After a DSP reset, the QEP module fails to detect the first transition that occurs on QEP input pins. Therefore, if the first transition occurs after a GP Timer has been initialized and enabled as the QEP counter (i.e., to use QEP as source of clock), the first transition will not be counted by the GP Timer. The result is an error of one count in the GP Timer out of a total of 1024 counts for a 256-line encoder, or 4096 counts for a 1024-line encoder. However, the issue is not a concern under any of the following conditions: 1. The first transition happens before the GP Timer is initialized and enabled as QEP counter. This ensures that all transitions are counted after initialization. 2. After the first index pulse is received and if the index pulse is used to recalibrate the GP Timer (through capture interrupt). The recalibration corrects the error in the GP Timer; therefore, from the time the first index pulse is received, the QEP counter becomes accurate. 7 LF2407A/LF2406A/LF2403A/LF2402A Silicon Errata SPRZ002E EV - QEP Circuit (Continued) Workaround(s): 1. Make the first transition happen before the GP timer is initialized and enabled as QEP counter. This is usually the case because typically the rotor shaft is locked to a known position before the GP Timer is initialized. Locking the rotor shaft will generate transitions on QEP input pins, unless the rotor shaft is exactly aligned to the known position (which is a rare case). Disturbing the rotor shaft on purpose takes care of the rare case. 2. Use the index pulse of the encoder to recalibrate the GP Timer used as QEP counter. Advisory Phantom Interrupts While Using the Real-Time Monitor Revision(s) Affected: 1.1 Details: When the real-time monitor (RTM) is used, phantom interrupts may be occasionally seen--i.e., the PIVR register is loaded with 0000h when an interrupt is asserted. This problem is seen only while debugging with the RTM and is not applicable in actual applications. Workaround: Check the PIVR value in the ISR. If a phantom interrupt is detected, return to the main code. Advisory SPI - SPISTE Timing Anomaly Revision(s) Affected: 1.1 Details: The SPISTE signal has a timing anomaly due to which, it goes high sooner than it should (i.e., before the last bit has ended). This results in unreliable read of the last bit of the word by both the master and the slave. Following is a summary of the bug description depending on which SPI clocking scheme is used: * CLOCK POLARITY = 0, PHASE = 0 The SPISTE signal goes high 3 CPU clock cycles after the falling edge of the SPICLK for the last bit of transmission. * CLOCK POLARITY = 0, PHASE = 1 The SPISTE signal goes high 3 CPU clock cycles after the rising edge of the SPICLK for the last bit of transmission. * CLOCK POLARITY = 1, PHASE = 0 The SPISTE signal goes high 3 CPU clock cycles after the rising edge of the SPICLK for the last bit of transmission. * CLOCK POLARITY = 1, PHASE = 1 The SPISTE signal goes high 3 CPU clock cycles after the falling edge of the SPICLK for the last bit of transmission. 8 LF2407A/LF2406A/LF2403A/LF2402A Silicon Errata SPRZ002E SPI - SPISTE Timing Anomaly (Continued) Note that the timing issue is aggravated when PHASE = 1, since the time window for which the SPISTE signal is valid for the last bit gets reduced further. Workaround: The SPISTE pin should be used in its GPIO configuration. This pin can then be manipulated manually in software. Note that this workaround does not require any hardware change. 9 LF2407A/LF2406A/LF2403A/LF2402A Silicon Errata 3 SPRZ002E Documentation Support For device-specific data sheets and related documentation, visit the TI web site at: http://www.ti.com To access documentation on the web site: 1. Go to http://www.ti.com 2. Click on DSP Product Tree 3. Click on the C2000 tab 4. Click on TMS320C24x DSP Generation 5. Click on a device name and then click on the documentation type you prefer. For further information regarding the TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, and TMS320LF2402A, please refer to the following publications: * TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357) * Manual Update Sheet for TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (SPRU357B) [literature number SPRZ015] * TMS320F/C24x DSP Controllers Reference Guide: CPU and Instruction Set (literature number SPRU160) * 3.3V DSP for Digital Motor Control application report (literature number SPRA550) * TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A, TMS320LC2406A, TMS320LC2404A, TMS320LC2402A DSP Controllers data sheet (literature number SPRS145) 10 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2004, Texas Instruments Incorporated