Low Noise, Rail-to-Rail,
Differential ADC Driver
Data Sheet
AD8139
Rev. C Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2004–2016 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Fully differential
Low noise
2.25 nV/√Hz
2.1 pA/√Hz
Low harmonic distortion
98 dBc SFDR at 1 MHz
85 dBc SFDR at 5 MHz
72 dBc SFDR at 20 MHz
High speed
410 MHz, 3 dB BW (G = 1)
800 V/µs slew rate
45 ns settling time to 0.01%
69 dB output balance at 1 MHz
80 dB dc CMRR
Low offset: ±0.5 mV maximum
Low input offset current: 0.5 µA maximum
Differential input and output
Differential-to-differential or single-ended-to-differential
operation
Rail-to-rail output
Adjustable output common-mode voltage
Wide supply voltage range: 5 V to 12 V
Available in a small SOIC package and an 8-lead LFCSP
APPLICATIONS
ADC drivers to 18 bits
Single-ended-to-differential converters
Differential filters
Level shifters
Differential PCB drivers
Differential cable drivers
GENERAL DESCRIPTION
The AD8139 is an ultralow noise, high performance differential
amplifier with rail-to-rail output. With its low noise, high
SFDR, and wide bandwidth, it is an ideal choice for driving
analog-to-digital converters (ADCs) with resolutions to 18 bits.
The AD8139 is easy to apply, and its internal common-mode
feedback architecture allows its output common-mode voltage
to be controlled by the voltage applied to one pin. The internal
feedback loop also provides outstanding output balance as well
as suppression of even-order harmonic distortion products. Fully
differential and single-ended-to-differential gain configurations
are easily realized by the AD8139. Simple external feedback
networks consisting of four resistors determine the closed-loop
gain of the amplifier.
FUNCTIONAL BLOCK DIAGRAMS
04679-001
–IN
VOCM
V+
+OUT
+IN
NIC
V–
–OUT
NIC = NO I NTERNAL CONNE CTI ON.
1
2
3
4
8
7
6
5
AD8139
Figure 1. 8-Lead SOIC
04679-102
–IN
V
OCM
V+
+OUT
NIC
+IN
V–
–OUT
NIC = NO I NTERNAL CONNE CTI ON.
3
4
1
2
6
5
8
7
AD8139
TOP VIEW
(No t t o Scal e)
Figure 2. 8-Lead LFCSP
The AD8139 is manufactured on the proprietary Analog Devices,
Inc., second-generation XFCB process, enabling it to achieve low
levels of distortion with input voltage noise of only 2.25 nV/√Hz.
The AD8139 is available in an 8-lead SOIC package with an
exposed paddle (EP) on the underside of its body and a 3 mm ×
3 mm LFCSP. It is rated to operate over the temperature range
of −40°C to +125°C.
110 100 1k 10k 100k 1M 10M 1G100M
10
100
FREQUENCY ( Hz )
INPUT VOLTAGE NOISE (nV/ Hz)
04679-078
Figure 3. Input Voltage Noise vs. Frequency
AD8139 Data Sheet
Rev. C | Page 2 of 26
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
VS = ±5 V, VOCM = 0 V .................................................................. 3
VS = 5 V, VOCM = 2.5 V ................................................................. 5
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ............................8
Typical Performance Characteristics ..............................................9
Test Circuits ..................................................................................... 18
Theory of Operation ...................................................................... 19
Typical Connection and Definition of Terms ........................ 19
Applications Information .............................................................. 20
Estimating Noise, Gain, and Bandwidth with Matched
Feedback Networks .................................................................... 20
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 26
REVISION HISTORY
6/2016—Rev. B to Rev. C
Changed CP-8-2 to CP-8-13 ........................................ Throughout
Changes to Figure 1 and Figure 2 ................................................... 1
Changes to Figure 5, Figure 6, and Table 5 ................................... 8
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide ......................................................... 26
10/2007—Rev. A to Rev. B
Changes to General Description Section ...................................... 1
Added Figure 2; Renumbered Sequentially .................................. 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 5
Changes to Table 6 and Layout ....................................................... 8
Added Figure 6 .................................................................................. 8
Changes to Figure 30 ...................................................................... 12
Changes to Layout .......................................................................... 17
Changes to Figure 63 ...................................................................... 22
Changes to Exposed Paddle (EP) Section ................................... 23
Updated Outline Dimensions ....................................................... 24
8/2004—Rev. 0 to Rev. A
Added 8-Lead LFCSP ......................................................... Universal
Changes to General Description Section ....................................... 1
Changes to Figure 2 ........................................................................... 1
Changes to VS = ±5 V, VOCM = 0 V Specifications ......................... 3
Changes to VS = 5 V, VOCM = 2.5 V Specifications ......................... 5
Changes to Table 4 ............................................................................. 7
Changes to Maximum Power Dissipation Section ........................ 7
Changes to Figure 26 and Figure 29............................................. 12
Added Figure 39 and Figure 42; Renumbered Sequentially ..... 14
Changes to Figure 45 to Figure 47 ................................................ 15
Added Figure 48 ............................................................................. 15
Changes to Figure 52 and Figure 53............................................. 16
Changes to Figure 55 and Figure 56............................................. 17
Changes to Table 6 .......................................................................... 19
Changes to Voltage Gain Section ................................................. 19
Changes to Driving a Capacitive Load Section .......................... 22
Changes to Ordering Guide .......................................................... 24
Updated Outline Dimensions ....................................................... 24
5/2004—Revision 0: Initial Version
Data Sheet AD8139
Rev. C | Page 3 of 26
SPECIFICATIONS
VS = ±5 V, VOCM = 0 V
TA = 25°C, differential gain = 1, RL, dm = 1 kΩ, RF = RG = 200 Ω, unless otherwise noted. TMIN to TMAX = −40°C to +125°C.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DIFFERENTIAL INPUT PERFORMANCE
Dynamic Performance
−3 dB Small Signal Bandwidth VO, dm = 0.1 V p-p 340 410 MHz
−3 dB Large Signal Bandwidth
O, dm
210
240
MHz
Bandwidth for 0.1 dB Flatness VO, dm = 0.1 V p-p 45 MHz
Slew Rate VO, dm = 2 V step 800 V/µs
Settling Time to 0.01% VO, dm = 2 V step, CF = 2 pF 45 ns
Overdrive Recovery Time G = 2, VIN, dm = 12 V p-p triangle wave 30 ns
Noise/Harmonic Performance
SFDR VO, dm = 2 V p-p, fC = 1 MHz 98 dBc
VO, dm = 2 V p-p, fC = 5 MHz 85 dBc
VO, dm = 2 V p-p, fC = 20 MHz 72 dBc
Third-Order IMD VO, dm = 2 V p-p, fC = 10.05 MHz ± 0.05 MHz −90 dBc
Input Voltage Noise f = 100 kHz 2.25 nV/√Hz
Input Current Noise
2.1
pA/√Hz
DC Performance
Input Offset Voltage VIP = VIN = VOCM = 0 V −500 ±150 +500 µV
Input Offset Voltage Drift TMIN to TMAX 1.25 µV/°C
Input Bias Current TMIN to TMAX 2.25 8.0 µA
Input Offset Current 0.12 0.5 µA
Open-Loop Gain 114 dB
Input Characteristics
Input Common-Mode Voltage Range −4 +4 V
Input Resistance Differential 600 kΩ
Common mode 1.5 MΩ
Input Capacitance
1.2
pF
CMRR ∆VICM = ±1 V dc, RF = RG = 10 kΩ 80 84 dB
Output Characteristics
Output Voltage Swing Each single-ended output, RF = RG = 10 kΩ −VS + 0.20 +VS – 0.20 V
Each single-ended output,
RL, dm = open circuit, RF = RG = 10 kΩ
−VS + 0.15 +VS − 0.15 V
Output Current Each single-ended output 100 mA
Output Balance Error f = 1 MHz −69 dB
VOCM TO VO, cm PERFORMANCE
VOCM Dynamic Performance
−3 dB Bandwidth VO, cm = 0.1 V p-p 515 MHz
Slew Rate VO, cm = 2 V p-p 250 V/µs
Gain 0.999 1.000 1.001 V/V
VOCM Input Characteristics
Input Voltage Range
−3.8
+3.8
V
Input Resistance 3.5 MΩ
Input Offset Voltage VOS, cm = VO, cm − VOCM; VIP = VIN = VOCM = 0 V −900 ±300 +900 µV
Input Voltage Noise f = 100 kHz 3.5 nV/√Hz
Input Bias Current 1.3 4.5 µA
CMRR ∆VOCM/∆VO, dm, ∆VOCM = ±1 V 74 88 dB
AD8139 Data Sheet
Rev. C | Page 4 of 26
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Operating Range +4.5 ±6 V
Quiescent Current 24.5 25.5 mA
+PSRR Change in +VS = ±1 V 95 112 dB
−PSRR
S
95
109
dB
OPERATING TEMPERATURE RANGE −40 +125 °C
Data Sheet AD8139
Rev. C | Page 5 of 26
VS = 5 V, VOCM = 2.5 V
TA = 25°C, differential gain = 1, RL, dm = 1 kΩ, RF = RG = 200 Ω, unless otherwise noted. TMIN to TMAX = −40°C to +125°C.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
DIFFERENTIAL INPUT PERFORMANCE
Dynamic Performance
−3 dB Small Signal Bandwidth VO, dm = 0.1 V p-p 330 385 MHz
−3 dB Large Signal Bandwidth VO, dm = 2 V p-p 135 165 MHz
Bandwidth for 0.1 dB Flatness VO, dm = 0.1 V p-p 34 MHz
Slew Rate
V
O, dm
= 2 V step
540
V/µs
Settling Time to 0.01% VO, dm = 2 V step 55 ns
Overdrive Recovery Time G = 2, VIN, dm = 7 V p-p triangle wave 35 ns
Noise/Harmonic Performance
SFDR VO, dm = 2 V p-p, fC = 1 MHz 99 dBc
VO, dm = 2 V p-p, fC = 5 MHz, RL = 800 Ω 87 dBc
V
O, dm
= 2 V p-p, f
C
= 20 MHz, R
L
= 800 Ω
75
dBc
Third-Order IMD VO, dm = 2 V p-p, fC = 10.05 MHz ± 0.05 MHz −87 dBc
Input Voltage Noise f = 100 kHz 2.25 nV/√Hz
Input Current Noise f = 100 kHz 2.1 pA/√Hz
DC Performance
Input Offset Voltage VIP = VIN = VOCM = 2.5 V −500 ±150 +500 µV
Input Offset Voltage Drift TMIN to TMAX 1.25 µV/°C
Input Bias Current TMIN to TMAX 2.2 7.5 µA
Input Offset Current 0.13 0.5 µA
Open-Loop Gain 112 dB
Input Characteristics
Input Common-Mode Voltage Range
1
4
V
Input Resistance Differential 600 kΩ
Common mode 1.5 MΩ
Input Capacitance Common mode 1.2 pF
CMRR ΔVICM = ±1 V dc, RF = RG = 10 kΩ 75 79 dB
Output Characteristics
Output Voltage Swing Each single-ended output, RF = RG = 10 kΩ −VS + 0.15 +VS − 0.15 V
Each single-ended output,
RL, dm = open circuit, RF = RG = 10 kΩ
−VS + 0.10 +VS − 0.10 V
Output Current Each single-ended output 80 mA
Output Balance Error f = 1 MHz −70 dB
VOCM TO VO, cm PERFORMANCE
VOCM Dynamic Performance
−3 dB Bandwidth VO, cm = 0.1 V p-p 440 MHz
Slew Rate
V
O, cm
= 2 V p-p
150
V/µs
Gain 0.999 1.000 1.001 V/V
VOCM Input Characteristics
Input Voltage Range 1.0 3.8 V
Input Resistance 3.5 MΩ
Input Offset Voltage
V
OS, cm
= V
O, cm
− V
OCM
; V
IP
= V
IN
= V
OCM
= 2.5 V
−1.0
±0.45
+1.0
mV
Input Voltage Noise f = 100 kHz 3.5 nV/√Hz
Input Bias Current 1.3 4.2 µA
CMRR ΔVOCM/ΔVO, dm, ΔVOCM = ±1 V 67 79 dB
AD8139 Data Sheet
Rev. C | Page 6 of 26
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Operating Range +4.5 ±6 V
Quiescent Current 21.5 22.5 mA
+PSRR Change in +VS = ±1 V 86 97 dB
−PSRR
Change in −V
S
= ±1 V
92
105
dB
OPERATING TEMPERATURE RANGE −40 +125 °C
Data Sheet AD8139
Rev. C | Page 7 of 26
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage 12 V
VOCM ±VS
Power Dissipation See Figure 4
Input Common-Mode Voltage ±VS
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +125°C
Lead Temperature (Soldering 10 sec) 300°C
Junction Temperature
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is specified
for device soldered in circuit board for surface-mount packages.
Table 4.
Package Type θJA Unit
8-Lead SOIC with EP/4-Layer 70 °C/W
8-Lead LFCSP/4-Layer
70
°C/W
Maximum Power Dissipation
The maximum safe power dissipation in the AD8139 package
is limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the AD8139. Exceeding a junction temperature
of 175°C for an extended period can result in changes in the
silicon devices potentially causing failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The load current consists of differential
and common-mode currents flowing to the load, as well as
currents flowing through the external feedback networks and
the internal common-mode feedback loop. The internal resistor
tap used in the common-mode feedback loop places a 1 kΩ
differential load on the output. RMS output voltages should be
considered when dealing with ac signals.
Airflow reduces θJA. In addition, more metal directly in contact
with the package leads from metal traces, through holes, ground,
and power planes reduce the θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the exposed paddle
(EP) 8-lead SOIC (θJA = 70°C/W) and the 8-lead LFCSP
(θJA = 70°C/W) on a JEDEC standard 4-layer board. θJA
values are approximations.
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
–40 –20 020 40 60 80 100 120
AMBI ENT T E M P E RATURE ( °C)
MAXIMUM POWER DISSIPATIO N (W)
SOIC
AND LFCSP
04679-055
Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
AD8139 Data Sheet
Rev. C | Page 8 of 26
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
–IN
V
OCM
V+
+OUT
+IN
NIC
V–
–OUT
04679-003
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. SOLDER THE EXPOSED PADDLE
ON THE BACK OF THE PACKAGE
TO THE GROUND PLANE OR TO
A POWER PLANE.
1
2
3
4
8
7
6
5
AD8139
(Not to Scale)
TOP VIEW
Figure 5. 8-Lead SOIC Pin Configuration
04679-103
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. SOLDER THE EXPOSED PADDLE
ON THE BACK OF THE PACKAGE
TO THE GROUND PLANE OR TO
A POWER PLANE.
–IN
V
OCM
V+
+OUT
NIC
+IN
V–
–OUT
3
4
1
2
6
5
8
7
AD8139
TOP VIEW
(Not to Scale)
Figure 6. 8-Lead LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 −IN Inverting Input.
2 VOCM An internal feedback loop drives the output common-mode voltage to be equal to the voltage applied to
the VOCM pin, provided the operation of the amplifier remains linear.
3 V+ Positive Power Supply Voltage.
4 +OUT Positive Side of the Differential Output.
5 −OUT Negative Side of the Differential Output.
6 V− Negative Power Supply Voltage.
7 NIC No Internal Connection.
8 +IN Noninverting Input.
0 EP Exposed Paddle. Solder the exposed paddle on the back of the package to the ground plane or to a power plane.
Data Sheet AD8139
Rev. C | Page 9 of 26
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, differential gain = +1, RG = RF = 200 Ω, RL, dm = 1 kΩ, VS = ±5 V, TA = 25°C, VOCM = 0 V. Refer to the basic test
circuit in Figure 57 for the definition of terms.
2
–13
–12
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
1 10 100 1000
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
G = 1
G = 2
G = 5
G = 10
R
G
= 200Ω
V
O, dm
= 0.1V p-p
0
4679-004
Figure 7. Small Signal Frequency Response for Various Gains
5
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
4
10 100 1000
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
V
S
= ±5V
V
S
= +5V
V
O, dm
= 0.1V p-p
0
4679-005
Figure 8. Small Signal Frequency Response for Various Power Supplies
3
–12
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
10 100 1000
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
V
O, dm
= 0.1V p-p
+125°C
+85°C
+25°C
–40°C
0
4679-006
Figure 9. Small Signal Frequency Response at Various Temperatures
2
–13
–12
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
1 10 100 1000
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
G = 1
G = 2G = 5
G = 10
R
G
= 200Ω
V
O, dm
= 2.0V p-p
0
4679-007
Figure 10. Large Signal Frequency Response for Various Gains
3
–12
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
10 100 1000
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
V
S
= ±5V
V
S
= +5V
V
O, dm
= 2.0V p-p
0
4679-008
Figure 11. Large Signal Frequency Response for Various Power Supplies
3
–12
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
10 100 1000
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
V
O, dm
= 2.0V p-p
+125°C +85°C
–40°C +25°C
0
4679-009
Figure 12. Large Signal Frequency Response at Various Temperatures
AD8139 Data Sheet
Rev. C | Page 10 of 26
3
–12
–10
–11
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
10 100 1000
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
V
O, dm
= 0.1V p-p
R
L
= 100Ω
R
L
= 200Ω
R
L
= 500Ω
R
L
= 1kΩ
0
4679-040
Figure 13. Small Signal Frequency Response for Various Loads
3
–12
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
10 100 1000
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
V
O, dm
= 0.1V p-p
C
F
= 1pF
C
F
= 2pF
C
F
= 0pF
0
4679-011
Figure 14. Small Signal Frequency Response for Various CF
6
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
10 100 1000
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
V
O, dm
= 0.1V p-p
V
OCM
= +4.3V V
OCM
= +4V
V
OCM
= 0V
V
OCM
= –4V
V
OCM
= –4.3V
0
4679-012
Figure 15. Small Signal Frequency Response at Various VOCM
–13
–12
–10
–11
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
10 100 1000
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
VO, dm = 2.0V p-p
RL = 100Ω
RL = 200Ω
RL = 500Ω
RL = 1kΩ
0
4679-041
Figure 16. Large Signal Frequency Response for Various Loads
2
–13
–11
–12
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
10 100 1000
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
VO, dm = 2.0V p-p
CF = 0pF CF = 1pF
CF = 2pF
0
4679-014
Figure 17. Large Signal Frequency Response for Various CF
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
1 10 100
04679-0-042
FREQUENCY (Hz)
NORMALIZED CLOSED-LOOP GAIN (dB)
RL = 1kΩ
(VO, dm = 0.1V p-p)
RL = 1kΩ
(VO, dm = 2.0V p-p)
RL = 100Ω
(VO, dm = 0.1V p-p)
RL = 100Ω
(VO, dm = 2.0V p-p)
Figure 18. 0.1 dB Flatness for Various Loads and Output Amplitudes
Data Sheet AD8139
Rev. C | Page 11 of 26
–
30
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
0.1 1 10 100
FREQUENCY (MHz)
DISTORTION (dBc)
V
O, dm
= 2.0V p-p
V
S
= +5V
V
S
= ±5V
0
4679-015
Figure 19. Second Harmonic Distortion vs. Frequency and Supply Voltage
–
30
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
0.1 1 10 100
FREQUENCY (MHz)
DISTORTION (dB)
V
O, dm
= 2.0V p-p
G = 1
G = 2
G = 5
0
4679-016
Figure 20. Second Harmonic Distortion vs. Frequency and Gain
–
30
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
0.1 1 10 100
FREQUENCY (MHz)
DISTORTION (dBc)
V
O, dm
= 2.0V p-p
R
L
= 100Ω
R
L
= 200Ω
R
L
= 500Ω
R
L
= 1kΩ
0
4679-017
Figure 21. Second Harmonic Distortion vs. Frequency and Load
–
30
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
0.1 1 10 100
FREQUENCY (MHz)
DISTORTION (dBc)
V
O, dm
= 2.0V p-p
V
S
= +5V
V
S
= ±5V
0
4679-018
Figure 22. Third Harmonic Distortion vs. Frequency and Supply Voltage
–
30
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
0.1 1 10 100
FREQUENCY (MHz)
DISTORTION (dB)
V
O, dm
= 2.0V p-p
G = 1 G = 2
G = 5
0
4679-019
Figure 23. Third Harmonic Distortion vs. Frequency and Gain
–
30
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
0.1 1 10 100
FREQUENCY (MHz)
DISTORTION (dBc)
V
O, dm
= 2.0V p-p
R
L
= 100Ω
R
L
= 200Ω
R
L
= 500Ω
R
L
= 1kΩ
0
4679-020
Figure 24. Third Harmonic Distortion vs. Frequency and Load
AD8139 Data Sheet
Rev. C | Page 12 of 26
–
30
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
0.1 1 10 100
FREQUENCY (MHz)
DISTORTION (dBc)
V
O, dm
= 2.0V p-p
R
F
= 200Ω
R
F
= 500Ω
R
F
= 1kΩ
0
4679-021
Figure 25. Second Harmonic Distortion vs. Frequency and RF
–
80
–90
–100
–110
–120
–130
–140
–150
012345678
V
O, dm
(V p-p)
DISTORTION (dBc)
F
C
= 2MHz
V
S
= +5V
V
S
= ±5V
0
4679-022
Figure 26. Second Harmonic Distortion vs. Output Amplitude
–
60
–130
–100
–120
–110
–90
–80
–70
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOCM (V)
DISTORTION (dBc)
VO, dm = 2V p-p
FC = 2MHz
SECOND HARMONIC
THIRD HARMONIC
0
4679-023
Figure 27. Harmonic Distortion vs. VOCM, VS = +5 V
–
30
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
0.1 1 10 100
FREQUENCY (MHz)
DISTORTION (dBc)
V
O, dm
= 2.0V p-p
R
F
= 200Ω
R
F
= 1kΩ
R
F
= 500Ω
0
4679-024
Figure 28. Third Harmonic Distortion vs. Frequency and RF
–
80
–90
–100
–110
–120
–130
–140
–150
087654321
VO, dm (V p-p)
DISTORTION (dBc)
FC = 2MHz
VS = +5V
VS = ±5V
0
4679-025
Figure 29. Third Harmonic Distortion vs. Output Amplitude
–
60
–130
–100
–120
–110
–90
–80
–70
–5 –4 –3 –2 –1 0 1 2 3 4 5
04679-026
V
OCM
(V)
DISTORTION (dBc)
V
O, dm
= 2V p-p
F
C
= 2MHz
SECOND HARMONIC
THIRD HARMONIC
Figure 30. Harmonic Distortion vs. VOCM, VS = ±5 V
Data Sheet AD8139
Rev. C | Page 13 of 26
–100
–75
–50
–25
50
25
75
0
100
TIME (ns)
V
O, dm
(V)
5ns/DIV
V
O, dm
= 100mV p-p
C
F
= 0pF
(C
F
= 0pF,
V
S
= ±5V)
V
O, dm
(C
F
= 2pF, V
S
= ±5V)
04679-043
Figure 31. Small Signal Transient Response for Various CF
–0.100
–0.075
–0.050
–0.025
0.050
0.025
0.075
0
0.100
TIME (ns)
V
O, dm
(V)
5ns/DIV
R
S
= 31.6Ω
C
L, dm
= 30pF
R
S
= 63.4Ω
C
L, dm
= 15pF
04679-064
Figure 32. Small Signal Transient Response for Capacitive Loads
5
–100
–95
–90
–85
–80
–75
–70
–65
–60
–55
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
9.55 9.65 9.75 9.85 9.95 10.05 10.15 10.25 10.35 10.45 10.55
FREQUENCY (MHz)
NORMALIZED OUTPUT (dBc)
V
O, dm
= 2V p-p
F
C
1 = 10MHz
F
C
2 = 10.1MHz
0
4679-027
Figure 33. Intermodulation Distortion
–2.5
–1.5
–1.0
–0.5
1.0
0.5
2.0
–2.0
1.5
0
2.5
TIME (ns)
V
O, dm
(V)
5ns/DIV
4V p-p
C
F
= 0pF
2V p-p
C
F
= 2pF
C
F
= 0pF
C
F
= 2pF
04679-044
Figure 34. Large Signal Transient Response for Various CF
–1.5
–1.0
–0.5
1.0
0.5
0
1.5
TIME (ns)
V
O, dm
(V)
5ns/DIV
R
S
= 63.4Ω
C
L, dm
= 15pF
R
S
= 31.6Ω
C
L, dm
= 30pF
04679-065
Figure 35. Large Signal Transient Response for Capacitive Loads
1.5
–1.5
–1.0
–0.5
0
0.5
1.0
600
–600
–400
–200
0
200
400
TIME (ns)
AMPLITUDE (V)
ERROR (µV) 1DIV = 0.01%
CF = 2pF
VO, dm = 2.0V p-p
35ns/DIV
ERROR
VIN
VO, dm
0
4679-034
Figure 36. Settling Time (0.01%)
AD8139 Data Sheet
Rev. C | Page 14 of 26
–1.5
–1.0
–0.5
1.0
0.5
0
1.5
TIME (ns)
V
OCM
(V)
10ns/DIV
V
O, cm
= 2V p-p
V
IN, dm
= 0V
±5V
+5V
04679-069
Figure 37. VOCM Large Signal Transient Response
0
–90
–80
–70
–60
–50
–40
–30
–20
–10
1 10 100 500
FREQUENCY (MHz)
CMRR (dB)
V
IN, cm
= 0.2V p-p
INPUT CMRR = ∆V
O, cm
/∆V
IN, cm
R
F
= R
G
= 200Ω
R
F
= R
G
= 10kΩ
0
4679-066
Figure 38. CMRR vs. Frequency
1
10 100 1k 10k 100k 1M 10M 1G100M
10
100
FREQUENCY (Hz)
INPUT VOLTAGE NOISE (nV/ Hz)
0
4679-079
Figure 39. Input Voltage Noise vs. Frequency
6
–9
–7
–8
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
10 100 1000
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
V
O, cm
= 0.1V p-p
V
O, cm
= 2.0V p-p
V
S
= +5V
V
S
= +5V
V
S
= ±5V V
S
= ±5V
0
4679-038
Figure 40. VOCM Frequency Response for Various Supplies
0
–90
–80
–70
–60
–50
–40
–30
–20
–10
1 10 100 500
FREQUENCY (MHz)
V
OCM
CMRR (dB)
V
O, cm
= 0.2V p-p
V
OCM
CMRR = ∆V
O, dm
/∆V
O, cm
0
4679-045
Figure 41. VOCM CMRR vs. Frequency
1
10 100 1k 10k 100k 1M 10M 1G100M
10
100
FREQUENCY (Hz)
V
OCM
VOLTAGE NOISE (nV/ Hz)
0
4679-080
Figure 42. VOCM Voltage Noise vs. Frequency
Data Sheet AD8139
Rev. C | Page 15 of 26
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
1 10 100 500
FREQUENCY (MHz)
PSRR (dB)
R
L, dm
= 1kΩ
PSRR = ∆V
O, dm
/∆V
S
–PSRR
+PSRR
0
4679-047
Figure 43. PSRR vs. Frequency
100
0.01
0.1
1
10
0.1 1 10 100 1000
FREQUENCY (MHz)
OUTPUT IMPEDANCE (Ω)
V
S
= +5V
V
S
= ±5V
0
4679-028
Figure 44. Single-Ended Output Impedance vs. Frequency
700
–700
–600
–500
–400
–300
–200
–100
0
100
200
300
400
500
600
100 1k 10k
RESISTIVE LOAD (Ω)
SINGLE-ENDED OUTPUT SWING FROM RAIL (mV)
V
S+
– V
OP
V
ON
– V
S–
V
S
= +5V
V
S
= ±5V
0
4679-068
Figure 45. Output Saturation Voltage vs. Output Load
–14
–12
–10
–8
–6
–4
–2
0
2
4
6
8
10
12
14
TIME (ns)
VOLTAGE (V)
50ns/DIV
V
O, dm
2 × V
IN, dm
G = 2
04679-046
Figure 46. Overdrive Recovery
0
–80
–70
–60
–50
–40
–30
–20
–10
1 10 100 500
FREQUENCY (MHz)
OUTPUT BALANCE (dB)
V
O, dm
= 1V p-p
OUTPUT BALANCE = ∆V
O, cm
/∆V
O, dm
0
4679-067
Figure 47. Output Balance vs. Frequency
50
100
150
200
250
–40 120100806040200–20
300
–300
–
50
–100
–150
–200
–250
TEMPERATURE (°C)
V
OP
SWING FROM RAIL (mV)
V
ON
SWING FROM RAIL (mV)
V
S
= ±5V
G = 1 (R
F
= R
G
= 200Ω)
R
L, dm
= 1kΩ
V
S+
– V
OP
V
ON
– V
S–
0
4679-077
Figure 48. Output Saturation Voltage vs. Temperature
AD8139 Data Sheet
Rev. C | Page 16 of 26
1.0
3.0
70
95
120
170
1452.5
2.0
1.5
–40 –20 0 20 40 60 80 100 120
TEMPERATURE (°C)
INPUT BIAS CURRENT (µA)
OFFSET CURRENT (nA)
I
OS
I
BIAS
0
4679-062
Figure 49. Input Bias and Offset Current vs. Temperature
–10
–5 –4 –3 –2 –1 0 1 2 3 4 5
–8
–6
–4
–2
0
2
4
6
8
10
V
ACM
(V)
INPUT BIAS CURRENT (µA)
V
S
= ±5V
V
S
= +5V
0
4679-073
Figure 50. Input Bias Current vs.
Input Common-Mode Voltage
5
–5
–4
–3
–2
–1
0
1
2
3
4
–5 543210–1–2–3–4
V
OCM
(V)
V
OUT, cm
(V)
V
S
= ±2.5V
V
S
= ±5V
0
4679-048
Figure 51. VOUT, cm vs. VOCM Input Voltage
20
26
25
24
23
22
21
–40 –20 0 20 40 60 80 100 120
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
V
S
= +5V
V
S
= ±5V
0
4679-060
Figure 52. Supply Current vs. Temperature
0
300
–600
–400
–200
0
200
400
600
250
200
150
100
50
–40 –20 0 20 40 60 80 100 120
TEMPERATURE (°C)
V
OS, dm
(µV)
V
OS, cm
(µV)
V
OS, cm
V
OS, dm
0
4679-061
Figure 53. Offset Voltage vs. Temperature
50
45
40
35
30
25
20
15
10
5
0
–500
–450
–400
–350
–300
–250
–200
–150
–100
–50
0
50
100
150
200
250
300
350
400
450
500
VOS, dm (µV)
FREQUENCY
COUNT = 350
MEAN = –50µV
STD DEV = 100µV
04679-071
Figure 54. VOS, dm Distribution
Data Sheet AD8139
Rev. C | Page 17 of 26
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
–40 –20 0 20 40 60 80 100 120
TEMPERATURE (°C)
V
OCM
BIAS CURRENT (µA)
0
4679-063
Figure 55. VOCM Bias Current vs. Temperature
–6
–5 –4 –3 –2 –1 0 1 2 3 4 5
–4
–2
0
2
4
6
V
OCM
(V)
V
OCM
BIAS CURRENT (µA)
V
S
= ±5V
V
S
= +5V
0
4679-074
Figure 56. VOCM Bias Current vs. VOCM Input Voltage
AD8139 Data Sheet
Rev. C | Page 18 of 26
TEST CIRCUITS
RG= 200Ω
60.4Ω
60.4Ω
50Ω
VTEST
TEST
SIGNAL
SOURCE
50Ω
RG= 200Ω
VOCM
–
+
VO, dm
RF
CF
CF
RF
RL, dm = 1kΩ
AD8139
0
4679-072
Figure 57. Basic Test Circuit
R
G
= 200Ω
60.4Ω
60.4Ω
50Ω
V
TEST
TEST
SIGNAL
SOURCE
50Ω
R
G
= 200Ω
V
OCM
–
+
V
O, dm
R
F
= 200Ω
R
F
= 200Ω
C
L, dm
R
L, dm
R
S
R
S
AD8139
04679-075
Figure 58. Capacitive Load Test Circuit, G = +1
Data Sheet AD8139
Rev. C | Page 19 of 26
THEORY OF OPERATION
The AD8139 is a high speed, low noise differential amplifier
fabricated on the Analog Devices second-generation extra fast
complementary bipolar (XFCB) process. It is designed to
provide two closely balanced differential outputs in response
to either differential or single-ended input signals. Differential
gain is set by external resistors, similar to traditional voltage-
feedback operational amplifiers. The common-mode level of
the output voltage is set by a voltage at the VOCM pin and is
independent of the input common-mode voltage. The AD8139
has an H-bridge input stage for high slew rate, low noise, and
low distortion operation and rail-to-rail output stages that
provide maximum dynamic output range. This set of features
allows for convenient single-ended-to-differential conversion,
a common need to take advantage of modern high resolution
ADCs with differential inputs.
TYPICAL CONNECTION AND DEFINITION OF
TERMS
Figure 59 shows a typical connection for the AD8139, using
matched external RF/RG networks. The differential input terminals
of the AD8139, VAP and VAN, are used as summing junctions.
An external reference voltage applied to the VOCM terminal sets
the output common-mode voltage. The two output terminals,
VOP and VON, move in opposite directions in a balanced fashion
in response to an input signal.
+
–
VAP
VAN
VON
VOP
–
+
VO, dm
RL, dm
AD8139
CF
RF
RG
RG
CF
RF
VIP
V
OCM
VIN
04679-050
Figure 59. Typical Connection
The differential output voltage is defined as
VO, dm = VOP − VON (1)
Common-mode voltage is the average of two voltages. The
output common-mode voltage is defined as
2
ONOP
cmO,
VV
V
(2)
Output Balance
Output balance is a measure of how well VOP and VON are
matched in amplitude and how precisely they are 180° out of
phase with each other. It is the internal common-mode feedback
loop that forces the signal component of the output common-mode
towards zero, resulting in the near perfectly balanced differential
outputs of identical amplitude and exactly 180° out of phase. The
output balance performance does not require tightly matched
external components, nor does it require that the feedback factors
of each loop be equal to each other. Low frequency output balance
is limited ultimately by the mismatch of an on-chip voltage divider,
which is trimmed for optimum performance.
Output balance is measured by placing a well-matched resistor
divider across the differential voltage outputs and comparing
the signal at the midpoint of the divider with the magnitude of
the differential output. By this definition, output balance is
equal to the magnitude of the change in output common-mode
voltage divided by the magnitude of the change in output
differential-mode voltage:
dmO,
cmO,
V
V
BalanceOutput
(3)
The block diagram of the AD8139 in Figure 60 shows the
external differential feedback loop (RF/RG networks and the
differential input transconductance amplifier, GDIFF) and the
internal common-mode feedback loop (voltage divider across
VOP and VON and the common-mode input transconductance
amplifier, GCM). The differential negative feedback drives the
voltages at the summing junctions VAN and VAP to be essentially
equal to each other.
VAN = VAP (4)
The common-mode feedback loop drives the output common-
mode voltage, sampled at the midpoint of the two 500 Ω resistors,
to equal the voltage set at the VOCM terminal. This ensures that
2
dmO,
OCMOP
V
VV (5)
and
2
dmO,
OCMON
V
VV (6)
V
OP
V
OCM
G
O
G
DIFF
G
O
G
CM
10pF
10pF
500Ω
500Ω
V
ON
MIDSUPPLY
+
+
V
AN
V
IN
V
IP
V
AP
R
G
R
G
R
F
R
F
04679-051
Figure 60. Block Diagram
AD8139 Data Sheet
Rev. C | Page 20 of 26
APPLICATIONS INFORMATION
ESTIMATING NOISE, GAIN, AND BANDWIDTH
WITH MATCHED FEEDBACK NETWORKS
Estimating Output Noise Voltage
The total output noise is calculated as the root-sum-squared
total of several statistically independent sources. Because the
sources are statistically independent, the contributions of each
must be individually included in the root-sum-square calculation.
Table 6 lists recommended resistor values and estimates of
bandwidth and output differential voltage noise for various
closed-loop gains. For most applications, 1% resistors are
sufficient.
Table 6. Recommended Values of Gain-Setting Resistors and
Voltage Noise for Various Closed-Loop Gains
Gain RG (Ω) RF (Ω)
3 dB
Bandwidth (MHz)
Total Output
Noise (nV/√Hz)
1 200 200 400 5.8
2 200 400 160 9.3
5 200 1 k 53 19.7
10 200 2 k 26 37
The differential output voltage noise contains contributions
from the input voltage noise and input current noise of the
AD8139 as well as those from the external feedback networks.
The contribution from the input voltage noise spectral density
is computed as
G
F
nR
R
vVo_n1 1 , or equivalently, vn/β (7)
where vn is defined as the input-referred differential voltage
noise. This equation is the same as that of traditional op amps.
The contribution from the input current noise of each input is
computed as
Vo_n2 = in (RF) (8)
where in is defined as the input noise current of one input.
Each input needs to be treated separately because the two
input currents are statistically independent processes.
The contribution from each RG is computed as
G
F
GR
R
kTRVo_n3 4 (9)
This result can be intuitively viewed as the thermal noise of
each RG multiplied by the magnitude of the differential gain.
The contribution from each RF is computed as
Vo_n4 = √4kTRF (10)
Voltage Gain
The behavior of the node voltages of the single-ended-to-
differential output topology can be deduced from the previous
definitions. Referring to Figure 59, (CF = 0) and setting VIN = 0,
one can write
F
ONAP
G
AP
IP
R
V
V
R
V
V
(11)
GF
G
OPAPAN RR R
VVV (12)
Solving the above two equations and setting VIP to Vi gives the
gain relationship for VO, dm/Vi.
i
G
F
dmO,
ONOP V
R
R
VVV (13)
An inverting configuration with the same gain magnitude can
be implemented by simply applying the input signal to VIN and
setting VIP = 0. For a balanced differential input, the gain from
VIN, dm to VO, dm is also equal to RF/RG, where VIN, dm = VIP − VIN.
Feedback Factor Notation
When working with differential amplifiers, it is convenient to
introduce the feedback factor β, which is defined as
G
F
G
RR
R
(14)
This notation is consistent with conventional feedback analysis
and is very useful, particularly when the two feedback loops are
not matched.
Input Common-Mode Voltage
The linear range of the VAN and VAP terminals extends to within
approximately 1 V of either supply rail. Because VAN and VAP are
essentially equal to each other, they are both equal to the input
common-mode voltage of the amplifier. Their range is indicated
in the Specifications tables as input common-mode range. The
voltage at VAN and VAP for the connection diagram in Figure 59
can be expressed as
ACMAPAN VVV
OCM
G
F
G
INIP
G
F
FV
RR
RVV
RR
R
2
)( (15)
where VACM is the common-mode voltage present at the
amplifier input terminals.
Using the β notation, Equation 15 can be written as follows:
VACM = βVOCM + (1 − β)VICM (16)
or equivalently,
VACM = VICM + β(VOCM − VICM) (17)
where VICM is the common-mode voltage of the input signal,
that is, VICM = VIP + VIN/2.
Data Sheet AD8139
Rev. C | Page 21 of 26
For proper operation, the voltages at VAN and VAP must stay
within their respective linear ranges.
Calculating Input Impedance
The input impedance of the circuit in Figure 59 depends on
whether the amplifier is being driven by a single-ended or a
differential signal source. For balanced differential input
signals, the differential input impedance (RIN, dm) is simply
RIN, dm = 2RG (18)
For a single-ended signal (for example, when VIN is grounded
and the input signal drives VIP), the input impedance becomes
)(2
1
F
G
F
G
IN
RR
R
R
R
(19)
The input impedance of a conventional inverting op amp
configuration is simply RG, but it is higher in Equation 19
because a fraction of the differential output voltage appears at
the summing junctions, VAN and VAP. This voltage partially
bootstraps the voltage across the input resistor RG, leading to
the increased input resistance.
Input Common-Mode Swing Considerations
In some single-ended-to-differential applications, when using a
single-supply voltage, attention must be paid to the swing of the
input common-mode voltage, VACM.
Consider the case in Figure 61, where VIN is 5 V p-p swinging
about a baseline at ground, and VREF is connected to ground.
The circuit has a differential gain of 1.6 and β = 0.38. VICM has
an amplitude of 2.5 V p-p and is swinging about ground. Using
the results in Equation 16, the common-mode voltage at the
inputs of the AD8139, VACM, is a 1.5 V p-p signal swinging
about a baseline of 0.95 V. The maximum negative excursion
of VACM in this case is 0.2 V, which exceeds the lower input
common-mode voltage limit.
DGND AGND REFGND REF REFBUFIN PDBUF
ADR431
2.5V
REFERENCE
47µF
AD7674
IN+
IN–
AVDD DVDD
AD8139
+
–
8
V
REF
2.5V 2
1
6
3
4
5
V
OCM
200Ω
200Ω324Ω
324Ω
5
V
20Ω
15Ω
15Ω
V
IN
2.7nF
2.7nF
0.1µF
0.1µF 0.1µF 0.1µF
+1.7V
+0.95V
V
ACM
WITH V
REF
= 0 +0.2V
+2.5V
GND
–2.5V
04679-052
Figure 61. AD8139 Driving AD7674, 18-Bit, 800 kSPS ADC
AD8139 Data Sheet
Rev. C | Page 22 of 26
One way to avoid the input common-mode swing limitation is
to bias VIN and VREF at midsupply. In this case, VIN is 5 V p-p
swinging about a baseline at 2.5 V, and VREF is connected to a
low-Z 2.5 V source. VICM now has an amplitude of 2.5 V p-p and
is swinging about 2.5 V. Using the results in Equation 17, VACM
is calculated to be equal to VICM because VOCM = VICM. Therefore,
VACM swings from 1.25 V to 3.75 V, which is well within the
input common-mode voltage limits of the AD8139. Another
benefit seen in this example is that because VOCM = VACM = VICM
no wasted common-mode current flows. Figure 62 illustrates
how to provide the low-Z bias voltage. For situations that do not
require a precise reference, a simple voltage divider suffices to
develop the input voltage to the buffer.
V
IN
0V TO 5V
AD8139
+
–
8
2
1
6
3
4
5
V
OCM
200Ω
324Ω
5
V
200Ω324Ω
0.1µF
0.1µF
10µF +
AD8031
+
–
0.1µF
5V
ADR431
2.5V
REFERENCE
TO AD7674 REFBUFIN
04679-053
Figure 62. Low-Z 2.5 V Buffer
Another way to avoid the input common-mode swing limitation is
to use dual power supplies on the AD8139. In this case, the
biasing circuitry is not required.
Bandwidth vs. Closed-Loop Gain
The 3 dB bandwidth of the AD8139 decreases proportionally
to increasing closed-loop gain in the same way as a traditional
voltage feedback operational amplifier. For closed-loop gains
greater than 4, the bandwidth obtained for a specific gain can be
estimated as
)MHz300(,dB3 ,
F
G
G
dmOUT RR
R
Vf (20)
or equivalently, β(300 MHz).
This estimate assumes a minimum 90° phase margin for the
amplifier loop, which is a condition approached for gains greater
than 4. Lower gains show more bandwidth than predicted by
the equation due to the peaking produced by the lower
phase margin.
Estimating DC Errors
Primary differential output offset errors in the AD8139 are due
to three major components: the input offset voltage, the offset
between the VAN and VAP input currents interacting with the
feedback network resistances, and the offset produced by the dc
voltage difference between the input and output common-mode
voltages in conjunction with matching errors in the feedback
network.
The first output error component is calculated as
G
G
F
IO R
RR
Ve1Vo _ , or equivalently as VIO/β (21)
where VIO is the input offset voltage. The input offset voltage of the
AD8139 is laser trimmed and guaranteed to be less than 500 µV.
The second error is calculated as

F
IO
G
F
F
G
G
G
F
IO RI
RR
RR
R
RR
Ie2Vo
_ (22)
where IIO is defined as the offset between the two input bias
currents.
The third error voltage is calculated as
Vo_e3 = enr × (VICM − VOCM) (23)
where enr is the fractional mismatch between the two
feedback resistors.
The total differential offset error is the sum of these three error
sources.
Other Impact of Mismatches in the Feedback Networks
The internal common-mode feedback network still forces the
output voltages to remain balanced, even when the RF/RG feedback
networks are mismatched. However, the mismatch causes a gain
error proportional to the feedback network mismatch.
Ratio-matching errors in the external resistors degrade the ability
to reject common-mode signals at the VAN and VIN input terminals,
much the same as with a four-resistor difference amplifier made
from a conventional op amp. Ratio-matching errors also produce a
differential output component that is equal to the VOCM input
voltage times the difference between the feedback factors (βs).
In most applications using 1% resistors, this component amounts
to a differential dc offset at the output that is small enough to be
ignored.
Data Sheet AD8139
Rev. C | Page 23 of 26
Driving a Capacitive Load
A purely capacitive load reacts with the bondwire and pin
inductance of the AD8139, resulting in high frequency ringing
in the transient response and loss of phase margin. One way to
minimize this effect is to place a small resistor in series with
each output to buffer the load capacitance (see Figure 58 and
Figure 63). The resistor and load capacitance form a first-order,
low-pass filter; therefore, the resistor value should be as small as
possible. In some cases, the ADCs require small series resistors
to be added on their inputs.
–13
–12
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
4
10M 100M 1G
5
FREQUENCY (Hz)
CLOSED LOOP GAIN (dB)
R
S
= 30.1Ω
C
L
= 15pF
R
S
= 60.4Ω
C
L
= 15pF
R
S
= 60.4Ω
C
L
= 5pF
R
S
= 0Ω
C
L, dm
= 0pF
R
S
= 30.1Ω
C
L
= 5pF
V
S
= ±5V
V
O, dm
= 0.1V p-p
G = 1 (R
F
= R
G
= 200Ω)
R
L, dm
= 1kΩ
0
4679-076
Figure 63. Frequency Response for
Various Capacitive Loads and Series Resistances
The Typical Performance Characteristics that illustrate transient
response vs. the capacitive load were generated using series
resistors in each output and a differential capacitive load.
Layout Considerations
Standard high speed PCB layout practices should be adhered
to when designing with the AD8139. A solid ground plane is
recommended, and good wideband power supply decoupling
networks should be placed as close as possible to the supply pins.
To minimize stray capacitance at the summing nodes, the copper
in all layers under all traces and pads that connect to the summing
nodes should be removed. Small amounts of stray summing-node
capacitance cause peaking in the frequency response, and large
amounts can cause instability. If some stray summing-node
capacitance is unavoidable, its effects can be compensated for
by placing small capacitors across the feedback resistors.
Terminating a Single-Ended Input
Controlled impedance interconnections are used in most
high speed signal applications, and they require at least one
line termination. In analog applications, a matched resistive
termination is generally placed at the load end of the line. This
section deals with how to properly terminate a single-ended
input to the AD8139.
The input resistance presented by the AD8139 input circuitry is
seen in parallel with the termination resistor, and its loading
effect must be taken into account. The Thevenin equivalent
circuit of the driver, its source resistance, and the termination
resistance must all be included in the calculation as well. An
exact solution to the problem requires the solution of several
simultaneous algebraic equations and is beyond the scope of
this data sheet. An iterative solution is also possible and simpler,
especially considering the fact that standard 1% resistor values
are generally used.
Figure 64 shows the AD8139 in a unity-gain configuration
driving the AD6645, which is a 14-bit, high speed ADC, and
with the following discussion, provides a good example of how
to provide a proper termination in a 50 Ω environment.
The termination resistor, RT, in parallel with the 268 Ω input
resistance of the AD8139 circuit (calculated using Equation 19),
yields an overall input resistance of 50 Ω that is seen by the signal
source. To have matched feedback loops, each loop must have
the same RG if they have the same RF. In the input (upper) loop,
RG is equal to the 200 Ω resistor in series with the (+) input plus
the parallel combination of RT and the source resistance of 50 Ω.
In the upper loop, RG is therefore equal to 228 Ω. The closest
standard 1% value to 228  is 226 Ω and is used for RG in the
lower loop. Greater accuracy could be achieved by using two
resistors in series to obtain a resistance closer to 228 Ω.
Things get more complicated when it comes to determining the
feedback resistor values. The amplitude of the signal source
generator VS is two times the amplitude of its output signal when
terminated in 50 Ω. Therefore, a 2 V p-p terminated amplitude
is produced by a 4 V p-p amplitude from VS. The Thevenin
equivalent circuit of the signal source and RT must be used when
calculating the closed-loop gain, because in the upper loop, RG is
split between the 200 Ω resistor and the Thevenin resistance
looking back toward the source. The Thevenin voltage of the
signal source is greater than the signal source output voltage
when terminated in 50 Ω because RT must always be greater than
50 Ω. In this case, RT is 61.9 Ω and the Thevenin voltage and
resistance are 2.2 V p-p and 28 Ω, respectively. Now the upper
input branch can be viewed as a 2.2 V p-p source in series
with 228 Ω. Because this is a unity-gain application, a 2 V p-p
differential output is required, and RF must therefore be 228 ×
(2/2.2) = 206 Ω. The closest standard value to this is 205 Ω.
When generating the Typical Performance Characteristics data,
the measurements were calibrated to take the effects of the
terminations on the closed-loop gain into account.
AD8139 Data Sheet
Rev. C | Page 24 of 26
Because this is a single-ended-to-differential application on a
single supply, the input common-mode voltage swing must be
checked. From Figure 64, β = 0.52, VOCM = 2.4 V, and VICM is
1.1 V p-p swinging about ground. Using Equation 16, VACM is
calculated to be 0.53 V p-p swinging about a baseline of 1.25 V,
and the minimum negative excursion is approximately 1 V.
Exposed Paddle (EP)
The 8-lead SOIC and the 8-lead LFCSP have an exposed paddle
on the bottom of the package. To achieve the specified thermal
resistance, the exposed paddle must be soldered to one of the
PCB planes. The exposed paddle mounting pad should contain
several thermal vias within it to ensure a low thermal path to
the plane.
AD8139
+
–
8
2
1
6
3
4
2.4V
2V p-p
R
T
61.9Ω
5
V
OCM
200Ω
226Ω
205Ω
205Ω25Ω
25Ω
0.01µF
0.01µF 0.01µF
AIN
AIN
GND C1
0.1µF
C2 VREF
0.1µF
AV
CC
DV
CC
5
V
3.3
V
AD6645
V
S
SIGNAL
SOURCE
50Ω
04679-054
Figure 64. AD8139 Driving AD6645, 14-Bit, 80 MSPS/105 MSPS ADC
Data Sheet AD8139
Rev. C | Page 25 of 26
OUTLINE DIMENSIONS
COMPLIANT TO JEDE C S TANDARDS MS-012-AA
06-02-2011-B
1.27
0.40
1.75
1.35
2.29
2.29
0.356
0.457
4.00
3.90
3.80
6.20
6.00
5.80
5.00
4.90
4.80
0.10 M AX
0.05 NO M
3.81 REF
0.25
0.17
8°
0°
0.50
0.25
45°
COPLANARITY
0.10
1.04 REF
8
14
5
1.27 BSC
SEATING
PLANE
FOR PRO P E R CONNECTION O F
THE EXPOSED PAD, REFER TO
THE P IN CO NFI GURATIO N AND
FUNCTION DES CRIPT IO NS
SECTION OF THIS DATA SHEET.
BOTTOM VIEW
TOP VIEW
0.51
0.31
1.65
1.25
Figure 65. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP]
Narrow Body
(RD-8-1)
Dimensions shown in millimeters
TOP VIEW
8
1
5
4
0.30
0.25
0.20
BOTTOM VIEW
PIN 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.55
1.45
1.35
1.84
1.74
1.64
0.203 REF
0.05 MAX
0.02 NOM
0.50 BSC
EXPOSED
PAD
3.10
3.00 SQ
2.90
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS MO-229-WEED
12-07-2010-A
PIN 1
INDICATOR
(R0.15)
Figure 66. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-8-13)
Dimensions shown in millimeters
AD8139 Data Sheet
Rev. C | Page 26 of 26
ORDERING GUIDE
Model1 Temperature Range Package Description
Package
Option Branding
AD8139ARDZ –40°C to +125°C 8-Lead Small Outline Package with Exposed Pad [SOIC_N_EP] RD-8-1
AD8139ARDZ-REEL –40°C to +125°C 8-Lead Small Outline Package with Exposed Pad [SOIC_N_EP] RD-8-1
AD8139ARDZ-REEL7 –40°C to +125°C 8-Lead Small Outline Package with Exposed Pad [SOIC_N_EP] RD-8-1
AD8139ACPZ-R2 –40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 HEB#
AD8139ACPZ-REEL –40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 HEB#
AD8139ACPZ-REEL7 –40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 HEB#
AD8139ACP-EBZ Evaluation Board
1 Z = RoHS Compliant Part, # denotes RoHS product may be top or bottom marked.
©2004–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04679-0-6/16(C)
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Analog Devices Inc.:
AD8139ARD-EBZ