Low Noise, Rail-to-Rail, Differential ADC Driver AD8139 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAMS APPLICATIONS ADC drivers to 18 bits Single-ended-to-differential converters Differential filters Level shifters Differential PCB drivers Differential cable drivers 8 +IN VOCM 2 7 NIC V+ 3 6 V- +OUT 4 5 -OUT NIC = NO INTERNAL CONNECTION. 04679-001 AD8139 -IN 1 Figure 1. 8-Lead SOIC AD8139 TOP VIEW (Not to Scale) -IN 1 8 +IN VOCM 2 7 NIC V+ 3 +OUT 4 6 V- 5 -OUT NIC = NO INTERNAL CONNECTION. 04679-102 Fully differential Low noise 2.25 nV/Hz 2.1 pA/Hz Low harmonic distortion 98 dBc SFDR at 1 MHz 85 dBc SFDR at 5 MHz 72 dBc SFDR at 20 MHz High speed 410 MHz, 3 dB BW (G = 1) 800 V/s slew rate 45 ns settling time to 0.01% 69 dB output balance at 1 MHz 80 dB dc CMRR Low offset: 0.5 mV maximum Low input offset current: 0.5 A maximum Differential input and output Differential-to-differential or single-ended-to-differential operation Rail-to-rail output Adjustable output common-mode voltage Wide supply voltage range: 5 V to 12 V Available in a small SOIC package and an 8-lead LFCSP Figure 2. 8-Lead LFCSP The AD8139 is manufactured on the proprietary Analog Devices, Inc., second-generation XFCB process, enabling it to achieve low levels of distortion with input voltage noise of only 2.25 nV/Hz. The AD8139 is available in an 8-lead SOIC package with an exposed paddle (EP) on the underside of its body and a 3 mm x 3 mm LFCSP. It is rated to operate over the temperature range of -40C to +125C. 100 Rev. C 10 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 1G 04679-078 The AD8139 is an ultralow noise, high performance differential amplifier with rail-to-rail output. With its low noise, high SFDR, and wide bandwidth, it is an ideal choice for driving analog-to-digital converters (ADCs) with resolutions to 18 bits. The AD8139 is easy to apply, and its internal common-mode feedback architecture allows its output common-mode voltage to be controlled by the voltage applied to one pin. The internal feedback loop also provides outstanding output balance as well as suppression of even-order harmonic distortion products. Fully differential and single-ended-to-differential gain configurations are easily realized by the AD8139. Simple external feedback networks consisting of four resistors determine the closed-loop gain of the amplifier. INPUT VOLTAGE NOISE (nV/ Hz) GENERAL DESCRIPTION Figure 3. Input Voltage Noise vs. Frequency Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2004-2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD8139 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configurations and Function Descriptions ............................8 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................9 General Description ......................................................................... 1 Test Circuits ..................................................................................... 18 Functional Block Diagrams ............................................................. 1 Theory of Operation ...................................................................... 19 Revision History ............................................................................... 2 Typical Connection and Definition of Terms ........................ 19 Specifications..................................................................................... 3 Applications Information .............................................................. 20 VS = 5 V, VOCM = 0 V .................................................................. 3 VS = 5 V, VOCM = 2.5 V ................................................................. 5 Estimating Noise, Gain, and Bandwidth with Matched Feedback Networks .................................................................... 20 Absolute Maximum Ratings............................................................ 7 Outline Dimensions ....................................................................... 25 Thermal Resistance ...................................................................... 7 Ordering Guide .......................................................................... 26 ESD Caution .................................................................................. 7 REVISION HISTORY 6/2016--Rev. B to Rev. C Changed CP-8-2 to CP-8-13 ........................................ Throughout Changes to Figure 1 and Figure 2 ................................................... 1 Changes to Figure 5, Figure 6, and Table 5 ................................... 8 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide ......................................................... 26 10/2007--Rev. A to Rev. B Changes to General Description Section ...................................... 1 Added Figure 2; Renumbered Sequentially .................................. 1 Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 5 Changes to Table 6 and Layout ....................................................... 8 Added Figure 6 .................................................................................. 8 Changes to Figure 30 ...................................................................... 12 Changes to Layout .......................................................................... 17 Changes to Figure 63 ...................................................................... 22 Changes to Exposed Paddle (EP) Section ................................... 23 Updated Outline Dimensions ....................................................... 24 8/2004--Rev. 0 to Rev. A Added 8-Lead LFCSP......................................................... Universal Changes to General Description Section .......................................1 Changes to Figure 2 ...........................................................................1 Changes to VS = 5 V, VOCM = 0 V Specifications .........................3 Changes to VS = 5 V, VOCM = 2.5 V Specifications.........................5 Changes to Table 4.............................................................................7 Changes to Maximum Power Dissipation Section........................7 Changes to Figure 26 and Figure 29............................................. 12 Added Figure 39 and Figure 42; Renumbered Sequentially ..... 14 Changes to Figure 45 to Figure 47................................................ 15 Added Figure 48 ............................................................................. 15 Changes to Figure 52 and Figure 53............................................. 16 Changes to Figure 55 and Figure 56............................................. 17 Changes to Table 6.......................................................................... 19 Changes to Voltage Gain Section ................................................. 19 Changes to Driving a Capacitive Load Section .......................... 22 Changes to Ordering Guide .......................................................... 24 Updated Outline Dimensions ....................................................... 24 5/2004--Revision 0: Initial Version Rev. C | Page 2 of 26 Data Sheet AD8139 SPECIFICATIONS VS = 5 V, VOCM = 0 V TA = 25C, differential gain = 1, RL, dm = 1 k, RF = RG = 200 , unless otherwise noted. TMIN to TMAX = -40C to +125C. Table 1. Parameter DIFFERENTIAL INPUT PERFORMANCE Dynamic Performance -3 dB Small Signal Bandwidth -3 dB Large Signal Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.01% Overdrive Recovery Time Noise/Harmonic Performance SFDR Third-Order IMD Input Voltage Noise Input Current Noise DC Performance Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Open-Loop Gain Input Characteristics Input Common-Mode Voltage Range Input Resistance Input Capacitance CMRR Output Characteristics Output Voltage Swing Output Current Output Balance Error VOCM TO VO, cm PERFORMANCE VOCM Dynamic Performance -3 dB Bandwidth Slew Rate Gain VOCM Input Characteristics Input Voltage Range Input Resistance Input Offset Voltage Input Voltage Noise Input Bias Current CMRR Test Conditions/Comments Min Typ VO, dm = 0.1 V p-p VO, dm = 2 V p-p VO, dm = 0.1 V p-p VO, dm = 2 V step VO, dm = 2 V step, CF = 2 pF G = 2, VIN, dm = 12 V p-p triangle wave 340 210 410 240 45 800 45 30 MHz MHz MHz V/s ns ns 98 85 72 -90 2.25 2.1 dBc dBc dBc dBc nV/Hz pA/Hz VO, dm = 2 V p-p, fC = 1 MHz VO, dm = 2 V p-p, fC = 5 MHz VO, dm = 2 V p-p, fC = 20 MHz VO, dm = 2 V p-p, fC = 10.05 MHz 0.05 MHz f = 100 kHz f = 100 kHz VIP = VIN = VOCM = 0 V TMIN to TMAX TMIN to TMAX -500 150 1.25 2.25 0.12 114 -4 Differential Common mode Common mode VICM = 1 V dc, RF = RG = 10 k Each single-ended output, RF = RG = 10 k Each single-ended output, RL, dm = open circuit, RF = RG = 10 k Each single-ended output f = 1 MHz 80 0.999 -900 VOCM/VO, dm, VOCM = 1 V 74 Rev. C | Page 3 of 26 8.0 0.5 Unit V V/C A A dB +4 V k M pF dB +VS - 0.20 +VS - 0.15 V V 100 -69 mA dB 515 250 1.000 MHz V/s V/V -3.8 VOS, cm = VO, cm - VOCM; VIP = VIN = VOCM = 0 V f = 100 kHz +500 600 1.5 1.2 84 -VS + 0.20 -VS + 0.15 VO, cm = 0.1 V p-p VO, cm = 2 V p-p Max 1.001 +3.8 3.5 300 3.5 1.3 88 +900 4.5 V M V nV/Hz A dB AD8139 Parameter POWER SUPPLY Operating Range Quiescent Current +PSRR -PSRR OPERATING TEMPERATURE RANGE Data Sheet Test Conditions/Comments Min Typ +4.5 Change in +VS = 1 V Change in -VS = 1 V Rev. C | Page 4 of 26 95 95 -40 24.5 112 109 Max Unit 6 25.5 V mA dB dB C +125 Data Sheet AD8139 VS = 5 V, VOCM = 2.5 V TA = 25C, differential gain = 1, RL, dm = 1 k, RF = RG = 200 , unless otherwise noted. TMIN to TMAX = -40C to +125C. Table 2. Parameter DIFFERENTIAL INPUT PERFORMANCE Dynamic Performance -3 dB Small Signal Bandwidth -3 dB Large Signal Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.01% Overdrive Recovery Time Noise/Harmonic Performance SFDR Third-Order IMD Input Voltage Noise Input Current Noise DC Performance Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Open-Loop Gain Input Characteristics Input Common-Mode Voltage Range Input Resistance Input Capacitance CMRR Output Characteristics Output Voltage Swing Output Current Output Balance Error VOCM TO VO, cm PERFORMANCE VOCM Dynamic Performance -3 dB Bandwidth Slew Rate Gain VOCM Input Characteristics Input Voltage Range Input Resistance Input Offset Voltage Input Voltage Noise Input Bias Current CMRR Test Conditions/Comments Min Typ VO, dm = 0.1 V p-p VO, dm = 2 V p-p VO, dm = 0.1 V p-p VO, dm = 2 V step VO, dm = 2 V step G = 2, VIN, dm = 7 V p-p triangle wave 330 135 385 165 34 540 55 35 MHz MHz MHz V/s ns ns 99 87 75 -87 2.25 2.1 dBc dBc dBc dBc nV/Hz pA/Hz VO, dm = 2 V p-p, fC = 1 MHz VO, dm = 2 V p-p, fC = 5 MHz, RL = 800 VO, dm = 2 V p-p, fC = 20 MHz, RL = 800 VO, dm = 2 V p-p, fC = 10.05 MHz 0.05 MHz f = 100 kHz f = 100 kHz VIP = VIN = VOCM = 2.5 V TMIN to TMAX TMIN to TMAX -500 150 1.25 2.2 0.13 112 1 Differential Common mode Common mode VICM = 1 V dc, RF = RG = 10 k Each single-ended output, RF = RG = 10 k Each single-ended output, RL, dm = open circuit, RF = RG = 10 k Each single-ended output f = 1 MHz 75 0.999 -1.0 VOCM/VO, dm, VOCM = 1 V 67 Rev. C | Page 5 of 26 7.5 0.5 Unit V V/C A A dB 4 V k M pF dB +VS - 0.15 +VS - 0.10 V V 80 -70 mA dB 440 150 1.000 MHz V/s V/V 1.0 VOS, cm = VO, cm - VOCM; VIP = VIN = VOCM = 2.5 V f = 100 kHz +500 600 1.5 1.2 79 -VS + 0.15 -VS + 0.10 VO, cm = 0.1 V p-p VO, cm = 2 V p-p Max 1.001 3.8 3.5 0.45 3.5 1.3 79 +1.0 4.2 V M mV nV/Hz A dB AD8139 Parameter POWER SUPPLY Operating Range Quiescent Current +PSRR -PSRR OPERATING TEMPERATURE RANGE Data Sheet Test Conditions/Comments Min Typ +4.5 Change in +VS = 1 V Change in -VS = 1 V Rev. C | Page 6 of 26 86 92 -40 21.5 97 105 Max Unit 6 22.5 V mA dB dB C +125 Data Sheet AD8139 ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage VOCM Power Dissipation Input Common-Mode Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature Rating 12 V VS See Figure 4 VS -65C to +125C -40C to +125C 300C 150C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). The load current consists of differential and common-mode currents flowing to the load, as well as currents flowing through the external feedback networks and the internal common-mode feedback loop. The internal resistor tap used in the common-mode feedback loop places a 1 k differential load on the output. RMS output voltages should be considered when dealing with ac signals. Airflow reduces JA. In addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduce the JA. Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the exposed paddle (EP) 8-lead SOIC (JA = 70C/W) and the 8-lead LFCSP (JA = 70C/W) on a JEDEC standard 4-layer board. JA values are approximations. JA is specified for the worst-case conditions, that is, JA is specified for device soldered in circuit board for surface-mount packages. MAXIMUM POWER DISSIPATION (W) 4.0 Table 4. Package Type 8-Lead SOIC with EP/4-Layer 8-Lead LFCSP/4-Layer JA 70 70 Unit C/W C/W Maximum Power Dissipation The maximum safe power dissipation in the AD8139 package is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8139. Exceeding a junction temperature of 175C for an extended period can result in changes in the silicon devices potentially causing failure. 3.5 3.0 2.5 2.0 1.5 SOIC AND LFCSP 1.0 0.5 0 -40 -20 0 20 40 60 80 AMBIENT TEMPERATURE (C) 100 120 04679-055 Table 3. Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board ESD CAUTION Rev. C | Page 7 of 26 AD8139 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS AD8139 +IN VOCM 2 7 NIC TOP VIEW V+ 3 (Not to Scale) 6 V- VOCM 2 +OUT 4 8 +IN -IN 1 8 5 V+ 3 +OUT 4 -OUT AD8139 7 NIC TOP VIEW (Not to Scale) 6 V- 5 -OUT NOTES 1. NIC = NO INTERNAL CONNECTION. 2. SOLDER THE EXPOSED PADDLE ON THE BACK OF THE PACKAGE TO THE GROUND PLANE OR TO A POWER PLANE. 04679-003 NOTES 1. NIC = NO INTERNAL CONNECTION. 2. SOLDER THE EXPOSED PADDLE ON THE BACK OF THE PACKAGE TO THE GROUND PLANE OR TO A POWER PLANE. Figure 5. 8-Lead SOIC Pin Configuration 04679-103 -IN 1 Figure 6. 8-Lead LFCSP Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 Mnemonic -IN VOCM 3 4 5 6 7 8 0 V+ +OUT -OUT V- NIC +IN EP Description Inverting Input. An internal feedback loop drives the output common-mode voltage to be equal to the voltage applied to the VOCM pin, provided the operation of the amplifier remains linear. Positive Power Supply Voltage. Positive Side of the Differential Output. Negative Side of the Differential Output. Negative Power Supply Voltage. No Internal Connection. Noninverting Input. Exposed Paddle. Solder the exposed paddle on the back of the package to the ground plane or to a power plane. Rev. C | Page 8 of 26 Data Sheet AD8139 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, differential gain = +1, RG = RF = 200 , RL, dm = 1 k, VS = 5 V, TA = 25C, VOCM = 0 V. Refer to the basic test circuit in Figure 57 for the definition of terms. 2 NORMALIZED CLOSED-LOOP GAIN (dB) G=2 -1 -2 -3 -4 -5 G=5 -6 -7 G = 10 -8 -9 -10 RG = 200 VO, dm = 0.1V p-p -13 1 10 100 1000 FREQUENCY (MHz) -5 -6 -8 -9 -10 -11 RG = 200 VO, dm = 2.0V p-p -12 1 10 100 1000 2 1 0 1 -1 0 CLOSED-LOOP GAIN (dB) 2 VS = 5V -1 -2 -3 -4 -5 -6 -2 -4 -6 -7 -8 -9 -10 -11 VO, dm = 0.1V p-p 1000 Figure 8. Small Signal Frequency Response for Various Power Supplies 3 3 CLOSED-LOOP GAIN (dB) 0 -1 -2 -3 -4 -40C -7 -8 -2 -3 -4 -5 -6 -7 -8 -9 -9 -10 -10 VO, dm = 0.1V p-p -11 +25C FREQUENCY (MHz) 1000 -12 10 04679-006 100 +85C 1 0 -6 +125C 2 -1 -5 1000 Figure 11. Large Signal Frequency Response for Various Power Supplies +85C 1 100 FREQUENCY (MHz) +125C 2 VO, dm = 2.0V p-p -12 10 04679-005 100 FREQUENCY (MHz) VS = +5V -5 -8 -10 10 VS = 5V -3 -7 -12 10 G = 10 -7 Figure 10. Large Signal Frequency Response for Various Gains VS = +5V 3 CLOSED-LOOP GAIN (dB) -4 3 4 -11 G=2 -3 FREQUENCY (MHz) 5 -9 G=5 -2 -13 Figure 7. Small Signal Frequency Response for Various Gains CLOSED-LOOP GAIN (dB) -1 04679-008 -12 0 Figure 9. Small Signal Frequency Response at Various Temperatures -40C +25C VO, dm = 2.0V p-p 100 FREQUENCY (MHz) 1000 04679-009 -11 G=1 1 G=1 0 04679-004 NORMALIZED CLOSED-LOOP GAIN (dB) 1 04679-007 2 Figure 12. Large Signal Frequency Response at Various Temperatures Rev. C | Page 9 of 26 AD8139 3 RL = 200 2 2 RL = 100 1 0 0 -1 -1 -2 RL = 500 -3 -4 -5 -6 -7 -8 -2 -3 -4 -5 -6 -7 -8 -12 1000 04679-040 100 Figure 16. Large Signal Frequency Response for Various Loads 2 CF = 0pF 2 1 0 CF = 2pF -5 -6 -7 -8 -4 -5 -6 -7 -8 -9 -11 -12 1000 VOCM = +4.3V 5 0.5 VOCM = +4V NORMALIZED CLOSED-LOOP GAIN (dB) 3 VOCM = -4V 2 1 0 VOCM = 0V -1 -2 -3 -4 -5 -6 -7 -9 10 VO, dm = 0.1V p-p 100 1000 FREQUENCY (MHz) 04679-012 -8 1000 Figure 17. Large Signal Frequency Response for Various CF VOCM = -4.3V 4 100 FREQUENCY (MHz) Figure 14. Small Signal Frequency Response for Various CF 6 VO, dm = 2.0V p-p -13 10 RL = 100 (VO, dm = 0.1V p-p) 0.4 RL = 100 (VO, dm = 2.0V p-p) 0.3 RL = 1k (VO, dm = 2.0V p-p) 0.2 0.1 RL = 1k (VO, dm = 0.1V p-p) 0 -0.1 -0.2 -0.3 04679-0-042 100 FREQUENCY (MHz) 04679-011 VO, dm = 0.1V p-p 04679-014 -10 -12 10 CF = 2pF -3 -10 -9 -11 -2 CLOSED-LOOP GAIN (dB) -2 -4 CF = 1pF -1 -1 -3 CF = 0pF 1 CF = 1pF 0 1000 FREQUENCY (MHz) Figure 13. Small Signal Frequency Response for Various Loads 3 RL = 200 100 04679-041 VO, dm = 2.0V p-p -13 10 RL = 1k FREQUENCY (MHz) CLOSED-LOOP GAIN (dB) RL = 1k -9 -11 VO, dm = 0.1V p-p -12 10 CLOSED-LOOP GAIN (dB) RL = 500 -10 -9 -10 -11 RL = 100 1 CLOSED-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) Data Sheet -0.4 -0.5 1 10 100 FREQUENCY (Hz) Figure 18. 0.1 dB Flatness for Various Loads and Output Amplitudes Figure 15. Small Signal Frequency Response at Various VOCM Rev. C | Page 10 of 26 Data Sheet AD8139 -30 -50 DISTORTION (dBc) VS = 5V -70 -80 VS = +5V -90 -100 -120 10 100 Figure 19. Second Harmonic Distortion vs. Frequency and Supply Voltage -130 0.1 1 10 100 FREQUENCY (MHz) Figure 22. Third Harmonic Distortion vs. Frequency and Supply Voltage -30 -30 VO, dm = 2.0V p-p -40 -50 VO, dm = 2.0V p-p -50 -60 DISTORTION (dB) G=1 -70 -80 G=5 -90 -100 G=2 -110 -70 -80 -90 -100 -110 -120 -120 -130 -130 1 10 100 FREQUENCY (MHz) -140 0.1 04679-016 -140 0.1 G=1 G=2 G=5 1 10 100 FREQUENCY (MHz) Figure 20. Second Harmonic Distortion vs. Frequency and Gain Figure 23. Third Harmonic Distortion vs. Frequency and Gain -30 -30 VO, dm = 2.0V p-p -40 -40 -50 -50 -60 DISTORTION (dBc) -70 RL = 100 RL = 200 -80 -90 RL = 500 -100 RL = 1k VO, dm = 2.0V p-p -80 -90 -100 -120 -130 0.1 -130 0.1 100 04679-017 -120 10 Figure 21. Second Harmonic Distortion vs. Frequency and Load RL = 200 -70 -110 FREQUENCY (MHz) RL = 100 -60 -110 1 RL = 500 RL = 1k 1 10 100 FREQUENCY (MHz) Figure 24. Third Harmonic Distortion vs. Frequency and Load Rev. C | Page 11 of 26 04679-019 -60 DISTORTION (dB) -90 -100 -120 1 VS = 5V -80 -110 FREQUENCY (MHz) DISTORTION (dBc) -70 -110 -130 0.1 VS = +5V -60 04679-018 -60 04679-015 DISTORTION (dBc) -50 -40 VO, dm = 2.0V p-p -40 04679-020 -40 -30 VO, dm = 2.0V p-p AD8139 Data Sheet -30 -30 VO, dm = 2.0V p-p -50 -50 -60 -60 RF = 200 RF = 500 -90 -100 -110 -70 -80 -90 RF = 200 -100 -110 RF = 1k -130 0.1 -120 1 10 100 FREQUENCY (MHz) 1 10 Figure 28. Third Harmonic Distortion vs. Frequency and RF -80 -80 FC = 2MHz VS = 5V -90 -90 VS = +5V VS = +5V -100 DISTORTION (dBc) -110 -120 -130 -130 -140 1 2 3 4 5 6 7 8 -150 04679-022 0 VO, dm (V p-p) -60 1 2 3 -60 5 6 7 8 VO, dm = 2V p-p FC = 2MHz -70 -80 -90 DISTORTION (dBc) -80 SECOND HARMONIC -100 -110 -90 SECOND HARMONIC -100 -110 -120 -120 THIRD HARMONIC 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VOCM (V) 5.0 04679-023 THIRD HARMONIC -130 4 Figure 29. Third Harmonic Distortion vs. Output Amplitude VO, dm = 2V p-p FC = 2MHz -70 0 VO, dm (V p-p) Figure 26. Second Harmonic Distortion vs. Output Amplitude DISTORTION (dBc) -120 04679-025 -140 VS = 5V -110 Figure 27. Harmonic Distortion vs. VOCM, VS = +5 V -130 -5 -4 -3 -2 -1 0 1 2 3 4 VOCM (V) Figure 30. Harmonic Distortion vs. VOCM, VS = 5 V Rev. C | Page 12 of 26 5 04679-026 DISTORTION (dBc) -100 -150 100 FREQUENCY (MHz) Figure 25. Second Harmonic Distortion vs. Frequency and RF FC = 2MHz RF = 500 -130 0.1 04679-021 -120 RF = 1k 04679-024 -70 -80 VO, dm = 2.0V p-p -40 DISTORTION (dBc) DISTORTION (dBc) -40 Data Sheet 100 AD8139 2.5 VO, dm = 100mV p-p CF = 0pF 75 CF = 2pF 1.5 CF = 0pF (CF = 0pF, VS = 5V) 25 CF = 0pF 1.0 VO, dm (CF = 2pF, VS = 5V) VO, dm (V) 50 VO, dm (V) 4V p-p 2.0 0 CF = 2pF 0.5 2V p-p 0 -0.5 -25 -1.0 -50 -1.5 -75 5ns/DIV 04679-043 -100 TIME (ns) -2.5 TIME (ns) Figure 31. Small Signal Transient Response for Various CF 0.100 Figure 34. Large Signal Transient Response for Various CF 1.5 RS = 31.6 CL, dm = 30pF 0.075 04679-044 -2.0 5ns/DIV RS = 63.4 CL, dm = 15pF 1.0 0.050 0.5 RS = 63.4 CL, dm = 15pF VO, dm (V) VO, dm (V) 0.025 0 -0.025 RS = 31.6 CL, dm = 30pF 0 -0.5 -0.050 -1.0 -0.075 TIME (ns) Figure 35. Large Signal Transient Response for Capacitive Loads AMPLITUDE (V) NORMALIZED OUTPUT (dBc) 1.5 CF = 2pF VO, dm = 2.0V p-p 1.0 400 0.5 200 0 0 ERROR -0.5 -200 VO, dm FREQUENCY (MHz) 04679-027 -1.0 9.95 10.05 10.15 10.25 10.35 10.45 10.55 600 -1.5 -400 35ns/DIV VIN -600 TIME (ns) Figure 36. Settling Time (0.01%) Figure 33. Intermodulation Distortion Rev. C | Page 13 of 26 04679-034 Figure 32. Small Signal Transient Response for Capacitive Loads 5 0 VO, dm = 2V p-p -5 FC1 = 10MHz -10 FC2 = 10.1MHz -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 9.55 9.65 9.75 9.85 04679-065 TIME (ns) 5ns/DIV -1.5 ERROR (V) 1DIV = 0.01% -0.100 04679-064 5ns/DIV AD8139 Data Sheet 6 5V 5 4 1.0 -0.5 VO, cm = 2V p-p VIN, dm = 0V 1 0 -2 -5 -7 -9 10 0 VIN, cm = 0.2V p-p INPUT CMRR = VO, cm/VIN, cm VO, cm = 0.2V p-p VOCM CMRR = VO, dm/VO, cm -10 -20 -20 -30 -30 RF = RG = 10k -50 -60 RF = RG = 200 -40 -50 -60 -70 10 100 500 FREQUENCY (MHz) -90 04679-066 1 1 10 500 Figure 41. VOCM CMRR vs. Frequency Figure 38. CMRR vs. Frequency 100 VOCM VOLTAGE NOISE (nV/ Hz) 100 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 1G 04679-079 10 1 10 100 FREQUENCY (MHz) 04679-045 -80 -80 INPUT VOLTAGE NOISE (nV/ Hz) 1000 Figure 40. VOCM Frequency Response for Various Supplies VOCM CMRR (dB) CMRR (dB) 100 FREQUENCY (MHz) Figure 37. VOCM Large Signal Transient Response -70 VS = +5V -8 04679-069 TIME (ns) -40 VS = 5V VO, cm = 2.0V p-p -4 -6 -1.5 -90 VS = 5V -3 10ns/DIV -10 VO, cm = 0.1V p-p -1 10 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M Figure 42. VOCM Voltage Noise vs. Frequency Figure 39. Input Voltage Noise vs. Frequency Rev. C | Page 14 of 26 1G 04679-080 VOCM (V) 0 -1.0 2 CLOSED-LOOP GAIN (dB) +5V 0.5 0 VS = +5V 3 04679-038 1.5 Data Sheet AD8139 0 14 2 x VIN, dm G=2 12 10 -20 8 -30 6 VOLTAGE (V) PSRR (dB) RL, dm = 1k -10 PSRR = VO, dm/VS -40 -PSRR -50 +PSRR -60 -70 VO, dm 4 2 0 -2 -4 -6 -8 -80 -90 -12 1 10 100 500 FREQUENCY (MHz) 50ns/DIV -14 04679-047 -100 TIME (ns) Figure 46. Overdrive Recovery Figure 43. PSRR vs. Frequency 0 100 VS = +5V VO, dm = 1V p-p OUTPUT BALANCE = VO, cm/VO, dm -10 10 OUTPUT BALANCE (dB) OUTPUT IMPEDANCE () 04679-046 -10 VS = 5V 1 0.1 -20 -30 -40 -50 -60 10 100 1000 FREQUENCY (MHz) -80 1 10 500 Figure 47. Output Balance vs. Frequency Figure 44. Single-Ended Output Impedance vs. Frequency -50 300 700 600 500 300 VOP SWING FROM RAIL (mV) 400 VS+ - VOP 200 100 0 VS = 5V VS = +5V -100 -200 VON - VS- -300 -400 250 VS = 5V G = 1 (RF = RG = 200) RL, dm = 1k -100 VS+ - VOP 200 -150 150 -200 VON - VS- 100 -250 -500 -700 100 1k RESISTIVE LOAD () 10k 50 -40 -20 0 20 40 60 80 100 120 -300 TEMPERATURE (C) Figure 48. Output Saturation Voltage vs. Temperature Figure 45. Output Saturation Voltage vs. Output Load Rev. C | Page 15 of 26 04679-077 -600 04679-068 SINGLE-ENDED OUTPUT SWING FROM RAIL (mV) 100 FREQUENCY (MHz) VON SWING FROM RAIL (mV) 1 04679-028 0.01 0.1 04679-067 -70 AD8139 Data Sheet 3.0 170 26 VS = 5V IBIAS 2.0 120 1.5 95 OFFSET CURRENT (nA) 145 SUPPLY CURRENT (mA) 25 2.5 24 23 VS = +5V 22 -20 0 20 40 60 80 100 120 70 20 -40 04679-062 TEMPERATURE (C) -20 20 40 60 80 100 120 TEMPERATURE (C) Figure 49. Input Bias and Offset Current vs. Temperature Figure 52. Supply Current vs. Temperature 10 600 300 8 VOS, cm 6 250 400 200 200 VS = 5V 4 VS = +5V 2 VOS, dm (V) INPUT BIAS CURRENT (A) 0 0 -2 -4 -6 150 0 VOS, dm 100 -200 50 -400 VOS, cm (V) 1.0 -40 04679-060 21 -3 -2 -1 0 1 2 3 4 5 VACM (V) 0 -40 -20 40 60 80 100 120 -600 TEMPERATURE (C) 5 50 4 45 VS = 2.5V COUNT = 350 MEAN = -50V STD DEV = 100V 40 35 2 FREQUENCY VS = 5V 1 0 -1 30 25 20 -2 15 -3 10 -4 5 -3 -2 -1 0 1 2 3 VOCM (V) 4 5 Figure 51. VOUT, cm vs. VOCM Input Voltage -500 -450 -400 -350 -300 -250 -200 -150 -100 -50 0 50 100 150 200 250 300 350 400 450 500 0 -4 04679-048 -5 -5 20 Figure 53. Offset Voltage vs. Temperature Figure 50. Input Bias Current vs. Input Common-Mode Voltage 3 0 04679-061 -4 VOS, dm (V) Figure 54. VOS, dm Distribution Rev. C | Page 16 of 26 04679-071 -10 -5 04679-073 -8 VOUT, cm (V) INPUT BIAS CURRENT (A) IOS Data Sheet AD8139 1.7 6 1.6 4 VOCM BIAS CURRENT (A) 1.4 1.3 1.2 1.1 1.0 0.9 VS = 5V VS = +5V 2 0 -2 -4 0.7 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) 120 -6 -5 -4 -3 -2 -1 0 1 2 3 4 VOCM (V) Figure 55. VOCM Bias Current vs. Temperature Figure 56. VOCM Bias Current vs. VOCM Input Voltage Rev. C | Page 17 of 26 5 04679-074 0.8 04679-063 VOCM BIAS CURRENT (A) 1.5 AD8139 Data Sheet TEST CIRCUITS RF 50 VOCM 60.4 TEST SIGNAL SOURCE RL, dm = 1k AD8139 RG = 200 50 - VO, dm + CF 04679-072 VTEST CF RG = 200 60.4 RF Figure 57. Basic Test Circuit RF = 200 TEST SIGNAL SOURCE 60.4 50 RS RG = 200 60.4 VTEST VOCM CL, dm AD8139 RG = 200 RS RF = 200 Figure 58. Capacitive Load Test Circuit, G = +1 Rev. C | Page 18 of 26 - RL, dm VO, dm + 04679-075 50 Data Sheet AD8139 THEORY OF OPERATION The AD8139 is a high speed, low noise differential amplifier fabricated on the Analog Devices second-generation extra fast complementary bipolar (XFCB) process. It is designed to provide two closely balanced differential outputs in response to either differential or single-ended input signals. Differential gain is set by external resistors, similar to traditional voltagefeedback operational amplifiers. The common-mode level of the output voltage is set by a voltage at the VOCM pin and is independent of the input common-mode voltage. The AD8139 has an H-bridge input stage for high slew rate, low noise, and low distortion operation and rail-to-rail output stages that provide maximum dynamic output range. This set of features allows for convenient single-ended-to-differential conversion, a common need to take advantage of modern high resolution ADCs with differential inputs. TYPICAL CONNECTION AND DEFINITION OF TERMS Figure 59 shows a typical connection for the AD8139, using matched external RF/RG networks. The differential input terminals of the AD8139, VAP and VAN, are used as summing junctions. An external reference voltage applied to the VOCM terminal sets the output common-mode voltage. The two output terminals, VOP and VON, move in opposite directions in a balanced fashion in response to an input signal. outputs of identical amplitude and exactly 180 out of phase. The output balance performance does not require tightly matched external components, nor does it require that the feedback factors of each loop be equal to each other. Low frequency output balance is limited ultimately by the mismatch of an on-chip voltage divider, which is trimmed for optimum performance. Output balance is measured by placing a well-matched resistor divider across the differential voltage outputs and comparing the signal at the midpoint of the divider with the magnitude of the differential output. By this definition, output balance is equal to the magnitude of the change in output common-mode voltage divided by the magnitude of the change in output differential-mode voltage: VAN = VAP VOCM VIN RG VON + AD8139 VAN - RL, dm VO, dm VOP - VOP VOCM + RF VON VOCM Figure 59. Typical Connection VIN The differential output voltage is defined as VO, dm = VOP - VON VOP VON 2 VO, dm (6) 2 RG RF 10pF (1) + Common-mode voltage is the average of two voltages. The output common-mode voltage is defined as VO, cm (5) 2 and 04679-050 CF VO, dm GO VOP 500 VAN VAP (2) Output Balance MIDSUPPLY GCM GDIFF + Output balance is a measure of how well VOP and VON are matched in amplitude and how precisely they are 180 out of phase with each other. It is the internal common-mode feedback loop that forces the signal component of the output common-mode towards zero, resulting in the near perfectly balanced differential 500 VOCM GO VON 10pF VIP Rev. C | Page 19 of 26 RG RF Figure 60. Block Diagram 04679-051 VAP (4) The common-mode feedback loop drives the output commonmode voltage, sampled at the midpoint of the two 500 resistors, to equal the voltage set at the VOCM terminal. This ensures that RF RG (3) VO, dm The block diagram of the AD8139 in Figure 60 shows the external differential feedback loop (RF/RG networks and the differential input transconductance amplifier, GDIFF) and the internal common-mode feedback loop (voltage divider across VOP and VON and the common-mode input transconductance amplifier, GCM). The differential negative feedback drives the voltages at the summing junctions VAN and VAP to be essentially equal to each other. CF VIP VO, cm Output Balance AD8139 Data Sheet APPLICATIONS INFORMATION Voltage Gain ESTIMATING NOISE, GAIN, AND BANDWIDTH WITH MATCHED FEEDBACK NETWORKS Estimating Output Noise Voltage The total output noise is calculated as the root-sum-squared total of several statistically independent sources. Because the sources are statistically independent, the contributions of each must be individually included in the root-sum-square calculation. Table 6 lists recommended resistor values and estimates of bandwidth and output differential voltage noise for various closed-loop gains. For most applications, 1% resistors are sufficient. Table 6. Recommended Values of Gain-Setting Resistors and Voltage Noise for Various Closed-Loop Gains Gain 1 2 5 10 RG () 200 200 200 200 RF () 200 400 1k 2k 3 dB Bandwidth (MHz) 400 160 53 26 Total Output Noise (nV/Hz) 5.8 9.3 19.7 37 The differential output voltage noise contains contributions from the input voltage noise and input current noise of the AD8139 as well as those from the external feedback networks. The behavior of the node voltages of the single-ended-todifferential output topology can be deduced from the previous definitions. Referring to Figure 59, (CF = 0) and setting VIN = 0, one can write VIP VAP VAP VON RG RF RG V AN V AP VOP RF RG (7) where vn is defined as the input-referred differential voltage noise. This equation is the same as that of traditional op amps. The contribution from the input current noise of each input is computed as Vo_n2 = in (RF) (8) where in is defined as the input noise current of one input. Each input needs to be treated separately because the two input currents are statistically independent processes. VOP VON VO, dm RF V RG i (13) Feedback Factor Notation When working with differential amplifiers, it is convenient to introduce the feedback factor , which is defined as RG RF RG (14) This notation is consistent with conventional feedback analysis and is very useful, particularly when the two feedback loops are not matched. Input Common-Mode Voltage The linear range of the VAN and VAP terminals extends to within approximately 1 V of either supply rail. Because VAN and VAP are essentially equal to each other, they are both equal to the input common-mode voltage of the amplifier. Their range is indicated in the Specifications tables as input common-mode range. The voltage at VAN and VAP for the connection diagram in Figure 59 can be expressed as VAN VAP VACM (V VIN ) RG RF IP VOCM R R 2 R R F F G G (9) (15) where VACM is the common-mode voltage present at the amplifier input terminals. This result can be intuitively viewed as the thermal noise of each RG multiplied by the magnitude of the differential gain. Using the notation, Equation 15 can be written as follows: The contribution from each RF is computed as Vo_n4 = 4kTRF (12) An inverting configuration with the same gain magnitude can be implemented by simply applying the input signal to VIN and setting VIP = 0. For a balanced differential input, the gain from VIN, dm to VO, dm is also equal to RF/RG, where VIN, dm = VIP - VIN. The contribution from each RG is computed as R Vo_n3 4kTRG F RG Solving the above two equations and setting VIP to Vi gives the gain relationship for VO, dm/Vi. The contribution from the input voltage noise spectral density is computed as R Vo_n1 vn 1 F , or equivalently, vn/ RG (11) VACM = VOCM + (1 - )VICM (10) (16) or equivalently, VACM = VICM + (VOCM - VICM) where VICM is the common-mode voltage of the input signal, that is, VICM = VIP + VIN/2. Rev. C | Page 20 of 26 (17) Data Sheet AD8139 For proper operation, the voltages at VAN and VAP must stay within their respective linear ranges. The input impedance of a conventional inverting op amp configuration is simply RG, but it is higher in Equation 19 because a fraction of the differential output voltage appears at the summing junctions, VAN and VAP. This voltage partially bootstraps the voltage across the input resistor RG, leading to the increased input resistance. Calculating Input Impedance The input impedance of the circuit in Figure 59 depends on whether the amplifier is being driven by a single-ended or a differential signal source. For balanced differential input signals, the differential input impedance (RIN, dm) is simply RIN, dm = 2RG Input Common-Mode Swing Considerations In some single-ended-to-differential applications, when using a single-supply voltage, attention must be paid to the swing of the input common-mode voltage, VACM. (18) For a single-ended signal (for example, when VIN is grounded and the input signal drives VIP), the input impedance becomes RG RF 1 2(RG RF ) Consider the case in Figure 61, where VIN is 5 V p-p swinging about a baseline at ground, and VREF is connected to ground. (19) The circuit has a differential gain of 1.6 and = 0.38. VICM has an amplitude of 2.5 V p-p and is swinging about ground. Using the results in Equation 16, the common-mode voltage at the inputs of the AD8139, VACM, is a 1.5 V p-p signal swinging about a baseline of 0.95 V. The maximum negative excursion of VACM in this case is 0.2 V, which exceeds the lower input common-mode voltage limit. 5V 0.1F 324 +2.5V GND -2.5V 2.5V 8 VOCM 2 1 VREF - VACM WITH VREF = 0 DVDD AVDD IN- AD8139 6 200 2.7nF 5 + 0.1F 15 3 200 VIN 20 0.1F AD7674 4 324 15 2.7nF IN+ DGND AGND REFGND REF REFBUFIN PDBUF 47F +1.7V +0.95V +0.2V 0.1F Figure 61. AD8139 Driving AD7674, 18-Bit, 800 kSPS ADC Rev. C | Page 21 of 26 ADR431 2.5V REFERENCE 04679-052 RIN AD8139 Data Sheet One way to avoid the input common-mode swing limitation is to bias VIN and VREF at midsupply. In this case, VIN is 5 V p-p swinging about a baseline at 2.5 V, and VREF is connected to a low-Z 2.5 V source. VICM now has an amplitude of 2.5 V p-p and is swinging about 2.5 V. Using the results in Equation 17, VACM is calculated to be equal to VICM because VOCM = VICM. Therefore, VACM swings from 1.25 V to 3.75 V, which is well within the input common-mode voltage limits of the AD8139. Another benefit seen in this example is that because VOCM = VACM = VICM no wasted common-mode current flows. Figure 62 illustrates how to provide the low-Z bias voltage. For situations that do not require a precise reference, a simple voltage divider suffices to develop the input voltage to the buffer. VIN 0V TO 5V 324 3 200 8 VOCM 2 1 10F - , or equivalently as VIO/ R RG Vo _ e2 I IO F RG RG RF R R G F I IO RF The third error voltage is calculated as TO AD7674 REFBUFIN Vo_e3 = enr x (VICM - VOCM) + AD8031 (22) where IIO is defined as the offset between the two input bias currents. 324 0.1F (21) The second error is calculated as 4 5V ADR431 2.5V REFERENCE 04679-053 Figure 62. Low-Z 2.5 V Buffer The total differential offset error is the sum of these three error sources. Other Impact of Mismatches in the Feedback Networks Another way to avoid the input common-mode swing limitation is to use dual power supplies on the AD8139. In this case, the biasing circuitry is not required. Bandwidth vs. Closed-Loop Gain The 3 dB bandwidth of the AD8139 decreases proportionally to increasing closed-loop gain in the same way as a traditional voltage feedback operational amplifier. For closed-loop gains greater than 4, the bandwidth obtained for a specific gain can be estimated as RG (300 MHz) RG RF (23) where enr is the fractional mismatch between the two feedback resistors. - f 3 dB,VOUT , dm R RG Vo _ e1 VIO F RG AD8139 200 + The first output error component is calculated as 5 + 6 0.1F Primary differential output offset errors in the AD8139 are due to three major components: the input offset voltage, the offset between the VAN and VAP input currents interacting with the feedback network resistances, and the offset produced by the dc voltage difference between the input and output common-mode voltages in conjunction with matching errors in the feedback network. where VIO is the input offset voltage. The input offset voltage of the AD8139 is laser trimmed and guaranteed to be less than 500 V. 5V 0.1F Estimating DC Errors (20) or equivalently, (300 MHz). The internal common-mode feedback network still forces the output voltages to remain balanced, even when the RF/RG feedback networks are mismatched. However, the mismatch causes a gain error proportional to the feedback network mismatch. Ratio-matching errors in the external resistors degrade the ability to reject common-mode signals at the VAN and VIN input terminals, much the same as with a four-resistor difference amplifier made from a conventional op amp. Ratio-matching errors also produce a differential output component that is equal to the VOCM input voltage times the difference between the feedback factors (s). In most applications using 1% resistors, this component amounts to a differential dc offset at the output that is small enough to be ignored. This estimate assumes a minimum 90 phase margin for the amplifier loop, which is a condition approached for gains greater than 4. Lower gains show more bandwidth than predicted by the equation due to the peaking produced by the lower phase margin. Rev. C | Page 22 of 26 Data Sheet AD8139 Driving a Capacitive Load 5 RS = 30.1 4 CL = 15pF 3 2 1 0 -1 -2 RS = 60.4 -3 CL = 15pF -4 -5 -6 -7 RS = 60.4 -8 CL = 5pF -9 VS = 5V -10 V = 0.1V p-p -11 GO,= dm 1 (RF = RG = 200) -12 R L, dm = 1k -13 10M 100M Figure 64 shows the AD8139 in a unity-gain configuration driving the AD6645, which is a 14-bit, high speed ADC, and with the following discussion, provides a good example of how to provide a proper termination in a 50 environment. RS = 30.1 CL = 5pF RS = 0 CL, dm = 0pF FREQUENCY (Hz) 1G 04679-076 CLOSED LOOP GAIN (dB) A purely capacitive load reacts with the bondwire and pin inductance of the AD8139, resulting in high frequency ringing in the transient response and loss of phase margin. One way to minimize this effect is to place a small resistor in series with each output to buffer the load capacitance (see Figure 58 and Figure 63). The resistor and load capacitance form a first-order, low-pass filter; therefore, the resistor value should be as small as possible. In some cases, the ADCs require small series resistors to be added on their inputs. The input resistance presented by the AD8139 input circuitry is seen in parallel with the termination resistor, and its loading effect must be taken into account. The Thevenin equivalent circuit of the driver, its source resistance, and the termination resistance must all be included in the calculation as well. An exact solution to the problem requires the solution of several simultaneous algebraic equations and is beyond the scope of this data sheet. An iterative solution is also possible and simpler, especially considering the fact that standard 1% resistor values are generally used. Figure 63. Frequency Response for Various Capacitive Loads and Series Resistances The Typical Performance Characteristics that illustrate transient response vs. the capacitive load were generated using series resistors in each output and a differential capacitive load. Layout Considerations Standard high speed PCB layout practices should be adhered to when designing with the AD8139. A solid ground plane is recommended, and good wideband power supply decoupling networks should be placed as close as possible to the supply pins. To minimize stray capacitance at the summing nodes, the copper in all layers under all traces and pads that connect to the summing nodes should be removed. Small amounts of stray summing-node capacitance cause peaking in the frequency response, and large amounts can cause instability. If some stray summing-node capacitance is unavoidable, its effects can be compensated for by placing small capacitors across the feedback resistors. Terminating a Single-Ended Input Controlled impedance interconnections are used in most high speed signal applications, and they require at least one line termination. In analog applications, a matched resistive termination is generally placed at the load end of the line. This section deals with how to properly terminate a single-ended input to the AD8139. The termination resistor, RT, in parallel with the 268 input resistance of the AD8139 circuit (calculated using Equation 19), yields an overall input resistance of 50 that is seen by the signal source. To have matched feedback loops, each loop must have the same RG if they have the same RF. In the input (upper) loop, RG is equal to the 200 resistor in series with the (+) input plus the parallel combination of RT and the source resistance of 50 . In the upper loop, RG is therefore equal to 228 . The closest standard 1% value to 228 is 226 and is used for RG in the lower loop. Greater accuracy could be achieved by using two resistors in series to obtain a resistance closer to 228 . Things get more complicated when it comes to determining the feedback resistor values. The amplitude of the signal source generator VS is two times the amplitude of its output signal when terminated in 50 . Therefore, a 2 V p-p terminated amplitude is produced by a 4 V p-p amplitude from VS. The Thevenin equivalent circuit of the signal source and RT must be used when calculating the closed-loop gain, because in the upper loop, RG is split between the 200 resistor and the Thevenin resistance looking back toward the source. The Thevenin voltage of the signal source is greater than the signal source output voltage when terminated in 50 because RT must always be greater than 50 . In this case, RT is 61.9 and the Thevenin voltage and resistance are 2.2 V p-p and 28 , respectively. Now the upper input branch can be viewed as a 2.2 V p-p source in series with 228 . Because this is a unity-gain application, a 2 V p-p differential output is required, and RF must therefore be 228 x (2/2.2) = 206 . The closest standard value to this is 205 . When generating the Typical Performance Characteristics data, the measurements were calibrated to take the effects of the terminations on the closed-loop gain into account. Rev. C | Page 23 of 26 AD8139 Data Sheet Exposed Paddle (EP) Because this is a single-ended-to-differential application on a single supply, the input common-mode voltage swing must be checked. From Figure 64, = 0.52, VOCM = 2.4 V, and VICM is 1.1 V p-p swinging about ground. Using Equation 16, VACM is calculated to be 0.53 V p-p swinging about a baseline of 1.25 V, and the minimum negative excursion is approximately 1 V. The 8-lead SOIC and the 8-lead LFCSP have an exposed paddle on the bottom of the package. To achieve the specified thermal resistance, the exposed paddle must be soldered to one of the PCB planes. The exposed paddle mounting pad should contain several thermal vias within it to ensure a low thermal path to the plane. 5V 3.3V 0.01F 0.01F 0.01F 205 VS SIGNAL SOURCE 2V p-p RT 61.9 200 8 VOCM 2 1 226 AIN AVCC DVCC 5 + AD8139 - 6 AD6645 4 AIN 205 25 GND C1 C2 0.1F 2.4V Figure 64. AD8139 Driving AD6645, 14-Bit, 80 MSPS/105 MSPS ADC Rev. C | Page 24 of 26 VREF 0.1F 04679-054 50 25 3 Data Sheet AD8139 OUTLINE DIMENSIONS 5.00 4.90 4.80 2.29 0.356 5 8 6.20 6.00 5.80 4.00 3.90 3.80 2.29 0.457 4 1 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. BOTTOM VIEW 1.27 BSC 3.81 REF TOP VIEW SEATING PLANE 0.50 0.25 0.10 MAX 0.05 NOM COPLANARITY 0.10 0.51 0.31 8 0 45 0.25 0.17 1.04 REF 1.27 0.40 06-02-2011-B 1.65 1.25 1.75 1.35 COMPLIANT TO JEDEC STANDARDS MS-012-A A Figure 65. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] Narrow Body (RD-8-1) Dimensions shown in millimeters 1.84 1.74 1.64 3.10 3.00 SQ 2.90 1.55 1.45 1.35 EXPOSED PAD 0.50 0.40 0.30 0.80 0.75 0.70 0.30 0.25 0.20 1 4 BOTTOM VIEW TOP VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-229-WEED Figure 66. 8-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm x 3 mm Body and 0.75 mm Package Height (CP-8-13) Dimensions shown in millimeters Rev. C | Page 25 of 26 PIN 1 INDICATOR (R 0.15) 12-07-2010-A PIN 1 INDEX AREA SEATING PLANE 0.50 BSC 8 5 AD8139 Data Sheet ORDERING GUIDE Model 1 AD8139ARDZ AD8139ARDZ-REEL AD8139ARDZ-REEL7 AD8139ACPZ-R2 AD8139ACPZ-REEL AD8139ACPZ-REEL7 AD8139ACP-EBZ 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 8-Lead Small Outline Package with Exposed Pad [SOIC_N_EP] 8-Lead Small Outline Package with Exposed Pad [SOIC_N_EP] 8-Lead Small Outline Package with Exposed Pad [SOIC_N_EP] 8-Lead Lead Frame Chip Scale Package [LFCSP] 8-Lead Lead Frame Chip Scale Package [LFCSP] 8-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board Z = RoHS Compliant Part, # denotes RoHS product may be top or bottom marked. (c)2004-2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04679-0-6/16(C) Rev. C | Page 26 of 26 Package Option RD-8-1 RD-8-1 RD-8-1 CP-8-13 CP-8-13 CP-8-13 Branding HEB# HEB# HEB# Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: AD8139ARD-EBZ