2013-2018 Microchip Technology Inc. DS20005193E-page 1
Features
• Single Voltage Read and Write Operations
- 1.65-1.95V
• Serial Interface Architecture
- SPI Compatible: Mode 0 and Mode 3
• High Speed Clock Frequency
- 40MHz
• Dual Input/Output Support
- Fast-Read Dual-Output Instruction (3BH)
- Fast-Read Dual I/O Instruction (BBH)
• Superior Reliability
- Endurance: 100,000 Cycles
- Greater than 20 years Data Retention
• Ultra-Low Power Consumption:
- Active Read Current: 4 mA (typical)
- Standby Current: 7 µA (typical)
- Power-down Mode Standby Current: 2 µA (typical)
• Flexible Erase Capability
- Uniform 4 KByte sectors
- Uniform 64 KByte overlay blocks
• Page Program Mode
- 256 Bytes/Page
• Fast Erase and Page-Program:
- Chip-Erase Time: 400 ms (typical)
- Sector-Erase Time: 40 ms (typical)
- Block-Erase Time: 80 ms (typical)
- Page-Program Time: 0.8 ms/ 256 bytes (typical)
•End-of-Write Detection
- Software polling the BUSY bit in Status Register
• Hold Pin (HOLD#)
- Suspend a serial sequence without deselecting the
device
• Write Protection (WP#)
- Enables/Disables the Lock-Down function of the
status register
• Software Write Protection
- Write protection through Block-Protection bits in
status register
• Temperature Range
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
• Packages Available
- 8-lead SOIC (150 mils)
- 8-contact USON (2mm x 3mm)
• All devices are RoHS compliant
Product Description
SST25WF040B is a member of the Serial Flash 25
Series family and feature a four-wire, SPI-compatible
interface that allows for a low pin-count package which
occupies less board space and ultimately lowers total
system costs. SPI serial flash memory is manufactured
with proprietary, high-performance CMOS SuperFlash
technology. The split-gate cell design and thick-oxide
tunneling injector attain better reliability and manufac-
turability compared with alternate approaches.
This Serial Flash significantly improve performance
and reliability, while lowering power consumption. The
device writes (Program or Erase) with a single power
supply of 1.65-1.95V. The total energy consumed is a
function of the applied voltage, current, and time of
application. Since for any given voltage range, the
SuperFlash technology uses less current to program
and has a shorter erase time, the total energy con-
sumed during any Erase or Program operation is less
than alternative flash memory technologies.
SST25WF040B is offered in 8-lead SOIC and 8-contact
USON packages. See Figure 2-1 for the pin assign-
ments.
SST25WF040B
4 Mbit 1.8V SPI Serial Flash
2013-2018 Microchip Technology Inc. DS20005193E-page 2
SST25WF040B
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2013-2018 Microchip Technology Inc. DS20005193E-page 3
SST25WF040B
1.0 FUNCTIONAL BLOCK DIAGRAM
FIGURE 1-1: FUNCTIONAL BLOCK DIAGRAM
20005193 F01.0
I/O Buffers
and
Data Latches
SuperFlash
Memory
X - Decoder
Control Logic
Address
Buffers
and
Latches
CE#
Y - Decoder
SCK SI/
SIO0SO/
SIO1WP# HOLD#
Serial Interface
2013-2018 Microchip Technology Inc. DS20005193E-page 4
SST25WF040B
2.0 PIN DESCRIPTION
FIGURE 2-1: PIN ASSIGNMENTS
TABLE 2-1: PIN DESCRIPTION
Symbol Pin Name Functions
SCK Serial Clock To provide the input/output timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
SI Serial Data Input To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO Serial Data Output To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
SIO[0:1] Serial Data Input/
Output for Dual I/O
Mode
To transfer commands, addresses, or data serially into the device, or data out of
the device. Inputs are latched on the rising edge of the serial clock. Data is
shifted out on the falling edge of the serial clock. These pins are used in Dual
I/O mode
CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low
for the duration of any command sequence. The device is deselected and
placed in Standby mode when CE# is high.
WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status reg-
ister.
HOLD# Hold To temporarily stop serial communication with SPI Flash memory while device
is selected.
VDD Power Supply To provide power supply voltage: 1.65-1.95V for SST25WF040B
VSS Ground
8-Lead SOIC 8-Contact USON
1
2
3
4
8
7
6
5
CE#
S
O/SIO1
WP#
VSS
VDD
HOLD#
SCK
SI/SIO0
20005193 08-soic-P0.0
1
2
3
4
8
7
6
5
CE#
SO/SIO1
WP#
VSS
Top View
VDD
HOLD#
SCK
SI/SIO0
20005193 08-uson Q3A P1.0
2013-2018 Microchip Technology Inc. DS20005193E-page 5
SST25WF040B
3.0 MEMORY ORGANIZATION
The SST25WF040B SuperFlash memory arrays are
organized in 128 uniform 4 KByte sectors, with 8
64 KByte overlay erasable blocks.
FIGURE 3-1: MEMORY MAP
4.0 DEVICE OPERATION
SST25WF040B is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI
bus consist of four control lines; Chip Enable (CE#) is
used to select the device, and data is accessed through
the Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK).
The SST25WF040B supports both Mode 0 (0,0) and
Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 4-1, is the
state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The
SCK signal is low for Mode 0 and SCK signal is high for
Mode 3. For both modes, the Serial Data In (SI) is sam-
pled at the rising edge of the SCK clock signal and the
Serial Data Output (SO) is driven after the falling edge
of the SCK clock signal.
FIGURE 4-1: SPI PROTOCOL
20005193 F51.0.eps
Top of Memory Block
00FFFFH
00F000H
000FFFH
000000H
001FFFH
001000H
Bottom of Memory Block
. . .
01FFFFH
01F000H
01FFFFH
010000H
. . . . . .
07FFFFH
07F000H
070FFFH
070000H
. . .
Number of Sectors
15
0
1
. . .
31
16
. . . . . .
127
112
. . .
1
0
. . .
7
Number of 64 KByte
Blocks
25000193 F03
.0
MODE 3
S
CK
SI
SO
C
E#
MODE 3
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MODE 0MODE 0
HIGH IMPEDANCE
MSB
MSB
2013-2018 Microchip Technology Inc. DS20005193E-page 6
SST25WF040B
4.0.1 HOLD
In the hold mode, serial sequences underway with the
SPI Flash memory are paused without resetting the
clocking sequence. To activate the HOLD# mode, CE#
must be in active low state. The HOLD# mode begins
when the SCK active low state coincides with the falling
edge of the HOLD# signal. The Hold mode ends when
the rising edge of the HOLD# signal coincides with the
SCK active low state. HOLD# must not rise or fall when
SCK logic level is high. See Figure 4-2 for Hold Condi-
tion waveform.
Once the device enters Hold mode, SO will be in high-
impedance state while SI and SCK can be VIL or VIH.
If CE# is driven active high during a Hold condition, the
device returns to standby mode. The device can then
be re-initiated with the command sequences listed in
Table 5-1. As long as HOLD# signal is low, the memory
remains in the Hold condition. To resume communica-
tion with the device, HOLD# must be driven active high,
and CE# must be driven active low. See Figure 4-2 for
Hold timing.
FIGURE 4-2: HOLD CONDITION WAVEFORM
4.1 Write Protection
SST25WF040B provides software Write protection. The
Write Protect pin (WP#) enables or disables the lock-
down function of the status register. The Block-Protec-
tion bits (BP0, BP1, BP2, TB, and BPL) in the status
register provide Write protection to the memory array
and the status register. See Table 4-3 for the Block-Pro-
tection description.
4.1.1 WRITE PROTECT PIN (WP#)
The Write Protect (WP#) pin enables the lock-down
function of the BPL bit (bit 7) in the status register.
When WP# is driven low, the execution of the Write-
Status-Register (WRSR) instruction is determined by
the value of the BPL bit (see Table 4-1). When WP# is
high, the lock-down function of the BPL bit is disabled.
Active Hold Active
20005193 F05.0
SCK
HOLD#
TABLE 4-1: CONDITIONS TO EXECUTE WRITE-STATUS-REGISTER (WRSR) INSTRUCTION
WP# BPL Execute WRSR Instruction
L 1 Not Allowed
L0Allowed
HXAllowed
2013-2018 Microchip Technology Inc. DS20005193E-page 7
SST25WF040B
4.2 Status Register
The software status register provides status on
whether the flash memory array is available for any
Read or Write operation, whether the device is Write
enabled, and the state of the Memory Write protection.
During an internal Erase or Program operation, the sta-
tus register may be read only to determine the comple-
tion of an operation in progress. Table 4-2 describes
the function of each bit in the software status register.
4.2.1 BUSY (BIT 0)
The Busy bit determines whether there is an internal
Erase or Program operation in progress. A ‘1’ for the
Busy bit indicates the device is busy with an operation
in progress. A ‘0’ indicates the device is ready for the
next valid operation.
4.2.2 WRITE ENABLE LATCH (WEL–BIT 1)
The Write-Enable-Latch bit indicates the status of the
internal Write-Enable-Latch memory. If the WEL bit is
set to ‘1’, it indicates the device is Write enabled. If the
bit is set to ‘0’ (reset), it indicates the device is not Write
enabled and does not accept any Write (Program/
Erase) commands. The Write-Enable-Latch bit is auto-
matically reset under the following conditions:
• Power-up
• Write-Disable (WRDI) instruction completion
• Page-Program instruction completion
• Sector-Erase instruction completion
• 64 KByte Block-Erase instruction completion
• Chip-Erase instruction completion
• Write-Status-Register instruction completion
4.2.3 BLOCK-PROTECTION (BP0, BP1,
BP2, AND TB–BITS 2, 3, 4, AND 5)
The Block-Protection (BP0, BP1, BP2, and TB) bits
define the size of the memory area to be software pro-
tected against any memory Write (Program or Erase)
operation, see Table 4-3. The Write-Status-Register
(WRSR) instruction is used to program the BP0, BP1,
BP2, and TB bits as long as WP# is high or the Block-
Protect-Lock (BPL) bit is ‘0’. Chip-Erase can only be
executed if Block-Protection bits are all ‘0’. BP0, BP1,
and BP2 select the protected area and TB allocates the
protected area to the higher-order address area (Top
Blocks) or lower-order address area (Bottom Blocks).
TABLE 4-2: SOFTWARE STATUS REGISTER
Bit Name Function
Default at
Power-up Read/Write
0 BUSY 1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
0R
1 WEL 1 = Device is memory Write enabled
0 = Device is not memory Write enabled
0R
2 BP01
1. BP0, BP1, BP2, TB, and BPL bits are non-volatile memory bits.
Indicate current level of block write protection (See Table 4-3) 0 or 1 R/W
3 BP11Indicate current level of block write protection (See Table 4-3) 0 or 1 R/W
4 BP21Indicate current level of block write protection (See Table 4-3) 0 or 1 R/W
5TB
11 = 1/8, 1/4, or 1/2 Bottom Memory Blocks are protected (See Table 4-3)
0 = 1/8, 1/4, or 1/2 Top Memory Blocks are protected
0 or 1 R/W
6 RES Reserved for future use 0 N/A
7 BPL11 = BP0, BP1, BP2, TB, and BPL are read-only bits
0 = BP0, BP1, BP2, TB, and BPL are read/writable
0 or 1 R/W
2013-2018 Microchip Technology Inc. DS20005193E-page 8
SST25WF040B
4.2.4 BLOCK PROTECTION LOCK-DOWN
(BPL–BIT 7)
When the WP# pin is driven low (VIL), it enables the
Block-Protection-Lock-Down (BPL) bit. When BPL is
set to ‘1’, it prevents any further alteration of the BP0,
BP1, BP2, TB, and BPL bits. When the WP# pin is
driven high (VIH), the BPL bit has no effect and its value
is ‘Don’t Care’.
TABLE 4-3: SOFTWARE STATUS REGISTER BLOCK PROTECTION
Protection Level
Status Register Bit
Protected Memory AddressTB BP2 BP1 BP0
0 (Full Memory Array unprotected) X 0 0 0 None
T1 (1/8 Top Memory Block protected) 0 0 0 1 070000H-07FFFFH
T2 (1/4 Top Memory Block protected) 0 0 1 0 060000H-07FFFFH
T3 (1/2 Top Memory Block protected) 0 0 1 1 040000H-07FFFFH
B1 (1/8 Bottom Memory Block protected) 1 0 0 1 000000H-00FFFFH
B2 (1/4 Bottom Memory Block protected) 1 0 1 0 000000H-01FFFFH
B3 (1/2 Bottom Memory Block protected) 1 0 1 1 000000H-03FFFFH
4 (Full Memory Block protected) X 1 X X 000000H-0FFFFFH
2013-2018 Microchip Technology Inc. DS20005193E-page 9
SST25WF040B
5.0 INSTRUCTIONS
Instructions are used to read, write (Erase and Pro-
gram), and configure the SST25WF040B devices. The
instruction bus cycles are 8 bits each for commands
(Op Code), data, and addresses. The Write-Enable
(WREN) instruction must be executed prior to Sector-
Erase, Block-Erase, Page-Program, Write-Status-Reg-
ister, or Chip-Erase instructions. The complete instruc-
tions are provided in Table 5-1. All instructions are
synchronized off a high-to-low transition of CE#. Inputs
will be accepted on the rising edge of SCK starting with
the most significant bit. CE# must be driven low before
an instruction is entered and must be driven high after
the last bit of the instruction has been shifted in (except
for Read, Read-ID, and Read-Status-Register instruc-
tions). Any low-to-high transition on CE#, before receiv-
ing the last bit of an instruction bus cycle, will terminate
the instruction in progress and return the device to
standby mode. Instruction commands (Op Code),
addresses, and data are all input from the most signifi-
cant bit (MSB) first.
TABLE 5-1: DEVICE OPERATION INSTRUCTIONS
Instruction Description Op Code Cycle1
1. One bus cycle is eight clock periods.
Address
Cycle(s)2
2. Address bits above the most significant bit of each density can be VIL or VIH.
Dummy
Cycle(s)
Data
Cycle(s)
Maximum
Frequency
Read Read Memory 0000 0011b (03H) 3 0 1 to 30 MHz
High-Speed Read Read Memory at Higher
Speed
0000 1011b (0BH) 3 1 1 to
40 MHz
Fast-Read Dual-
Output
Read Memory with Dual Out-
put
0011 1011b (3BH) 3 13
3. One bus cycle is four clock periods in Dual Operation
1 to 3
Fast-Read Dual I/O Read Memory with Dual
Address Input and Data Output
1011 1011b (BBH) 33131 to 3
4 KByte Sector-
Erase4
4. 4 KByte Sector-Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH.
Erase 4 KByte of memory array 0010 0000b (20H)
1101 0111b (D7H)
300
64 KByte Block-
Erase5
5. 64 KByte Block-Erase addresses: use AMS-A16, remaining addresses are don’t care but must be set either at VIL or VIH.
Erase 64 KByte block
of memory array
1101 1000b (D8H) 3 0 0
Chip-Erase Erase Full Memory Array 0110 0000b (60H)
or
1100 0111b (C7H)
000
Page-Program To program up to 256 Bytes 0000 0010b (02H) 3 0 1 to 256
RDSR6
6. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
Read-Status-Register 0000 0101b (05H) 0 0 1 to
WRSR Write-Status-Register 0000 0001b (01H) 0 0 1
WREN Write-Enable 0000 0110b (06H) 0 0 0
WRDI Write-Disable 0000 0100b (04H) 0 0 0
RDID7, 8
7. Device ID is read after three dummy address bytes. The Device ID output stream is continuous until terminated by a low-to-
high transition on CE#.
8. The instructions Release from Deep Power down and Read-ID are similar instructions (ABH). Executing Read-ID requires
the ABH instruction, followed by 24 dummy address bits to retrieve the Device ID. Release from Deep Power-Down only
requires the instruction ABH.
Read-ID 1010 1011b (ABH) 3 0 1 to
JEDEC-ID JEDEC ID Read 1001 1111b (9FH) 0 0 4 to
DPD Deep Power-Down Mode 1011 1001b (B9H) 0 0 0
RDPD8Release from Deep Power-
Down or Read ID
1010 1011b (ABH) 0 0 0
2013-2018 Microchip Technology Inc. DS20005193E-page 10
SST25WF040B
5.1 Read (30 MHz)
The Read instruction, 03H, supports up to 30 MHz
Read. The device outputs a data stream starting from
the specified address location. The data stream is con-
tinuous through all addresses until terminated by a low-
to-high transition on CE#. The internal address pointer
automatically increments until the highest memory
address is reached. Once the highest memory address
is reached, the address pointer automatically incre-
ments to the beginning (wrap-around) of the address
space. For example, for 4 Mbit density, once the data
from the address location 7FFFFH is read, the next out-
put is from address location 000000H. The Read
instruction is initiated by executing an 8-bit command,
03H, followed by address bits A23-A0. CE# must
remain active low for the duration of the Read cycle.
See Figure 5-1 for the Read sequence.
FIGURE 5-1: READ SEQUENCE
5.2 High-Speed-Read (40 MHz)
The High-Speed-Read instruction supporting up to 40
MHz Read is initiated by executing an 8-bit command,
0BH, followed by address bits [A23-A0] and a dummy
byte. CE# must remain active low for the duration of the
High-Speed-Read cycle. See Figure 5-2 for the High-
Speed-Read sequence.
Following a dummy cycle, the High-Speed-Read
instruction outputs the data starting from the specified
address location. The data output stream is continuous
through all addresses until terminated by a low-to-high
transition on CE#. The internal address pointer will
automatically increment until the highest memory
address is reached. Once the highest memory address
is reached, the address pointer will automatically incre-
ment to the beginning (wrap-around) of the address
space. For example, for 4 Mbit density, once the data
from address location 7FFFFH is read, the next output
will be from address location 000000H.
FIGURE 5-2: HIGH-SPEED-READ SEQUENCE
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD.
03
HIGH IMPEDANCE
15 16 23 24 31 32 39 40 7047 48 55 56 63 64
N+2 N+3 N+4N N+1
D
OUT
MSB MSB
MSB
MODE 0
MODE 3
D
OUT
D
OUT
D
OUT
D
OUT
20005193 F07.0
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD.0B
HIGH IMPEDANCE
15 16 23 24 31 32 39 40 47 48 55 56 63 64
N+2 N+3 N+4
NN+1
X
MSB
MODE 0
MODE 3
DOUT DOUT DOUT DOUT
80
71 72
DOUT
MSB
2013-2018 Microchip Technology Inc. DS20005193E-page 11
SST25WF040B
5.3 Fast-Read Dual Output (40 MHz)
The Fast-Read Dual-Output (3BH) instruction outputs
data up to 40 MHz from the SIO0 and SIO1 pins. To ini-
tiate the instruction, execute an 8-bit command (3BH)
followed by address bits A23-A0 and a dummy byte on
SI/SIO0. Following a dummy cycle, the Fast-Read
Dual-Output instruction outputs the data starting from
the specified address location on the SIO1 and SIO0
lines. SIO1 outputs, per clock sequence, odd data bits
D7, D5, D3, and D1; and SIO0 outputs even data bits
D6, D4, D2, and D0. CE# must remain active low for the
duration of the Fast-Read Dual-Output instruction
cycle. See Figure 5-3 for the Fast-Read Dual-Output
sequence.
The data output stream is continuous through all
addresses until terminated by a low-to-high transition
on CE#. The internal address pointer will automatically
increment until the highest memory address is
reached. Once the highest memory address is
reached, the address pointer automatically increments
to the beginning (wraparound) of the address space.
For 4 Mbit density, once the data from address location
7FFFFH has been read the next output will be from
address location 000000H.
FIGURE 5-3: FAST-READ DUAL OUTPUT SEQUENCE
2013-2018 Microchip Technology Inc. DS20005193E-page 12
SST25WF040B
5.4 Fast-Read Dual I/O (40 MHz)
The Fast-Read Dual I/O (BBH) instruction reduces the
total number of input clock cycles, which results in
faster data access. The device is first selected by driv-
ing Chip Enable CE# low. Fast-Read Dual I/O is initi-
ated by executing an 8-bit command (BBH) on SI/SIO0,
thereafter, the device accepts address bits A23-A0 and
a dummy byte on SI/SIO0 and SO/SIO1. It offers the
capability to input address bits A23-A0 at a rate of two
bits per clock. Odd address bits A23 through A1 are
input on SIO1 and even address bits A22 through A0
are input on SIO0, alternately For example, the most
significant bit is input first followed by A23/22, A21/A20,
and so on. Each bit is latched at the same rising edge
of the Serial Clock (SCK). The input data during the
dummy clocks is “don’t care”. However, the SIO0 and
SIO1 pin must be in high-impedance prior to the falling
edge of the first data output clock.
Following a dummy cycle, the Fast-Read Dual I/O
instruction outputs the data starting from the specified
address location on the SIO1 and SIO0 lines. SIO1 out-
puts, per clock sequence, odd data bits D7, D5, D3,
and D1; and SIO0 outputs even data bits D6, D4, D2,
and D0 per clock edge. CE# must remain active low for
the duration of the Fast-Read Dual I/O instruction
cycle. The data output stream is continuous through all
addresses until terminated by a low-to-high transition
on CE#.
The internal address pointer will automatically incre-
ment until the highest memory address is reached.
Once the highest memory address is reached, the
address pointer automatically increments to the begin-
ning (wraparound) of the address space. For example,
once the data from address location 7FFFFH is read,
the next output is from address location 000000H. See
Figure 5-4 for the Fast-Read Dual I/O sequence.
FIGURE 5-4: FAST-READ DUAL I/O SEQUENCE
20005193 F53.0
CE#
SIO1
SIO0
SCK
01234567891011121314
MODE 3
MODE 0
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
642064206420
75317531 7531
MSB
6420642064206420
75317531 7531 7531
MSB MSB MSB
A23-16 A15-8 A7-0
6
7
39
BB
DOUT DOUT DOUT DOUT
N N+1 N+2 N+3
IO, Switches from Input to Output
X
X
Dummy
Cycle
2013-2018 Microchip Technology Inc. DS20005193E-page 13
SST25WF040B
5.5 Page-Program
The Page-Program instruction programs up to 256
Bytes of data in the memory. The data for the selected
page address must be in the erased state (FFH) before
initiating the Page-Program operation. A Page-Pro-
gram applied to a protected memory area will be
ignored. Prior to the program operation, execute the
WREN instruction.
To execute a Page-Program operation, the host drives
CE# low, then sends the Page-Program command
cycle (02H), three address cycles, followed by the data
to be programmed, and then drives CE# high. The pro-
grammed data must be between 1 to 256 Bytes and in
whole byte increments; sending less than a full byte will
cause the partial byte to be ignored. Poll the BUSY bit
in the Status register, or wait TPP, for the completion of
the internal, self-timed, Page-Program operation. See
Figure 5-5 for the Page-Program sequence and Figure
6-8 for the Page-Program flow chart.
When executing Page-Program, the memory range for
the SST25WF040B is divided into 256-Byte page
boundaries. The device handles the shifting of more
than 256 Bytes of data by maintaining the last 256
Bytes as the correct data to be programmed. If the tar-
get address for the Page-Program instruction is not the
beginning of the page boundary (A[7:0] are not all
zero), and the number of bytes of data input exceeds or
overlaps the end of the address of the page boundary,
the excess data inputs wrap around and will be pro-
grammed at the start of that target page.
FIGURE 5-5: PAGE-PROGRAM SEQUENCE
20005193 F60.1
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD. Data Byte 0
02
HIGH IMPEDANCE
15 16 23 24 31 32 39
MODE 0
MODE 3
MSBMSB
MSB LSB
CE#(cont’)
SO(cont’)
SI(cont’)
SCK(cont’)
40 41 42 43 44 45 46 47 48
Data Byte 1
HIGH IMPEDANCE
MSBMSB
MSB LSB
50 51 52 53 54 55
2072
49
Data Byte 2
2073
2074
2075
2076
2077
2078
2079
Data Byte 255
LSBLSB
LSB LSB
2013-2018 Microchip Technology Inc. DS20005193E-page 14
SST25WF040B
5.6 Sector-Erase
The Sector-Erase instruction clears all bits in the
selected 4 KByte sector to FFH. A Sector-Erase
instruction applied to a protected memory area will be
ignored. Prior to any Write operation, the Write-Enable
(WREN) instruction must be executed. CE# must
remain active low for the duration of any command
sequence. The Sector-Erase instruction is initiated by
executing an 8-bit command, 20H or D7H, followed by
address bits [A23-A0]. Address bits [AMS-A12]
(AMS = Most Significant address) are used to deter-
mine the sector address (SAX), remaining address bits
can be VIL or VIH. CE# must be driven high before the
instruction is executed. Poll the BUSY bit in the Soft-
ware Status register, or wait TSE, for the completion of
the internal self-timed Sector-Erase cycle. See Figure
5-6 for the Sector-Erase sequence and Figure 6-9 for
the flow chart.
FIGURE 5-6: SECTOR-ERASE SEQUENCE
5.7 64-KByte Block-Erase
The 64-KByte Block-Erase instruction clears all bits in
the selected 64 KByte block to FFH. Applying this
instruction to a protected memory area results in the
instruction being ignored. Prior to any Write operation, the
Write-Enable (WREN) instruction must be executed. CE#
must remain active low for the duration of any com-
mand sequence.
Initiate the 64-Byte Block-Erase instruction by execut-
ing an 8-bit command, D8H, followed by address bits
[A23-A0]. Address bits [AMS-A16] (AMS = Most Signifi-
cant Address) determine the block address (BAX),
remaining address bits can be VIL or VIH. CE# must be
driven high before executing the instruction. Poll the Busy bit
in the software status register or wait TBE for the com-
pletion of the internal self-timed Block-Erase cycle. See
Figure 5-7 for the 64-KByte Block-Erase sequences
and Figure 6-9 for the flow chart.
FIGURE 5-7: 64-KBYTE BLOCK-ERASE SEQUENCE
C
E#
SO
SI
S
CK
ADD.
012345678
ADD. ADD.
20 or D7
HIGH IMPEDANCE
15 16 23 24 31
MODE 0
MODE 3
20005193 F13.
0
MSBMSB
CE#
SO
SI
SCK
ADDR
012345678
ADDR ADDR
D8
HIGH IMPEDANCE
15 16 23 24 31
MODE 0
MODE 3
20005193 F15.0
MSB MSB
2013-2018 Microchip Technology Inc. DS20005193E-page 15
SST25WF040B
5.8 Chip-Erase
The Chip-Erase instruction clears all bits in the device
to FFH. A Chip-Erase instruction is ignored if any of the
memory area is protected. Prior to any Write operation,
the Write-Enable (WREN) instruction must be executed.
CE# must remain active low for the duration of the
Chip-Erase instruction sequence. Initiate the Chip-
Erase instruction by executing an 8-bit command, 60H
or C7H. CE# must be driven high before the instruction is
executed. Poll the BUSY bit in the Software Status reg-
ister, or wait TSCE, for the completion of the internal
self-timed Chip-Erase cycle. See Figure 5-8 for the
Chip-Erase sequence and Figure 6-10 for the flow
chart.
FIGURE 5-8: CHIP-ERASE SEQUENCE
5.9 Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction, 05H,
allows reading of the status register. The status register
may be read at any time even during a Write (Program/
Erase) operation. When a Write operation is in prog-
ress, the Busy bit may be checked before sending any
new commands to assure that the new commands are
properly received by the device. CE# must be driven
low before the RDSR instruction is entered and remain
low until the status data is read. Read-Status-Register
is continuous with ongoing clock cycles until it is termi-
nated by a low to high transition of the CE#. See Figure
5-9 for the RDSR instruction sequence.
FIGURE 5-9: READ-STATUS-REGISTER (RDSR) SEQUENCE
C
E#
SO
SI
S
CK 01234567
60 or C7
HIGH IMPEDANCE
MODE 0
MODE 3
20005193 F16.0
MSB
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
20005193 F17
.0
MODE 3
S
CK
SI
SO
C
E#
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
05
MODE 0
HIGH IMPEDANCE
Status
Register Out
MSB
MSB
2013-2018 Microchip Technology Inc. DS20005193E-page 16
SST25WF040B
5.10 Write-Enable (WREN)
The Write-Enable (WREN) instruction, 06H, sets the
Write-Enable-Latch bit in the Status Register to 1 allow-
ing Write operations to occur. The WREN instruction
must be executed prior to any Write (Program/Erase)
operation. The WREN instruction may also be used to
allow execution of the Write-Status-Register (WRSR)
instruction; however, the Write-Enable-Latch bit in the
Status Register will be cleared upon the rising edge
CE# of the WRSR instruction. CE# must be driven low
before entering the WREN instruction, and CE# must
be driven high before executing the WREN instruction.
See Figure 5-10 for the WREN instruction sequence.
FIGURE 5-10: WRITE ENABLE (WREN) SEQUENCE
5.11 Write-Disable (WRDI)
The Write-Disable (WRDI) instruction, 04H, resets the
Write-Enable-Latch bit to ‘0’, thus preventing any new
Write operations. CE# must be driven low before enter-
ing the WRDI instruction, and CE# must be driven high
before executing the WRDI instruction. See Figure 5-11
for the WRDI instruction sequence.
FIGURE 5-11: WRITE DISABLE (WRDI) SEQUENCE
CE#
SO
SI
SCK 01234567
06
HIGH IMPEDANCE
MODE 0
MODE 3
20005193 F18.0
MSB
C
E#
SO
SI
S
CK 01234567
04
HIGH IMPEDANCE
MODE 0
MODE 3
20005193 F19
.0
MSB
2013-2018 Microchip Technology Inc. DS20005193E-page 17
SST25WF040B
5.12 Write-Status-Register (WRSR)
The Write-Status-Register instruction writes new val-
ues to the BP0, BP1, BP2, TB, and BPL bits of the sta-
tus register. CE# must be driven low before the
command sequence of the WRSR instruction is
entered and driven high before the WRSR instruction is
executed. Poll the BUSY bit in the Software Status reg-
ister, or wait TWRSR, for the completion of the internal
self-timed Write-Status-Register cycle. See Figure 5-12
for WREN and WRSR instruction sequences and Fig-
ure 6-11 for the WRSR flow chart.
Executing the Write-Status-Register instruction will be
ignored when WP# is low and BPL bit is set to ‘1’. When
the WP# is low, the BPL bit can only be set from ‘0’ to
‘1’ to lock-down the status register, but cannot be reset
from ‘1’ to ‘0’. When WP# is high, the lock-down func-
tion of the BPL bit is disabled and the BPL, BP0, BP1,
BP2, and TB bits in the status register can all be
changed. As long as BPL bit is set to ‘0’ or WP# pin is
driven high (VIH) prior to the low-to-high transition of the
CE# pin at the end of the WRSR instruction, the bits in
the status register can all be altered by the WRSR
instruction. In this case, a single WRSR instruction can
set the BPL bit to ‘1’ to lock down the status register as
well as altering the BP0, BP1, BP2, and TB bits at the
same time. See Table 4-1 for a summary description of
WP# and BPL functions.
FIGURE 5-12: WRITE-ENABLE (WREN) AND WRITE-STATUS-REGISTER (WRSR) SEQUENCE
20005193 F20.0
MODE 3
HIGH IMPEDANCE
MODE 0
STATUS
REGISTER IN
76543210
MSBMSBMSB 01
MODE 3
SCK
SI
SO
CE#
MODE 0
06
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
2013-2018 Microchip Technology Inc. DS20005193E-page 18
SST25WF040B
5.13 Power-Down
The Deep Power-Down (DPD) instruction puts the
device in the lowest power consumption mode – the
Deep Power-Down mode. This instruction is ignored if
the device is busy with an internal write operation.
While the device is in DPD mode, all instructions are
ignored except for the Release Deep Power-Down
instruction or Read ID.
To initiate deep power-down, input the Deep Power-
Down instruction (B9H) while driving CE# low. CE#
must be driven high before executing the DPD instruc-
tion. After driving CE# high, it requires a delay of TDPD
before the standby current ISB is reduced to the deep
power-down current IDPD. See Figure 5-13 for the DPD
instruction sequence.
Exit the power-down state using the Release from
Deep Power-Down or Read ID instruction. CE# must
be driven low before sending the Release from Deep
Power-Down command cycle (ABH), and then driving
CE# high. The device will return to Standby mode and
be ready for the next instruction after TSBR. See Figure
5-14. for the Release from Deep Power-Down
sequence.
FIGURE 5-13: DEEP POWER-DOWN SEQUENCE
FIGURE 5-14: RELEASE FROM DEEP POWER-DOWN SEQUENCE
CE#
SO
SI
SCK
01234567
B9
HIGH IMPEDANCE
MODE 0
MODE 3
20005193 F46.1
MSB
T
DPD
CE#
SO
SI
SCK
01234567
AB
HIGH IMPEDANCE
MODE 0
MODE 3
20005193 F47.1
MSB
T
SBR
2013-2018 Microchip Technology Inc. DS20005193E-page 19
SST25WF040B
5.14 Read-ID
The Read-ID instruction identifies the device as
SST25WF040B. Use the Read-ID instruction to identify
SST25WF040B when using multiple manufacturers in
the same socket. See Table 5-2.
The device ID information is read by executing an 8-bit
command, ABH, followed by 24 dummy address bits.
Following the Read-ID instruction, and 24 address
dummy bits, the device ID continues to output with con-
tinuous clock input until terminated by a low-to-high
transition on CE#.
FIGURE 5-15: READ-ID SEQUENCE
5.15 JEDEC Read-ID
The JEDEC Read-ID instruction identifies the device ID
information of SST25WF040B. The device information
can be read by executing the 8-bit command, 9FH. Fol-
lowing the JEDEC Read-ID instruction, a 32bit device
ID information is output from the device. The Device ID
information is assigned by the manufacturer and con-
tains the Device ID 1 in the first byte, the type of mem-
ory in the second byte, the memory capacity of the
device in the third byte, and a reserved code in the
fourth byte. The 4-Byte code outputs repeatedly with
continuous clock input until a low-to-high transition on
CE#. See Figure 5-16 for the instruction sequence. The
JEDEC Read ID instruction is terminated by a low to
high transition on CE# at any time during data output.
FIGURE 5-16: JEDEC READ-ID SEQUENCE
TABLE 5-2: PRODUCT IDENTIFICATION
Address Data
SST25WF040B ID XXXXXXH 3EH
20005193 F22.1
CE#
SO
SI
SCK
XX
012345678
XX XX
AB
HIGH IMPEDANCE
15 16 23 24 31 32 39 40 47 48 55 56 63
Device ID Device ID
HIGH
IMPEDANCE
MODE 3
MODE 0
MSB MSB
MSB
Device ID Device ID
Note: The Device ID output stream is continuous until terminated by a low-to-high transition on CE#.
TABLE 5-3: JEDEC READ-ID DATA-OUT
Product
Device ID
Device ID 1
(Byte 1) Memory Type (Byte 2) Memory Capacity (Byte 3)
Reserved Code (Byte
4)
SST25WF040B 62H 16H 13H 00H
16 13 00
20005193 F23.2
CE#
SO
SI
SCK
012345678
HIGH IMPEDANCE
15 1614 28 29 30 31
62
MODE 3
MODE 0
MSBMSB
9 10111213 1718 32 34
9F
19 20 21 22 23 3324 25 26 27 37 38 3935 36
2013-2018 Microchip Technology Inc. DS20005193E-page 20
SST25WF040B
6.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maxi-
mum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these conditions or conditions greater than those defined in the operational
sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may
affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Output shorted for no more than one second. No more than one output shorted at a time.
TABLE 6-1: OPERATING RANGE
Range Ambient Temp VDD
Industrial -40°C to +85°C 1.65-1.95V
Extended -40°C to +125°C 1.65-1.95V
TABLE 6-2: AC CONDITIONS OF TEST
Input Rise/Fall Time Output Load
5ns CL = 30 pF
2013-2018 Microchip Technology Inc. DS20005193E-page 21
SST25WF040B
6.1 Power-Up Specifications
All functionalities and DC specifications are specified
for a VDD ramp rate of greater than 1V per 100 ms (0V
to 1.8V in less than 180 ms). See Table 6-3 and Figure
6-2 for more information.
FIGURE 6-1: POWER-UP TIMING DIAGRAM
TABLE 6-3: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol Parameter Minimum Units
TPU-READ1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
VDD Min to Read Operation 500 µs
TPU-WRITE1VDD Min to Write Operation 500 µs
Tim
e
V
DD
Min
V
DD
Max
V
DD
Device fully accessible
T
PU-READ
T
PU-WRITE
Chip selection is not allowed.
Commands may not be accepted or properly
interpreted by the device.
2013-2018 Microchip Technology Inc. DS20005193E-page 22
SST25WF040B
6.2 Hardware Data Protection
SST25WF040B provides a power-up reset function. To
ensure that the power reset circuit will operate cor-
rectly, the device must meet the conditions shown in
Figure 6-2 and Table 6-4. Microchip does not guaran-
tee the data in the event of an instantaneous power fail-
ure that occurs during a Write operation.
FIGURE 6-2: POWER-DOWN TIMING DIAGRAM
6.3 Software Data Protection
SST25WF040B prevents unintentional operations by
not recognizing commands under the following condi-
tions:
• After inputting a Write command, if the rising CE#
edge timing is not in a bus cycle (8 CLK units of
SCK)
• When the Page-Program data is not in 1-byte
increments
• If the Write Status Register instruction is input for
two bus cycles or more.
6.4 Decoupling Capacitor
A 0.1µF ceramic capacitor must be provided to each
device and connected between VDD and VSS to ensure
that the device will operate correctly.
TABLE 6-4: RECOMMENDED SYSTEM POWER-DOWN TIMINGS
Symbol Parameter Min Max Units
TPD Power-down time 10 ms
VBOT Power-down voltage 0.2 V
TPD
VDD Min
VDD Max
VDD
20005193 F48.0
0V
VBOT
2013-2018 Microchip Technology Inc. DS20005193E-page 23
SST25WF040B
6.5 DC Characteristics
TABLE 6-5: DC OPERATING CHARACTERISTICS
Symbol Parameter
Limits
Test ConditionsMin Typ1
1. Value characterized, not fully tested in production.
Max Units
IDDR Read Current 6 mA CE#=0.1 VDD/0.9 VDD@30
MHz, SO=open; Single I/O
IDDR2 Read Current 8 mA CE#=0.1 VDD/0.9VDD@40
MHz, SO=open
IDDR3 Read Current 10 mA CE#=0.1 VDD/0.9VDD@40
MHz, SO=open; Dual I/O;
IDDW Program and Erase Current 15 mA CE#=VDD
ISB Standby Current Industrial 750µACE#=V
DD, VIN=VDD or VSS
Extended 770µACE#=V
DD, VIN=VDD or VSS
IDPD Deep Power-Down Industrial 210µACE#=V
DD, VIN=VDD or VSS
Extended 250µACE#=V
DD, VIN=VDD or VSS
ILI Input Leakage Current 2 µA VIN=GND to VDD, VDD=VDD
Max
ILO Output Leakage Current 2 µA VOUT=GND to VDD, VDD=VDD
Max
VIL Input Low Voltage -0.3 0.3 V VDD=VDD Min
VIH Input High Voltage 0.7 VDD VDD+0.3 V VDD=VDD Max
VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min
VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min
TABLE 6-6: CAPACITANCE (TA = 25°C, F=1 MHZ, OTHER PINS OPEN)
Parameter Description Test Condition Maximum
COUT1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Output Pin Capacitance VOUT = 0V 12 pF
CIN1Input Capacitance VIN = 0V 6 pF
TABLE 6-7: RELIABILITY CHARACTERISTICS
Symbol Parameter Minimum Specification Units Test Method
NEND1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Endurance 100,000 Cycles JEDEC Standard A117
Status Register Write Cycle 100,000 Cycles JEDEC Standard A117
TDR1Data Retention 20 Years JEDEC Standard A103
ILTH1Latch Up 100 + IDD mA JEDEC Standard 78
2013-2018 Microchip Technology Inc. DS20005193E-page 24
SST25WF040B
6.6 AC Characteristics
TABLE 6-8: AC OPERATING CHARACTERISTICS
Symbol Parameter
Limits - 30 MHz Limits - 40 MHz Units
Min Max Min Max
FCLK1
1. Maximum clock frequency for Read instruction, 03H, is 30 MHz
Serial Clock Frequency 30 40 MHz
TSCKH Serial Clock High Time 14 11.5 ns
TSCKL Serial Clock Low Time 14 11.5 ns
TSCKR Serial Clock Rise Time 5 5 ns
TSCKF Serial Clock Fall Time 5 5 ns
TCES2
2. Relative to SCK
CE# Active Setup Time 10 10 ns
TCEH2CE# Active Hold Time 10 10 ns
TCHS2CE# Not Active Setup Time 10 10 ns
TCHH2CE# Not Active Hold Time 10 10 ns
TCPH CE# High Time 25 25 ns
TCHZ CE# High to High-Z Output 15 15 ns
TCLZ SCK Low to Low-Z Output 0 0 ns
TDS Data In Setup Time 5 5 ns
TDH Data In Hold Time 5 5 ns
THLS HOLD# Low Setup Time 5 5 ns
THHS HOLD# High Setup Time 5 5 ns
THLH HOLD# Low Hold Time 5 5 ns
THHH HOLD# High Hold Time 5 5 ns
THZ HOLD# Low to High-Z Output 9 9 ns
TLZ HOLD# High to Low-Z Output 12 12 ns
TOH Output Hold from SCK Change 1 1 ns
TVOutput Valid from SCK 11 11 ns
TWPS WP# Setup Time 20 20 ns
TWPH WP# Hold Time 20 20 ns
TWRSR Status Register Write Time 10 10 ms
TDPD CE# High to Deep Power-Down 5 5 µs
TSBR
Deep Power-Down (CE# High) to
Standby Mode 500 500µs
TSE Sector-Erase 40 150 40 150 ms
TBE Block-Erase 80 250 80 250 ms
TSCE Chip-Erase 0.4 4 0.4 4 s
TPP
Page-Program (256 Byte) Industrial 0.8 1 0.8 1 ms
Extended 0.81.3 0.81.3ms
n Byte
Industrial
0.15 +
n*0.65/
256
0.20 +
n*0.8/
256
0.15 +
n*0.65/
256
0.20 +
n*0.8/
256
ms
Extended
0.15 +
n*0.65/
256
0.50 +
n*0.8/
256
0.15 +
n*0.65/
256
0.20 +
n*0.8/
256
ms
2013-2018 Microchip Technology Inc. DS20005193E-page 25
SST25WF040B
FIGURE 6-3: SERIAL OUTPUT TIMING DIAGRAM
FIGURE 6-4: SERIAL INPUT TIMING DIAGRAM
FIGURE 6-5: HOLD TIMING DIAGRAM
HIGH-Z HIGH-Z
C
E#
SO
SI
S
CK
MSB LSB
TDS TDH
TCHH TCES TCEH TCHS
TSCKR TSCKF
T
CPH
20005193 F24.0
20005193 F25.0
CE#
SI
SO
SCK
MSB
TCLZ
TV
TSCKH
TCHZ
TOH
TSCKL
LSB
THZ TLZ
THHH THLS
THLH
THHS
20005193 F26.1
HOLD#
CE#
SCK
SO
SI
THLH
2013-2018 Microchip Technology Inc. DS20005193E-page 26
SST25WF040B
FIGURE 6-6: STATUS REGISTER WRITE TIMING
FIGURE 6-7: AC INPUT/OUTPUT REFERENCE WAVEFORMS
20005193 F49.0
TWPS TWPH
CE#
WP#
20005193 F28
.0
REFERENCE POINTS OUTPUTINPUT
VHT
VLT
VHT
VLT
V
IHT
VILT
AC test inputs are driven at VIHT (0.8VDD) for a logic ‘1’ and VILT (0.2VDD) for a logic ‘0’. Measurement reference
points for inputs and outputs are VHT (0.5VDD) and VLT (0.5VDD). Input rise and fall times (10% 90%) are <5
ns.
Note: VHT - VHIGH Test
VLT - VLOW Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
2013-2018 Microchip Technology Inc. DS20005193E-page 27
SST25WF040B
FIGURE 6-8: PAGE-PROGRAM FLOW CHART
20005193 F41.1
06H
Ye s
No
Start
02H
Address 1
Address 2
Address 3
Data 0
Data 255
05H
Start program on rising
edge of CE#
Busy (Bit 0) = ‘0’?
End of
programming
Write Enable
Page Program
sequence
Status Register
Read command
Check Program
Completion
•
•
•
2013-2018 Microchip Technology Inc. DS20005193E-page 28
SST25WF040B
FIGURE 6-9: SECTOR-ERASE OR 64-KBYTE BLOCK-ERASE FLOW CHART
20005193 F42.1
06H
Ye s
No
Start
20H/D7
or D8H
Address 1
Address 2
Address 3
05H
Start Erase on rising
edge of CE#
Busy (Bit 0) = ‘0’?
End of
Erase
Write Enable
Sector-Erase (20H/D7H) or
64-KByte Block-Erase (D8H)
sequence
Status Register
Read command
Check Erase
Completion
2013-2018 Microchip Technology Inc. DS20005193E-page 29
SST25WF040B
FIGURE 6-10: CHIP-ERASE FLOW CHART
20005193 F44.1
06H
Ye s
No
Start
60H/C7H
05H
Start Erase on rising
edge of CE#
Busy (Bit 0) = ‘0’?
End of
Erase
Write Enable
Chip-Erase
Status Register
Read command
Check Erase
Completion
2013-2018 Microchip Technology Inc. DS20005193E-page 30
SST25WF040B
FIGURE 6-11: WRITE-STATUS-REGISTER (WRSR) FLOW CHART
20005193 F45.1
06H
Ye s
No
Start
01H
Data
05H
Start Write on rising
edge of CE#
Busy (Bit 0) = ‘0’?
End Write-
Status-Register
Write Enable
Write-Status-
Register Sequence
Status Register
Read command
Check Write
Completion
2013-2018 Microchip Technology Inc. DS20005193E-page 31
SST25WF040B
7.0 PACKAGING DIAGRAMS
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2013-2018 Microchip Technology Inc. DS20005193E-page 32
SST25WF040B
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2013-2018 Microchip Technology Inc. DS20005193E-page 33
SST25WF040B
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2013-2018 Microchip Technology Inc. DS20005193E-page 34
SST25WF040B
B
A
0.20 C
0.20 C
D
D2
E2
E
8 X b
0.10 C A B
0.05 C
(DATUM B)
(DATUM A)
C
SEATING
PLANE
NOTE 1
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
Microchip Technology Drawing C04-203C [PRX] Sheet 1 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
NOTE 1
0.10 C A B
0.10 C A B
0.10 C
0.08 C
A1
A
e
SEE DETAIL A
12
N
12
N
2X
8-Lead Plastic Ultra Thin Small Outline No Lead Package (PRX) - 2x3 mm Body [USON]
[Also called UDFN]
2013-2018 Microchip Technology Inc. DS20005193E-page 35
SST25WF040B
Microchip Technology Drawing C04-203C [PRX] Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
L
(DATUM A)
e
e/2
L3
DETAIL A
L1
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
2.
3.
Notes:
Pin 1 visual index feature may vary, but must be located within the hatched area.
Package is saw singulated
Dimensioning and tolerancing per ASME Y14.5M
Number of Terminals
Overall Height
Terminal Width
Overall Width
Overall Length
Package Edge to Terminal Edge
Exposed Pad Width
Exposed Pad Length
Terminal Length
Pitch
Standoff
Units
Dimension Limits
A1
A
b
E
D2
E2
L3
e
L
D
N
0.50 BSC
0.35
1.50
0.10
0.40
0.20
0.45
0.00
0.25
3.00 BSC
0.45
0.20
1.60
0.55
0.02
2.00 BSC
MILLIMETERS
MIN NOM
8
1.70
0.30
0.50
0.30
0.60
0.05
MAX
0.30 0.40
Package Edge to Terminal Edge L1 — 0.10 —
8-Lead Plastic Ultra Thin Small Outline No Lead Package (PRX) - 2x3 mm Body [USON]
[Also called UDFN]
2013-2018 Microchip Technology Inc. DS20005193E-page 36
SST25WF040B
RECOMMENDED LAND PATTERN
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Y2
SILK SCREEN
Y1
C
X2
X1
Dimension Limits
Units
C
Optional Center Pad Width
Terminal Pad Spacing
Optional Center Pad Length
Terminal Pitch
Y2
X2
1.70
0.30
MILLIMETERS
0.50 BSC
MIN
E
MAX
2.80
Terminal Pad Length (X8)
Terminal Pad Width (X8)
Y1
X1
0.90
0.30
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
Microchip Technology Drawing C04-2203B [PRX]
NOM
E
G
Mininum Between Terminal Pads G 0.20
8-Lead Plastic Ultra Thin Small Outline No Lead Package (PRX) - 2x3 mm Body [USON]
[Also called UDFN]
2013-2018 Microchip Technology Inc. DS20005193E-page 37
SST25WF040B
TABLE 7-1: REVISION HISTORY
Revision •Description Date
A•Initial release of data sheet Apr 2013
B•Updated “Product Identification System” on page 39
•Changed all occurrences of TCE to TSCE.
•Updated Figure 6-7 on page 26 and Table 6-8 on page 24
Aug 2013
C•Removed “Preliminary” status from the footer. Jan 2014
D•Updated package drawings. Nov 2017
E•Added Extended temperature content Dec 2018
2013-2018 Microchip Technology Inc. DS20005193E-page 38
SST25WF040B
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following informa-
tion:
•Product Support – Data sheets and errata, appli-
cation notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of Micro-
chip sales offices, distributors and factory repre-
sentatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a spec-
ified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on “Cus-
tomer Change Notification” and follow the registration
instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor, representa-
tive or Field Application Engineer (FAE) for support
Local sales offices are also available to help custom-
ers. A listing of sales offices and locations is included in
the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
2013-2018 Microchip Technology Inc. DS20005193E-page 39
SST25WF040B
8.0 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. XXX
XX
Endurance/
Operating Device
Device: SST25WF040B = 4 Mbit,1.65-1.95V, Serial Flash Memory
Tape and
Reel Flag:
T = Tape and Reel
Operating
Frequency:
40 = 40 MHz
Temperature: I = -40°C to +85°C
E = -40°C to +125°C
Package: NP = USON (2mm x 3mm Body), 8-contact
SN = SOIC (150 mil Body), 8-lead
Valid Combinations:
SST25WF040BT-40I/NP
SST25WF040B-40I/SN
SST25WF040BT-40I/SN
SST25WF040B-40E/SN
SST25WF040BT-40E/SN
X
Tape/Reel
Indicator Frequency
XX
Package
Temperature
2018 Microchip Technology Inc. DS20005193E-page 40
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,
JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,
SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity,
JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon,
QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2018, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-3944-8
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS20005193E-page 41 2017 Microchip Technology Inc.
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08/15/18