VAGND1 10
N/C DIN
2 9
N/C SCLK
3 8
4 7
N/C N/C5 6
VOUT SYNC
DAC121S101QML
www.ti.com
SNAS410D –MAY 2008–REVISED APRIL 2012
DAC121S101QML 12-Bit Micro Power Digital-to-Analog Converter with Rail-to-Rail Output
Check for Samples: DAC121S101QML
1FEATURES DESCRIPTION
The DAC121S101 is a full-featured, general purpose
2• Total Ionizing Dose 100 krad(Si) 12-bit voltage-output digital-to-analog converter
• Single Event Latch-up 120 MeV-cm2/mg (DAC) that can operate from a single +2.7 V to 5.5 V
• Guaranteed Monotonicity supply and consumes just 177 µA of current at 3.6 V.
The on-chip output amplifier allows rail-to-rail output
• Low Power Operation swing and the three wire serial interface operates at
• Rail-to-Rail Voltage Output clock rates up to 20 MHz over the specified supply
• Power-on Reset to Zero Volts Output voltage range and is compatible with standard SPI,
QSPI, MICROWIRE and DSP interfaces.
• SYNC Interrupt Facility
• Wide power supply range (+2.7 V to +5.5 V) The supply voltage for the DAC121S101 serves as its
voltage reference, providing the widest possible
• Small Packages output dynamic range. A power-on reset circuit
• Power Down Feature ensures that the DAC output powers up to zero volts
and remains there until there is a valid write to the
APPLICATIONS device. A power-down feature reduces power
consumption to less than a microWatt.
• Battery-Powered Instruments
• Digital Gain and Offset Adjustment The low power consumption and small packages of
the DAC121S101 make it an excellent choice for use
• Programmable Voltage & Current Sources in battery operated equipment.
• Programmable Attenuators The DAC121S101 operates over the extended
temperature range of -55°C to +125°C.
KEY SPECIFICATIONS See Radiation Environments for dose rate
• Resolution: 12 bits environment information.
• DNL: +0.21, -0.10 LSB (typ)
• Output Settling Time: 12.5 µs (typ)
• Zero Code Error: 2.1 mV (typ)
• Full-Scale Error: −0.04 %FS (typ)
• Power Dissipation
– Normal Mode: 0.52 mW (3.6 V) / 1.19 mW
(5.5 V) typ
– Power Down Mode: 0.014 µW (3.6 V) / 0.033
µW (5.5 V) typ
Connection Diagram
Top View
Figure 1. 10 Lead CLGA Package
See Package Number NAC0010A
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2008–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
POWER-ON
RESET
DAC
REGISTER
INPUT
CONTROL
LOGIC
12-BIT DAC
12
12
POWER-DOWN
CONTROL
LOGIC
BUFFER
5k 100k
SCLK DIN
SYNC
REF(+) REF(-)
VAGND
DAC121S101
VOUT
DAC121S101QML
SNAS410D –MAY 2008–REVISED APRIL 2012
www.ti.com
Block Diagram
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage, VA6.5 V
Voltage on any Input Pin −0.3 V to (VA+ 0.3 V)
Input Current at Any Pin(3) 10 mA
Maximum Output Current(4) 10 mA
VOUT Pin in Powerdown Mode 1.0 mA
Package Input Current(3) 20 mA
Power Dissipation at TA= 25°C See(5)
Maximum Junction Temperature 175°C
Lead Temperature
CLGA package
(Soldering 10 Seconds) 260°C
Storage Temperature −65°C to +150°C
Package Weight (Typical)
CLGA package 220 mg
ESD Tolerance(6) Class 3A (5000 V)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see
the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND = 0 V, unless otherwise specified
(3) When the input voltage at any pin exceeds the power supplies (that is, less than GND, or greater than VA), the current at that pin should
be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power
supplies with an input current of 10 mA to two.
(4) Maximum Output Current may not exceed 10 mA. At VDD = 5.5 V the minimum external resistive load can be no less than 550 Ω, (360
Ωat VDD = 3.6 V).
(5) The absolute maximum junction temperature (TJmax) for this device is 175°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax −TA) / θJA. The values for maximum power dissipation will be reached only when the device is operated in a severe
fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed).
Obviously, such conditions should always be avoided.
(6) Human body model is 100 pF capacitor discharged through a 1.5 kΩresistor. Machine model is 220 pF discharged through ZERO
Ohms.
2Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated
Product Folder Links: DAC121S101QML
DAC121S101QML
www.ti.com
SNAS410D –MAY 2008–REVISED APRIL 2012
Operating Ratings(1)(2)
Operating Temperature Range −55°C to +125°C
Supply Voltage, VA+2.7 V to 5.5 V
Any Input Voltage(3) −0.1 V to (VA+ 0.1 V)
Output Load 0 to 1500 pF
SCLK Frequency Up to 20 MHz
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see
the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND = 0 V, unless otherwise specified
(3) The analog inputs are protected as shown below. Input voltage magnitudes up to VA+ 300 mV or to 300 mV below GND will not
damage this device. However, errors in the conversion result can occur if any input goes above VAor below GND by more than 100 mV.
For example, if VAis 2.7 VDC, ensure that −100 mV ≤input voltages ≤2.8 VDC to ensure accurate conversions. See Figure 2.
Package Thermal Resistance
θJA
Package θJC
(Still Air)
10-lead CLGA Package on 2 layer, 1oz. PCB 214°C/W 25.7°C/W
Quality Conformance Inspection
MIL-STD-883, Method 5005 - Group A
Subgroup Description Temp (° C)
1 Static tests at +25
2 Static tests at +125
3 Static tests at -55
4 Dynamic tests at +25
5 Dynamic tests at +125
6 Dynamic tests at -55
7 Functional tests at +25
8A Functional tests at +125
8B Functional tests at -55
9 Switching tests at +25
10 Switching tests at +125
11 Switching tests at -55
12 Setting time at +25
13 Setting time at +125
14 Setting time at -55
Copyright © 2008–2012, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: DAC121S101QML
DAC121S101QML
SNAS410D –MAY 2008–REVISED APRIL 2012
www.ti.com
DAC121S101 Electrical Characteristics DC Parameters
The following specifications apply for VA= +2.7 V to +5.5 V, RL=∞, CL= 200 pF to GND, fSCLK = 20 MHz, input code range
48 to 4047. Boldface limits apply for TMIN ≤TA≤TMAX: all other limits TA= 25°C, unless otherwise specified. Sub-
Parameter Test Conditions Notes Typical(1) Min Max Units groups
STATIC PERFORMANCE
Resolution See(2) 12 Bits
Monotonicity See(2) 12 Bits
Over Decimal codes 48 to
INL Integral Non-Linearity ±2.75 −8.0 8.0 LSB 1, 2, 3
4047 +0.21 +1.0 LSB 1, 2, 3
DNL Differential Non-Linearity VA= 2.7 V to 5.5 V −0.10 −0.7 LSB 1, 2, 3
ZE Zero Code Error IOUT = 0 +2.12 +15 mV 1, 2, 3
FSE Full-Scale Error IOUT = 0 −0.04 −1.0 %FSR 1, 2, 3
All ones Loaded to DAC
GE Gain Error −0.11 ±1.0 %FSR 1, 2, 3
register
ZCED Zero Code Error Drift See(2) −20 µV/°C
VA= 3 V −0.7 ppm/°C
TC GE Gain Error Tempco See(2)
VA= 5 V −1.0 ppm/°C
OUTPUT CHARACTERISTICS
IPD SINK Vout Pin in Powerdown Mode All PD Modes See(2) 1.0 mA
Output Voltage Range See(2) 0 VAV
VA= 3 V, IOUT = 10 µA 2.0 6mV 1, 2, 3
VA= 3 V, IOUT = 100 µA 4 10 mV 1, 2, 3
ZCO Zero Code Output VA= 5 V, IOUT = 10 µA 2 8mV 1, 2, 3
VA= 5 V, IOUT = 100 µA 4 9mV 1, 2, 3
VA= 3 V, IOUT = 10 µA 2.997 2.990 V 1, 2, 3
VA= 3 V, IOUT = 100 µA 2.991 2.985 V 1, 2, 3
FSO Full Scale Output VA= 5 V, IOUT = 10 µA 4.994 4.985 V 1, 2, 3
VA= 5 V, IOUT = 100 µA 4.992 4.985 V 1, 2, 3
RL=∞1500 pF
Maximum Load Capacitance See(2)
RL= 2 kΩ1500 pF
DC Output Impedance 8 16 Ω1, 2, 3
(1) Typical figures are at TJ= 25°C, and represent most likely parametric norms.
(2) This parameter is guaranteed by design and/or characterization and is not tested in production.
4Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated
Product Folder Links: DAC121S101QML
DAC121S101QML
www.ti.com
SNAS410D –MAY 2008–REVISED APRIL 2012
DAC121S101 Electrical Characteristics DC Parameters (Continued)
The following specifications apply for VA= +2.7 V to +5.5 V, RL=∞, CL= 200 pF to GND, fSCLK = 20 MHz, input code range
48 to 4047. Boldface limits apply for TMIN ≤TA≤TMAX: all other limits TA= 25°C, unless otherwise specified.
Typical Sub-
Parameter Test Conditions Notes Min Max Units
(1) groups
LOGIC INPUT
IIN Input Current 6 −200 +200 nA 1, 2, 3
VA= 5 V 0.8 V 1, 2, 3
VIL Input Low Voltage VA= 3 V 0.5 V 1, 2, 3
VA= 5 V 2.4 V 1, 2, 3
VIH Input High Voltage VA= 3 V 2.1 V 1, 2, 3
CIN Input Capacitance See(2) 5 pF
POWER REQUIREMENTS
5.5 V 216 270 µA 1, 2, 3
Normal Mode
fSCLK = 20 MHz 3.6 V 145 200 µA 1, 2, 3
5.5 V 185 230 µA 1, 2, 3
Normal Mode
fSCLK = 10 MHz 3.6 V 132 175 µA 1, 2, 3
5.5 V 150 190 µA 1, 2, 3
Normal Mode
fSCLK = 0 3.6 V 115 160 µA 1, 2, 3
IASupply Current (output unloaded) 5.5 V 22 60 µA 1, 2, 3
All PD Modes,
fSCLK = 20 MHz 3.6 V 12 30 µA 1, 2, 3
5.5 V 12 40 µA 1, 2, 3
All PD Modes,
fSCLK = 10 MHz 3.6 V 6 20 µA 1, 2, 3
5.5 V .006 1.0 µA 1, 2, 3
All PD Modes,
fSCLK = 0 3.6 V .004 1.0 µA 1, 2, 3
5.5 V 1.19 1.49 mW
Normal Mode See(2)
fSCLK = 20 MHz 3.6 V 0.52 .72 mW
5.5 V 1.02 1.27 mW
Normal Mode See(2)
fSCLK = 10 MHz 3.6 V 0.47 .63 mW
5.5 V 0.82 1.05 mW
Normal Mode See(2)
fSCLK = 0 3.6 V 0.41 .58 mW
Power Consumption (output
PCunloaded) 5.5 V 0.12 .33 mW
All PD Modes, See(2)
fSCLK = 20 MHz 3.6 V 0.07 .11 mW
5.5 V 0.04 .22 mW
All PD Modes, See(2)
fSCLK = 10 MHz 3.6 V 0.02 .08 mW
5.5 V 0.033 5.5 µW
All PD Modes, See(2)
fSCLK = 0 3.6 V 0.014 3.6 µW
91 %
IOUT / IAPower Efficiency ILOAD = 2 mA See(2) 94 %
(1) Typical figures are at TJ= 25°C, and represent most likely parametric norms.
(2) This parameter is guaranteed by design and/or characterization and is not tested in production.
Copyright © 2008–2012, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: DAC121S101QML
DAC121S101QML
SNAS410D –MAY 2008–REVISED APRIL 2012
www.ti.com
DAC121S101 Electrical Characteristics AC and Timing Characteristics
The following specifications apply for VA= +2.7 V to +5.5 V, RL=∞, CL= 200 pF to GND, fSCLK = 20 MHz, input code range
48 to 4047. Boldface limits apply for TMIN ≤TA≤TMAX: all other limits TA= 25°C, unless otherwise specified. Sub-
Parameter Test Conditions Notes Typical(1) Min Max Units groups
fSCLK SCLK Frequency (See Figure 4) See(2) 20 MHz 9, 10, 11
CL≤200 pF 12.5 15 µs 9, 10, 11
FF0 to 00F code change,
RL=∞
CL= 500 pF 12.5 15 µs 9, 10, 11
tsOutput Voltage Settling Time
CL≤200 pF 12.5 15 µs 9, 10, 11
00Fh to FF0h code
change, RL=∞
CL= 500 pF 12.5 15 µs 9, 10, 11
SR Output Slew Rate See(2) 1 V/µs
Code change from 800h to
Glitch Impulse See(2) 12 nV-sec
7FFh
Digital Feedthrough See(2) 0.5 nV-sec
VA= 5 V .65 µs
tWU Wake-Up Time See(2)
VA= 3 V 1.1 µs
1/fSCLK SCLK Cycle Time (See Figure 4)50 ns 9, 10, 11
tHSCLK High time (See Figure 4)20 ns 9, 10, 11
tLSCLK Low Time (See Figure 4)20 ns 9, 10, 11
Set-up Time SYNC to SCLK
tSUCL (See Figure 4)0ns 9, 10, 11
Rising Edge
tSUD Data Set-Up Time (See Figure 4)6ns 9, 10, 11
tDHD Data Hold Time (See Figure 4)4.5 ns 9, 10, 11
VA= 5.5 V (See Figure 4)10 ns 9, 10, 11
tCS SCLK fall to rise of SYNC VA= 2.7 V (See Figure 4)18 ns 9, 10, 11
VA= 5.5 V (See Figure 4)37 ns 9, 10, 11
tSYNC SYNC High Time VA= 2.7 V (See Figure 4)36 ns 9, 10, 11
(1) Typical figures are at TJ= 25°C, and represent most likely parametric norms.
(2) This parameter is guaranteed by design and/or characterization and is not tested in production.
6Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated
Product Folder Links: DAC121S101QML
I/O
GND
TO INTERNAL
CIRCUITRY
DAC121S101QML
www.ti.com
SNAS410D –MAY 2008–REVISED APRIL 2012
DAC121S101 Electrical Characteristics Radiation Electrical Characteristics(1)
The following specifications apply for VA= +2.7 V to +5.5 V, RL=∞, CL= 200 pF to GND, fSCLK = 20 MHz, input code range
48 to 4047. Sub-
Parameter Test Conditions Min Max Units groups
POWER REQUIREMENTS
Normal Mode 5.5 V 325 µA 1
fSCLK = 20 MHz 3.6 V 250 µA 1
Normal Mode 5.5 V 300 µA 1
fSCLK = 10 MHz 3.6 V 225 µA 1
Normal Mode 5.5 V 275 µA 1
fSCLK = 0 3.6 V 200 µA 1
Supply Current (output
IAunloaded) All PD Modes, 5.5 V 125 µA 1
fSCLK = 20 MHz 3.6 V 100 µA 1
All PD Modes, 5.5 V 115 µA 1
fSCLK = 10 MHz 3.6 V 95 µA 1
All PD Modes, 5.5 V 100 µA 1
fSCLK = 0 3.6 V 100 µA 1
(1) Pre and post irradiation limits are identical to those listed in the “DC Parameters” and “AC and Timing Characteristics” tables, except as
listed in the “Radiation Electrical Characteristics” table. When performing post irradiation electrical measurements for any RHA level, TA
= +25°C. See Radiation Environments for dose rate and test conditions.
DAC121S101 Electrical Characteristics Operating Life Test Delta Parameters TAat 25°C(1)
Parameter Test Conditions Min Max Units
INL Integral non-linearity ±2 LBS
ts Output voltage settling time ±5 µA
Normal Mode, VA= 5.5V fSCLK = 20 MHz ±10 µA
Normal Mode, VA= 3.6V fSCLK = 20 MHz ±6 µA
Normal Mode, VA= 5.5V fSCLK = 10 MHz ±10 µA
Normal Mode, VA= 3.6V fSCLK = 10 MHz ±6 µA
Normal Mode, VA= 5.5V fSCLK = 0 ±8 µA
Normal Mode, VA= 3.6V fSCLK = 0 ±6 µA
IASupply Current (output unloaded) All PD Modes, VA= 5.5V fSCLK = 20 MHz ±2 µA
All PD Modes, VA= 3.6V fSCLK = 20 MHz ±1 µA
All PD Modes, VA= 5.5V fSCLK = 10 MHz ±1 µA
All PD Modes, VA= 3.6V fSCLK = 10 MHz ±1 µA
All PD Modes, VA= 5.5V fSCLK = 0 ±0.1 µA
All PD Modes, VA= 3.6V fSCLK = 0 ±0.1 µA
(1) These parameters are worse case drift. Deltas are performed at room temperature Post OP Life. All other parameters no Deltas are
required.
Figure 2.
Copyright © 2008–2012, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: DAC121S101QML
DAC121S101QML
SNAS410D –MAY 2008–REVISED APRIL 2012
www.ti.com
Specification Definitions
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB, which is VREF / 4096 = VA/ 4096.
DIGITAL FEEDTHROUGH is a measure of the energy injected into the analog output of the DAC from the digital
inputs when the DAC outputs are not updated. It is measured with a full-scale code change on the data bus.
FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (FFFh) loaded
into the DAC and the value of VAx 4095 / 4096.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and
Full-Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is Zero Error.
GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register
changes. It is specified as the area of the glitch in nanovolt-seconds.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line
through the input to output transfer function. The deviation of any given code from this straight line is measured
from the center of that code value. The end point method is used. INL for this product is specified over a limited
range, per the Electrical Tables.
LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value is
LSB = VREF / 2n(1)
where VREF is the supply voltage for this product, and "n" is the DAC resolution in bits, which is 12 for the
DAC121S101.
MAXIMUM LOAD CAPACITANCE is the maximum capacitance that can be driven by the DAC with output
stability maintained.
MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when
the input code increases.
MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is
1/2 of VA.
POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from
the power supply. The difference between the supply and output currents is the power consumed by the device
without a load.
SETTLING TIME is the time for the output to settle to within 1/2 LSB of the final value after the input code is
updated.
WAKE-UP TIME is the time for the output to exit power-down mode. This is the time measured from the falling
edge of 16th SCLK pulse to when the output voltage deviates from the power-down voltage of 0 V.
ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 000h has been
entered.
8Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated
Product Folder Links: DAC121S101QML
DB15 DB0
SCLK
DIN
SYNC
tSYNC tSUCL
tSUD
tDHD
tLtH
1 / fSCLK
tCS
|||
|
|
||
1 2 13 14 15 16
OUTPUT
VOLTAGE
DIGITAL INPUT CODE
00 4095
ZE
FSE
GE = FSE - ZE
FSE = GE + ZE
4095 x VA
4096
DAC121S101QML
www.ti.com
SNAS410D –MAY 2008–REVISED APRIL 2012
Transfer Characteristic
Figure 3. Input / Output Transfer Characteristic
Timing Diagram
Figure 4. DAC121S101 Timing
Copyright © 2008–2012, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: DAC121S101QML
DAC121S101QML
SNAS410D –MAY 2008–REVISED APRIL 2012
www.ti.com
Typical Performance Characteristics
fSCLK = 20 MHz, TA= 25C, Input Code Range 48 to 4047, unless otherwise stated
DNL at VA= 2.7V DNL at VA= 5.5V
Figure 5. Figure 6.
INL at VA= 2.7V INL at VA= 5.5V
Figure 7. Figure 8.
DNL vs. VAINL vs. VA
Figure 9. Figure 10.
10 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated
Product Folder Links: DAC121S101QML
DAC121S101QML
www.ti.com
SNAS410D –MAY 2008–REVISED APRIL 2012
Typical Performance Characteristics (continued)
fSCLK = 20 MHz, TA= 25C, Input Code Range 48 to 4047, unless otherwise stated
2.7V DNL vs. fSCLK 5.5V DNL vs. fSCLK
Figure 11. Figure 12.
2.7V DNL vs. Clock Duty Cycle 5.5V DNL vs. Clock Duty Cycle
Figure 13. Figure 14.
2.7V DNL vs. Temperature 5.5V DNL vs. Temperature
Figure 15. Figure 16.
Copyright © 2008–2012, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: DAC121S101QML
DAC121S101QML
SNAS410D –MAY 2008–REVISED APRIL 2012
www.ti.com
Typical Performance Characteristics (continued)
fSCLK = 20 MHz, TA= 25C, Input Code Range 48 to 4047, unless otherwise stated
2.7V INL vs. fSCLK 5.5V INL vs. fSCLK
Figure 17. Figure 18.
2.7V INL vs. Clock Duty Cycle 5.5V INL vs. Clock Duty Cycle
Figure 19. Figure 20.
2.7V INL vs. Temperature 5.5V INL vs. Temperature
Figure 21. Figure 22.
12 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated
Product Folder Links: DAC121S101QML
DAC121S101QML
www.ti.com
SNAS410D –MAY 2008–REVISED APRIL 2012
Typical Performance Characteristics (continued)
fSCLK = 20 MHz, TA= 25C, Input Code Range 48 to 4047, unless otherwise stated
Zero Code Error vs. fSCLK Zero Code Error vs. Temperature
Figure 23. Figure 24.
Full-Scale Error vs. fSCLK Full-Scale Error vs. Temperature
Figure 25. Figure 26.
Supply Current vs. VASupply Current vs. Temperature
Figure 27. Figure 28.
Copyright © 2008–2012, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: DAC121S101QML
DAC121S101QML
SNAS410D –MAY 2008–REVISED APRIL 2012
www.ti.com
Typical Performance Characteristics (continued)
fSCLK = 20 MHz, TA= 25C, Input Code Range 48 to 4047, unless otherwise stated
5V Glitch Response Power-On Reset
Figure 29. Figure 30.
3V Wake-Up Time 5V Wake-Up Time
Figure 31. Figure 32.
14 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated
Product Folder Links: DAC121S101QML
VA
R
R
R
R
To Output Amplifier
R
DAC121S101QML
www.ti.com
SNAS410D –MAY 2008–REVISED APRIL 2012
FUNCTIONAL DESCRIPTION
DAC SECTION
The DAC121S101 is fabricated on a CMOS process with an architecture that consists of switches and a resistor
string that are followed by an output buffer. The power supply serves as the reference voltage. The input coding
is straight binary with an ideal output voltage of:
VOUT = VAx (D / 4096) (2)
where Dis the decimal equivalent of the binary code that is loaded into the DAC register and can take on any
value between 0 and 4095.
RESISTOR STRING
The simplified resistor string is shown in Figure 33. Conceptually, this string consists of 4096 equal valued
resistors with a switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC
register determines which switch is closed, connecting the proper node to the amplifier. This configuration
guarantees that the DAC is monotonic.
Figure 33. DAC Resistor String
OUTPUT AMPLIFIER
The output buffer amplifier is a rail-to-rail type, providing an output voltage range of 0V to VA. All amplifiers, even
rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0V and VA, in this case). For
this reason, linearity is specified over less than the full output range of the DAC. The output capabilities of the
amplifier are described in the Electrical Tables.
SERIAL INTERFACE
The three-wire interface is compatible with SPI, QSPI and MICROWIRE, as well as most DSPs. See the Timing
Diagram for information on a write sequence.
A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the DIN line is clocked
into the 16-bit serial input register on the falling edges of SCLK. On the 16th falling clock edge, the last data bit is
clocked in and the programmed function (a change in the mode of operation and/or a change in the DAC register
contents) is executed. At this point the SYNC line may be kept low or brought high. In either case, it must be
brought high for the minimum specified time before the next write sequence as a falling edge of SYNC can
initiate the next write cycle.
Copyright © 2008–2012, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: DAC121S101QML
DB15 (MSB)
X X PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATA BITS
DB0 (LSB)
5 k:
100 k:Power-Down Modes
0 0 Normal Operation
0 1 to GND
1 0 to GND
1 1 High Impedance
DAC121S101QML
SNAS410D –MAY 2008–REVISED APRIL 2012
www.ti.com
Since the SYNC and DIN buffers draw more current when they are high, they should be idled low between write
sequences to minimize power consumption.
INPUT SHIFT REGISTER
The input shift register, Figure 34, has sixteen bits. The first two bits are "don't cares" and are followed by two
bits that determine the mode of operation (normal mode or one of three power-down modes). The contents of the
serial input register are transferred to the DAC register on the sixteenth falling edge of SCLK. See Timing
Diagram, Figure 4.
Figure 34. Input Register Contents
Normally, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th
SCLK falling edge. However, if SYNC is brought high before the 16th falling edge, the shift register is reset and
the write sequence is invalid. The DAC register is not updated and there is no change in the mode of operation
or in the output voltage.
POWER-ON RESET
The power-on reset circuit controls the output voltage during power-up. Upon application of power the DAC
register is filled with zeros and the output voltage is 0 Volts and remains there until a valid write sequence is
made to the DAC.
POWER-DOWN MODES
The DAC121S101 has four modes of operation. These modes are set with two bits (DB13 and DB12) in the
control register.
Table 1. Modes of Operation
DB13 DB12 Operating Mode
0 0 Normal Operation
0 1 Power-Down with 5kΩto GND
1 0 Power-Down with 100kΩto GND
1 1 Power-Down with Hi-Z
When both DB13 and DB12 are 0, the device operates normally. For the other three possible combinations of
these bits the supply current drops to its power-down level and the output is pulled down with either a 5kΩor a
100kΩresistor, or is in a high impedance state, as described in Table 1.
The bias generator, output amplifier, the resistor string and other linear circuitry are all shut down in any of the
power-down modes. Minimum power consumption is achieved in the power-down mode with SCLK disabled and
SYNC and DIN idled low.
16 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated
Product Folder Links: DAC121S101QML
68HC11 DAC121S101
PC7
SCK
MOSI
SCLK
DIN
SYNC
80C51/80L51 DAC121S101
P3.3
TXD
RXD
SCLK
DIN
SYNC
DAC121S101QML
www.ti.com
SNAS410D –MAY 2008–REVISED APRIL 2012
Applications Information
The simplicity of the DAC121S101 implies ease of use. However, it is important to recognize that any data
converter that utilizes its supply voltage as its reference voltage will have essentially zero PSRR (Power Supply
Rejection Ratio). Therefore, it is necessary to provide a noise-free supply voltage to the device.
DSP/MICROPROCESSOR INTERFACING
Interfacing the DAC121S101 to microprocessors and DSPs is quite simple. The following guidelines are offered
to hasten the design process.
ADSP-2101/ADSP2103 Interfacing
Figure 35 shows a serial interface between the DAC121S101 and the ADSP-2101/ADSP2103. The DSP should
be set to operate in the SPORT Transmit Alternate Framing Mode. It is programmed through the SPORT control
register and should be configured for Internal Clock Operation, Active Low Framing and 16-bit Word Length.
Transmission is started by writing a word to the Tx register after the SPORT mode has been enabled.
Figure 35. ADSP-2101/2103 Interface
80C51/80L51 Interface
A serial interface between the DAC121S101 and the 80C51/80L51 microcontroller is shown in Figure 36. The
SYNC signal comes from a bit-programmable pin on the microcontroller. The example shown here uses port line
P3.3. This line is taken low when data is to transmitted to the DAC121S101. Since the 80C51/80L51 transmits 8-
bit bytes, only eight falling clock edges occur in the transmit cycle. To load data into the DAC, the P3.3 line must
be left low after the first eight bits are transmitted. A second write cycle is initiated to transmit the second byte of
data, after which port line P3.3 is brought high. The 80C51/80L51 transmit routine must recognize that the
80C51/80L51 transmits data with the LSB first while the DAC121S101 requires data with the MSB first.
Figure 36. 80C51/80L51 Interface
68HC11 Interface
A serial interface between the DAC121S101 and the 68HC11 microcontroller is shown in Figure 37. The SYNC
line of the DAC121S101 is driven from a port line (PC7 in the figure), similar to the 80C51/80L51.
The 68HC11 should be configured with its CPOL bit as a zero and its CPHA bit as a one. This configuration
causes data on the MOSI output to be valid on the falling edge of SCLK. PC7 is taken low to transmit data to the
DAC. The 68HC11 transmits data in 8-bit bytes with eight falling clock edges. Data is transmitted with the MSB
first. PC7 must remain low after the first eight bits are transferred. A second write cycle is initiated to transmit the
second byte of data to the DAC, after which PC7 should be raised to end the write sequence.
Figure 37. 68HC11 Interface
Copyright © 2008–2012, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: DAC121S101QML
LM4050-4.1
or
LM4050-5.0
DAC121S101
DIN
SCLK
SYNC VOUT = 0V to 5V
0.47 PF
Input
Voltage
R
VZ
LM4130-4.1
DAC121S101
DIN
SCLK
SYNC VOUT = 0V to 4.095V
C1
0.1 PFC2
2.2 PF
Input
Voltage
MICROWIRE
DEVICE
DAC121S101
CS
SK
SO
SCLK
DIN
SYNC
DAC121S101QML
SNAS410D –MAY 2008–REVISED APRIL 2012
www.ti.com
Microwire Interface
Figure 38 shows an interface between a Microwire compatible device and the DAC121S101. Data is clocked out
on the rising edges of the SCLK signal.
Figure 38. Microwire Interface
USING REFERENCES AS POWER SUPPLIES
Recall the need for a quiet supply source for devices that use their power supply voltage as a reference voltage.
Since the DAC121S101 consumes very little power, a reference source may be used as the supply voltage. The
advantages of using a reference source over a voltage regulator are accuracy and stability. Some low noise
regulators can also be used for the power supply of the DAC121S101. Listed below are a few power supply
options for the DAC121S101.
LM4130
The LM4130 reference, with its 0.05% accuracy over temperature, is a good choice as a power source for the
DAC121S101. Its primary disadvantage is the lack of 3 V and 5 V versions. However, the 4.096 V version is
useful if a 0 to 4.095 V output range is desirable or acceptable. Bypassing the LM4130 VIN pin with a 0.1 µF
capacitor and the VOUT pin with a 2.2 µF capacitor will improve stability and reduce output noise. The LM4130
comes in a space-saving 5-pin SOT23.
Figure 39. The LM4130 as a power supply
LM4050
Available with accuracy of 0.44%, the LM4050 shunt reference is also a good choice as a power regulator for the
DAC121S101. It does not come in a 3 Volt version, but 4.096 V and 5 V versions are available. It comes in a
space-saving 3-pin SOT23.
Figure 40. The LM4050 as a power supply
18 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated
Product Folder Links: DAC121S101QML
LP2980
DAC121S101
DIN
SCLK
SYNC VOUT = 0V to 5V
1 PF
Input
Voltage ON / OFF
VIN VOUT
LP3985
DAC121S101
DIN
SCLK
SYNC VOUT = 0V to 5V
1 PF0.1 PF
Input
Voltage
0.01 PF
DAC121S101QML
www.ti.com
SNAS410D –MAY 2008–REVISED APRIL 2012
The minimum resistor value in the circuit of Figure 40 should be chosen such that the maximum current through
the LM4050 does not exceed its 15 mA rating. The conditions for maximum current include the input voltage at
its maximum, the LM4050 voltage at its minimum, the resistor value at its minimum due to tolerance, and the
DAC121S101 draws zero current. The maximum resistor value must allow the LM4050 to draw more than its
minimum current for regulation plus the maximum DAC121S101 current in full operation. The conditions for
minimum current include the input voltage at its minimum, the LM4050 voltage at its maximum, the resistor value
at its maximum due to tolerance, and the DAC121S101 draws its maximum current. These conditions can be
summarized as
R(min) = ( VIN(max) −VZ(min) / (IA(min) + IZ(max)) (3)
and R(max) = ( VIN(min) −VZ(max) / (IA(max) + IZ(min) ) (4)
where VZ(min) and VZ(max) are the nominal LM4050 output voltages ± the LM4050 output tolerance over
temperature, IZ(max) is the maximum allowable current through the LM4050, IZ(min) is the minimum current
required by the LM4050 for proper regulation, IA(max) is the maximum DAC121S101 supply current, and IA(min)
is the minimum DAC121S101 supply current.
LP3985
The LP3985 is a low noise, ultra low dropout voltage regulator with a 3% accuracy over temperature. It is a good
choice for applications that do not require a precision reference for the DAC121S101. It comes in 3.0V, 3.3V and
5V versions, among others, and sports a low 30 µV noise specification at low frequencies. Since low frequency
noise is relatively difficult to filter, this specification could be important for some applications. The LP3985 comes
in a space-saving 5-pin SOT-23 and 5-bump DSBGA packages.
Figure 41. Using the LP3985 regulator
An input capacitance of 1.0µF without any ESR requirement is required at the LP3985 input, while a 1.0µF
ceramic capacitor with an ESR requirement of 5mΩto 500mΩis required at the output. Careful interpretation
and understanding of the capacitor specification is required to ensure correct device operation.
LP2980
The LP2980 is an ultra low dropout regulator with a 0.5% or 1.0% accuracy over temperature, depending upon
grade. It is available in 3.0V, 3.3V and 5V versions, among others.
Figure 42. Using the LP2980 regulator
Copyright © 2008–2012, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: DAC121S101QML
DAC121S101
DIN
SCLK
SYNC VOUT
0.1 PF
+
10 PF
+
-
+5V
R1
R2
-5V
+5V
±5V
10 pF
DAC121S101QML
SNAS410D –MAY 2008–REVISED APRIL 2012
www.ti.com
Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability. This output capacitor
must be at least 1.0µF over temperature, but values of 2.2µF or more will provide even better performance. The
ESR of this capacitor should be within the range specified in the LP2980 data sheet. Surface-mount solid
tantalum capacitors offer a good combination of small size and ESR. Ceramic capacitors are attractive due to
their small size but generally have ESR values that are too low for use with the LP2980. Aluminum electrolytic
capacitors are typically not a good choice due to their large size and have ESR values that may be too high at
low temperatures.
BIPOLAR OPERATION
The DAC121S101 is designed for single supply operation and thus has a unipolar output. However, a bipolar
output may be obtained with the circuit in Figure 43. This circuit will provide an output voltage range of ±5 Volts.
A rail-to-rail amplifier should be used if the amplifier supplies are limited to ±5V.
Figure 43. Bipolar Operation
The output voltage of this circuit for any code is found to be
VO= (VAx (D / 4096) x ((R1 + R2) / R1) - VAx R2 / R1) (5)
where D is the input code in decimal form. With VA = 5V and R1 = R2,
VO= (10 x D / 4096) - 5V (6)
A list of rail-to-rail amplifiers suitable for this application are indicated in Table 2.
Table 2. Some Rail-to-Rail Amplifiers
AMP PKGS Typ VOS Typ ISUPPLY
DIP-8
LMC7111 0.9 mV 25 µA
SOT23-5
SO-8
LM7301 0.03 mV 620 µA
SOT23-5
LM8261 SOT23-5 0.7 mV 1 mA
LAYOUT, GROUNDING, AND BYPASSING
For best accuracy and minimum noise, the printed circuit board containing the DAC121S101 should have
separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes.
Both of these planes should be located in the same board layer. There should be a single ground plane. A single
ground plane is preferred if digital return current does not flow through the analog ground area. Frequently a
single ground plane design will utilize a "fencing" technique to prevent the mixing of analog and digital ground
current. Separate ground planes should only be utilized when the fencing technique is inadequate. The separate
ground planes must be connected in one place, preferably near the DAC121S101. Special care is required to
guarantee that digital signals with fast edge rates do not pass over split ground planes. They must always have a
continuous return path below their traces.
The DAC121S101 power supply should be bypassed with a 10µF and a 0.1µF capacitor as close as possible to
the device with the 0.1µF right at the device supply pin. The 10µF capacitor should be a tantalum type and the
0.1µF capacitor should be a low ESL, low ESR type. The power supply for the DAC121S101 should only be
used for analog circuits.
20 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated
Product Folder Links: DAC121S101QML
DAC121S101QML
www.ti.com
SNAS410D –MAY 2008–REVISED APRIL 2012
Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the
board. The clock and data lines should have controlled impedances.
Radiation Environments
Careful consideration should be given to environmental conditions when using a product in a radiation
environment.
Total Ionizing Dose
The products with the radiation hardness assurance (RHA) levels listed in the Ordering Information table listed
on the front page are qualified for low dose rate environments only.
DAC121S101WGRQV 5962R0722601VZA
This product is tested and qualified per MIL-STD-883 Test Method 1019, Condition A and the “Extended room
temperature anneal test” where a high dose irradiation followed by a room temperature anneal is used to
simulate a dose rate of 0.027 rad(Si)/s and is qualified for environments with radiation levels of 0.027 rad(Si)/s or
lower.
DAC121S101WGRLV 5962R0722602VZA
This product is tested and qualified per MIL-STD-883 Test Method 1019, Condition D at a dose rate of 0.01
rad(Si)/s and are qualified for environments with radiation levels of 0.01 rad(Si)/s or lower.
Single Event Latch-Up and Functional Interrupt
One time single event latch-up (SEL) and single event functional interrupt (SEFI) testing was preformed
according to EIA/JEDEC Standard, EIA/JEDEC57. The linear energy transfer threshold (LETth) shown in the Key
Specifications section on the front page is the maximum LET tested. A test report is available upon request.
Single Event Upset
A report on single event upset (SEU) is available upon request.
Copyright © 2008–2012, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: DAC121S101QML
PACKAGE OPTION ADDENDUM
www.ti.com 1-Mar-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
5962R0722601VZA ACTIVE CLGA NAC 10 TBD A42 SNPB Level-1-NA-UNLIM -55 to 125 DAC121S101
WGRQMLV Q
5962R07226
01VZA ACO
01VZA >T
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
MECHANICAL DATA
NAC0010A
www.ti.com
WG10A (Rev H)
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated