10473907249 - AMPHENOL - Product.Network

1. General description

NTAG I2C - The entry to the NFC world: simple and lowest cost.

The NTAG I2C is the first product of NXP’s NTAG family offering both contactless and

contact interfaces (see Figure 1). In addition to the passive NFC Forum compliant

contactless interface, the IC features an I2C contact interface, which can communicate

with a microcontroller if the NTAG I2C is powered from an external power supply. An

additional externally powered SRAM mapped into the memory allows a fast data transfer

between the RF a nd I2C interfaces and vice ver sa, without the write cycle limit ations of the

EEPROM memory.

The NTAG I2C product features a configurable field de tection pin, which provides a trigge r

to an external device depending on the a ctivitie s at the RF interface.

The NTAG I2C product can also supply power to external (low power) devices (e.g. a

microcontroller) via the embedded energy harvesting circuitry.

NT3H1101/NT3H1201

NTAG I2C - Energy harvesting NFC Forum Type 2 Tag with

field detection pin and I2C interface

Rev. 3.3 — 15 July 2015

265433 Product data sheet

COMPANY PUBLIC

Fig 1. Contactless and cont act system

aaa-010357

NFC

enabled

device

Data

Energy

Data

Energy

I2C

111111000000

EEPROM

Energy Harvesting

Field detection

Micro

controller

Product data sheet

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265433 2 of 65

NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

2. Features and benefits

2.1 Key features

RF interface NFC Forum Type 2 Tag compliant

I2C interface

Configurable field detection pin based on open drain implementation that can be

triggered upon the following events:

RF field presence

First start of communication

Selection of the tag only

64 byte SRAM buffer for fast transfer of dat a (Pass-through mode) between the RF

and the I2C interfaces located outside the User Memory

Wake up signal at the field de te ct pin whe n:

New data has arrived from one interface

Data has been read by the receiving interface

Clear arbitration between RF and I2C interfaces:

First come, first serve strategy

Status flag bits to signal if one interface is busy writing to or reading data from the

EEPROM

Energy harve stin g funct i on a lity to po wer external devices (e .g . micr oc on tr olle r)

FAST READ command for faster data re ading

2.2 RF interface

Contactless transmission of data

NFC Forum Type 2 Tag compliant (see Ref. 1)

Operating frequency of 13.56 MHz

Data transfer of 106 kbit/s

4 bytes (one page) written including all overhead in 4.8 ms via EEPROM or 0.8 ms via

SRAM (Pass-through mode)

Data integrity of 16-bit CRC, parity, bit coding, bit counting

Operating distance of up to 100 mm (depending on various parameters, such as field

strength and antenna geometry)

True anticollision

Unique 7 byte serial number (cascade level 2 according to ISO/IEC 14443-3

(see Ref. 2)

2.3 Memory

1904 bytes freely available with User Read/Write area (476 pages with 4 bytes per

pages) for the NTAG I2C 2k version

888 bytes freely available with User Read/Write area (222 pages with 4 bytes per

pages) for the NTAG I2C 1k version

Field programmable RF read-only locking function with static and dynamic lock bits

configurable from both I²C and NFC interfaces

64 bytes SRAM volatile memory without write endurance limitation

Product data sheet

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

Data retention time of 20 years

Write endurance 500,000 cycles

2.4 I2C interface

I2C slave interface supports Standard (100 kHz) and Fast (up to 400 kHz) mode (see

Ref. 3)

16 bytes (one block) written in 4.5 ms (EEPROM) or 0.4 ms (SRAM - Pass-through

mode) including all overhead

RFID chip can be used as standard I2C EEPROM

2.5 Security

Manufacturer -programmed 7-byte UID for each device

Capability container with one time programmable bits

Field programmable read-only locking function per page for first 12 pages and per 16

(1k version) or 32 (2k version) pages for the extended memory section

2.6 Key benefits

The Pass-through mode allows fast download and upload of da ta from RF to I²C and

vice versa without the cycling limitation of EEPROM

NDEF message storage up to 1904 bytes (2k version) or up to 888 bytes (1k version)

The mapping of the SRAM inside the User Memory buffer allows dynamic update of

NDEF messag e co nt en t

3. Applications

With all its integrated features and functions the NTAG I2C is the ideal solution to enable a

contactless communication via an NFC device (e.g., NFC enabled mobile phone) to an

electronic device for:

Zero power configuration (late customization)

Smart customer interaction (e.g., easier after sales service, such as firmware update)

Advanced pairing ( for e.g., WiFi or Blue tooth) for dynamic gener ation of sessions keys

Easier product customization and customer experience for the following applications:

Home automation

Home appliances

Consumer electronics

Healthcare

Printers

Smart meters

Product data sheet

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

4. Ordering information

5. Marking

Table 1. Ordering information

Type number Package

Name Description Version

NT3H1101W0FUG FFC

bumped 8 inch wafer, 150um thickness, on film frame carrier, electronic fail die

marking according to SECS-II format), Au bumps, 1k Bytes memory, 50pF

input capacitance

NT3H1201W0FUG FFC

bumped 8 inch wafer, 150um thickness, on film frame carrier, electronic fail die

marking according to SECS-II format), Au bumps, 2k Bytes memory, 50pF

input capacitance

NT3H1101W0FHK XQFN8 Plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 x

1.6 x 0.6mm; 1k bytes memory, 50pF input capacitance SOT902-3

NT3H1201W0FHK XQFN8 Plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 x

1.6 x 0.6mm; 2k bytes memory, 50pF input capacitance SOT902-3

NT3H1101W0FTT TSSOP8 Plastic thin shrink small outline package; 8 leads; body width 3 mm; 1k

bytes memory; 50pF input capacitance SOT505-1

NT3H1201W0FTT TSSOP8 Plastic thin shrink small outline package; 8 leads; body width 3 mm; 2k

bytes memory; 50pF input capacitance SOT505-1

Table 2. Marking codes

Type number Marking code

NT3H1201FHK N12

NT3H1101FHK N11

NT3H1101W0FFT 31101

NT3H1201W0FFT 31201

Product data sheet

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265433 5 of 65

NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

6. Block diagram

Fig 2. Block diagram

aaa-010358

I2C

SLAVE

I2C

CONTROL

INTERFACE

POWER MANAGEMENT/

ENERGY HAR VESTING

DIGITAL CONTROL UNIT MEMORY

EEPROM

SRAM

ARBITER/STATUS

REGISTERS

ANTICOLLISION

COMMAND

INTERPRETER

MEMORY

INTERFACE

SDA

SCL

GND

VoutVCC

Product data sheet

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

7. Pinning information

7.1 Pinning

7.1.1 XQFN8

7.1.2 TSSOP8

(1) Dimension A: 1.6 mm

(2) Dimension B: 0.5 mm

Fig 3. Pin confi guration for XQFN8

aaa-010359

Transparent top view

side view

2VSS

SCL

VCC

SDA

VOUT

(1) Dimension A: 5.1 mm

(2) Dimension B: 3.1 mm

(3) Dimension C: 1.1 mm

Fig 4. Pin confi gura tio n for TSSOP8

aaa-017246

Transparent top view Side view

SDA

VCC

VOUT

SCL

VSS

LA 1

Product data sheet

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

7.2 Pin description

NXP recommends leaving the central pad of the XQFN8 package unconnected.

Table 3. Pin description for XQFN8 and TSSOP8

Pin Symbol Description

1 LA Antenna connection LA

2 VSS GND

3 SCL Serial Clock I2C

4 FD Field detection

5 SDA Serial data I2C

6 VCC VCC in connection (external power suppl y)

7 VOUT Voltage out (energy harvesting)

8 LB Antenna connection LB

Product data sheet

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

8. Functional description

8.1 Block description

NTAG I2C ICs consist of (see details below): 2016 bytes of EEPROM memory, 64 Bytes of

SRAM, a RF interface, Digital Control Unit (DCU), Power Ma nagement Unit (PMU) and an

I²C interface. Energy and data are transferred via an antenna consisting of a coil with a

few turns, which is directly connected to NTAG I2C IC.

•RF interface:

–modulator/demodulator

–rectifier

–clock regenerator

–Power-On Reset (POR)

–voltage regulator

•Anticollision: multiple cards may be selected and managed in sequence

•Command interpreter : processes memory access commands suppor ted by the NTAG

I2C

•EEPROM interface

8.2 RF interface

The RF-interface is based on the ISO/IEC 14443 Type A standard.

This RF interface is passive and therefore requires to be supplied by an RF field (e.g. NFC

enabled device) at all times to be ab le to opera te. It is not operating even if the NTAG I2C

is powered via its contact interface (Vcc).

Data transmission from the RF interface is only happening if RF field from an NFC

enabled device is available and adequate commands are sent to retrieve data from the

NTAG I2C.

For both directions of data communication, there is one start bit (start of communication)

at the beginning of ea ch fra me . Eac h by te is transmitted with an odd parity bit at the end.

The LSB of the byte with the lowest address of the selected block is transmitted first.

The maximum length of an NFC device to t ag frame used in this prod uct is 82 bit s (7 dat a

bytes + 2 CRC bytes = 7×9 + 2×9 + 1 start bit).

The maximum length of a tag to NFC device frame (response to READ command) is 163

bits (16 da ta bytes + 2 CRC bytes = 16  9 + 2  9 + 1 start bit).

In addition the proprietary FAST_READ command has a variable response frame length,

which depends on the start and end address parameters. E.g. when reading the SRAM at

once the length of the response is 595 bits (64 data bytes + 2 CRC bytes = 64  9 + 2  9

+ 1 start bit). The overall maximum supported response frame length for FAST READ is

up to 9235 bits (1024 data bytes + 2 CRC bytes = 1024  9 + 2  9 + 1 start bit), but here

the maximum frame length supported by the NFC device must be taken into account

when issuing this command.

Product data sheet

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

For a multi-byte parameter, the least significant byte is always transmitted first. For

example, when reading from the memory using the READ command, byte 0 from the

addressed block is transmitted first, followed by bytes 1 to byte 3 out of this block. The

same sequence continues for the next block and all subsequent blocks.

8.2.1 Data integrity

The following mechanisms are implemented i n the contactless communi cation link

between the NFC device and the NTAG I²C IC to ensure very reliable data transmission:

•16 bits CRC per block

•Parity bits for each byte

•Bit count checking

•Bit coding to distinguish between “1”, “0 ” and “no information”

•Channel monitoring (protocol sequence and bit stream analysis)

The commands are initiated by the NFC device and controlled by the Digital Control Unit

of the NTAG I2C IC. The command response depends on the state of the IC, and for

memory operations , also on the access conditions valid for the corresponding page.

Product data sheet

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

8.2.2 RF communication principle

The overall RF communication principle is summarized in Figure 5.

8.2.2.1 IDL E state

After a power-on reset (POR), the NTAG I2C switches to the IDLE state. It only exits this

state when a REQA or a WUPA command is received from the NFC device. Any other

data received while in this state is interpreted as an error, and the NTAG I2C remains in

the IDLE state.

After a correctly executed HLTA command e.g., out of the ACTIVE state, the default

waiting state changes from the IDLE state to the HALT state. This state can then only be

exited with a WUPA command.

8.2.2.2 READY 1 state

In the READY 1 state, the NFC de vice resolves the first part of the UID (3 bytes) using the

ANTICOLLISION or SELECT commands in cascade level 1. This state is correctly exited

after execution of the following command:

•SELECT command from cascade leve l 1: the NFC device switches the NTAG I2C into

READY2 state where the second part of the UID is resolved.

Fig 5. RF communication principle of NTAG I2C

SELECT

cascade level 2

READY 1

READY 2

SELECT

cascade level 1

ACTIVE

IDLEHALT

POR

ANTICOLLISION

HLTA

identification

and

selection

procedure

memory

operations

aaa-012797

REQA

WUPA

READ (16 Byte)

FAST_READ

WRITE

SECTOR_SELECT

GET_VERSION

Product data sheet

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

8.2.2.3 READY 2 state

In the READY 2 state, the NTAG I2C supports the NF C device in resolving the seco nd part

of its UID (4 bytes) with the cascade level 2 ANTICOLLISION command. This state is

usually exited using the cascade level 2 SELECT command.

Remark: The response of the NTAG I2C to the SELECT command is the Select

AcKnowledge (SAK) byte. In accordance with ISO/IEC 14443, this byte indicates if the

anticollision cascade procedure has finished. If finished, the NTAG I2C is now uniquely

selected and only this device will communicate with the NFC device even when other

contactless devices are present in the NFC device field.

8.2.2.4 ACTIVE state

All memory operations are operated in the ACTIVE state.

The ACTIVE state is exited with the HLTA command and upon r eception, the NTAG I2C

transits to the HALT state. Any other data received when the device is in this state is

interpreted as an e rror. Depending on its previous state, the NTAG I2C returns to either to

the IDLE state or HALT state.

8.2.2.5 HALT state

HALT and IDLE states constitute the two wait states implemented in the NTAG I2C. An

already processed NTAG I2C can be set into the HALT state using the HLTA command. In

the anticollision phase, this state helps the NFC device distinguish between processed

tags an d tags yet to be selected. The NTAG I2C can only exit this state upon execution of

the WUPA command . Any othe r da ta received when the device is in this state is

interpreted as an error, and NTAG I2C state remains unchanged.

8.3 Memory organization

The memory map is detailed in Table 4 (1 k me mo ry ) an d Table 5 (2k memor y) from the

RF interface and in Table 6 (1k memory) and Table 7 (2k memory) from the I2C interface.

The SRAM memory is not mapped from the RF interface, because in the default settings

of the NTAG I2C the Pass-through mode is not enabled. Please refer to Section 11 for

examples of memory map from the RF interface with SRAM mappin g.

The structure of manufacturing data, static lock bytes, capability container and user

memory pages (except of the user memory length) are compatible with other NTAG

products.

Any memory access which starts at a valid address and exte nds into an invalid access

region will return 00h value in the invalid region.

8.3.1 Memory map from RF interface

Memory access from the RF interface is orga nized in pages of 4 bytes each.

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

Table 4. NTAG I2C 1k memory organization from the RF interface

Sector

address Page address Byte number within a page Access

conditions

Dec. Hex. 0123

0 0 00h Serial number READ

1 01h Serial number Internal READ

2 02h Internal Static lock bytes READ/R&W

3 03h Capability Container (CC) READ&WRITE

4 04h

User memory READ&WRITE

... ...

15 0Fh

... ...

225 E1h

226 E2h Dynamic lock bytes 00h R&W/READ

227 E3h

Invalid access - returns NAK n.a.

228 E4h

229 E5h

230 E6h

231 E7h

232 E8h Configuration registers see 8.3.11

233 E9h

234 EAh Invalid access - returns NAK n.a.... ...

255 FFh

1 ... ... Invalid access - returns NAK n.a.

2 ... ... Invalid access - returns NAK n.a.

3 0 00h Invalid access - returns NAK n.a.

... ...

248 F8h Session registers see 8.3.11

249 F9h

... ... Invalid access - returns NAK n.a.

255 FFh

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

8.3.2 Memory map from I²C interface

The memory access of NTAG I²C from the I²C interface is organized in blocks of 16 bytes

each.

Table 5. NTAG I2C 2k memory organization from the RF interface

Sector

address Page address Byte number within a page Access

conditions

Dec. Hex. 0123

0 0 00h Serial number READ

1 01h Serial number Internal READ

2 02h Internal Static lock bytes READ/R&W

3 03h Capability Container (CC) READ&WRITE

4 04h

User memory READ&WRITE

... ...

15 0Fh

... ...

255 FFh

10...

1...

... ...

223 DFh

224 E0h Dynamic lock bytes 00h R&W/READ

225 E1h

Invalid access - returns NAK n.a.

226 E2h

227 E3h

228 E4h

229 E5h

230 E6h

231 E7h

232 E8h Configuration registers see 8.3.11

233 E9h

234 EAh Invalid access - returns NAK n.a.... ...

255 FFh

2 ... ... Invalid access - returns NAK n.a.

3 0 00h Invalid access - returns NAK n.a.

... ...

248 F8h Session registers see 8.3.11

249 F9h

... ... Invalid access - returns NAK n.a.

255 FFh

Product data sheet

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

Table 6. NTAG I2C 1k memory organization from the I2C interface

I2C block

address

Byte number within a block

Access

conditions

0 1 2 3

4 5 6 7

8 9 10 11

Dec. Hex. 12 13 14 15

0 00h I2C addr.* Serial number R&W/READ

Serial numb er Internal READ

Internal Static lock bytes READ/R&W

Capability Container (CC) READ&WRITE

1 01h User memory READ&WRITE... ...

55 37h

56 38h User memory READ&WRITE

User memory READ&WRITE

Dynamic lock bytes 00h READ&WRITE

00h 00h 00h 00h READ

57 39h

Invalid access - returns NAK n.a.

58 3Ah Configuration registers see 8.3.11

00h 00h 00h 00h READ

00h 00h 00h 00h

59 3Bh Invalid access - returns NAK n.a.... ...

247 F7h

248 F8h SRAM memory (64 bytes) READ&WRITE... ...

251 FBh

... ... Invalid access - returns NAK n.a.

254 FEh Session registers

(requires READ register command) see 8.3.11

00h 00h 00h 00h READ

00h 00h 00h 00h

... ... Invalid access - returns NAK n.a.

Remark: * The byte 0 of bl ock 0 is always read as 04h. Writing to this byte modifies the I2C

address.

Product data sheet

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

Table 7. NTAG I2C 2k memory organization from the I2C interface

I2C block

address

Byte number within a block

Access

conditions

0 1 2 3

4 5 6 7

8 9 10 11

Dec. Hex. 12 13 14 15

0 00h I2C addr.* Serial number R&W/READ

Serial numb er Internal READ

Internal Static lock bytes READ/R&W

Capability Container (CC) READ&WRITE

1 01h User memory READ&WRITE... ...

119 77h

120 78h Dynamic lock bytes 00h READ&WRITE

00h 00h 00h 00h READ00h 00h 00h 00h

00h 00h 00h 00h

121 79h

Invalid access - returns NAK n.a.

122 7Ah Configuration registers see 8.3.11

00h 00h 00h 00h READ

00h 00h 00h 00h

127 7Bh Invalid access - returns NAK n.a.... ...

247 F7h

248 F8h SRAM memory (64 bytes) READ&WRITE... ...

251 FBh

... ... Invalid access - returns NAK n.a.

254 FEh Session registers

(requires READ register command) see 8.3.11

00h 00h 00h 00h READ

00h 00h 00h 00h

... ... Invalid access - returns NAK n.a.

Remark: * The byte 0 of bl ock 0 is always read as 04h. Writing to this byte modifies the I2C

address.

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

8.3.3 EEPROM

The EEPROM is a non volatile memory that stores th e 7 byt e UID , the mem o ry lock

conditions, IC configuration information and th e 1 904 b ytes use r data (888 byte user data

in case of the NTAG I2C 1k version).

8.3.4 SRAM

For frequently changing data, a volatile memory of 64 bytes with unlimited endurance is

built in. The 64 bytes are mapped in a similar way as done in the EEPROM, i.e., 64 bytes

are seen as 16 pages of 4 bytes.

The SRAM is only available if the tag is powered via the VCC pin.

The SRAM is located at the end of the memory space and it is always directly accessible

by the I2C host (addresses F8h to FBh). An RF reader cannot access the SRAM memory

in normal mode (i.e., out side the Pass-through mode). The SRAM is only accessible by

the RF reader if the SRAM is mirrored onto the EEPROM memory space.

With Memory Mirror enabled (SRAM_MIRROR_ON_OFF = 1b - see Section 11.2), the

SRAM can be mirrored in the User Memory (page 1 to page 116 - see Section 11.2) for

access from the RF side.

The Memory mirror must be enabled once both interfaces are ON as this feature is

disabled after each POR.

The register SRAM_MIRROR_BLOCK (see Table 14) indicates the address of the first

page of the SRAM buffer. In the case where the SRAM mirror is enabled and the READ

command is addressing blocks where the SRAM mirror is located, the SRAM mirror byte

values will be returned instead of the EEPROM byte values. Similarly, if the tag is not VCC

powered, the SRAM mirror is disabled and reading out the bytes related to the SRAM

mirror position would return the values from the EEPROM.

In the Pass-through mode (PTHRU_ON_OFF = 1b - see Section 8.3.11), the SRAM is

mirrored to the fixe d address 240 - 255 for RF access (se e Section 11) in the first memory

sector for NTAG I2C 1k and in the seco nd memory sector for NTAG I2C 2k.

8.3.5 UID/serial number

The unique 7-byte serial number (UID) is programmed into the first 7 bytes of memory

covering page addresses 00h and 01h - see Figure 6. These bytes are programmed and

write protected in the production test.

SN0 holds the Manufacturer ID for NXP Semiconductors (04h) in accordance with

ISO/IEC 14443-3.

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

8.3.6 Static lock bytes

The bits of byte 2 and byte 3 of page 02h (via RF) or byte 10 and 11 address 0h (via I2C)

represent the field programmable, read-only locking mechanism (see Figure 7). Each

page from 0 3h (CC) to 0Fh can be individually locked by setting the corresponding locking

bit Lx to logic 1 to prevent further write access. After locking, the corresponding page

becomes read-only memory.

The three least significant bits of lock byte 0 are the block-locking bits. Bit 2 controls

pages 0Ah to 0Fh (via RF), bit 1 controls pages 04h to 09h (via RF) and bit 0 controls

page 03h (CC). Once the block-locking bits are set, the locking configur ation for the

corresponding memory area is frozen.

For example, if BL15-10 is set to logic 1, then bits L15 to L10 (lock byte 1, bit[7:2]) can no

longer be changed. The static locking and block-locking bits are set by the bytes 2 and 3

of the WRITE command to page 02h. The contents of the lock bytes are bit-wise OR’ed

and the result then becomes the ne w content of the lock bytes.

This process is irreversible from RF perspective. If a bit is set to logic 1, it cannot be

changed back to logic 0. From I²C perspe ctive, the bit s can be reset to 0b by writing bytes

10 and 11 of block 0. I²C address is coded in byte 0 of block 0 and may be changed

unintentionally.

The contents of bytes 0 and 1 of page 02h are unaffected by the corresponding dat a bytes

of the WRITE.

The default value of the static lock bytes is 00 00h.

Fig 6. UID/serial number

aaa-012802

MSB LSB

page 0

byte

manufacturer ID for NXP Semiconductors (04h)00000100

UID0 UID1 UID2 UID3 UID4 UID5 UID6 SAK

page 1 page 2

0123

ATQA1

ATQA07 bytes UID

lock bytes

Fig 7. Static lock bytes 0 and 1

CC BL

15-10 BL

9-4 BL

MSB

page 2

Lx locks page x to read-only

BLx blocks further locking for the memory area x

lock byte 0

lock byte 1

123

LSB L

15 L

14 L

13 L

12 L

11 L

10 L

MSB LSB

aaa-006983

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

8.3.7 Dynamic Lock Bytes

To lock the pages of NTAG I2C starting at page address 10h and onwards, the dynamic

lock bytes are used. The dynamic lock bytes are located at p ag e E2h sector 0 (NTAG I2C

1k) or address E0h sector 1 (NTAG I2C 2k). The three lock bytes cover the memory area

of 830 data bytes (NTAG I2C 1k) or 1846 dat a bytes (NTAG I2C 2k). The granularity is 16

pages for NTAG I2C 1k (see Figure 8) and 32 pages for NTAG I2C 2k (see Figure 9)

compared to a single page for the first 48 bytes (see Figure 7).

Remark: Set all bits marked with RFUI to 0 when writing to the dynamic lock bytes.

Fig 8. NTAG I2C 1k Dynamic lock bytes 0, 1 and 2

aaa-008092

0123

page 226 (E2h)

LOCK PAGE

128-143

MSB LSB

bit 7 6

LOCK PAGE

112-127

LOCK PAGE

96-111

LOCK PAGE

80-95

LOCK PAGE

64-79

LOCK PAGE

48-63

LOCK PAGE

32-47

LOCK PAGE

16-31

LOCK PAGE

224-225

543210

RFUI

MSB LSB

bit 7 6

RFUI

LOCK PAGE

208-223

LOCK PAGE

192-207

LOCK PAGE

176-191

LOCK PAGE

160-175

LOCK PAGE

144-159

543210

RFUI

MSB LSB

bit 7 6

BL 208-225

BL 176-207

BL 144-175

BL 112-143

BL 80-111

BL 48-79

BL 16-47

543210

Product data sheet

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

The default value of the dynamic lock bytes is 00 00 00h. The value of Byte 3 is always

00h when read.

Reading the 3 bytes for the dynamic lock bytes and the Byte 3 (00h) from RF interface

(address E2h sector 0 (NTAG I2C 1k) or E0h sector 1 (NTAG I2C 2k) or from I2C (address

38h (NTAG I2C 1k) or 78h (NTAG I2C 2k)) will also return a fixed value for the next 12

bytes of 00h.

Like for the static lock bytes, this process of modifying the dynamic lock bytes is

irreversible from RF perspective. If a bit is set to log ic 1, it cannot be changed back to

logic 0. From I²C perspective, the bits can be reset to 0b.

Fig 9. NTAG I2C 2k Dynamic lock bytes 0, 1 and 2

0 1 2 3page 224 (E0h)

Block Locking (BL) bits

LOCK PAGE

240-271

MSB LSB

bit 7 6 5 4 3 2 1 0

MSB LSB

bit 7 6 5 4 3 2 1 0

MSB LSB

bit 7 6 5 4 3 2 1 0

aaa-012803

LOCK PAGE

208-239

LOCK PAGE

176-207

LOCK PAGE

144-175

LOCK PAGE

112-143

LOCK PAGE

80-111

LOCK PAGE

48-79

LOCK PAGE

16-47

RFUIBL 464-479

LOCK PAGE

464-479

LOCK PAGE

432-463

LOCK PAGE

400-431

LOCK PAGE

368-399

LOCK PAGE

336-367

LOCK PAGE

304-335

LOCK PAGE

272-303

BL 400-463

BL 336-399

BL 272-335

BL 208-271

BL 144-207

BL 80-143

BL 16-79

Product data sheet

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

8.3.8 Capability Container (CC bytes)

The Capability Container CC (page 03h) is programmed during the IC production

according to the NFC Fo rum Type 2 Tag specification (see Ref. 1). These bytes may be

bit-wise modified by a WRITE command from the I²C or RF interface . Once set to 1b , it is

only possible to reset it to 0b from I²C perspective. I²C address (byte 0) and static lock

bytes (byte 10 and byte 11) are coded in block 0 and may be changed unintentionally.

See examples for NTAG I2C 1k version in Figure 10 and for NTAG I2C 2k version in

Figure 11.

The default values of the CC bytes at delivery are defined in Section 8.3.10.

8.3.9 User Memory pages

Pages 04h to E1h via the RF interface - Block 01h to 37h, plus the first 8 bytes of block

38h via the I2C interface are the user memory read/write areas for NTAG I2C 1k version.

Pages 04h (sector 0) to DFh (sector 1) via the RF interface - Block 1h to 77h via the I2C

interface are the user memory read/write areas for NTAG I2C 2k version.

The default values of the data pages at delivery are defined in Section 8.3.10.

Fig 10. CC bytes of NTAG I2C 1k version

Fig 11. CC bytes of NTAG I2C 2k version

aaa-012804

byte E1h 10h 6Dh 00h

Example NTAG I

C 1k version

CC bytes

byte 0123

page 3

default value (initialized state)

11100001 00010000 01101101 00000000

write command to page 3

00000000 00000000 00000000 00001111

result in page 3 (read-only state)

11100001 00010000 01101101 00001111

aaa-012805

Example NTAG I2C 2k version

CC bytesdefault value (initialized state)

11100001 00010000 11101010 00000000

write command to page 3

00000000 00000000 00000000 00001111

result in page 3 (read-only state)

11100001 00010000 11101010 00001111

data E1h 10h EAh 00h

CC bytes

byte 0 1 2 3

page 3

Product data sheet

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

8.3.10 Memory content at delivery

The capability container in page 03h and the page 04h and 05h of NTAG I2C is

pre-programmed to the initialized state according to the NFC Forum Type 2 Tag

specification (see Ref. 1) as defined in Table 8 (NTAG I2C 1k version) and Table 9 (NTAG

I2C 2k version). This content is READ only from the RF side and READ&WRITE from the

I²C side.

The User memory contains an empty NDEF TLV.

Remark: The default conten t of the data pages from page 05h onwards is not defined at

delivery.

8.3.11 NTAG I 2C configuration and session registers

NTAG I2C functionalities can be configured and read in two sep ara te loca tions depending

if the configurations shall be effective within the communication session (ses sio n

registers) or by default after Power On Reset (POR) (configuration bits).

The configuration registers of pages E8h to E9h (sector 0 - see Table 10, or 1 - see

Table 11, depending if it is for NTAG I²C 1k or 2k) via the RF interface or block 3Ah or 7Ah

(depending if it is for NTAG I²C 1k or 2k) via the I2C interface are used to configure the

default functionalities of the NTAG I2C. Those bit values are stored in the EEPROM and

represent the defaul t settings to be effective a fter POR. Their values can be read & written

by both interfaces when applicable and when not locked by the register lock bits (see

REG_LOCK in Table 13).

Table 8. Memory content at delivery NTAG I2C 1k version

Page Address Byte number within page

0 1 2 3

03h E1h 10h 6Dh 00h

04h 03h 00h FEh 00h

05h 00h 00h 00h 00h

Table 9. Memory content at delivery NTAG I2C 2k version

Page Address Byte number within page

0 1 2 3

03h E1h 10h EAh 00h

04h 03h 00h FEh 00h

05h 00h 00h 00h 00h

Table 10. Configuration registers NTAG I²C 1k

RF address

(sector 0) I2C Address Byte number

Dec Hex Dec Hex 0 1 2 3

232 E8h 58 3Ah NC_REG LAST_NDEF_BLOCK SRAM_MIRROR_

BLOCK WDT_LS

233 E9h WDT_MS I2C_CLOCK_STR REG_LOCK 00h fixed

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

The session registers Pages F8h to F9h (sector 3) via the RF interface or block FEh via

I2C, see Table 12, are used to con fig ur e or mo nito r the value s of th e cur ren t

communication session. Those bits can only be read via the RF interface but both read

and written via the I2C interface.

Both the session and the configuration bits have the same register except the

REG_LOCK bits, which are only available in the configuration bits and the NS_REG bits

which are only available in the session registers. After POR, the configura tio n bits are

loaded into the session registers. During the communication session, the values can be

changed, but the related effect will only be visible within the communication session for

the session registers or after POR for the configuration bits. After POR, the registers

values will be again brought back to the default configuration values.

All registers and configuration default values, access conditions and descriptions are

defined in Table 13 and Table 14.

Reading and writing the session re gisters via I²C can only be done via the READ and

WRITE registers operation - see Section 9.8.

Table 11. Configuration registers NTAG I²C 2k

RF address

(sector 1) I2C Address Byte number

Dec Hex Dec Hex 0 1 2 3

232 E8h 122 7Ah NC_REG LAST_NDEF_BLOCK SRAM_MIRROR_

BLOCK WDT_LS

233 E9h WDT_MS I2C_CLOCK_STR REG_LOCK 00h fixed

Table 12. Session register s NTAG I²C 1k and 2k

RF address

(sector 3) I2C Address Byte number

Dec Hex Dec Hex 0 1 2 3

248 F8h 254 FEh NC_REG LAST_NDEF_BLOCK SRAM_MIRROR

_BLOCK WDT_LS

249 F9h WDT_MS I2C_CLOCK_STR NS_REG 00h fixed

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

Table 13. Configuration bytes

Bit Field Access

via RF Access

via I²C Default

values Description

Configuration register: NC_REG

7 I2C_RST_ON_OFF R&W R&W 0b enables soft reset through I²C repeated start -

see Section 9.3

6RFU READ R&W 0b reserved for future use - keep at 0b

5 FD_OFF R&W R&W 00b defines the event upon which the signal output

on the FD pin is brought up

00b… if the field is switched off

01b… if the field is switched off or the tag is set

to the HALT state

10b… if the field is switched off or the last page

of the NDEF message has been read (defined

in LAST_NDEF_BLOCK)

41 1b... (if FD_ON = 1 1b) if the field is switched off

or if last data is read by I²C (in Pass-through

mode RF ---> I²C) or last data is written by I²C

(in Pass-through mode I²C---> RF)

11b... (if FD_ON = 00b or 01b or 10b) if the field

is switched off

See Section 8.4 for more details

3 FD_ON R&W R&W 00b defines the even t upon which the signal output

on the FD pin is brought down

00b… if the field is switched on

01b... by first valid start of communication (SoC)

10b... by selection of the tag

211b (in Pass-through mode RF-->I²C) if the data

is ready to be read from the I²C interface

11b (in Pass-through mode I²C--> RF) if the

data is re ad by th e R F in te rfa c e

See Section 8.4for more details

1 RFU READ R&W 0b reserved for future use - keep at 0b

0 TRANSFER_DIR R&W R&W 1b defines the data flow direction for the data

transfer

0b… From I²C to RF interface

1b… From RF to I²C interface

In case the Pass-through mode is not enabled

0b… no WRITE access from the RF side

Product data sheet

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

Configuration register: LAST _NDEF_BLOCK

7-0 LAST_NDEF_BLOCK R&W R&W 00h Address of last BLOCK (16bytes) of NDEF

message from I²C addressing. An RF read of

the last page of the I2C block, specified by

LAST_NDEF_BLOCK sets the register

NDEF_DATA_READ to 1b and triggers

FD_OFF if FD_OFF is set to 10b

01h is page 04h (first page of the User Memory)

from RF addressing

02h is page 08h

03h is page 0Ch

………

37h is page DCh - memory sector 0 (last

possible page of User memory for NTAG I²C 1k)

......

77h is page DCh - memory sector 1 (last page

possible of the User Memory for NTAG I²C 2k)

Configuration register: SRAM_MIRROR_BLOCK

7-0 SRAM_MIRROR_

BLOCK R&W R&W F8h Address of first BLOCK (16bytes) of SRAM

buff er when mirrored into the User memory from

I²C addressing

01h is page 04h (first page of the User Memory)

from RF addressing

02h is page 08h

03h is page 0Ch

………

34h is page D0h - memory sector 0 (last

possible page of User memory for NTAG I²C 1k)

......

74h is page D0h - memory sector 1 (last page

possible of the User Memory for NTAG I²C 2k)

Configura t ion register: WDT_LS

7-0 WDT_LS R&W R&W 48h Least Significant byte of watchdog time

control register

Table 13. …continuedConfiguration bytes

Bit Field Access

via RF Access

via I²C Default

values Description

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

Configuration reg is ter: WDT _MS

7-0 WDT_MS R&W R&W 08h Most Significant byte of watchdog time

control register.

When writing WDT_MS byte, the content of

WDT_MS and WDT_LS gets active for the

watchdog timer.

Configuration register: I2C_CLOCK_STR

7-1 RFU READ READ 0 ...0b reserved for future use, all 7 bits locked to 0b

0 I2C_CLOCK_STR R&W R&W 1b Enables (1b) or disable (0b) the I²C clock

stretching

Configuration reg ister: REG_LOCK

7-2 RFU READ READ 0 00000b reserved for future use, all 6 bits locked to 0b

1 REG_LOCK_I2C R&W R&W 0b 0b… Enable writing of the configuration bytes

via I²C

1b… Disable writing of the configuration bytes

via I²C

Once set to 1b, cannot be reset to 0b anymore.

0 REG_LOCK_RF R&W R&W 0b 0b… Enable writing of the configuration bytes

via RF

1b… Disable writing of the configuration bytes

via RF

Once set to 1b, cannot be reset to 0b anymore.

Table 13. …continuedConfiguration bytes

Bit Field Access

via RF Access

via I²C Default

values Description

Product data sheet

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

Table 14. Session register bytes

Bit Field Access

via RF Access

via I²C Default

values Description

Session register: NC_REG

7 I2C_RST_ON_OFF READ R&W - see configuration bytes description

6PTHRU_ON_OFF READ R&W 0b 1b… enables data transfer via the SRAM buffer

(Pass-through mode)

5 FD_OFF READ R&W

3 FD_ON READ R&W - see configuration bytes description

1 SRAM_MIRROR_

ON_OFF READ R&W 0b 1b enables SRAM mirroring

0 PTHRU_DIR READ R&W see configuration bytes description

Session register: LAST_NDEF_BLOCK

7-0 LAST_NDEF_

BLOCK READ R&W - see configuration bytes description

Session register: SRAM_MIRROR_BLOCK

7-0 SRAM_MIRROR_

BLOCK READ R&W - see configuration bytes description

Session register: WDT_LS

7-0 WDT_LS READ R&W - see configuration bytes description

Product data sheet

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

Session register: WDT_MS

7-0 WDT_MS READ R&W - see configuration bytes description

Session register: I2C_CLOCK_STR

7-1 RFU READ READ - reserved for future use, all 7 bits locked to 0b

0 I2C_CLOCK_STR READ READ See configuration bytes description

Session register: NS_REG

7 NDEF_DATA_READ READ READ 0b 1b… all data bytes read from the address

specified in LAST_NDEF_BLOCK. value is

reset to 0b when read

6I2C_LOCKED READ R&W 0b 1b… Memory access is locked to the I²C

interface

5 RF_LOCKED READ READ 0b 1b… Memory access is locked to the RF

interface

4 SRAM_I2C_ READY READ READ 0b 1b… dat a is ready in SR AM buffer to be read by

I2C

3 SRAM_RF_R EADY READ READ 0b 1b… dat a is ready in SRAM buf fer to be read by

2 EEPROM_WR_ERR READ R&W 0b 1b… HV volt age error during EEPROM write or

erase cycle

Needs to be written back via I²C to 0b to be

cleared

1 EEPROM_WR_BUSY READ READ 0b 1b… EEPROM write cycle in progress - access

to EEPROM disabled

0b… EEPROM access possible

0 RF_FIELD_PRESENT READ READ 0b 1b… RF field is detected

Table 14. …continuedSession register bytes

Bit Field Access

via RF Access

via I²C Default

values Description

Product data sheet

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

8.4 Configurable Field Detection Pin

The field detection feature provides the capability to trigger an external device (e.g.

Controller) or switch on the connected circuitry by an external power management unit

depending on activities on the RF interface.

The conditions for the activation of the field detection signal (FD_ON) can be:

•The presence of the RF field

•The detection of a valid command (Start of Communication)

•The selection of the IC.

The conditions for the de-activation of the field detection signal (FD_OFF) can be:

•The absence of the RF field

•The detection of the HALT state

•The RF interface ha s re ad the last part of the NDEF me ssa g e defin ed with

LAST_NDEF_BLOCK

All the various combinations of configurations are described in Table 13 and illustrated in

Figure 12, Figure 13 and Figure 14 for all various combination o f the filed detection signal

configuration.

The field detection pin can also be used as a handshake mechanism in the Pass-through

mode to signal to the external microcontroller if

•New data are written to SRAM on the RF interface

•Data written to SRAM from the microcontroller are read via the RF interface.

See Section 11 for more information on this handshake mechanism.

Product data sheet

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

Fig 12. Il lu stra tio n of the fie ld de te ction feature when config ured for simple field

detection

aaa-017239

RF field

switches ON

First valid start of

communication

Tag selected

Tag set to HALT

OFF

HIGH

LOW

RF field

FD pin

Event

RF_FIELD_PRESENT 0

01h

NS_REG

FD_ON = 00b

FD_OFF = 00b

NC_REG

RF field

switches OFF

Product data sheet

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

Fig 13. Illustration of the field detection feature when configured for first valid start of

communication detection

aaa-017242

RF field

switches ON

First valid start of

communication

Tag selected

Tag set to HALT

OFF

HIGH

LOW

RF field

FD pin

Event

RF_FIELD_PRESENT 0

15h

NS_REG

FD_ON = 01b

FD_OFF = 01b

NC_REG

RF field

switches OFF

Product data sheet

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

Fig 14. Illustration of the field detection feature when configured for selection of the tag

detection

aaa-017243

RF field

switches ON

First valid start of

communication

Tag selected

Tag set to HALT

OFF

HIGH

LOW

RF field

FD pin

Event

RF_FIELD_PRESENT 0

29h

NS_REG

FD_ON = 10b

FD_OFF = 10b

NC_REG

RF field

switches OFF

Product data sheet

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

8.5 Watchdog timer

In order to allow the I²C interface to perform all necessary commands (READ, WRITE...),

the memory access remains locked to the I²C interface until the register I2C_LOCKED is

cleared by the host - see Table 14.

In order however to avoid that the memory stays 'locked' to the I²C for a long period of

time, it is possible to program a watchdog timer to unlock the I2C host from the tag, so tha t

the RF reader can access the tag after a period of time of inactivity. The host itself will not

be notified of this event directly, but the NS_REG register is updated accordingly (the

The default value is set to 20 ms (848h), but the watch dog timer can be freely set from

0001h (9.4 3 s) up to FFFFh (617.995 ms). The timer starts ticking when the

communication between the NTAG I2C and the I2C interface starts. In case the

communication with the I2C is still going on after the watchdog timer expires, the

communicat ion wi ll co nt inu e un til th e comm u nica tio n has co mp le te d. T hen th e status

In the case where the communication with the I2C inter face has completed befor e the end

of the timer and the status register I2C_LOCKED was not cleared by the host, it will be

cleared at the end of the watchdog timer.

The watchdog timer is only effective if the VCC pin is powered and will be reset and

stopped if the NTAG I2C is not VCC powered or if the register status I2C_LOCKED is set

to 0b and RF_LOCKED is set to 1b.

8.6 Energy harvesting

The NTAG I2C provides the capability to supply external low power devices with energy

generated from the RF field of a NFC device.

The voltage and current from the energy harvesting depend on various parameters, such

as the strength of the RF field, the t ag anten na size, or the dist ance fr om the NF C device.

At room temperature, NTAG I2C could provide typically 5 mA at 2 V on the VOUT pin with

an NFC Phone.

Operating NTAG I2C in energy harvesting mode requires a number of precautions:

•A significant capacitor is needed to guarantee operation during RF communication.

The tota l capa citor be tween VOUT and GND sha ll be in th e range of 15 0nF to 200 nF.

•If NTAG I2C also powers the I2C bus, then VCC must be connected to VOUT, and

pull-up resistors on the SCL and SDA pins must be sized to control SCL and SDA sink

current when those lines are pulled low by NTAG I2C or the I2C host

•If NTAG I2C also powers the Field Detect bus, then the pull-up resistor on the Field

Detect line must be sized to control the sink cur rent into the Field Detect pin when

NTAG I2C pulls it low

•The NFC reader device communicating with NTAG I2C shall apply polling cycles

including an RF Field Off condition of at least 5.1 ms as defined in NFC Forum Activity

specification (see Ref. 4, chapter 6).

Note that increasing the output current on the Vout decreases the RF communication

range.

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NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

9. I²C commands

For det ails about I2C interface refer to Ref. 3.

The NTAG I2C supports the I2C protocol. This protocol is summarized in Figure 15. Any

device that sends data onto the bus is defined as a transmitter, and any device that reads

the data from the bus is defined as a receiver . The device that controls the da ta transfer is

known as the “bus master”, and th e other as the “slave” device. A data transfer can only

be initiated by the bus master, which will also provide the serial clock for synchronization.

The NTAG I2C is always a slave in all communications.

9.1 Start condition

Start is identified by a falling edge of Serial Data (SDA), while Serial Clock (SCL) is stable

in the high state. A Start cond ition mu st pr ec ed e any data transfe r com ma n d. The NTAG

I2C continuously monitors SDA (except during a Write cycle) and SCL for a Start

condition, and will not respond unless one is given.

9.2 Stop condition

Stop is identified by a rising edge of SDA while SCL is stable and driven high. A Stop

condition terminates communication between the NTAG I2C and the bus master. A Stop

condition at the end of a Write command triggers the internal Write cycle.

Fig 15. I2C bus protocol

SCL

SDA

SCL 123 789

123 789

ACKMSB

Start

Condition SDA

Input SDA

Change Stop

Condition

Stop

Condition

Start

Condition

SDA

SCL

SDA

001aao231

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NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

9.3 Soft reset feature

In the case where the I2C interface is constantly powered on, NTAG I2C can trigger a reset

of the I2C interface via its soft reset feature- see Table 13.

When this feature is enabled, if the microcontroller does not issue a stop condition

between two start conditions, this situation will trigger a reset of the I2C interface and

hence may hamper the communication via the I2C interface.

9.4 Acknowledge bit (ACK)

The acknowledge bit is used to indi cate a successful byte transfer. The bus transmitter,

whether it is the bus master or slave device, releases Serial Data (SDA) af ter sending

eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA)

low to acknowledge the receipt of the eight data bits.

9.5 Data input

During data input, the NTAG I2C samples SDA on the rising edge of SCL. For correct

device opera tion, SDA mu st be stable durin g the rising edge of SCL, and the SDA signal

must change only when SCL is driven low.

9.6 Addressing

To start communication between a bus master and the NTAG I2C sla ve de vic e, the bu s

master must initiate a Start condition. Following this initiation, the bus master sends the

device address. T he NTAG I2C address from I2C consists of a 7-bit device identifier (see

Table 15 for default value).

The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write

operations.

If a match occurs on the device address, the NTAG I2C gives an acknowledgment on SDA

during the 9th bit time. If the NTAG I2C does not match the device select code, it deselects

itself from the bus and clear the register I2C_LOCKED (see Table 12).

[1] Initial values - can be changed.

The I2C address of the NTAG I2C (byte 0 - block 0h) can only be modified by the I2C

interface. Both interfaces have no READ access to this address and a READ command

from the RF or I²C interface to this byte will only return 04h (manufacturer ID for NXP

Semiconductors - see Figure 6).

Table 15. Default NTAG I2C address from I2C

Device address R/W

b7 b6 b5 b4 b3 b2 b1 b0

Value 1[1] 0[1] 1[1] 0[1] 1 [1] 0 [1] 1 [1] 1/0

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

9.7 READ and WRITE Operation

Fig 16. I2C READ and WRITE operation

aaa-012811

7 bits SA and ‘0’Host

Tag

Start Stop

Stop

D0 D1

D15

MEMA

A A A

A A

7 bits SA and ‘0’Host Start

Write:

Read:

7 bits SA and ‘1’StartStopMEMA

A A

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

The READ and WRITE operation handle always 16 bytes to be read or written (one block

- see Table 7)

For the READ operation (see Figure 16), following a Start condition, the bus master/host

sends the NTAG I2C slave address code (SA - 7 bits) with the Rea d/Write bit (R W) reset to

0. The NTAG I2C acknowledges this (A), and waits for one address byte (MEMA), which

should correspond to the address of the block of memory (SRAM or EEPROM) that is

intended to be read. The NT AG I2C re sponds to a valid address byte with an acknowledge

(A). A Stop condition can be then issued. Then the host again issu es a start condition

followed by the NTAG I2C slave address with the Read/Write bit set to 1b. When

I2C_CLOCK_STR is set to 0b, a pause of at least 50 s shall be kept before this start

condition. The NTAG I2C acknowledges this (A) and sends the first byte of data read

(D0).The bus master/host acknowledges it (A) and the NTAG I2C will subsequently

transmit the followin g 15 byte s of mem o ry re ad with an acknowledge from the host after

every byte. After the la st byte o f memo ry data has been tran smi tted by the NTAG I2C, the

bus master/host will acknowledge it and issue a Stop condition.

For the WRITE operation (see Figure 16), following a Start condition, the bu s master/host

sends the NTAG I2C slave address code (SA - 7 bits) with the Rea d/Write bit (R W) reset to

0. The NTAG I2C acknowledges this (A), and waits for one address byte (MEMA), which

should correspond to the address of the block of memory (SRAM or EEPROM) that is

intended to be written. The NTAG I2C responds to a valid address byte with an

acknowledge (A) and, in the case of a WRITE operation, the bus ma ster/host starts

transmitting each 16 bytes (D0...D15) that shall be written at the specified address with an

acknowledge of the NTAG I²C after each byte (A). Afte r the last byte acknowledge from

the NTAG I²C, the bus master/host issues a Stop condition.

The memory address accessible via the READ and WRITE operations can only

correspond to the EEPROM or SRAM (respectively 00h to 3Ah or F8h to FBh for NTAG

I²C 1k and 00h to 7Ah or F8h to FBh for NTAG I²C 2k).

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

9.8 WRITE and READ register operation

In order to modify or read the session register bytes (see Table 14), NTAG I²C requires the WRITE and READ register

operation (see Figure 17).

Fig 17. WRITE and READ register operation

aaa-012812

7 bits SA and ‘0’Host

Tag

Start

Stop

MEMA REGA

A A

7 bits SA and ‘0’Host Start

Write:

Read:

7 bits SA and ‘1’StartStop

Stop

MEMA

MASK REGDAT

REGDAT

REGA

A A

A A A

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

For the READ register operation, followin g a S tart condition the bus ma ster/host sends the

NTAG I²C slave address code (SA - 7 bits) with the Read/Write bit (R W) reset to 0. The

NTAG I2C acknowledges this (A), and waits for one address byte (MEMA) which

corresponds to the address of the block of memory with the session register bytes (FEh).

The NTAG I2C responds to the address byte with an acknowledge (A). Then the bus

master/host issues a register address (REGA), which corresponds to the address of the

targeted byte inside the block FEh (00h, 01h...to 07h) and then waits for the Stop

condition.

Then the bus master/host again issues a start condition followed by the NTAG I²C slave

address with the Read/Write bit set to 1b. The NTAG I²C acknowledges this (A), and

sends the selected byte of session reg ister dat a (REGDAT) within the block FEh. The bus

master/host will acknowledge it and issue a Stop condition.

For the WRITE register operation, following a Start condition, the bus master/host sends

the NTAG I²C slave address code (SA - 7 bits) with the Read/Write bit (RW) reset to 0.

The NTAG I2C acknowledges this (A), and waits for one address byte (MEMA), which

corresponds to the address of the block of memory within the session register by tes

(FEh). After the NTAG I2C acknowledge (A), the bus master/host issues a register

address (REGA), which corresponds to the address of the targeted byte inside the block

FEh (00h, 01h. ..t o 07 h ). After ackno wle dg e men t (A ) by NTAG I2C, the bus master/host

issues a MASK byte that defines exactly which bits shall be modified by a 1b bit value at

the corresponding bit positio n. Following the NTAG I²C acknowledge (A), the new register

data (one byte - REGDAT) to be written is transmitted by the bus master/host. T he NTAG

I²C acknowledges it (A), and the bus master/host issues a stop condition.

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

10. RF Command

NTAG activation follows the ISO/IEC 14443 Type A specification. After NTAG I2C has

been selected, it can either be deactivated using the ISO/IEC 14443 HALT command, or

NTAG commands (e.g., READ or WRITE) can be performed. For more details about the

card activation refer to Ref. 2.

10.1 NTAG I2C command overview

All available commands for NTAG I2C are shown in Table 16.

[1] Unless otherwise specified, all commands use the coding and framing as described in Ref. 1.

10.2 Timing

The command and response timing shown in this document are not to scale and va lues

are rounded to 1 s.

All given command and response times refer to the data frames, including start of

communication and end of communication. They do not include the encoding (like the

Miller pulses). An NFC device data frame contains the start of communication (1

“start bit”) and the end of communication (one logic 0 + 1 bit length of unmodulated

carrier). An NFC tag data frame contains the start of communication (1 “start bit”) and the

end of communication (1 bit length of no subcarrier).

The minimum command response time is specified according to Ref. 1 as an integer n,

which specifies the NFC device to NFC tag frame delay time. The frame delay time from

NFC tag to NFC device is at least 87 s. The maximum command response time is

specified as a time-out value. Depending on the command, the TACK value specified for

command responses defines the NFC device to NFC tag frame delay time. It does it for

either the 4-bit ACK value specified or for a data frame.

All timing can be measured according to the ISO/IEC 14443-3 frame specification as

shown for the Frame Delay Time in Figure 18. For more details refer to Ref. 2.

Table 16. Command overview

Command[1] ISO/IEC 14443 NFC FORUM Command code

(hexadecimal)

Request REQA SENS_REQ 26h (7 bit)

Wake-up WUPA ALL_REQ 52h (7 bit)

Anticollision CL1 Anticollision CL1 SDD_REQ CL1 93h 20h

Select CL1 Select CL1 SEL_REQ CL1 93h 70h

Anticollision CL2 Anticollision CL2 SDD_REQ CL2 95h 20h

Select CL2 Select CL2 SEL_REQ CL2 95h 70h

Halt HLTA SLP_REQ 50h 00h

GET_VERSION - - 60h

READ - READ 30h

FAST_READ - - 3Ah

WRITE - WRITE A2h

SECTOR_SELECT SECTOR_SELECT C2h

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

Remark: Due to the coding of commands, the measured timings usually e xcludes (a part

of) the end of communication. Consider this factor when comparing the specified with the

measured times.

10.3 NTAG ACK and NAK

NTAG uses a 4 bit ACK / NAK as shown in Table 17.

10.4 ATQA and SAK responses

NTAG I2C replies to a REQA or WUPA command with the ATQA value shown in Table 18.

It replies to a Select CL2 command with the SAK value shown in Table 19. The 2-byte

ATQA value is transmitted with the least significant byte first (44h).

Fig 18. Frame Delay Time (from NFC device to NFC tag), TACK and TNAK

last data bit transmitted by the NFC device

FDT = (n* 128 + 84)/fc

first modulation of the NFC TAG

FDT = (n* 128 + 20)/fc

aaa-006986

128/fc

logic „1“

128/fc

logic „0“

256/fc

end of communication (E)

256/fc

end of communication (E)

128/fc

start of

communication (S)

128/fc

start of

Table 17. ACK and NAK values

Code (4-bit) ACK/NAK

Ah Acknowledge (ACK)

0h NAK for invalid argument (i.e. invalid page address)

1h NAK for parity or CRC error

3h NAK for Arbiter locked to I²C

7h NAK for EEPROM write error

Table 18. ATQA response of the NTA G I2C

Bit number

Sales type Hex value 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

NTAG I2C 00 44h 0000000001000100

Table 19. SAK response of the NTAG I2C

Bit number

Sales type Hex valu e 8 7 6 5 4 3 2 1

NTAG I2C 00h 00000000

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

Remark: The ATQA coding in bits 7 and 8 indicate the UID size according to

ISO/IEC 14443 independent from the settings of the UID usage.

Remark: The bit numbering in the ISO/IEC 144 43 specification start s with LSB = bit 1 and

not with LSB = bit 0. So 1 byte counts bit 1 to bit 8 instead of bit 0 to bit 7.

10.5 GET_VERSION

The GET_VERSION command is used to r etrie ve information about the NTAG family, the

product version, storage size and othe r product data required to identify the specific NTAG

I2C.

This command is also available on other NTAG products to have a common way of

identifying products across platforms and evolution steps.

The GET_VERSION command has no arguments and returns the version information for

the specific NTAG I2C type. The command structure is shown in Figure 19 and Table 20.

Table 21 shows the re quired timing.

[1] Refer to Section 10.2 “Timing”.

Fig 19. GET_VERSION command

Table 20. GET_VERSION command

Name Code Description Length

Cmd 60h Get product version 1 byte

CRC - CRC according to Ref. 1 2 bytes

Data - Product version information 8 bytes

NAK see Table 17 see Section 10.3 4-bit

Table 21. GET_VERSION timing

These times exclude the end of communi cation of the NFC device.

TACK/NAK min TACK/NAK max TTimeOut

GET_VERSION n=9[1] TTimeOut 5 ms

CRC

NFC device Cmd

Data

NTAG ,,ACK''

283 µs 868 µs

NTAG ,,NAK'' NAK

Time out TTimeOut

TNAK

TACK

57 µs

aaa-006987

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

The most significant 7 bits of the storage size byte are interpr eted as an unsigned in teger

value n. As a result, it codes the total available user memory size as 2n. If the least

significant bit is 0b, the user memory size is exactly 2 n. If the least significa nt bit is 1b, the

user memory size is between 2n and 2n+1.

The user memory for NTAG I²C 1k is 888 bytes. This memory size is between 512 bytes

and 1024 bytes. Therefore, the most significant 7 bits of the value 13h, are interpreted as

9d, and the least significant bit is 1b.

The user memory for NTAG I²C 2k is 1904 bytes. This memory size is between 1024

bytes and 2048 bytes. Therefore, the most significant 7 bits of the value 15h, are

interpreted as 10d, and the least significant bit is 1b.

10.6 READ

The READ command requires a start page address, and returns the 16 bytes of four

NTAG I2C pages. For example, if address (Addr) is 03h then pages 03h, 04h, 05h, 06h ar e

returned. Special conditions apply if the READ command ad dress is near the end of the

accessible mem o ry ar ea . Fo r de tails on thos e cas es and the comman d struct ure refer to

Figure 20 and Table 23.

Table 24 shows the required timing.

Table 22. GET_VERSION response for NTAG I²C 1k and 2k

Byte no. Description NTAG I²C 1k NTAG I²C 2k Interpretation

0 fixed Header 00h 00h

1 vendor ID 04h 04h NXP Semiconductors

2 product type 04h 04h NTAG

3 product subtype 05h 05h 50 pF I2C, Field detection

4 major product version 02h 02h 2

5 minor product version 01h 01h V1

6 storage size 13h 15h see following information

7 protocol type 03h 03h ISO/IEC 14443-3 compliant

Fig 20. READ command

CRC

AddrNFC device Cmd

Data

NTAG ,,ACK''

368 µs 1548 µs

NTAG ,,NAK'' NAK

Time out TTimeOut

TNAK

TACK

57 µs

aaa-006988

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

[1] Refer to Section 10.2 “Timing”.

In the initial state of NTAG I2C, all memory pages are allowed as Addr parameter to the

READ command:

•Page address from 00h to E2h and E8h for NTAG I²C 1k

•Page address from 00h to FFh (sector 0), fr om page 00h to E0h and E8h (sector 1 ) for

NTAG I²C 2k

•SRAM buffer address when Pass-through mode is enabled

Addressing a start memory page beyond the limits above results in a NAK response from

NTAG I2C.

In case a READ command a ddressing st art with a valid memory area but extends over an

invalid memory area, the content of the invalid memory area will be reported as 00h.

10.7 FAST_READ

The FAST_READ command requires a start p age addr ess and an end page address and

returns all n*4 bytes of the addressed pages. For example, if the start address is 03h and

the end address is 07h, then pages 03h, 04h, 05h, 06h and 07h are returned.

For details on those cases and the command structure, refer to Figure 21 and Table 25.

Table 26 shows the required timing.

Table 23. READ command

Name Code Description Length

Cmd 30h read four pages 1 byte

Addr - start page address 1 byte

CRC - CRC according to Ref. 1 2 bytes

Data - Data content of the addressed pages 16 bytes

NAK see Table 17 see Section 10.3 4-bit

Table 24. READ timing

These times exclude the end of communication of the NFC device.

TACK/NAK min TACK/NAK max TTimeOut

READ n=9[1] TTimeOut 5 ms

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

[1] Refer to Section 10.2 “Timing”.

In the initial state of NTAG I2C, all memory pages are allowed as StartAddr parameter to

the FAST_READ command:

•Page address from 00h to E2h and E8h for NTAG I²C 1k

•Page address from 00h to FFh (sector 0), fr om page 00h to E0h and E8h (sector 1 ) for

NTAG I²C 2k

•SRAM buffer address when Pass-through mode is enabled

If the start addressed memory page (StartAdd r) is outside of accessible area, NTAG I2C

replies a NAK.

In case the FAST_READ command starts with a valid memory area but extends over an

invalid memory area, the content of the invalid memory area will be reported as 00h.

The EndAddr parame te r m ust be equa l to or hi gh er tha n the StartAddr.

Remark: The FAST_READ command is able to read out the entire memory of one secto r

with one command. Nevertheless, the r eceive buffer of the NFC device must be able to

handle the requested amount of data as no chaining is possible.

Fig 21. FAST_READ command

Table 25. FAST_READ command

Name Code Description Length

Cmd 3Ah read multipl e pages 1 byte

StartAddr - start page address 1 by te

EndAddr - end page address 1 byte

CRC - CRC according to Ref. 1 2 bytes

Data - data content of the addressed pages n*4 bytes

NAK see Table 17 see Section 10.3 4-bit

Table 26. FAST_READ timing

These times exclude the end of communi cation of the NFC device.

TACK/NAK min TACK/NAK max TTimeOut

FAST_READ n=9[1] TTimeOut 5 ms

CRC

StartAddrNFC device Cmd

Data

NTAG ,,ACK''

453 µs depending on nr of read pages

NTAG ,,NAK'' NAK

Time out TTimeOut

TNAK

TACK

57 µs

EndAddr

aaa-006989

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NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

10.8 WRITE

The WRITE command requires a block address, and writes 4 bytes of data into the

addressed NTAG I2C page. The WRITE command is shown in Figure 22 and Table 27.

Table 28 shows the required timing.

[1] Refer to Section 10.2 “Timing”.

In the initial state of NTAG I2C, the following memory pages are valid Addr parameters to

the WRITE command:

•Page address from 02h to E2h, E8h and E9h (sector 0) for NTAG I²C 1k

•Page address from 02h to FFh (sector 0), from 00h to E0 h, E8h and E9h (sector 1) for

NTAG I²C 2k

•SRAM buffer addresses when Pass-through mode is enabled

Addressing a memory page beyond the limits above results in a NAK response from

NTAG I2C.

Pages that are locked against writing cannot be reprogrammed using any write comm and.

The locking mechanisms include st atic and dynamic lock bits, as well as the locking of the

configuration p ages.

Fig 22. WRITE command

Table 27. WRITE command

Name Code Description Length

Cmd A2h write one page 1 byte

Addr - page addres s 1 byte

CRC - CRC according to Ref. 1 2 bytes

Data - data 4 bytes

NAK see Table 17 see Section 10.3 4-bit

Table 28. WRITE timing

These times exclude the end of communi cation of the NFC device.

TACK/NAK min TACK/NAK max TTimeOut

WRITE n=9[1] TTimeOut 10 ms

CRCAddrNFC device Cmd

NTAG ,,ACK''

708 µs

NTAG ,,NAK'' NAK

Time out TTimeOut

TNAK

TACK

57 µs

ACK

57 µs

Data

aaa-006990

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

10.9 SECTOR SELECT

The SECTOR SELECT command consists of two commands packet: the first one is the

SECTOR SELECT command (C2h), FFh and CRC. Upon an ACK answer from the Tag,

the second command packet needs to be issu ed with the related sector address to be

accessed and 3 bytes RFU.

To successfully access to the requested memory sector, the tag shall issue a passive

ACK, which is sending NO REPLY for more than 1ms after the CRC of the second

command set.

The SECTOR SELECT command is shown in Figure 23 and Table 29.

Table 30 shows the re quired timing.

Fig 23. SECTOR_SELECT command

Table 29. SECTOR_SELECT command

Name Code Description Length

Cmd C2h sector select 1 byte

FFh - 1 byte

CRC - CRC according to Ref. 1 2 bytes

SecNo - Memory sector to be selected

(00h-FEh) 1 byte

NAK see Table 17 see Section 10.3 4-bit

aaa-014051

CRCFFhNFC device Cmd

SecNo 00h 00h 00h CRC

368 µs

NTAG I2C ,,NAK''

NTAG I2C ,,ACK''

NTAG I2C ,,NAK''

NTAG I2C ,,ACK''

NAK

Time out

NFC device

TTimeOut

TNAK

TACK

57 µs

ACK

57 µs

NAK

<1ms

>1ms

537 µs

57 µs

Passive ACK

SECTOR SELECT packet 2

SECTOR SELECT packet 1

(any reply)

(no reply)

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

[1] Refer to Section 10.2 “Timing”.

Table 30. SECTOR_SELECT timing

These times exclude the end of communi cation of the NFC device.

TACK/NAK min TACK/NAK max TTimeOut

SECTOR SELECT n=9[1] TTimeOut 10 ms

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

11. Communication and arbitration between RF and I²C interface

If both interfaces are powered by their corresponding source, only one interface shall

have access according to the "first-come, first-serve" principle.

In NS_REG, the two status bits I2C_LOCKED and RF_LOCKED reflect the status of the

NTAG I²C memory access and indicate which interface is locking the memory access. At

power on, both bits are 0, setting the arbi tration in idle mode.

In the case arbiter locks to the I²C interface, an RF reader still can access the session

registers. If the ISO state machine is in ACTIVE state, only the SECTOR SELECT

command is allowed. But any other command requiring EEPROM access like READ or

WRITE is handled as an illegal command and replied to with a special NAK value.

In the case where the memory access is locked to the RF interface, the I²C host still can

access the NFC register, by issuing a 'Register READ/WRIT E' command. All other read or

write commands will be replied to with a NACK to the I²C host.

11.1 Non-Pass-through mode

PTHRU_ON_OFF = 0b (see Table 14) indicates non-Pass-through mo de.

11.1.1 I²C interface access

If the tag is in the IDLE or HALT state (RF state after POR or HALT-command) and the

correct I²C slave ad d ress of NTAG I²C is specified following the START condition, the bit

I2C_LOCKED will be automatically set to 1b. If I2C_LOCKED = 1b, the I²C interface has

access to the tag memory and the tag will respond with a NACK to any memory

READ/WRITE command on the RF interface other than reading the register bytes

command during this time.

I2C_LOCKED must be either reset to 0b at the end of the I²C sequence or wait until the

end of the watch dog timer.

11.1.2 RF interface access

The arbitration will allow the RF interface read and write accesses to EEPROM only when

I2C_LOCKED is set to 0b.

RF_LOCKED is automatically set to 1b if the tag receives a valid command (EEPROM

Access Commands) o n the RF inter face. If RF_L OCKED = 1b, the tag is locked to the RF

interface and will not respond to any command from the I²C interface other than READ

RF_LOCKED is automatically set to 0b in one of the following conditions

•At POR or if the RF field is switched off

•If the tag is set to the HALT state with a HALT command on the RF interface

•If the memory access command is finished on the RF interface

When the RF interface has read the last page of the NDEF message specified in

LAST_NDEF_BLOCK (see Table 13 and Table 14) the bit NDEF_DATA_READ - in the

example, new NDEF da ta can be written.

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11.2 SRAM buffer mapping with Memory Mirror enabled

With SRAM_MIRROR_ON_OFF= 1b, the SRAM buffer mirroring is enabled. This mode

cannot be combined with the Pass-through mode (see Section 11.3).

With the memory mirror enabled, the SRAM is now mapped into the user memory from

the RF interface perspective using the SRAM mirror lower page address specified in

SRAM_MIRROR_BLOCK byte (Table 13 and Table 14). See Table 31 (NTAG I²C 1k) and

Table 32 (NTAG I²C 2k) for an illustration of this SRAM memory mapping when

SRAM_MIRROR_BLOCK is set to 01h. The SRAM buffer will be then available in two

locations: inside the user memo ry and at the end of the first or second memory sector

(respectively NTAG I²C 1k or NTAG I²C 2k).

The tag must be VCC powered to make this mode work, because without VCC, the SRAM

will not be accessible via RF powered only.

When mapping the SRAM buffer to the user memo ry, the user shall be awar e that al l da t a

written into the SRAM part of the user memory will be lost once the NTAG I²C is no longer

powered from the I²C side (as SRAM is a volatile memory).

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Table 31. Illustration of the SRAM memory addressing via the RF interface (with

SRAM_MIRROR_ON_OFF set to 1b and SRAM_MIRROR_ BLOCK set to 01h) for

the NTAG I2C 1k

Sector

address Page address Byte number within a page Access

conditions

Dec. Hex. 0 1 2 3

0 0 00h Serial number READ

1 01h Serial number Internal READ

2 02h Intern al Static lock bytes READ/R&W

3 03h Capability Container (CC) READ&WRITE

4 04h SRAM memory (16 blocks) READ&WRITE... ...

19 13h

... ... User memory READ&WRITE

225 E1h

226 E2h Dynamic lock bytes 00h R&W/READ

227 E3h

Invalid access - returns NAK n.a.

228 E4h

229 E5h

230 E6h

231 E7h

232 E8h Configuration regi sters see 8.3.11

233 E9h

234 EAh Invalid access - returns NAK n.a.... ...

255 FFh

1 ... ... Invalid access - returns NAK n.a.

2 ... ... Invalid access - returns NAK n.a.

3 0 00h Invalid access - returns NAK n.a.

... ...

248 F8h Session registers see 8.3.11

249 F9h

... ... Invalid access - returns NAK n.a.

255 FFh

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NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

Table 32. Illustration of the SRAM memory addressing via the RF interface (with

SRAM_MIRROR_ON_OFF set to 1b and SRAM_MIRROR_ BLOCK set to 01h) for

the NTAG I2C 2k

Sector

address Page address Byte number within a page Access

conditions

Dec. Hex. 0 1 2 3

0 0 00h Serial number READ

1 01h Serial number Internal READ

2 02h Intern al Static lock bytes READ/R&W

3 03h Capability Container (CC) READ&WRITE

4 04h SRAM memory (16 blocks) READ&WRITE... ...

19 13h

... ...

User memory READ&WRITE

... ...

255 FFh

10...

1...

... ...

223 DFh

224 E0h Dynamic lock bytes 00h R&W/READ

225 E1h

Invalid access - returns NAK n.a.

226 E2h

227 E3h

228 E4h

229 E5h

230 E6h

231 E7h

232 E8h Configuration regi sters see 8.3.11

233 E9h

234 EAh Invalid access - returns NAK n.a.... ...

255 FFh

2 ... ... Invalid access - returns NAK n.a.

3 0 00h Invalid access - returns NAK n.a.

... ...

248 F8h Session registers see 8.3.11

249 F9h

... ... Invalid access - returns NAK n.a.

255 FFh

Product data sheet

COMPANY PUBLIC Rev. 3.3 — 15 July 2015

265433 52 of 65

NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

11.3 Pass-through mode

PTHRU_ON_OFF = 1b (see Table 14) enables and indicates Pass-through mode.

To handle large amount of data transfer from one interface to the other, NTAG I²C offers

the Pass-through mode where data is transferred via a 64 byte SRAM buffer. This buffer

offers fast write access and unlimited write endurance as well as an easy handshake

mechanism be tw ee n th e two inte rfa ce s.

This buffer is mapped directly at the end of the sector 0 (N TAG I²C 1k) or sector 1 (NTAG

I²C 2k) of the memory (from the RF interface perspective).

In both cases, the principle of access to the SRAM bu ffer via the RF and I²C interface is

exactly the same (see Section 11.3.2 and Section 11.3.3).

The data flow direction must be set with the PTHRU_DIR bit (see Table 14) within the

current communication session with the session registers (in this case, it can only be set

via the I²C interfaces) or for the configuratio n bits after POR (in this case both RF and I²C

interface can set it). This Pass-through direction settings avoids locking the memory

access during th e da ta transfer from one interface to the SRAM buffer.

The Pass-through mode can only be enabled via I²C interface when both interfaces are

powered. The PTHRU_ON_OFF bit, located in the session registers NC_REG (see

Section 8.3.11), needs to be set to 1b. In case one interface powers of f, the Pass-th rough

mode is disabled automatically.

11.3.1 SRAM buffer mapping

In Pass-through mode, the SRAM is mirror ed to pages F0h to FFh sector 0 for the NTAG

I²C 1k - see Table 33 - or sector 1 for the NTAG I²C 2k - see Table 34 - outside the user

memory.

The last page/block of the SRAM buffer (page 16) is used as the terminator page. Once

the terminator page/block in the respective interfaces is read/written, the control would be

transferre d to othe r int er fa c e (RF/ I² C) - s ee Section 11.3.2 and Section 11.3.3 for more

details.

Accordingly, the application can align on the Reader & Host side to transfer 16/3 2/ 48 /6 4

bytes of data in one Pass-thr o ug h ste p by on ly using the last blocks/page of the SRAM

buffer.

When using FAST_READ to read the SRAM buffer from RF, the EndAddr input of the

FAST_READ command has to be always set to FFh.

Product data sheet

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265433 53 of 65

NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

Table 33. Illustration of the SRAM memory addressing via the RF interface in Pass-through

mode (PTHRU_ON_OFF set to 1b) for the NTAG I2C 1k

Sector

address Page address Byte number within a page Access

conditions

Dec. Hex. 0 1 2 3

0 0 00h Serial number READ

1 01h Serial number Internal READ

2 02h Intern al Static lock bytes READ/R&W

3 03h Capability Container (CC) READ&WRITE

4 04h

User memory READ&WRITE

... ...

15 0Fh

... ...

225 E1h

226 E2h Dynamic lock bytes 00h R&W/READ

227 E3h

Invalid access - returns NAK n.a.

228 E4h

229 E5h

230 E6h

231 E7h

232 E8h Configuration regi sters see 8.3.11

233 E9h

234 EAh Invalid access - returns NAK n.a.

... ...

240 F0h SRAM memory (16 pages) READ&WRITE... ...

255 FFh

1 ... ... Invalid access - returns NAK n.a.

2 ... ... Invalid access - returns NAK n.a.

3 0 00h Invalid access - returns NAK n.a.

... ...

248 F8h Session registers see 8.3.11

249 F9h

... ... Invalid access - returns NAK n.a.

255 FFh

Product data sheet

COMPANY PUBLIC Rev. 3.3 — 15 July 2015

265433 54 of 65

NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

Table 34. Illustration of the SRAM memory addressing via the RF interface in Pass-through

mode (PTHRU_ON_OFF set to 1b) for the NTAG I2C 2k

Sector

address Page address Byte number within a page Access

conditions

Dec. Hex. 0 1 2 3

0 0 00h Serial number READ

1 01h Serial number Internal READ

2 02h Intern al Static lock bytes READ/R&W

3 03h Capability Container (CC) READ&WRITE

4 04h

User memory READ&WRITE

... ...

19 13h

... ...

255 FFh

10...

1...

... ...

223 DFh

224 E0h Dynamic lock bytes 00h R&W/READ

225 E1h

Invalid access - returns NAK n.a.

226 E2h

227 E3h

228 E4h

229 E5h

230 E6h

231 E7h

232 E8h Configuration regi sters see 8.3.11

233 E9h

234 EAh Invalid access - returns NAK n.a.

... ...

240 F0h SRAM (16 pages) READ&WRITE... ...

255 FFh

2 ... ... Invalid access - returns NAK n.a.

3 0 00h Invalid access - returns NAK n.a.

... ...

248 F8h Session registers see 8.3.11

249 F9h

... ... Invalid access - returns NAK n.a.

255 FFh

Product data sheet

COMPANY PUBLIC Rev. 3.3 — 15 July 2015

265433 55 of 65

NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

11.3.2 RF to I²C Data transfer

If the RF interface is enabled (RF_LOCKED = 1b) and data is written to the terminator

block/page of the SRAM via the RF interface, at the end of the WRITE command, bit

SRAM_I2C_READY is set to 1b and bit RF_LOCKED is set to 0b automatically, and the

NTAG I²C is locked to the I²C interface.

To signal to the host that data is ready to be read following mechanisms are in place:

•The host polls/reads bit SRAM_I2C_READY from NS_REG (see Table 14) to know if

data is ready in SRAM

•A trigger on the FD pin indicates to the host that data is ready to be read from SRAM.

This feature can be enabled by progr amming bits 5:2 (FD_OFF, FD_ON) of the

NC_REG appropriately (see Table 13)

This is illustrated in the Figure 24.

If the tag is addressed with the correct I²C slave address, the I2C_LOCKED bit is

automatically set to 1b (according to the interface arbitration). After a READ from the

terminator page of the SRAM, bit SRAM_I2C_READY and bit I2C_LOCKED are

automatically reset to 0b, and the tag returns to the arbitration idle mode where, for

example, further data from the RF interface can be transferred.

Product data sheet

COMPANY PUBLIC Rev. 3.3 — 15 July 2015

265433 56 of 65

NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

11.3.3 I²C to RF Data transfer

If the I²C interface is enabled (I2C_LOCKED is 1b) and data is written to the terminator

page of the SRAM via the I²C interface, at the end of the WRITE command, bit

SRAM_RF_READY is set to 1b and bit I2C_LOCKED is automatic ally reset to 0b to set

the tag in the arbitration idle state.

The RF_LOCKED bit is then automatically set to 1b (accord ing to the interface

arbitration). After a READ or FAST_READ command involving the terminator block/page

of the SRAM, bit SRAM_RF_READY and bit RF_LOCKED are automatically reset to 0b

allowing the I²C interface to further write data into the SRAM buffer.

To signal to the host that further data is ready to be written, the following mechanisms are

in place:

Fig 24. Illustration of the Field detection feature in combination with the Pass-through mode

for data transfer from RF to I²C

aaa-017244

Enable pass through

PTHRU_ON_OFF = 1b

RF starts writing data

to SRAM buffer

Last 4 bytes of

SRAM written by RF

Start reading

SRAM by I2C

Last 16 bytes

SRAM by I2C

OFF

HIGH

LOW

RF field

FD pin

Event

I2C_LOCKED

RF_LOCKED

SRAM_I2C_READY

RF_FIELD_PRESENT

3Dh 7Dh

more data available?

01h

NS_REG

PTHRU_ON_OFF = 0b,

FD_ON = 11b, FD_OFF = 11b

SRAM_MIRROR_ON_OFF = 0b

PTHRU_DIR = 1b

NC_REG

RF OFF

0 0

1 0

Product data sheet

COMPANY PUBLIC Rev. 3.3 — 15 July 2015

265433 57 of 65

NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

•The RF inte rface polls/reads the bi t SRAM_RF_READY from NS_REG (see Table 14)

to know if new data has been written by the I²C interface in the SRAM

•A trigger on the FD pin indicates to the host that data has been read from SRAM by

the RF interface. This feature can be enabled by programming bits 5:2 (FD_OFF,

FD_ON) of the NC_REG appropriately (see Table 13)

The above mechanism is illustrated in the Figure 25.

Fig 25. Illustration of the Field detection signal feature in combination with Pass-through mode

for data transfer from I²C to RF

aaa-017245

Enable pass through

PTHRU_ON_OFF = 1b

I2C starts writing

data to SRAM buffer

Last 4 bytes written

to SRAM by I2C

Start reading

SRAM by RF

Last 4 bytes

read by RF

OFF

HIGH

LOW

RF field

FD pin

Event

I2C_LOCKED

RF_LOCKED

SRAM_RF_READY

RF_FIELD_PRESENT

3Ch 7Ch

more data available?

01h

NS_REG

PTHRU_ON_OFF = 0b,

FD_ON = 11b, FD_OFF = 11b

SRAM_MIRROR_ON_OFF = 0b

PTHRU_DIR = 1b

NC_REG

RF OFF

0 1

Product data sheet

COMPANY PUBLIC Rev. 3.3 — 15 July 2015

265433 58 of 65

NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

12. Limiting values

Exceeding the limi t s of one or more values in reference may cau se permane nt damage to

the device. Exposure to limiting values for extended periods may affect device reliability.

[1] Stresses above one or more of the limiting values may cause permanent damage to the device.

[2] Exposure to limiting values for extended periods may affect device reliability.

[3] ANSI/ESDA/JEDEC JS-001; Human body model: C = 100 pF, R = 1.5 k.

13. Characteristics

13.1 Electrical characteristics

[1] A minimum supply voltage of 1.8 V is required, when RF field is present.

Table 35. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).[1][2][3]

Symbol Parameter Conditions Min Max Unit

IIinput current LA - LB - 40 mA

Tstg storage temperature 55 +125 C

VESD electrostatic discharge voltage [3] 2- kV

VFD Voltage on the FD pin - 3.6 V

VSDA Voltage on the SDA line - 3.6 V

VSCL Voltage on the SCL line - 3.6 V

Table 36. Characteristics

Symbol Parameter Conditions Min Typ Max Unit

Ciinput capacitance LA - LB 44 50 56 pF

fiinput frequency - 13.56 - MHz

Toper operating temperature 40 - +95 C

Energy harvesting characteristics

Vout voltage generated at the Vout

pin --3.2V

I²C interface characteristics

VCC supply voltage NTAG I²C supplied via VCC only 1.7 [1] 3.6 V

IDD supply current - 155 - A

EEPROM characteristics

tret retention time full operating temperature range 20 - - year

Nendu(W) write endurance full operating temperature range 500000 - - cycle

Product data sheet

COMPANY PUBLIC Rev. 3.3 — 15 July 2015

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NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

14. Package outline

Fig 26. Package outline SOT902-3 (XQFN8)

References

Outline

version European

projection Issue date

IEC JEDEC JEITA

SOT902-3 - - -

MO-255

- - -

sot902-3_po

11-08-16

11-08-18

Unit

mm max

nom

min

0.5 0.05

0.00

1.65

1.60

1.55

1.65

1.60

1.55 0.6 0.5 0.1 0.05

Dimensions

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

XQFN8: plastic, extremely thin quad flat package; no leads;

8 terminals; body 1.6 x 1.6 x 0.5 mm SOT902-3

A1b

0.25

0.20

0.15

DEee

0.45

0.40

0.35

0.05

0 1 2 mm

scale

terminal 1

index area

terminal 1

index area

eAC B

vCw

metal area

not for soldering

detail X

Product data sheet

COMPANY PUBLIC Rev. 3.3 — 15 July 2015

265433 60 of 65

NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

Fig 27. Package outline SOT501-1 (TSSOP8)

UNIT A1

max. A2A3bpLHELpwyv

ceD(1) E(2) Z(1) θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.45

0.25 0.28

0.15 3.1

2.9 3.1

2.9 0.65 5.1

4.7 0.70

0.35 6°

0°

0.1 0.10.10.94

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.7

0.4

SOT505-1 99-04-09

03-02-18

0.25

A2A1

(A3)

detail X

vMA

2.5 5 mm0

scale

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1

1.1

pin 1 index

Product data sheet

COMPANY PUBLIC Rev. 3.3 — 15 July 2015

265433 61 of 65

NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

15. Abbreviations

16. References

[1] NFC Forum - Type 2 Tag Operation V1.2

Technical Specification

[2] ISO/IEC 14443 - Identification cards - Contactless integrated circuit cards -

Proximity cards

International Standard

[3] I2C-bus specification and user manual

NXP standard UM10204

[4] NFC Forum - Activity V1.1

Technical Specification

Table 37. Pin description

Pin no. Symbol Description

1 LA Antenna connection LA

2 VSS GND

3 SCL Serial Clock I2C

4 FD Field detection

5 SDA Serial data I2C

6 VCC VCC in connection (external power supply)

out Voltage out (energy harvesting)

8 LB Antenna connection LB

Table 38. Abbreviations

Acronym Description

POR Power On Reset

Product data sheet

COMPANY PUBLIC Rev. 3.3 — 15 July 2015

265433 62 of 65

NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

17. Revision history

Table 39. Revision history

Document ID Release date Data sheet status Change notice Supersedes

NT3H1101_1201 v. 3.3 201 50715 Product data sheet - NT3H1101_1201 v. 3.2

Modifications: •Table 1 “Ordering information”: updated

•Capacitor value for energy harvesting corrected

•Table 35 “Limiting values”: updated

•Table 36 “Characteristics”: updated

NT3H1101_1201 v. 3.2 201 50325 Product data sheet - NT3H1101_1201 v. 3.1

Modifications: •Table 1 “Ordering information”: updated

•Table 2 “Marking codes”: updated

•Section 7.1: Figure 4 added

•Section 14 “Package outline”: Figure 27 added

•General update

NT3H1101_1201 v. 3.1 201 41009 Product data sheet - NT3H1101_1201 v. 3.0

Modifications: •Section 8.6 “Energy harvesting”: updated

•Section 10.5 “GET_VERSION”: updated

•Figure 24 and Figure 25: updated

•Section 12 “Limiting values” and Section 13 “Characteristics”: remark removed

NT3H1101_1201 v. 3.0 201 40806 Product data sheet - NT3H1101_1201 v. 2.3

Modifications: •Section 8.6 “Energy harvesting” updated

•Section 16 “References”: updated

•Data sheet status changed to “Product data sheet”

NT3H1101_1201 v. 2.3 201 40708 Objective data sheet - NT3H1201 _1101 v. 2.2

Modifications: •Figures upda te d

•General update

NT3H1101_1201 v. 2.2 201 40306 Objective data sheet - NT3H1201 _1101 v. 2.1

Modifications: •General updates

NT3H1101_1201 v. 2.1 201 31218 Objective data sheet - NT3H1201 _1101 v. 2.0

Modifications: •Section 4 “Ordering information”: type number co rrected

NT3H1101_120 1 v. 2.0 201 31212 Objective data sheet NT3H1201 v. 1.4

Modifications: •Additional description for the Field detection functionality for Pass-through mode

•General update

NT3H1201 v. 1.4 20130802 Objective data sheet - NT3H1201 v. 1.3

Modifications: •Update for 1k memory version and RF commands

NT3H1201 v. 1.3 20130613 Objective data sheet -

Modifications: •Pinning package update NT3H1201 v. 1.0

NT3H1201 v. 1.0 20130425 Objective data sheet - -

Product data sheet

COMPANY PUBLIC Rev. 3.3 — 15 July 2015

265433 63 of 65

NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

18. Legal information

18.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

18.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

Product specificat ion — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

18.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregat e and cumulative liabil ity towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applicat ions where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe prop erty or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for t he customer’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Custo mers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by custo mer’s

third party custo mer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third p arty

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms an d conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or inte llectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specif ication.

Product data sheet

COMPANY PUBLIC Rev. 3.3 — 15 July 2015

265433 64 of 65

NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is a utomotive qualified,

the product is not suitable for automotive use. It i s neither qua lified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standards, custome r

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such au tomotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive appl ications beyond NXP Semiconduct ors’

standard warrant y and NXP Semiconductors’ product specifications.

Translations — A non-En glish (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

18.4 Licenses

18.5 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

I2C-bus — logo is a trademark of NXP Semi conductors N.V.

19. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Purchase of NXP ICs with NFC technology

Purchase of an NXP Semiconductors IC that co mplies with one of the Near

Field Communication (NFC) standards ISO/IEC 18092 and ISO/IEC 21481

does not convey an implied license under any patent right infringed by

implementat ion of any of those standards.

NXP Semiconductors NT3H1101/NT3H1201

NTAG I2C - Energy harvesting Type 2 Tag with I2C interface

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 15 July 2015

265433

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

20. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2

2.1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.2 RF interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.3 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.4 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.5 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.6 Key benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 4

5 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5

7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

7.1.1 XQFN8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

7.1.2 TSSOP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7

8 Functional description . . . . . . . . . . . . . . . . . . . 8

8.1 Block description . . . . . . . . . . . . . . . . . . . . . . . 8

8.2 RF interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

8.2.1 Data integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . 9

8.2.2 RF communication principle. . . . . . . . . . . . . . 10

8.2.2.1 IDLE state. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

8.2.2.2 READY 1 state . . . . . . . . . . . . . . . . . . . . . . . . 10

8.2.2.3 READY 2 state . . . . . . . . . . . . . . . . . . . . . . . . 11

8.2.2.4 ACTIVE state . . . . . . . . . . . . . . . . . . . . . . . . . 11

8.2.2.5 HALT state . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

8.3 Memory organization . . . . . . . . . . . . . . . . . . . 11

8.3.1 Memory map from RF interface . . . . . . . . . . . 11

8.3.2 Memory map from I²C interface . . . . . . . . . . . 13

8.3.3 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

8.3.4 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

8.3.5 UID/serial number. . . . . . . . . . . . . . . . . . . . . . 16

8.3.6 Static lock bytes . . . . . . . . . . . . . . . . . . . . . . . 17

8.3.7 Dynamic Lock Bytes. . . . . . . . . . . . . . . . . . . . 18

8.3.8 Capability Container (CC bytes). . . . . . . . . . . 20

8.3.9 User Memory pages . . . . . . . . . . . . . . . . . . . . 20

8.3.10 Memory content at delivery . . . . . . . . . . . . . . 21

8.3.11 NTAG I2C configuration and session

registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8.4 Configurable Field Detection Pin . . . . . . . . . . 28

8.5 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 32

8.6 Energy harvesting. . . . . . . . . . . . . . . . . . . . . . 32

9 I²C commands . . . . . . . . . . . . . . . . . . . . . . . . . 33

9.1 Start condition. . . . . . . . . . . . . . . . . . . . . . . . . 33

9.2 Stop condition. . . . . . . . . . . . . . . . . . . . . . . . . 33

9.3 Soft reset feature . . . . . . . . . . . . . . . . . . . . . . 34

9.4 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . 34

9.5 Data input. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

9.6 Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . 34

9.7 READ and WRITE Operation. . . . . . . . . . . . . 35

9.8 W RITE and READ register operation . . . . . . 37

10 RF Command . . . . . . . . . . . . . . . . . . . . . . . . . 39

10.1 NTAG I2C command overview. . . . . . . . . . . . 39

10.2 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

10.3 NTAG ACK and NAK . . . . . . . . . . . . . . . . . . 40

10.4 ATQA and SAK responses. . . . . . . . . . . . . . . 40

10.5 GET_VERSION . . . . . . . . . . . . . . . . . . . . . . . 41

10.6 READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

10.7 FAST_READ . . . . . . . . . . . . . . . . . . . . . . . . . 43

10.8 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

10.9 SECTOR SELECT. . . . . . . . . . . . . . . . . . . . . 46

11 Communication and arbitration between

RF and I²C interface . . . . . . . . . . . . . . . . . . . . 48

11.1 Non-Pass-through mode . . . . . . . . . . . . . . . . 48

11.1.1 I²C interface access . . . . . . . . . . . . . . . . . . . . 48

11.1.2 RF interface access . . . . . . . . . . . . . . . . . . . . 48

11.2 SRAM buffer mapping with Memory Mirror

enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

11.3 Pass-through mode . . . . . . . . . . . . . . . . . . . . 52

11.3.1 SRAM buffer mapping . . . . . . . . . . . . . . . . . . 52

11.3.2 RF to I²C Data transfer . . . . . . . . . . . . . . . . . 55

11.3.3 I²C to RF Data transfer . . . . . . . . . . . . . . . . . 56

12 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 58

13 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 58

13.1 Electrical characteristics . . . . . . . . . . . . . . . . 58

14 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 59

15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 61

16 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

17 Revision history . . . . . . . . . . . . . . . . . . . . . . . 62

18 Legal information . . . . . . . . . . . . . . . . . . . . . . 63

18.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 63

18.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 63

18.4 Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

18.5 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 64

19 Contact information . . . . . . . . . . . . . . . . . . . . 64

20 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65