AK8817VQP - AKM Semiconductor

[AK8817VQ]

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AK8817VQ

NTSC/PAL Digital Video Encoder

General Description

The AK8817VQ is a Digital Video Encoder for Portable and Mobile application. ITU-R BT.601 level compatible Y, Cb,and Cr

signals which correspond to 27MHz or square pixel are encoded into either NTSC or PAL compatible composite video signal.

Interface is made in HSYNC-, VSYNC- synchronized slave-mode operation or ITU-R.Bt656. AK8817VQ has 75ohm driver

with LPF. It is possible to encode the VBID(CGMS-A) and WSS signal on the output video signal. Host Control interface is

I2C Bus I/F.

Features

• NTSC-M, PAL-B, D, G, H, I Composite Video encoding

• Y:Cb:Cr 4:2:2

• H/V Slave Operation / ITU-R.BT656 Interface

• Y filtering: 2 x over-sampling

• C filtering: 4 x over-sampling

• 9bit DAC

• Setup

• VBID ( CGMS-A ) Compatible

• WSS Compatible

• Operation Clock rate : 27MHz or Square-pixel Clock rate(NTSC:24.5454MHz/PAL29.50MHz)

• Video Amp with LPF

• On-chip Color Bar Output

• Black Burst Output

• Power Supply (AVDD, DVDD) 2.7V - 3.6V

• I/F Power Supply (PVDD) 1.6V - DVDD

• Power Down mode

• Monolithic CMOS

• 48pin LQFP (Pb Free)

• Temperature Range: -40 ~ 105°C

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Block Diagram

VREF

Generator

AVDD AVSSDVDD DVSS

VREF

IREF

CLKIN

Input Data Control

Synchronization Control

SubCarrier

Generator

Chroma

LPF Filter

(x 2 Interpolator)

DACOUT

VDI

HDI

SDA SCL

RSTN PDN

Color Bar Gen

B.B. Gen

Cb/Cr

LPF Filter

(x 2 Interpolator)

Y

LPF Filter

(x 2 Interpolator)

SYNC

Generato

r

9-bit

DAC

(Macrovision

&)

CGMS

D[7:0]

u-p I/F

Register

Timing Controller

Cb

Cr

Y

V

U

C

CLK

Generator

CLKINV

Sin

Cos

PVDD PVSS

TEST

LOGIC UD[4:0]

TEST ATPG

VOUT

6dB AMP

LPF

SAG

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Ordering Guide

AK8817VQ 48pin LQFP

Pin Assignment

1 2 3 4 10689751112

20

13

18

17

16

15

14

19

24

22

21

23

2726 2530 29 283332 3136 35 34

41

48

43

44

45

46

47

42

37

39

40

38

NC

DACOUT

AVSS

SAG

BVSS

VOUT

NC

DVDD

DVSS

RSTN

PDN

AT PG

NC

AVDD

IREF

VREF

UD4

UD3

UD2

UD1

UD0

NC

CLKINV

CLKIN

DVSS

DVDD

D7

D6

D5

D4

D3

D2

NC

SCL

SDA

HDI

VDI

PVSS

PVDD

D0

D1

TEST

NC

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Pin Functional Description

Pin# Pin Name I/O Functional Outline

1 N.C. - For normal operation, left open.

2 N.C. - For normal operation, left open.

3 AVDD P Analog power supply pin.

4 IREF O

IREF output pin. Connect this pin to Analog ground via a 12k ohm resistor

( better than +/- 1% accuracy ).

5 VREF O

On-chip VREF output pin.

AVSS level is output on this pin at PDN = L.

Connect this pin to Analog Ground via a 0.1 uF or larger capacitor.

6 UD4 O Test output pin. For normal operation, left open.

7 UD3 O Test output pin. For normal operation, left open.

8 UD2 O Test output pin. For normal operation, left open.

9 UD1 O Test output pin. For normal operation, left open.

10 UD0 O Test output pin. For normal operation, left open.

11 N.C. - For normal operation, left open.

12 N.C. - For normal operation, left open.

13 N.C. - For normal operation, left open.

14 CLKINV I

Internal clock is inverted (internal operation timing edge is inverted.)

Connect to either DVDD or DGND.

15 CLKIN I

Clock input pin.

Input a clock which is synchronized with data.

When to input 601 data : 27 MHz.

When to input square pixel data : 24.5454 MHz ( NTSC )/ 29.50 MHz ( PAL )

16 DVSS G Digital ground pin (digital core ground).

17 DVDD P Digital power supply pin (digital core power supply).

18 D7 I

Data Video Signal input pin (MSB).

Hi-Z input is acceptable to this pin at PDN = L.

19 D6 I

Data Video Signal input pin.

Hi-Z input is acceptable to this pin at PDN = L.

20 D5 I

Data Video Signal input pin.

Hi-Z input is acceptable to this pin at PDN = L.

21 D4 I

Data Video Signal input pin.

Hi-Z input is acceptable to this pin at PDN = L.

22 D3 I

Data Video Signal input pin.

Hi-Z input is acceptable to this pin at PDN = L.

23 D2 I

Data Video Signal input pin.

Hi-Z input is acceptable to this pin at PDN = L.

24 N.C. - For normal operation, left open.

25 N.C. - For normal operation, left open.

26 N.C. - For normal operation, left open.

27 TEST I For normal operation, connect to ground.

28 D1 I

Data Video Signal input pin.

Hi-Z input is acceptable to this pin at PDN = L.

29 D0 I

Data Video Signal input pin (LSB).

Hi-Z input is acceptable to this pin at PDN = L.

30 PVDD P Power supply pin for chip pad.

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Pin# Pin Name I/O Functional Outline

31 PVSS G Ground pin for PVDD.

32 VDI I

Vertical SYNC signal input pin.

Hi-Z input is acceptable to this pin at PDN = L.

33 HDI I

Horizontal SYNC signal input pin.

Hi-Z input is acceptable to this pin at PDN = L.

34 SDA I/O

I2C data pin.

This pin is pulled-up to PVDD.

Hi-Z input is possible when PDN is at low.

SDA input is not accepted during the reset sequence operation.

35 SCL I

I2C clock input pin

An input level of lower-than-PVDD should be input.

Hi-Z input is possible when PDN is at low.

SCL input is not accepted during the reset sequence operation.

36 N.C. - For normal operation, left open.

37 ATPG I For normal operation, connect to ground.

38 PDN I

Power Down Pin. After returning from PD mode to normal operation, RESET

Sequence should be done to AK8817VQ.

“L “(GND level): Power-down

“H “: normal operation

39 RSTN I

Reset input pin. In order to initialize the device , an initialization must be made in

accordance with the reset sequence.

“L “ : reset

“H “ : normal operation

Hi-Z input is acceptable to this pin at PDN = L.

40 DVSS G Digital ground pin (digital core ground).

41 DVDD P Digital power supply pin (digital core power supply).

42 N.C. - For normal operation, left open.

43 VOUT O Video output pin.

44 BVSS G

Substrate ground pin.

Connect this pin to Analog ground

45 SAG O SAG Compensation Input pin

46 AVSS G Analog ground pin.

47 DACOUT O

DAC output pin. Connect this pin to Analog ground via a 390 ohm resistor

( better than +/- 1% accuracy ).

48 N.C. - For normal operation, left open.

Analog Output pin status

MODE / PIN name IREF VREF DACOUT VOUT

PDN＝L Hi-Z Hi-Z Hi-Z Hi-Z

PDN=H、DAC=L

VIDEOAMP=L Output Outpu Hi-Z

DAC Power Down

Hi-Z

VIDEOAMP Power Down

PDN=H、DAC=H

VIDEOAMP=L Output Output Output VIDEOAMP Power Down(1)

PDN=H、DAC=H

VIDEOAMP=H Output Output Output Output

DAC: Sub Address 0x00 bit7 0: L->DACOFF 1: H->DACON

VIDEOAMP: Sub Address 0x01 bit3,4 00: L->VIDEOAMP_OFF 01,10: H-> VIDEOAMP_ON

Note1) Video Amp becomes power down. Since DACOUT pin and VOUT pin are connected with RESISTOR in the LSI,

DACOUT pin are not Hi-Z. In case of using only DAC, VOUT pin and SAG pin should be open states.

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Electrical Characteristics

(1) Absolute Maximum Ratings

Parameter Min Max Units Note

Supply voltage

DVDD, AVDD, PVDD -0.3 4.5 V

Digital Input pin voltage

(VinP) -0.3 PVDD +0.3 V

D[7:0], HDI, VDI,

RSTN, PDN,

CLKIN,

CLKINV,SCL,

SDA

Input pin current (Iin) -10 10 mA Exclude Power

supply pin.

Storage temperature -40 125 °C

(Note1)

Power supply voltages are values where each ground pin ( DVSS = AVSS = PVSS ) is at 0 V( voltage reference ).

All power supply ground pins DVSS, AVSS and PVSS should be at same potential.

(2) Recommended Operating Conditions

Parameter Min Typ. Max Units Conditions

Supply voltage *

AVDD,DVDD 2.7 3.3 3.6 V AVDD = DVDD

Interface power supply

PVDD 1.6 1.8 DVDD V

Operating temperature

(Ta) -40 105

°C

* Power supply voltages are values where each ground pin ( PVSS = AVSS = PVSS ) is at 0 V( voltage reference ).

All power supply ground pins DVSS, AVSS and PVSS should be at same potential.

(3) DC Characteristics

< Operating voltage: DVDD 2.7V~3.6V / PVDD 1.6 V~DVDD, loading condition 15 pF, temperature -40~+105°C >

Parameter Symbol Min Typ Max Units Conditions

Digital input H voltage (VIH) 0.7PVDD

0.8PVDD V 2.7V≦PVDD≦DVDD

1.6V≦PVDD＜2.7V

0.7PVDD

0.8PVDD

Digital input L voltage (VIL) 0.3PVDD

0.2PVDD V 2.7V≦PVDD≦DVDD

1.6V≦PVDD＜2.7V

Digital input leak current IL +/-10 uA

I2C (SDA) L output VOLC 0.4 V IOLC = 3mA

( Note )

Digital output pins refer to D[7:0], HDI, VDI, PDN, RSTN, SCL, SDA,CLKIN and CLKINV pin outputs in general term.

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(4) Analog Characteristics

< AVDD = 3.3 V, temperature 25 °C >

Parameter Symbol Min Typ Max Units

DAC resolution 9 bit

DAC integral non-linearity ( error ) +/- 0.6 +/- 2.0 LSB

DAC differential non-linearity ( error ) +/- 0.4 +/- 1.0 LSB

DAC output full scale voltage 1.18 1.28 1.38 V Note1)

DAC output offset voltage 5.0 mV Note2)

Video Amp Output Gain 5.0 6.0 7.0 dB Amp Input Level 1Vpp

Video Amp Full scale Level 2.0 Vpp Note3)

Video Amp THD -45 -51 dB 100kHz - 5.5MHz Note4)

Video Amp S/N 54 dB 100kHz - 5.5MHz Note4)

LPF Ripple -1 +/- 0.5 +1 dB 100kHz - 5.5MHz

0dB = 100kHz input

LPF Stop Band Level 20 30 dB 27MHz

0dB = 100kHz input

LPF Group Delay 10 100 ns |GD3MHz - GD6MHz|

On-chip reference voltage (VREF) 1.17 1.23 1.30 V

Reference voltage drift -50 ppm/°C

Note1) Values are when a 390 ohm output load, a 12k ohm IREF pin resistor and on-chip VREF are used.

Full scale output current is calculated as Iout = full scale output voltage ( typ. 1.28 V ) / 390 ohm = typ. 3.28 mA.

Note2) A voltage referenced to VSS when a decimal zero voltage is input to DAC.

Note3) VOUT Output Level Output Load Resistor: 150ohm, Load Capacitor: 15pF Internal Color Bar output

Note4) Output signal from DAC to which Input data corresponded 1Vpp. This signal is input to AMP.

Load resistor is 150ohm and Load capacitor is 15pF as shown bellow figure at (5) Current Consumption.

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(5) Current consumption

< Operating voltage : DVDD = AVDD = PVDD = 3.3 V, Ta = +25 °C >

Parameter Symbol Min Typ Max Units

Total power consumption 29 38 mA Note1)

Power-down current 1 10 30 uA Note2)

Digital part operating current 1 15 mA Note3)

Analog part operating current 1 14 mA Note4)

Analog part operating current 2 5.5 mA Note5)

Analog part operating current 3 0.8 mA Note6)

Note1) operation at 27 MHz, NTSC mode on-chip 75% color bar output is enabled and Video Amp output is “ on “ ( no

external output loads are connected , other than those recommended, connecting-components ).

SAG Compensation ON SAG Compensation OFF

75ohm

AK8817

VOUT

SAG

75ohm

100uF

15pF

AK8817

VOU

T

SAG

47uF

1uF 75ohm

75ohm

15pF 15pF 15pF

Note2) measuring conditions :

input / output settings after power-down sequence are, PDN pin is at GND level, CLKOUT and SDO output are at high

level ( power supply voltage ) with no external connection, input voltage on those input pins is 1/2 level of power supply

which are set to accept Hi-Z input at power-down, and TEST = ATPG = GND ( or left open ).

Power supplies are AVDD = DVSS = PVDD.

Each ground pin ( DVSS, AVSS, PVSS ) is always 0 V ( voltage reference ).

Note3) Operation at 27 MHz, NTSC mode on-chip 75% color bar output is enabled.

Note4) DAC ON, Video Amp On SAG Compensation On

Note5) DAC ON, Video Amp Off (SAG Compensation Off)

Note6) DAC Off, Video Amp Off (SAG Compensation Off)

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AC Timing

< DVDD 2.7 V ~ 3.6 V / PVDD 1.6 V ~ DVDD, Ta at -40 ~ +105 °C > loading condition : CL = 15 pF

(1) CLK

CLKIN

fCLKI

tCLKIHtCLKIL

VIL

VIH

1/2 PVDD

Parameter Symbol Min. Typ. Max Unit Conditions

24.5454 PIXRT=1

NTSC

27 PIXRT=0

NTSC/PA

CLKIN fCLKI

29.50

MHz

PIXRT=1

PAL

CLK duty ratio pCLKID 40

60 %

CLK Accuracy 100 ppm

tCLKIL, tCLKIH : minimum pulse width 12 nS ( tr/tf10%-90%Level Rising/Falling time ≤ 2nS)

(2) Pixel Data Input Timing

tDS tDH

D[7:0]

HDI

VDI

CLKIN

VIH

VIL

CLKINV = Low

Parameter Symbol Min. Typ. Max Unit Conditions

Data Setup Time tDS 5 nsec

Data Hold Time tDH 8 nsec

When CLKINV = High, similar tDS and tDH are specified at the falling edge of CLKOUT.

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(3) HSYNC pulse width

HSYNC

p

HSW

Parameter Symbol Min. Typ. Max Unit Conditions

15 116 NTSC

(24.5454MHz)

15 128 27MHz

HDI Pulse Width pHSW

15 139

CLKs

PAL

(29.50MHz)

* typical values are calculated by converting the HSYNC pulse width of Analog Video specification into number of system

clock pulses.

(4) Reset

(4-1) Reset Timing

RSTN

pRES

CLKIN

1 2 99 100

Parameter Symbol Min. Typ. Max Unit

RSTN Pulse Width pRES 100 CLKs

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(4-2) Power Down Sequence / Reset Sequence

Before PDN setting ( PDN to low ), Reset must be enabled for a duration of longer-than-100 clock time.

After PDN release ( PDN to high ), Reset must be enabled for 10 mS or longer till analog part reference voltage &

current are stabilized.

VIL

VIH

RSTN

PDN

CLKIN

hRES

sRES VIH

(CLKOUT=H)

GND

Parameter Symbol Min. Typ. Max Unit

RSTN Pulse Width sRES 100 CLKs

Time from PDN to high to RSTN to

high hRES 10 msec

At power-down, all control signals must be surely connected to either the selected power supply or ground level, and not

to VIH / VIL levels.

(4-3) Power Down Sequence/Power up sequence

A

VDD/DVDD

PVDD

PDN

RSTN

VREF

10mS(min)

Recover from Power Down state

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(4-4) Power On Reset

After Power up, It is necessary to make reset sequence until Analog Reference voltage(VREF) becomes stable.

PVDD/DVDD/AVDD should be power up at same time or 1st PVDD power up and AVDD/DVDD makes up.

RSTN

0.2PVDD

AVDD

DVDD

2.7V

PVDD

1.6V

VREF

PDN

10mS

(

min

)

0.8PVDD

item Symbol Min Typ Max Unit Note

RESETN Pulse width pRES_PON 10 msec

Remark: Reset sequence requires clock input.

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(5) I2C Bus Input/Output Timing < Ta = -40 ~ +105 °C >

(5-1) Timing 1

VSDAH: 0.8PVDD

VSDAL : 0.2PVDD

Parameter Symbol Min. Max. Unit

Bus Free Time tBUF 1.3 usec

Hold Time (Start Condition) tHD:STA 0.6 usec

Clock Pulse Low Time tLOW 1.3 usec

Input Signal Rise Time tR 300 nsec

Input Signal Fall Time tF 300 nsec

Setup Time(Start Condition) tSU:STA 0.6 usec

Setup Time(Stop Condition) tSU:STO 0.6 usec

The above I2C bus related timing is specified by the I2C Bus Specification, and it is not limited by the device

performance. For details, please refer to the I2C Bus Specification.

(5-2) Timing 2

SDA

tHD:DAT

tHIGH

tSU:DAT

SCL

VSDAH

VSDAL

VSDAH

VSDAL

VSDAH: 0.8PVDD

VSDAL : 0.2PVDD

Parameter Symbol Min. Max. Unit

Data Setup Time tSU:DAT 100 (note1) nsec

Data Hold Time tHD:DAT 0.0 0.9 (note2) usec

Clock Pulse High Time tHIGH 0.6 usec

note 1 : when to use I2C Bus Standard mode, tSU:DAT >- 250 ns must be met.

note 2 : when the AK8817VQ is used in such bus interface where tLOW is not extended ( at minimum specification of

tLOW ), this condition must be met.

tR

tLOW

SDA

tBUF tHD:STA

tF tR

tF tSU:STO

tSU:STA

SCL

VSDAH

VSDAL

VSDAH

VSDAL

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Device Control Interface

The AK8817VQ is controlled via I2C Bus Control Interface.

[ I2C SLAVE Address ]

2C Slave Address is 0x40

[ I2C Control Sequence ]

(1) Write Sequence

When the Slave Address of the AK8817VQ Write mode is received at the first byte, Sub Address at the second byte and

Data at the third and succeeding bytes are received.

There are 2 operations in Write Sequence - a sequence to write at every single byte, and a sequential write operation to

write multiple bytes successively.

(a) 1 Byte Write Sequence

S Slave

Address w A Sub

Address A Data A Stp

8-bits 1bit 8-bits 1bit 8-bits 1bit

(b) Multiple Bytes ( m-bytes ) Write Sequence ( Sequential Write Operation )

S Slave

Address w A

Sub

Address

(n)

A Data(n) A Data(n+

1) A Data(n+m) A stp

8-bits 1bit 8-bits 1bit 8-bits 1bit 8-bits 1bit

….

8-bits 1bit

(2) Read Sequence

When the Slave Address of the AK8817VQ Read mode is received, Data at the second and succeeding bytes are

transmitted.

S Slave

Address

w A

Sub

Address

(n)

A

rS Slave

Address

RA

Data1

A

Data2

A

Data3

A

… Data n

Ā

stp

8-bits 1 8-bits 1 8-bits 1 8-bits 1 8-bits 1 8-bits 1 8-bits 1

Abbreviated terms listed above mean :

S, rS : Start Condition

A : Acknowledge ( SDA Low )

A- : Not Acknowledge ( SDA High )

stp : Stop Condition

R/W 1 : Read 0 : Write

: to be controlled by the Master Device. Micro-computer interface is output normally .

: to be controlled by the Slave Device. To be output by the AK8817VQ.

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Video Encoder Functional Outline

(1) Reset

(1-1) Reset of Serial Interface part ( asynchronous reset )

Reset is made by setting RSTN pin to low.

(1-2) Reset of other than Serial Interface blocks

Reset is made by keeping RSTN pin low for a longer than 100 clock time, in normal operation.

(1-3) at Power-On-Reset ( including power-down release case )

Follow the power-on-reset sequence.

At the completion of each initialization, all internal registers are set to default values ( refer to Register Map ). Right after

the reset, Video output of the AK8817VQ is put into Hi-Z condition.

(2) Power-Down

It is possible to put the device into power-down mode by setting the AK8817VQ power-down pin to GND.

Transition to power-down mode should be followed by the power-down sequence. As for the recover from the

power-down mode, it should be followed by the power-down release sequence.

(3) Master Clock

A following clock should be input as a Master clock.

In Encoder Mode operation ( a synchronized clock with input data is required )

When ITU-R BT.601 data is input

( PIXRT-bit = 0 )

When Square Pixel data is input

( PIXRT-bit = 1 )

NTSC Encoder 27MHz 24.5454MHz

PAL Encoder 27MHz 29.50MHz

(4) Video Signal Interface

Video input signal ( data ) should be synchronized in either of the following methods :

* Slave mode operation where synchronization is made with HSYNC ( HDI ) / VSYNC ( VDI ).

* ITU-R BT. 656 I / F ( EAV decode ) (only 27MHz operation)

(5) Pixel Data

Input data to the AK8817VQ is YCbCr ( 4:2:2 ).

Data with Y : 16 ~ 235 and CbCr : 16 ~ 240 should be input.

(6) Video Signal Conversion

Video Re-Composition module converts the multiplexed data ( ITU-R BT.601 Level Y, Cb, Cr ) into interlaced

NTSC-M and PAL-B, D, G, H, I data. Video encoding setting is done by “Control 1 Register “.

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(7) Luminance Signal Filter ( Luma Filter )

Luminance signal is output via LPF ( see x2 Luma Filter in the block diagram ).

-50

-40

-30

-20

-10

0

10

0.01.02.03.04.05.06.07.08.09.010.011.012.013.0

frequency[MHz]

Gain[dB]

(8) Chroma Signal Filter ( Chroma Filter )

Chroma input signal components ( Cb, Cr ) prior to the modulation go through a 1.3 MHz Band Limiting Filter

( see 4:2:2 to 4:4:4 x2 interpolator in the block diagram ).

Chroma signal which is modulated by the sub-carrier is output via a low pass filter ( Chroma LPF in the block diagram ).

Frequency response of each filter is shown below.

4:2:2 to 4:4:4 Interpolator Filter

-50

-40

-30

-20

-10

0

10

0.00.51.01.52.02.53.03.54.04.55.05.56.06.5

Frequency[MHz]

Gain[dB]

x 2 Interpolator Filter

-50

-40

-30

-20

-10

0

10

0.01.02.03.04.05.06.07.08.09.010.011.012.013.0

frequency[MHz]

Gain[dB]

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(9) Color Burst Signal

Burst signal is generated by a 32 bit digital frequency synthesizer.

Color Burst Frequency is selected by mode setting of NTSC / PAL.

Standerd Subcarrier Freq

(MHz)

Video Process 1

VMOD-bit

NTSC-M 3.57954545 0

PAL-B,D,G,H,I 4.43361875 1

Burst Signal Table

(10) Sub - Carrier Reset

A function to reset sub-carrier by Color Frame sequence.

Reset function can be turned “OFF “ by setting SCR-bit of Control 1 Register.

Default value is set to enable Sub-carrier reset.

SCR 0 1

NTSC Sub-carrier phase is reset in every 2 Frames

( 4 Fields ) Sub-carrier reset is not done

PAL Sub-carrier phase is reset inevery 4 Frames

( 8 Fields ) Sub-carrier reset is not done

(11) Setup processing

Setup processing can be performed on Video signal by Control 2 Register Setup-bit.

Following processing is made on Luminance signal ( Y signal ) and Chroma signal ( C signal ) by the Setup processing.

Y Setup = Y x 0.925 + 7.5 IRE where Y setup is the Luminance signal after Setup processing.

C Setup = C x 0.925 where C Setup is the Chroma signal after Setup processing.

(12) Video DAC

The AK8817VQ has a 9 Bit resolution, current-drive DAC as a video DAC which runs at 29.5 / 24.5454 MHz or 27.00MHz

clock frequency.

This DAC is designed to output 1.28 V o-p at full scale under the following conditions loading resistance of 390 ohms,

VREF at 1.23 V and IREF pin resistor of 12k ohms.

[ VREF ] pin should be connected to ground via a 0.1 uF or larger capacitor.

DAC output can be turned “ON” or “OFF” by register setting and current consumption can be lowered.

When the output is turned off, it is put into high impedance condition.

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(13) Video Amp

AK8817VQ has Video amp that can drive 150ohm with Low pass filter. It can also possible to compensate SAG distortion.

To compensate SAG external capacitor is 47uF and 1uF as shown following figure. Recommendation voltage when SAG

compensation circuit is used is 3V or more.

VOUT pin and SAG pin should be shorten when SAG Compensation is not used. Output pin should make AC coupling.

SAG Compensation circuit can be set on or off with setting register.

In case of not using internal Video amp (Only DAC use case), Video Amp becomes power down. In this case SAG and

VOUT should be Open.

AK8817

VOU

T

SAG

47uF

1uF 75ohm

SAG Compensation ON

AK8817

VOUT

SAG

75ohm

SAG Compensation Off

100uF

VAMPMD[1:0] Operation Conditions

00 Video Amp OFF + SAG Compensation OFF Only DAC output

01 Video AMP ON + SAG Compensation ON Recommendation Voltage of

DVDD/AVDD is 3v or more.

10 Video Amp ON + No SAG Compensation SAG pin and VOUT should be

shorten.

11 Reserved

[AK8817VQ]

MS1113-E-00 2009/08

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(14) Video Data Interface Timing

Data is captured by a clock which is fed on CLKIN pin.

The Video Encoder receives a clock from a controller ( refer to the following diagram ).

In Slave mode operation, Synchronization is made with HDI / VDI.

In ITU-R BT.656 mode operation, HDI / VDI are not required.

Controller

AK8817

CLKIN

(H D I)

(VD I)

D[7:0]

[AK8817VQ]

MS1113-E-00 2009/08

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(14-2) Video Interface mode

The AK8817VQ synchronizes with input signal by the following, 2 interface modes.

(a) Slave-mode interface where synchronization is made with externally-fed synchronization signals HDI / VDI

( HDI / VDI interface )

(b) ITU-R BT.656 Interface mode ( 656 interface )

interface mode setting is controlled by [REC656]-bit of Control 2 Register.

REC656-bit Operation

0 HDI / VDI Slave mode

1 ITU-R BT.656 Interface mode

(a-1) Timing signal ( HDI / VDI ) VS Data input relation

Horizontal Synchronization ( in-line Pixel Sync ) is made with HDI synchronization timing signal.

Vertical Synchronization ( in-line Frame Line Sync ) is made with VDI synchronization timing signal.

Recognition of Video Field ( Odd Field or Even Field ) is made by VDI input signal which is referenced with HDI.

In normal operation, the AK8817VQ checks changes of HDI and VDI at the clock edge ( CLK synchronization )

which becomes a data capture reference position.

At a pixel position where HDI is judged to become “ Low “, it is recognized as 0H (zero th position ).

Cb0 data position depends on input data rate ( ITU-R BT.601 or Square Pixel data ).

Cb0 Data

At ITU-R BT.601 Data input At Square Pixel data input

NTSC Encoder 244th data 236th data

PAL Encoder 264th data 310th data

Video Field is recognized by the VDI relation with HDI.

Field recognition is made as follows :

The AK8817VQ distinguishes at every Field if it is Odd Field ( 1st Field ) or not. Even Field Sync signal is not usually input.

1 ) Recognition timing of Odd Field is decided by those timing signal relations which are fed on HDI and VDI pins.

When the VDI falling pulse is input on VDI input pin during the time from 3 clocks prior to the falling edge of

HDI timing pulse which is fed on HDI input till 3 clocks prior to the rising edge of HDI timing pulse, the Line is

recognized to be Line 4.

HDI

Line4/Line1(NTSC/PAL) Line5/Line2(NTSC/PAL)

VDI

3CLK

Line6/Line3(NTSC/PAL)

2 ) Whenever Horizontal / Vertical SYNC signal inputs are not fed as expected in the Video Specifications, in term of

timing and # of pulses ( kept at “ High “ level ), the AK8817VQ continues to self-run the operation which is based on the

Sync

signals, fed just before.

But it is recommended to feed Sync signals as specified every time in order to prevent erroneous operation.

3 ) VD pulse input at other than Odd Field synchronization is ignored ( Synchronization is made with Odd Field only ).

[AK8817VQ]

MS1113-E-00 2009/08

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(a-2) Horizontal Synchronization ( Pixel Data synchronization within a Line )

(a-2-1) at ITU-R BT. 601 data input case

(a-2-1-1) NTSC

CLKIN

(27.00MHz)

DTI[7:0] Cb0 Y0 Cr0 Y1 Cb1 Cr359 Y719

HDI

720 x 2 Clock

Active Video Area

(0x80) (0x10)(0x80) (0x10) (0x80) (0x10)(0x10)

0H

1715 0 244 245 246 247 248 1684 1683

244T

(0x10)

1713

(0x80)

1714

* ) when D [7:0], HDI and CLKIN are in same phase relation as a timing example above, the AK8817VQ takes input data

at

the falling edge of each CLKIN if CLKEDGE-bit = 1.(CLKINV = 1.)

* ) as an input data other than during active video period, Black level ( C / Y = 0x80 / 0x10 ) or other than 0x00 / 0xFF

codes in non Hi-Z state should be input.

(a-2-1-2) PAL

CLKIN

(27.00MHz)

DTI[7:0] Cb0 Y0 Cr0 Y1 Cb1 Cr359 Y719

HDI

720 x 2 Clock

Active Video Area

(0x80) (0x10)(0x80) (0x10) (0x80) (0x10)(0x10)

H0

1727 0 264 265 266 267 268 1704 1703 1702

264T

(0x10)

1725

(0x80)

1726

*) when D [7:0], HDI and CLKIN are in same phase relation as a timing example above, the AK8817VQ takes input data at

the falling edge of each CLKIN if CLKEDGE-bit = 1. .( CLKINV = 1.)

* ) as an input data other than during active video period, Black level ( C / Y = 0x80 / 0x10 ) or other than 0x00 / 0xFF

codes in non Hi-Z state should be input.

[AK8817VQ]

MS1113-E-00 2009/08

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(a-2-2) at Square Pixel Rate input case

(a-2-2-1) NTSC

CLKIN

(24.5454MHz)

D[7:0] Cb0 Y0 Cr0 Y1 Cb1 Cr319 Y639

HDI

640 x 2 Clock

Active Video Area

(0x80) (0x10)(0x80) (0x10)(0x80) (0x10) (0x10)

H0

1559 0 TBD 236 237 238 239 240 151615151514

* ) when D [7:0], HDI and CLKIN are in same phase relation as a timing example above, the AK8817VQ takes input data

at

the falling edge of each CLKIN if CLKINV = 1.

* ) as an input data other than during active video period, Black level ( C / Y = 0x80 / 0x10 ) or other than 0x00 / 0xFF

codes in non Hi-Z state should be input.

(a-2-2-2) PAL

CLKIN

(29.5MHz)

D[7:0] Cb0 Y0 Cr0 Y1 Cb1 Cr383 Y767

HDI

768 x 2 Clock

Active Video Area

(0x80) (0x10)

(0x80) (0x10)(0x80) (0x10) (0x10)

H0

1887 0 TBD 310 311 312 313 314 1844 1845 1846

* ) when D [7:0], HDI and CLKIN are in same phase relation as a timing example above, the AK8817VQ takes input data

at

the falling edge of each CLKIN if CLKINV-bit = 1. .(CLKINV = 1.)

* ) as an input data other than during active video period, Black level ( C / Y = 0x80 / 0x10 ) or other than 0x00 / 0xFF

codes in non Hi-Z state should be input.

[AK8817VQ]

MS1113-E-00 2009/08

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( a-3 ) HDI and VDI relation in each Frame

( a-3-1 ) NTSC ( Frame ) 525 Line 480 active lines

The First Field ( ODD )

HDI

VDI

4 5 6 7 22 233 1 525 2 261 262 263 264

240 lines

263 lines

* )VDI negative-going should be fed during the time from 3 clocks prior to negative-going of HDI at L4 till 3 clocks prior to positive-going of HDI.

VDI positive-going can occurs at arbitrary location, but keep VDI low for 3 line duration time as a rough idea.

The Second Field ( EVEN )

HDI

VDI

267 268 269 270 285 286266264 263 265 524 525 1 2

240 lines

High

262 lines

* ) VDI negative-going is not required for the Second Field. It is required for the First Field only ( VDI fed during the Second Field is ignored ).

[AK8817VQ]

MS1113-E-00 2009/08

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( a-3-2 ) PAL ( Frame ) 625 Line 576 active lines

The First Field ( ODD )

HDI

VDI

4 5 22 23 243 1 625 2 310 311 312 313

288lines

313lines

314

* ) VDI negative-going should be fed during the time from 3 clocks prior to negative-going of HDI at L1 till 3 clocks prior to positive-going of HDI.

VDI positive-going can occur at arbitrary location, but as a rough idea, keep VDI low for 2.5, or 2 or 3 line- duration time.

Data fed at Line 23 is not output on Video output

The Second Field (EVEN)

HDI

VDI

317 318 335 336 337316314 313 315 623 624 625 1

288lines

313lines

2

High

*) VDI negative-going is not required for the Second Field. It is required for the First Field only ( VDI fed during the Second Field is ignored ).

Data fed at Line 623 is not output.

[AK8817VQ]

MS1113-E-00 2009/08

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( b-1 ) ITU-R BT.656 Interface mode

The AK8817VQ makes a synchronization with an incoming signal by decoding EAV in the signal when ITU-R BT.656

encoded signal is input.

EAV code is located at the following position in the Video stream ( this mode of operation is not supported in the Square

Pixel clock operation ).

EAV SAV

Y/ Cb/ Cr Cb Y Cr Y Cb Y Cr Y Cb Y Cr Y Cb Y Cr Y Cb Y Cr Y Cb

Dat a#

525 syst em 360 720 360 721 361 722 361 723 368 736 368 855 428 856 428 857 0 0 0 1 1

Dat a#

625 syst em 360 720 360 721 361 722 361 723 366 732 366 861 431 862 431 863 0 0 0 1 1

33 / 25T (525 / 625) 243 / 263T (525 / 625)

CLKI

N

HDI

276/ 288T (525 / 625)

[AK8817VQ]

MS1113-E-00 2009/08

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( 1 ) EAV Synchronization

an EAV code which is encoded on input signal is decoded, and the device makes synchronization with its timing.

EAV / SAV codes are as follows.

Those codes succeeding 0xFF- 0x00- 0x00 which are fed as input data in 8-bit form become EAV / SAV codes.

EAV / SAV codes have following meanings, starting with MSB.

Bit Number MSB LSB

WORD VALUE 7 6 5 4 3 2 1 0

0 0xFF 1 1 1 1 1 1 1 1

1 0x00 0 0 0 0 0 0 0 0

2 0x00 0 0 0 0 0 0 0 0

3 0xxx 1 F V H P3 P2 P1 P0

here,

F = 0 : Field 1

= 1 : Field 2

V = 0 : other than Filed Blanking (V-Blanking)

= 1 : Filed Blanking (V-Blanking)

H = 0 : SAV

= 1 : EAV

P3, P2, P1, P0 : Protection Bit

Protection Bit and F / V / H relation is shown in the following table.

F V H P3 P2 P1 P0

0 0 0 0 0 0 0

0 0 1 1 1 0 1

0 1 0 1 0 1 1

0 1 1 0 1 1 0

1 0 0 0 1 1 1

1 0 1 1 0 1 0

1 1 0 1 1 0 0

1 1 1 0 0 0 1

At NTSC data input case

Cb Y Cr Y Cb Y Cr Y Cb Y Cr Y Cb Y Cr Y

359 718 359 719 360 720 360 721 428 856 428 857 0 0 0 1

EAV

……

SAV

At PAL data input case

Cb Y Cr Y Cb Y Cr Y Cb Y Cr Y Cb Y Cr Y

359 718 359 719 360 720 360 721 431 862 431 863 0 0 0 1

EAV

……

SAV

[AK8817VQ]

MS1113-E-00 2009/08

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( 1-1 ) EAV / SAV Code and Line Synchronization

The AK8817VQ makes Vertical synchronization ( Line synchronization ) when F-bit in EAV makes transition from

“ 1 “ to “ 0 “.

F-bit of EAV / SAV and Line relation is as follows

F-bit NTSC PAL

0 Line4 – Line265 Line1 – Line312

1 Line266 – Line525

Line1 – Line3 Line313 – Line625

For reference, V-bit of EAV / SAV and Line relation is also shown below.

Field V-bit NTSC PAL

Start (V=1) Line1 – Line19 Line624 – Line625 – Line22

Field 1 End (V=0) Line20 – Line263 Line23 – Line310

Start (V=1) Line264 – Line282 Line311 – Line335

Field 2 End (V=0) Line283 – Line525 Line336 – Line623

Digital

Line-No.

F-bit

267 268 269 270 271 272266

Digital

Line-No.

F-bit

4 5 6 7 8 9 3 2 1

265 264 263

Line Synchronization by EAV at NTSC input case

synchronization is made at this timing

Digital

Line-No.

F-bit

314 315 316 317 318 319313

Digital

Line-No.

F-bit

1 2 3 4 5 6 625624 623

312 311 310

Line Synchronization by EAV at PAL input

622

synchronization is made at this timing

[AK8817VQ]

MS1113-E-00 2009/08

-28-

(15) On-chip Color Bar

The AK8817VQ can output Color Bar signal.

Color Bar signal to be generated has 100 % amplitude and 75 % Saturation levels.

Color Bar signal is output by setting register.

When to output Color Bar signal, there are 2 modes of operation – one is external Sync timing mode for normal

operation, and the other is internal self-operation mode.

In internal self-operating mode, required timing is internally generated automatically. Namely, it is no need to input

synchronization timing from outside of the chip.

Operation mode setting is done by Control 1 Register .

When BBG-bit is set, BBG-bit is prioritized ( Black Burst is output ).

Blanking Level

100%White

Synctip Level

WHITE

YELLOW

CYAN

GREEN

MAGENTA

RED

BLUE

BLACK

The following values are code for ITU-R. BT601

WHITE YELLOW CYAN GREEN MAGENTA RED BLUE BLACK

Cb 128 44 156 72 184 100 212 128

Y 235 162 131 112 84 65 35 16

Cr 128 142 44 58 198 212 114 128

(16) Black Burst Signal generation function

The AK8817VQ can output Black Burst signal ( Black level output ).

When to output Black Burst signal, there are 2 modes of operation – one is external Sync timing mode for normal

operation , and the other is internal self-operation mode.

In internal self-operation mode, required timing is internally generated automatically. Namely, it is no need to input

synchronization timing from outside of the chip.

When BBG-bit of [ Control 1 Register ] is set to “1”, same operation is processed as in the case where fixed-16 Y signal

and

fixed-128 Cb / Cr signal outputs are input.

Operation mode setting is done by Control 1 Register setting.

[AK8817VQ]

MS1113-E-00 2009/08

-29-

(17) Video ID

The AK8817VQ supports to encode the Video ID ( EIAJ CPR-1204 ) which distinguishes the aspect ratio etc..

This is also used as CGMS ( Copy Generation Management System ).

Turning “ON/OFF” of this function is made by setting both VMOD-bit = 0 and VBID-bit = 1 of { Control 1 Register (0x00) }.

And data to be set is written into { VBID / WSS Data1 & 2 Registers ( 0x02,0x03 )}.

Video ID information is the highest order of priority information among VBI information

VBID Data Update timing .

VSYNC

NEW DATA

DATA OLD DATA NEW DATA

u-P Data

Set Control Register

VBID Code assignment

20 bit data is configured with WORD0 = 2 bit, WORD1 = 4 bit, WORD2 = 8 bit and CRC = 6 bit.

CRC is automatically calculated and added by the AK8817VQ.

Default values of CRC polynomial expression X6 + X + 1 are all ones.

-data configuration

bit1 bit20

DATA

WORD0

2bit

WORD1

4bit

WORD2

8bit

CRC

6bit

VBID Waveform

Ref. bit1 bit2 bit3 bit20

•••

2.235usec +/- 50nsec

11.2usec +/- 0.3usec 49.1usec +/- 0.44usec

1H

70IRE +/- 10IRE

0IRE + 10 IRE

− 5 IRE

525/60 System

Amplitude 70IRE

Encode Line 20/283

[AK8817VQ]

MS1113-E-00 2009/08

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( 17 ) WSS function

The AK8817VQ supports to encode the WSS ( ITU-R. BT.1119 ) which distinguishes the aspect ratio and sets CGMS-A

etc..

Turning “ON/OFF“ of this function is made by setting both VMOD-bit = 1 and WSS-bit = 1 of { Control 1 Register ( 0x00 ) }.

And data to be set is written into { VBID / WSS Data1 & 2 Registers ( 0x02, 0x03 )}.

WSS Data Update timing

VSYNC

NEW DATA

DATA OLD DATA NEW DATA

u-P Data

Set Control Register

WSS Waveform

10.5usec

27.4usec

38.4usec

500mV +/- 5%

11.0 +/- 0.25usec

44.5usec

1.5usec

0H

Encode line : former half of Line 23 ( Blank output during latter half )

Coding : Bi-phase modulation coding

Clock : 5 MHz ( Ts = 200 nS )

Encoding details as follows

Run-in Start code

Group 1

Aspect ratio

Group 2

Enhanced

Services

Group 3

Subtitles Group4 Reserved

29 elements 24 elements 24 elements 24 elements 18 elements 18 elements

Bit numbering

0 1 2 3

LSB MSB

0 : 000111

1 : 111000

Bit numbering

4 5 6 7

LSB MSB

0 : 000111

1 : 111000

Bit numbering

8 9 10

LSB MSB

0 : 000111

1 : 111000

Bit numbering

11 12 13

LSB MSB

0 : 000111

1 : 111000

0x1F1C71C7 0x1E3C1F

[AK8817VQ]

MS1113-E-00 2009/08

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SYNC Signal waveform, Burst Waveform generator

(1) NTSC-J

90%

50%

10%

50%

Sync rise time

Sync

Horizontal

reference point

50%

Sync Level

50%

H . ref. to B urst Start

Burst Height

Burst

measurement

point value Consumer Quality

tolerance

units

Total line period(derived) 63.556 usec

Sync Level 40 +/- 3 IRE

Sync rise time 10% - 90% 140 Max 250 nsec

Horizontal Sync width 50% 4.7 +/- 0.1 usec

Horizontal reference point to

burst start 50% 19 defined by SC/H cycles

Burst * 50% 9 +/- 1 cycles

Burst Height ** 40 +/- 3 IRE

* there is a case where tolerance of Sync rise time is added to Sync width tolerance.

* Measurement of Burst time length is made between the Burst start point which is defined as the zero-cross point,

preceding the first half-cycle of the sub-carrier where Burst amplitude becomes higher than 50 % level and the Burst end

point, defined in the same manner.

9 cycles +/- 1cycle

19 cycles +/-10°

50%

NTSC Signal

[AK8817VQ]

MS1113-E-00 2009/08

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(2) Vertical Sync Signal timing ( NTSC )

3H 3H

1 2 3 456 789

0.5H

3H

3H 3H

263 264

0.5H

3H

265 266 2 67 268 269 270 271 272 2 73

21

285

525

262

Equalizing Pulse and Serration Pulse

Equalizing Pulse Serration Pulse

G H

40IRE

I I I I

+/-3IRE

Symbol Measurement

point Value Recommended

tolerance units

G Pre-equalizing pulse width 50% 2.3 +/- 0.1 usec

H Vertical serration pulse width 50% 4.7 +/- 0.2 usec

G Post-equalizing pulse width 50% 2.3 +/- 0.1 usec

I Sync rise time 140 Max 250 nsec

* there is a case where tolerance of Sync rise time is added to Pulse width tolerance.

[AK8817VQ]

MS1113-E-00 2009/08

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(3) PAL-B,D,G,H,I

90%

50%

10%

50%

Sync rise time

Horizontal Sync

Horizontal

reference point

50%

Sync Level

50%

H . ref. to B urst Start

Burst Height

Burst

measurement

point value Consumer Quality

tolerance units

Total line period(derived) 64.0 usec

Sync Level 300 +/- 20 mV

Sync rise time 10% - 90% 0.2 Max 0.3 usec

Horizontal Sync width 50% 4.7 +/- 0.2 usec

Horizontal reference point to

burst start 50% 5.6 +/- 0.1 usec

Burst * 50% 10 +/- 1 cycles

Burst Height ** 300 +/- 30 mV

* there is case where tolerance of Sync rise time is added to Sync width tolerance.

[AK8817VQ]

MS1113-E-00 2009/08

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(4) Vertical Sync Signal timing and Burst Phase

PAL-B,D,G,H,I

313 314 315 316 317 318 320 319 321 322311 312 310 309 308

A B

313 314 315 316 317 318 320 319 321 322311 312 310 309 308

A B

623 624 625 123 456 87 622 621 620

A B

623 624 625 123 456 87 622 621 620

A : Phase of Burst : nominal Value + 135°

B : Phase of Burst : nominal Value - 135°

Since Burst frequency and Line frequency are not practically in integer-multiple relation, specified phase value is not

exactly 135 degrees.

Diagram below shows phase direction.

Equalizing Pulse and Serration Pulse

Equalizing Pulse Serration Pulse

G H

300mV

I I I I

+/-30mV

Symbol Measurement

point Value Recommended

tolerance units

G Pre-equalizing pulse width 50% 2.35 +/- 0.1 usec

H Vertical serration pulse width 50% 4.7 +/- 0.2 usec

G Post-equalizing pulse width 50% 2.35 +/- 0.1 usec

I Sync rise time 200 Max 300 nsec

* there is a case where tolerance of Sync rise time is added to Pulse width tolerance.

[AK8817VQ]

MS1113-E-00 2009/08

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Register Map

Address Register Default R/W Function

0x00 Control 1 Register 0x00 R/W Mode set Register

0x01 Control 2 Register 0x00 R/W Mode set Register

0x02 VBID/WSS Data 1 Register 0x00 R/W VBID data is set, WSS data is set

0x03 VBID/WSS Data 2 Register 0x00 R/W VBID data is set, WSS data is set

0x04 Input Control Register 0x00 R/W Input control register for out-of-standard quality input

signal

0x05 Device ID & Revision ID Register 0x17 R Register for Device ID and Revision ID

[AK8817VQ]

MS1113-E-00 2009/08

-36-

Control 1 Register (R/W) [Address 0x00]

Sub Address 0x00 Default Value 0x00

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

DAC BBG CBG MASMD WSS VBID SCR VMOD

Default Value

0 0 0 0 0 0 0 0

Control 1 Register Definition

BIT Register Name R/W Definition

bit 0 VMOD Video Mode bit R/W 0: NTSC

1: PAL

bit 1 SCR Sub-Carrier Reset bit R/W 0 : Sub-Carrier Reset

1 : Sub-Carrier Reset off

bit 2 VBID VBID Set bit R/W 0 : VBID OFF

1 : VBID ON

bit 3 WSS WSS Set bit R/W 0 : WSS OFF

1 : WSS ON

bit 4 MASMD Master Mode bit R/W

Master Mode bit to set Sync mode when Color Bar signal and

Black Burst signal are generated

0 : operation by an external Sync timing

1 : operation by an internal self-operating mode ( master

mode )

note ) Master mode bit is still valid in normal data input, but

output video is not synchronized.

bit 5 CBG Color Bar Generator

bit R/W

0: OFF

1: ON

when BBG is set, BBG is prioritized.

bit 6 BBG Black Burst Generator

bit R/W 0 : OFF

1 : ON

bit 7 DAC DAC Set bit R/W 0 : DAC OFF

1 : DAC ON

[AK8817VQ]

MS1113-E-00 2009/08

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Control 2 Register (R/W) [Address 0x01]

Sub Address 0x01 Default Value 0x00

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Reserved Reserved Reserved VAMPMD1 VAMPMD0 SETUP REC656 PIXRT

Default Value

0 0 0 0 0 0 0 0

Control 2 Register Definition

BIT Register Name R/W Definition

bit 0 PIXRT Pixel Rate Set bit R/W

Pixel rate setting is done.

0 : ITU-R BT.601 data input ( at 27 MHz rate )

1 : Square Pixel data input

NTSC : 24.5454 MHz PAL : 29.50 MHz

bit 1 REC656 Rec656 Set bit R/W

Synchronization mode setting is done.

0 : synchronization is made with HDI / VDI input.

1 : synchronization is made with ITU-R BT.656 data input

bit 2 SETUP Setup bit R/W

Set-up setting is done

0 : with no set-up

1 : with 7.5 IRE set-up

bit 3

~

bit 4

VAMPMD0

~

VAMPMD1

VIdeo Amp Mode Set

bit R/W

Operation mode for Video Amp.

VAMPMD[1:0]

00: Video Amp OFF + SAG Compensation OFF

01: Video AMP ON + SAG Compensation ON

10: Video Amp ON + No SAG Compensation

11: Reserved

bit 5

~

bit 7

Reserved Reserved bit R/W Set “0”

[AK8817VQ]

MS1113-E-00 2009/08

-38-

VBID/WSS 1 Register (R/W) [Address 0x02]

VBID/WSS 2 Register (R/W) [Address 0x03]

Video ID and WSS data setting are made. A common data register is used for both video ID and WSS data.

When VBID bit of mode register is set in NTSC mode, data is for VBID data ,and when WSS bit of Control 1 Register is set

in

PAL mode, data is for WSS data.

When VBID-bit is “1” and VMOD-bit is “0” in Control 1 Register , the following bits are assigned.

Sub Address 0x02 default Value 0x00

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

VBID7 VBID8 VBID9 VBID10 VBID11 VBID12 VBID13 VBID14

Default Value

0 0 0 0 0 0 0 0

Sub Address 0x03 default Value 0x00

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Reserved Reserved VBID1 VBID2 VBID3 VBID4 VBID5 VBID6

Default Value

0 0 0 0 0 0 0 0

Note ) “0” should be written into reserved bits.

VBID1 ---- VBID14 above correspond to the bit 1 ---- bit 14 which are described at { VBID Data Code Assignment } in

{ ( 14 ) Video ID } section.

A 6-bit CRC code from bit 15 ~ bit 20 is automatically added by the AK8817VQ.

Data is retained till data is updated to a new one.

Following bits are assigned when WSS-bit is “1” and VMOD-bit is “1” in Control 1 Register .

Sub Address 0x02 default Value 0x00

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

G2-7 G2-6 G2-5 G2-4 G1-3 G1-2 G1-1 G1-0

Default Value

0 0 0 0 0 0 0 0

Sub Address 0x03 default Value 0x00

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Reserved Reserved G4-13 G412 G4-11 G3-10 G3-9 G3-8

Default Value

0 0 0 0 0 0 0 0

Note ) WSS data is written with 0x01 first, then 0x02 in this order.

When the 2nd byte ( 0x02 ) of WSS data is written, the AK8817VQ interprets that data is updated to a new one and then

encodes it to the next video line ( Line 23 ).

Data is retained till data is updated to a new one.

[AK8817VQ]

MS1113-E-00 2009/08

-39-

Input Control Register (R/W) [Address 0x04]

This is an out-of-standard quality input signal control register.

Sub Address 0x04 default Value 0x00

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Reserved CBCR VD2 VD1 VD0 HD2 HD1 HD0

0 0 0 0 0 0 0 0

Adjustment of Sync input timing is made.

BIT Register Name R/W Definition

bit 0

~

bit 2

HD0

~

HD2

HDI Input Delay R/W HDI signal input is delayed by the set value.

HD [ 2:0 ] system clock count delay ( + 0 ~ + 7 CLK delay )

bit 3

~

bit 5

VD0

~

VD2

VDI Input Delay R/W VDI signal input is delayed by the set value.

VD [ 2:0 ] system clock count delay ( + 0 ~ + 7 CLK delay )

bit 6 CBCR Exchange CbCr R/W Cb, Cr timing data are interchanged at CBCR = 1.

bit 7 Reserved Reserved R/W Reserved

[AK8817VQ]

MS1113-E-00 2009/08

-40-

Device ID and Revision ID Register (R) [Address 0x05]

Register to show Device ID & Revision of the AK8817VQ.

Device ID for AK8817VQ is 0x17(decimal)

Initial Version of the Revision ID is 0x00.

Revision number is modified only when a control software needs to be modified.

Sub Address 0x5 default Value 0x17

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Rev1 REV0 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0

0 0 0 1 0 1 1 1

Device ID and Revision ID Register Definition

BIT Register Name R/W Definition

bit 0

~

bit 5

DEV0

~

DEV2

Device ID bit R To show Device ID

Device ID is 0x17h.

bit 6

~

bit 7

REV0

~

REV2

Revision ID bit R

To show Revision information

Revision ID is updated when software modification is to be

expected.

It is 0x00.

[AK8817VQ]

MS1113-E-00 2009/08

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System Connection Example

HSYNC

VSYNC

D[7:0]

A

nalog 3.0V

390ohm

DACOUT

IREF

VREF

0.1uF

A

VSS

12kohm

A

VDD

0.1uF 10uF

CLKIN

TEST

ATPG

DVSS

DVDD

AK8817VQ

VOUT

SAG

75 ohm

Clock

CLKINV

I2C SDA

SCL

RSTN

PDN

u-P

PVD

D

PVSS

PVD

D

HDI

VDI

47uF

1uF

Digital 3.0V

AVSS DVSS

[AK8817VQ]

MS1113-E-00 2009/08

-42-

Package Drawing

48pin LQFP

0.10 M

0.17±0.05

1.00

0.50±0.20

0.10±0.07

0.10

12

13

24

2536

37

48

7.00

9.00±0.20

7.00

0.19±0.05

1

0.50 0～゜ 10゜

S

1.4TYP

1.60MAX

[AK8817VQ]

MS1113-E-00 2009/08

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Package Marking Drawing

1

A

KM

AK8817VQ

XXXXXXX

AKM: AKM Logo

AK8817VQ: Marketing Code

XXXXXXX (7 digits): Date Code

[AK8817VQ]

MS1113-E-00 2009/08

-44-

• These products and their specifications are subject to change without notice. Before considering any use or

application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor

concerning their current status.

• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or

use of any information contained herein.

• Any export of these products, or devices or systems containing them, may require an export license or other

official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency

exchange, or strategic materials.

• AKM products are neither intended nor authorized for use as critical components in any safety, life support, or

other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with

the express written consent of the Representative Director of AKM. As used here:

(a) A hazard related device or system is one designed or intended for life support or maintenance of

safety or for applications in medicine, aerospace, unclear energy, or other fields, in which its failure to

function or perform may reasonably be expected to result in loss of life or in significant injury or

damage to person or property.

(b) A critical component is one whose failure to function or perform may reasonably be expected to result,

whether directly or indirectly, in the loss of the safety or effectiveness of the device or system

containing it, and which must therefore meet very high standards of performance and reliability.

• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise

places the product with a third party to notify that party in advance of the above content and conditions, and the

buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any

and all claims arising from the use of said product in the absence of such notification.

IMPORTANT NOTICE