Am79761YC-14 - Advanced Micro Devices

PRELIMINARY

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to help you e valuate this product. AMD reserves the right to change or discontinue work on this proposed

product without notice.

Publication# 21560 Rev: AAmendment/+1

Issue Date: April 1998

Am79761

Physical Layer 10-Bit Transceiver for Gigabit Ethernet

(GigaPHY™-SD)

DISTINCTIVE CHARACTERISTICS

Gigabit Ethernet Transceiver operates at

1.25 Gigabits per second (Gbps)

Suitable for both Coaxial and Optical Link

applications

10-bit TTL Interface for Transmit and Receive

Data

Monolithic Clock Synthesis and Clock Recovery

requires no external components

Word Synchronization Function (Comma

Detect)

Low Power Operation - 700 mW typical

64-pin Standard PQFP

— 14 x 14 mm (0˚ C - 70˚ C)

— 10 x 10 mm (0˚ C - 50˚ C)

125 MHz TTL Reference Clock

Loopback Diagnostic

Single +3.3 V Supply

GENERAL DESCRIPTION

The Am79761 Gigabit Ethernet Physical Layer Serial-

izer/Deserializer (GigaPHY-SD) device is a 1.25 Gbps

Ethernet Transceiver optimized for Gigabit Ethernet/

1000BASE-X applications. It implements the Physical

Medium Attachment (PMA) layer for a single port.

The GigaPHY-SD device can interface to ﬁber-optic

media to support 1000BASE-LX and 1000BASE-SX

applications and can interface to copper coax to sup-

port 1000BASE-CX applications.

The functions perf ormed by the de vice include serializ-

ing the 8B/10B 10-bit data for transmission, deserializ-

ing received code g roups, recovering the clock from the

incoming data stream, and word synchronization.

When transmitting, the GigaPHY-SD device receives

10-bit 8B/10B code groups at 125 million code groups

per second. It then serializes the parallel data stream,

adding a reference clock, and transmits it through the

PECL drivers.

When receiving, the GigaPHY-SD device receives the

PECL data stream from the network. It then recovers

the clock from the data stream, deserializes the data

stream into a 10-bit code group, and transmits it to the

Physical Coding Sublayer (PCS) logic above. Option-

ally, it detects comma characters used to align the in-

coming word.

2 Am79761

PRELIMINARY

BLOCK DIAGRAM

D Q

Q D Serial to

Parallel

to Serial

RX+

RX-

Frame

Logic

TX+

TX-

EWRAP

RXD[0:9]

RCLK

RCLKN

COM_DET

EN_CDET

TXD[0:9]

REFCLK PLL Clock

Multiply

Clock

Recovery

Comma

Detect

21560A-1

Am79761 3

PRELIMINARY

CONNECTION DIAGRAM

LOGIC SYMBOL

DVSS

TXD0

TXD1

TXD2

DVDD

TXD3

TXD4

TXD5

TXD6

DVDD

TXD7

TXD8

TXD9

DVSS

N/C

COM_DET

DVSS_T

RXD0

RXD1

RXD2

DVDD_T

RXD3

RXD4

RXD5

RXD6

DVDD_T

RXD7

RXD8

RXD9

DVSS_T

N/C

TEST1

EWRAP

TEST2

DVSS

REFCLK

TEST3

EN_CDET

DVSS

TEST4

N/C

DVDD

DVDD_T

RCLKN

RCLK

DVSS_T

N/C

DVDD_P

TX+

TX-

DVDD_P

DVDD

AVSS

AVDD

DVSS

DVDD

RX+

DVDD_P

RX-

DVSS

DVDD

N/C

21560A-2

Note:

N/C = No Connect

Am79761

GigaPHY-SD

DVDD DVDD_T DVDD_P AVDD

DVSS DVSS_D DVSS

REFCLK

RCLK

RCLKN

EN_CDET

EWRAP

COM_DET

TEST4

TDST [3:1]

TXD [0:9]

RXD [0:9]

TX+

TX–

RX+

RX–

To PCS

Transceiver

PHY

Control

Test

Port

21560A-3

4 Am79761

PRELIMINARY

ORDERING INFORMATION

Standard Products

AMD standard products are av ailable in se veral pac kages and operating ranges. The order n umber (V alid Combination) is formed

by a combination of the elements below.

Valid Combinations

Valid Combinations list conﬁgurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

ofﬁce to conﬁrm availability of speciﬁc v alid combinations and

to check on newly released combinations.

DEVICE NUMBER/DESCRIPTION

Am79761

Physical Layer 10-Bit Transceiver for Gigabit Ethernet

GigaPHY™-SD)

PACKAGE SIZE OPTION

-10 = 10 x 10 mm body size

-14 = 14 x 14 mm body size

TEMPERATURE RANGE

C = Commercial (0˚C to +70˚C)

Am79761 CY

P ACKAGE TYPE

Y = 64-Pin Plastic Quad Flat Pack (PDH064)

-10

Valid Combinations

Am79761YC

Am79761YC -10

-14

Am79761 5

PRELIMINARY

RELATED PRODUCTS

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Am7992B Serial Interface Adapter (SIA)

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Am79C98 Twisted Pair Ethernet Transceiver (TPEX)

Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+)

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Am79C981 Integrated Multiport Repeater Plus (IMR+™)

Am79C982 basic Integrated Multiport Repeater (bIMR™)

Am79C983 Integrated Multiport Repeater 2 (IMR2™)

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Am79C985 enhanced Integrated Multiport Repeater Plus (eIMR+™)

Am79C987 Hardware Implemented Management Information Base

(HIMIB™)

Am79C988A Quad Integrated Ethernet Transceiver (QuIET™)

Am79C900 Integrated Local Area Communications Controller (ILACC™)

Am79C940 Media Access Controller for Ethernet (MACE™)

Am79C960 PCnet™-ISA Single-Chip Ethernet Controller (for ISA bus)

Am79C961 PCnet™-ISA+ Single-Chip Ethernet Controller for ISA (with Microsoft® Plug n’ Play® Support)

Am79C961A PCnet™-ISA II Full Duplex Single-Chip Ethernet Controller for ISA

Am79C965 PCnet™-32 Single-Chip 32-Bit Ethernet Controller

Am79C970 PCnet™-PCI Single-Chip Ethernet Controller (for PCI bus)

Am79C970A PCnet™-PCI II Full Duplex Single-Chip Ethernet Controller (for PCI bus)

Am79C971 PCnet™-

FAST

Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus

6 Am79761

PRELIMINARY

PIN DESIGNATION

Listed by Pin Number

Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name

1DVSS 17 N/C 33 DVSS_T 49 N/C

2 TXD0 18 TEST1 34 RXD9 50 DVDD

3 TXD1 19 EWRAP 35 RXD8 51 DVSS

4 TXD2 20 TEST2 36 RXD7 52 RX-

5 DVDD 21 DVSS 37 DVDD_T 53 DVDD_P

6 TXD3 22 REFCLK 38 RXD6 54 RX+

7 TXD4 23 TEST3 39 RXD5 55 DVDD

8 TXD5 24 EN_CDET 40 RXD4 56 DVSS

9 TXD6 25 DVSS 41 RXD3 57 AVDD

10 DVDD 26 TEST4 42 DVDD_T 58 AVSS

11 TXD7 27 N/C 43 RXD2 59 DVDD

12 TXD8 28 DVDD 44 RXD1 60 DVDD_P

13 TXD9 29 DVDD_T 45 RXD0 61 TX-

14 DVSS 30 RCLKN 46 DVSS_T 62 TX+

15 DVSS 31 RCLK 47 COM_DET 63 DVDD_P

16 N/C 32 DVSS_T 48 N/C 64 N/C

Am79761 7

PRELIMINARY

PIN DESCRIPTION

TX+, TX-

Serial T ransmit Data

PECL Output

These pins are the 1000BASE-X por t differential dr iv-

ers which transmit the serial stream to the network.

These pins are connected to the copper or ﬁber optic

connectors.

When EWRAP is LOW, the pins assume normal oper-

ation. When HIGH, TX+ is logic HIGH and TX- is logic

LOW.

RX+, RX-

Serial Receive Data

PECL Input

These pins are the 1000BASE-X port differential re-

ceiver pair, receiving a serial stream of data from the

network. These pins are connected to the copper or

ﬁber optic connectors.

When EWRAP is LOW, the pins assume normal oper-

ation. The pins are internally biased.

TXD[0:9]

Transmit Data

TTL Input

The TXD[0:9] pin is a set of 10 data signals which are

driven from the Physical Coding Subla yer (PCS) abov e.

The 10 bits of data are clocked in parallel on the rising

edge of REFCLK. TXD0 is transmitted ﬁrst on TX

RXD[0:9]

Receive Data

TTL Output

The RXD[0:9] pin is a set of 10 data signals which are

sent to the Ph ysical Coding Subla yer (PCS) abov e. The

10 bits of data are clocked out in parallel on the rising

edges of RCLK and RCLKN. RXD0 is received ﬁrst on

REFCLK

Reference Clock

TTL Input

This input is used for the 125-Mhz clock. The rising

edge of this clock latches TXD[0:9] into an input regis-

ter. This clock serves as the reference clock at 1/10th

the baud rate for the PLL.

RCLK, RCLKN

Receive Clock

TTL Output

These pins provide the differential receive clock sig-

nals, derived from the RX

data stream, and are at

1/20th the baud rate of the receiv e stream. P arallel data

on RXD[0:9] is provided at each rising transition of

RCLK and RCLKN.

EN_CDET

Enable Comma Detect

TTL Input

This pin is used to enable the word synchronization

mode. When logic HIGH, the COM_DET output is en-

abled and word synchronization is active.

COM_DET

Comma Detect Indicator

TTL Output

Comma Detect is asserted to indicate that the incoming

word on RXD[0:9] contains a Comma character

(0011111xxx). COM_DET goes HIGH f or half of a RCLK

period, and can be captured when RCKLN is rising.

In order for COM_DET to provide indication, EN_CDET

must be enabled (logic HIGH).

EWRAP

Loopback Enable

TTL Input

When EWRAP is asserted, the transmitted data stream

is sent back to the receiver through an inter nal loop-

back path. TX+ is logic HIGH, and TX- is logic LOW in

this mode.

This pin is logic LOW for normal operation.

TEST[1:3]

Factory Test Pins

Input

These pins should be tied to D VDD for normal operation.

TEST[4]

Factory Test Pin

Output

This pin should be left unconnected for normal operation.

DVDD

Power

These pins supply power to the digital blocks of the

de vice. They must be connected to a 3.3 V

5% source.

DVDD_T

TTL Power

These pins supply power to the TTL blocks of the de-

vice. They must be connected to a 3.3 V

5% source.

DVDD_P

PECL Power

These pins supply power to the PECL b loc ks of the de-

vice. The y m ust be connected to a 3.3 V

5% source. It

is critical that the signal supplied to these pins are

clean to ensure good performance of the device.

8 Am79761

PRELIMINARY

AVDD

Analog Power

These pins supply power to the analog blocks of the

device. They must be connected to a 3m.3 V

source and require careful decoupling to ensure

proper device performance.

DVSS

Ground

These pins are the ground connections for the digital

blocks. They must be connected to the common

external ground plane.

DVSS_T

Ground

These pins are the ground connections for the TTL

blocks. They must be connected to the common exter-

nal ground plane.

AVSS

Ground

These pins are the ground connections for the

analog blocks. They must be connected to an analog

ground plane.

Am79761 9

PRELIMINARY

FUNCTIONAL DESCRIPTION

Overview

The GigaPHY-SD de vice provides the PMA functionality

for 1000BASE-X systems. The GigiaPHY-SD communi-

cates with the PCS through the 10-bit code groups and

communicates with the Physical Medium Dependent

(PMD) layer to transmit and receive data from the net-

work, through either ﬁber optic or copper coax media.

The GigaPHY-SD device consists of the following

functional blocks:

1000BASE-X Transmit block including:

— Clock Synthesizer

— Serializer and Transmission interface

1000BASE-X Receive block including:

— Clock Recovery

— Deserializer

— Word Alignment and synchronization

Clock Synthesizer

The Am79761 clock synthesizer multiplies the refer-

ence frequency provided on the REFCLK pin by 10 to

achieve a baud rate clock at nominally 1.25 GHz. The

clock synthesiz er contains a fully monolithic PLL which

does not require any external components.

Serializer

The Am79761 de vice accepts TTL input data as a par-

allel 10-bit character on the TXD[0:9] bus which is

latched into the input latch on the rising edge of

REFCLK. This data will be serialized and transmitted

on the TX PECL differential outputs at a baud rate of

ten times the frequency of the REFCLK input, with bit

TXD0 transmitted ﬁrst. User data should be encoded

for transmission using the 8B/10B block code de-

scribed in the IEEE 802.3 speciﬁcation.

Transmission Character Interface

An encoded byte is 10 bits and is ref erred to as a trans-

mission character. The 10-bit interface on the

Am79761 device corresponds to a transmission char-

acter. This mapping is shown in Table 20.

Table 20. Transmission Order and Mapping of an 8B/10B Character

Clock Recovery

The Am79761 device accepts differential high speed

serial inputs on the RX

pins, extracts the clock and

retimes the data. The Am79761 cloc k recov ery circuitry

is completely monolithic and requires no e xternal com-

ponents. For proper operation, the baud rate of the

data stream to be recov ered should be within 0.01% of

ten times the REFCLK frequency. For example, if the

REFCLK used is 125 MHz, then the incoming serial

baud rate must be 1.25 gigabaud

0.01 percent.

Deserializer

The re-timed serial bit stream is conver ted into a 10-bit

parallel output character. The Am79761 device provides

complementary TTL recovered clocks, RCLK and

RCLKN, which are at 1/20th of the serial baud rate. This

architecture is designed to simplify demultiple xing of the

10-bit data characters into a 20-bit half-word in the

downstream controller chip . The clocks are generated b y

dividing down the high-speed clock which is phase

locked to the serial data. The serial data is re-timed by

the internal high-speed clock and deserialized.

The resulting parallel data will be captured by the

adjoining protocol logic on the rising edges of RCLK and

RCLKN. In order to maximize the setup and hold times

av ailab le at this interf ace , the parallel data is loaded into

the output register at a point nominally midwa y betw een

the transition edges of RCLK and RCLKN.

If serial input data is not present or does not meet the

required baud rate, the Am79761 will continue to pro-

duce a recov ered clock so that downstream logic may

continue to function. The RCLK and RCLKN output

frequency under these circumstances may differ from

their e xpected frequency b y no more than

1 percent.

Parallel Data Bits T9 T8 T7 T6 T5 T4 T3 T2 T1 T0

8B/10B Bit Position j h g f i e d c b a

Comma Character X X X 1111100

Last Data Bit

Transmitted First Data Bit

Transmitted

10 Am79761

PRELIMINARY

Word Alignment

The Am79761 device provides 7-bit comma character

recognition and data word alignment. Word synchroni-

zation is enabled by asserting EN_CDET HIGH. When

synchronization is enabled, the Am79761 device con-

stantly e xamines the serial data for the presence of the

Comma character. This pattern is 0011111XXX, where

the leading zero corresponds to the ﬁrst bit received.

The comma sequence is not contained in any normal

8B/10B coded data character or pair of adjacent char-

acters. It occurs only within special characters, known

as K28.1, K28.5, and K28.7, which are deﬁned speciﬁ-

cally f or synchronization purposes. Improper alignment

of the comma character is deﬁned as any of the follow-

ing conditions:

1. The comma is not aligned within the 10-bit trans-

mission character such that TXD0...TXD6 =

“0011111.”

2. The comma straddles the boundary between two

10-bit transmission characters.

3. The comma is properly aligned but occurs in the re-

ceived character presented during the rising edge

of RCLK rather than RCLKN.

When EN_CDET is HIGH and an improperly aligned

comma is encountered, the internal data is shifted in

such a manner that the comma character is aligned

properly in RXD[0:9]. This results in proper character

and half-word alignment. When the parallel data

alignment changes in response to an improperly

aligned comma pattern, some data which would have

been presented on the parallel output port may be

lost. However, the synchronization character and

subsequent data will be output correctly and properly

aligned. When EN_CDET is LOW, the current align-

ment of the serial data is maintained indeﬁnitely,

regardless of data pattern.

When encountering a comma character, COM_DET is

driven HIGH to inform the user that realignment of the

parallel data ﬁeld may have occurred. The COM_DET

pulse is presented simultaneously with the comma char-

acter and has a duration equal to the data, or half of an

RCLK period. The COM_DET signal is timed such that it

can be captured by the adjoining protocol logic on the

rising edge of RCLKN. Functional waveforms for

synchronization are given in Figure 18 and Figure 19.

Figure 18 shows the case when a comma character is

detected and no phase adjustment is necessary. It illus-

trates the position of the COM_DET pulse in relation to

the comma character on RXD[0:9]. Figure 19 shows the

case where K28.5 is detected, but it is out of phase and

a change in the output data alignment is required. Note

that up to three characters prior to the comma character

ma y be corrupted by the realignment process.

Figure 18. Detection of a Properly Aligned Comma Character

RCLK

RCLKN

COM_DET

RXD[0:9] K28.5 TChar TChar TChar

21560A-4

Note : TChar = 10-bit Transmission Character

Am79761 11

PRELIMINARY

Figure 19. Receiving Two Consecutive K28.5 + TCharacter Transmission Words

RCLK

RCLKN

COM_DET

RXD[0:9] K28.5 K28.5TChar TChar TChar TChar

Potentially Corrupted

21560A-5

12 Am79761

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Storage Temperature . . . . . . . . . . . .-65

C to +150

Ambient Temperature Under Bias . .-55

C to +125

Power Supply Voltage (V

) . . . . . . . -0.5 V to +4.0 V

DC Voltage (PECL Inputs) . . . . . .-0.5 V to V

+0.5 V

DC Voltage (TTL Inputs). . . . . . . . . . . -0.5 V to +5.5 V

Output Current (TTL Outputs) . . . . . . . . . . . .-

50 mA

Output Current (PECL Outputs). . . . . . . . . . .-

50 mA

Maximum Input ESD (Human Body Model). . . 1500 V

Stresses above those listed under Absolute Maximum

Ratings may cause permanent device failure.

Functionality at or above these limits is not implied.

Exposure to absolute maximum ratings for extended

periods may affect device reliability.

OPERATING RANGES

Temperature (T

) 0

C to +70

C f or 14 x 14 mm PQFP

. . . . . . . . . . . . .0

C to +50

C for 10 x 10 mm PQFP

Power Supply Voltage (D

VDD

) . . . . . . . . . +3.3 V

Operating ranges deﬁne those limits between which

functionality of the device is guaranteed.

DC CHARACTERISTICS (over recommended operating conditions)

Symbol Parameter Description Test Conditions Min Typ Max Unit

Input HIGH voltage (TTL) 2.0 — 5.5 V

Input LOW voltage (TTL) 0 — 0.8 V

Input HIGH current (TTL) V

=2.4 V — 50 500

Input LOW current (TTL) V

=0.5 V — — -500

Output HIGH voltage (TTL) I

= -1.0 mA 2.4 — — V

Output LOW voltage (TTL) I

= +1.0 mA — — 0.5 V

∆

OUT75

TX Output differential peak-to-

peak voltage swing 75

Ω

to V

– 2.0 V 1200 — 2200 mVp-p

∆

OUT50

TX Output differential peak-to-

peak voltage swing 50

Ω

to V

– 2.0 V 1200 — 2200 mVp-p

∆

Receiver differential peak-to-

peak Input Sensitivity RX Internally biased to V

/2 400 — 3200 mVp-p

Supply Current Outputs open,

= V

max — 210 290 mA

Power dissipation Outputs open,

= V

max — 700 1000 mW

Am79761 13

PRELIMINARY

Figure 20. Input Structures

DVDD

INPUT Current

Limit

DVSS DVSS

REFCLK and TTL Inputs

High Speed Differential Input

(RX±)

INPUT

INPUT All Resistors

3.3K

DVDD

21560A-6

14 Am79761

PRELIMINARY

KEY TO SWITCHING WAVEFORMS

AC CHARACTERISTICS

Figure 21. Transmit Timing Waveforms

Table 21. Transmit AC Characteristics

Must be

Steady

May

Change

from H to L

May

Change

from L to H

Does Not

Apply

Don’t Care,

Any Change

Permitted

Will be

Steady

Will be

Changing

from H to L

Will be

Changing

from L to H

Changing,

State

Unknown

Center

Line is High-

Impedance

“Off” State

WAVEFORM INPUTS OUTPUTS

KS000010-PAL

Symbol Parameter Description Test Conditions Min Max Unit

T1TXD[0:9] Setup time to the rising

edge of REFCLK

Measured between the valid data

le v el of TXD[0:9] to the 1.4 V point of

REFCLK 1.5 — ns

T2TXD[0:9] hold time after the rising

edge of REFCLK 1.0 — ns

TSDR,TSDF TX± rise and fall time 20% to 80%, 75 Ω load to VSS, T ested

on a sample basis — 300 ps

TLAT

Latency from rising edge of

REFCLK to TXD0 appearing on

TX±-

bc = Bit clocks

ns = Nano second 11bc - 1ns — —

REFCLK

TXD[0:9]

10 Bit Data Data Valid Data Valid Data Valid

T1T2

21560A-7

Am79761 15

PRELIMINARY

AC CHARACTERISTICS (Continued)

Figure 22. Receive Timing Waveform

Table 22. Receive AC Characteristics

Symbol Parameter Description Test Conditions Min Max Unit

T1Data or COM_DET Valid prior

to RCLK/RCLKN rise Measured between the 1.4 V

point of RCLK or RCLKN and a

valid level of RXD[0:9]. All

outputs driving 10 pF load.

3.0 — ns

T2Data or COM_DET Valid after

RCLK or RCLKN rise 2.0 — ns

De viation of RCLK rising edge

to RCLKN rising edge delay

from nominal. Nominal delay is 10 bit times.

Tested on sample basis -500 500 ps

Deviation of RCLK, RCLKN

frequency from nominal. Whether or not locked to serial

data -1.0 1.0 %

TR, TFRXD[0:9], COM_DET, RCLK,

RCLKN rise and fall time Between VIL(MAX) and VIH(MIN),

into 10 pf load. — 2.4 ns

Rlat Latency from RX± to RXD[0:9] bc = Bit clock

ns = Nano second 15 bc + 2 ns 34 bc + 2 ns —

TLOCK Data acquisition lock time @

1.25 Gbps 8B/10B IDLE pattern.

Tested on a sample basis — 2.0 µs

Receive Data

Jitter Receive Data Jitter Power dBc, RMS for 10-12 Bit Error

Ratio Tested on a sample basis

—40ps

RCLK

RCLKN

RXD[0:9] Data Valid Data Valid Data Valid

21560A-8

delay fbaud

----------- T 3

±=

fRCLK fREFCLK

--------------------T

±=

PhaseNoise

100KHz

2 BitTime×

--------------------------------

∫

16 Am79761

PRELIMINARY

REFERENCE CLOCK REQUIREMENTS

Figure 23. REFCLK Timing Waveform

Table 23. Reference Clock Requirements

Symbol Parameter Description Test Conditions Min Max Units

FR Frequency Range

Range over which both transmit and

receive ref erence clocks on any link ma y be

centered 123 127 MHz

FO Frequency Offset

Maximum frequency offset between

transmit and receive reference clocks on

one link -200 200 ppm

DC REFCLK duty cycle Measured at 1.5 V 30 70 %

TRCR,TRCF REFCLK rise and fall time Between VIL(MAX) and VIH(MIN) — 1.0 ns

REFCLK

TLTH

Vih (min)

Vil (max)

21560A-9

Am79761 17

PRELIMINARY

MEASUREMENTS

Figure 24. Parametric Measurement Information

TrTf

Vih(min)

Vil(max)

TTL Input and Output Rise and Fall Time

Receiver Input Eye Diagram Jitter Tolerance Task Mask

Serial Input Rise and Fall Time

80%

TrTf

20%

Bit Time

Amplitude

Eye Width%

75Ω

VDD – 2.0 V

Z0 = 75W

10 pF

Parametric Test Load Circuit

TTL AC Output LoadSerial Output Load

21560A-10

18 Am79761

PRELIMINARY

MEASUREMENTS (Continued)

Figure 25. Transmitter Jitter Measurement Method

BERT

Pattern

Generator

CLK = 1.25 GHz

DATA = 00000 0000011111 11111

DATA

PAT SYNC

Am79761

TXD[0:9]

REFCLK TX+

TX-

Digitizing

Scope

Trigger

1.25 Gbps

Single-Ended Measurement

125 MHz

TRIGGER

DATA

2 bit time 7 bit time

8 bit time

9 bit time

12 bit time

17 bit time

19 bit time

20 bit time

18 bit time

10 bit time

BERT

Pattern

Generator

CLK = 1.25 GHz

DATA = 00000 0000011111 11111

DATA

Am79761

TXD[0:9]

REFCLK TX+

TX-

Digitizing

Scope

Trigger

1.25 Gbps

Single-Ended Measurement

125 MHz

-K28.7

0011111000

Random Jitter Measurement

Random jitter (RJ) measurements performed according to Fibre Channel 4.3 Annex A, Test Methods, Section

A.4.4. Measure standard deviation of all 50% crossing points. Peak to peak RJ is

7 sigma of distribution.

Deterministic Jitter Measurement

Deterministic jitter (DJ) measurements

performed according to Fibre Channel

4.3 Annex A, Test Methods, Section A.4.3.

Measure time of all the 50% points of

all ten transitions. DJ is the range of

the timing variation from expected.

-K28.7

0011111000

-K28.5

0011111010 K28.5

1100000101

21560A-11

Transmitter Output Jitter Allocation

Trj Serial data output random jitter

(RMS) RMS, tested on a sample basis

(refer to Figure 8) —20ps

DJ Serial data output deterministic

jitter (p-p) Peak to peak, tested on a sample

basis (refer to Figure 8) — 100 ps

Am79761 19

PRELIMINARY

THERMAL CONSIDERATIONS

The Am79761 is packaged in a 14-mm or a 10-mm

conv entional PQFP with an internal heat spreader . These

packages use an industry-standard EIAJ footprint, but

have been enhanced to improve thermal dissipation. The

construction of the packages are as shown in Figure 26.

Figure 26. Package Cross Section

Table 24. Thermal Resistance

The Am79761 is designed to operate with a junction

temperature up to 105oC. The user must guarantee

that the temperature speciﬁcation is not violated. With

the Thermal Resistances shown above, the 10x10

PQFP can operate in still air ambient temperatures of

50oC , while the 14x14 PQFP can operate in still air am-

bient temperatures of 72oC . If the ambient air tempera-

ture exceeds these limits then some form of cooling

through a heatsink or an increase in airﬂow must be

provided.

Notes:

1. 50

C=110

C-1W*(10

C/W+50.8

C/W)

2. 72

C=110

C-1W*(95

C/W+29

C/W)

Symbol Description 10 mm Value 14 mm Value Units

θjc Thermal resistance from junction to case 10.0 9.5 oC/W

θca Thermal resistance from case to ambient in still air including

conduction through the leads. 50.8 29 oC/W

θca-100 Thermal resistance from case to ambient with 100 LFM airﬂow 41.2 26.1 oC/W

θca-200 Thermal resistance from case to ambient with 200 LFM airﬂow 36.9 23.8 oC/W

θca-400 Thermal resistance from case to ambient with 400 LFM airﬂow 31.8 20.5 oC/W

θca-600 Thermal resistance from case to ambient with 600 LFM airﬂow 27.8 17.9 oC/W

Copper Heat SpreaderPlastic Molding Compound

Lead Bond Wire Die

21560A-12

20 Am79761

PRELIMINARY

PHYSICAL DIMENSIONS

PDH064

64-Pin (measured in millimeters)

Trademarks

AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.

GigaPHY is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identiﬁcation purposes only and may be trademarks of their respective companies.