0.5 Ω CMOS 1.65 V TO 3.6 V
Dual SPDT/2:1 MUX
ADG836
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
0.5 Ω typical on resistance
0.8 Ω maximum on resistance at 125°C
1.65 V to 3.6 V operation
Automotive temperature range: –40°C to +125°C
High current carrying capability: 300 mA continuous
Rail-to-rail switching operation
Fast-switching times <20 ns
Typical power consumption (<0.1 µW)
APPLICATIONS
Cellular phones
PDAs
MP3 players
Power routing
Battery-powered systems
PCMCIA cards
Modems
Audio and video signal routing
Communication systems
04308-001
S1A
S1B
S2A
S2B
IN2
ADG836
D1
D2
SWITCHES SHOWN FOR A LOGIC 1 INPUT
IN1
Figure 1.
GENERAL DESCRIPTION
The ADG836 is a low voltage CMOS device containing two
independently selectable single-pole, double-throw (SPDT)
switches. This device offers ultralow on resistance of less than
0.8 Ω over the full temperature range. The ADG836 is fully
specified for 3.3 V, 2.5 V, and 1.8 V supply operation.
Each switch conducts equally well in both directions when on,
and has an input signal range that extends to the supplies. The
ADG836 exhibits break-before-make switching action.
The ADG836 is available in a 10-lead MSOP and a 3 mm × 3 mm
12-lead LFCSP.
PRODUCT HIGHLIGHTS
1. <0.8 Ω over full temperature range of –40°C to +125°C.
2. Single 1.65 V to 3.6 V operation.
3. Compatible with 1.8 V CMOS logic.
4. High current handling capability (300 mA continuous
current at 3.3 V).
5. Low THD + N (0.02% typ).
6. 3 mm × 3 mm LFCSP package and 10-lead MSOP package.
ADG836
Rev. A | Page 2 of 16
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations ........................................................................... 7
Typical Performance Characteristics ..............................................8
Test Circuits..................................................................................... 11
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 13
REVISION HISTORY
4/05—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Table 3............................................................................ 5
Changes to Ordering Guide .......................................................... 13
Revision 0: Initial Version
ADG836
Rev. A | Page 3 of 16
SPECIFICATIONS
VDD = 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted.
Table 1.
Temperature1
Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V
On Resistance (RON) 0.5 Ω typ VDD = 2.7 V, VS = 0 V to VDD, IS = 100 mA;
0.65 0.75 0.8 Ω max Figure 19
On Resistance Match 0.04 Ω typ VDD = 2.7 V, VS = 0.65 V, IS = 100 mA
Between Channels (∆RON) 0.075 0.08 Ω max
On Resistance Flatness (RFLAT (ON)) 0.1 Ω typ VDD = 2.7 V, VS = 0 V to VDD
0.15 0.16 Ω max IS = 100 mA
LEAKAGE CURRENTS VDD = 3.6 V
Source Off Leakage IS (OFF) ±0.2 nA typ VS = 0.6 V/3.3 V, VD = 3.3 V/0.6 V;
Figure 20
Channel On Leakage ID, IS (ON) ±0.2 nA typ VS = VD = 0.6 V or 3.3 V; Figure 21
DIGITAL INPUTS
Input High Voltage, VINH 2 V min
Input Low Voltage, VINL 0.8 V max
Input Current
IINL or IINH 0.005 µA typ VIN = VINL or VINH
±0.1 µA max
CIN, Digital Input Capacitance 4 pF typ
DYNAMIC CHARACTERISTICS2
tON 21 ns typ RL = 50 Ω, CL = 35 pF
26 28 29 ns max VS = 1.5 V/0 V; Figure 22
tOFF 4 ns typ RL = 50 Ω, CL = 35 pF
7 8 9 ns max VS = 1.5 V; Figure 22
Break-Before-Make Time Delay 17 ns typ RL = 50 Ω, CL = 35 pF
(tBBM) 5 ns min VS1 = VS2 = 1.5 V; Figure 23
Charge Injection 40 pC typ VS = 1.5 V, RS = 0 Ω, CL = 1 nF; Figure 24
Off Isolation −67 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz;
Figure 25
Channel-to-Channel Crosstalk −90 dB typ S1A−S2A/S1B−S2B, RL = 50 Ω,
CL = 5 pF, f = 100 kHz; Figure 28
−67 dB typ
S1A−S1B/S2A−S2B, RL = 50 Ω,
CL = 5 pF, f = 100 kHz; Figure 27
Total Harmonic Distortion (THD + N) 0.02 % RL = 32 Ω, f = 20 Hz to 20 kHz,
VS = 2 V p-p
Insertion Loss −0.05 dB typ RL = 50 Ω, CL = 5 pF; Figure 26
−3 dB Bandwidth 57 MHz typ RL = 50 Ω, CL = 5 pF; Figure 26
CS (OFF) 25 pF typ
CD, CS (ON) 75 pF typ
POWER REQUIREMENTS VDD = 3.6 V
IDD 0.003 µA typ Digital inputs = 0 V or 3.6 V
1 4 µA max
1 Temperature range for Y version is −40°C to +125°C.
2 Guaranteed by design, not subject to production test.
ADG836
Rev. A | Page 4 of 16
VDD = 2.5 V ± 0.2 V, GND = 0 V, unless otherwise noted.
Table 2.
Temperature1
Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V
On Resistance (RON) 0.65 Ω typ VDD = 2.3 V, VS = 0 V to VDD, IS = 100 mA;
0.72 0.8 0.88 Ω max Figure 19
On Resistance Match Between 0.04 Ω typ VDD = 2.3 V, VS = 0.7 V, IS = 100 mA
Channels (∆RON) 0.08 0.085 Ω max
On Resistance Flatness (RFLAT (ON)) 0.16 Ω typ VDD = 2.3 V, VS = 0 V to VDD, IS = 100 mA
0.23 0.24 Ω max
LEAKAGE CURRENTS VDD = 2.7 V
Source Off Leakage IS (OFF) ±0.2 nA typ VS = 0.6 V/2.4 V, VD = 2.4 V/0.6 V; Figure 20
Channel On Leakage ID, IS (ON) ±0.2 nA typ VS = VD = 0.6 V or 2.4 V; Figure 21
DIGITAL INPUTS
Input High Voltage, VINH 1.7 V min
Input Low Voltage, VINL 0.7 V max
Input Current
IINL or IINH 0.005 µA typ VIN = VINL or VINH
±0.1 µA max
CIN, Digital Input Capacitance 4 pF typ
DYNAMIC CHARACTERISTICS2
tON 23 ns typ RL = 50 Ω, CL = 35 pF
29 30 31 ns max VS = 1.5 V/0 V; Figure 22
tOFF 5 ns typ RL = 50 Ω, CL = 35 pF
7 8 9 ns max VS = 1.5 V; Figure 22
Break-before-Make Time Delay (tBBM) 17 ns typ RL = 50 Ω, CL = 35 pF
5 ns min VS1 = VS2 = 1.5 V; Figure 23
Charge Injection 30 pC typ VS = 1.25 V, RS = 0 Ω, CL = 1 nF; Figure 24
Off Isolation −67 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; Figure 25
Channel-to-Channel Crosstalk −90 dB typ S1A−S2A/S1B−S2B,
RL = 50 Ω, CL = 5 pF, f = 100 kHz; Figure 28
−67 dB typ S1A−S1B/S2A−S2B,
RL = 50 Ω, CL = 5 pF, f = 100 kHz; Figure 27
Total Harmonic Distortion (THD + N) 0.022 % RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 1.5 V p-p
Insertion Loss −0.06 dB typ RL = 50 Ω, CL = 5 pF; Figure 26
–3 dB Bandwidth 57 MHz typ RL = 50 Ω, CL = 5 pF; Figure 26
CS (OFF) 25 pF typ
CD, CS (ON) 75 pF typ
POWER REQUIREMENTS VDD = 2.7 V
IDD 0.003 µA typ Digital inputs = 0 V or 2.7 V
1 4 µA max
1 Temperature range for Y version is −40°C to +125°C.
2 Guaranteed by design, not subject to production test.
ADG836
Rev. A | Page 5 of 16
VDD = 1.65 V ± 1.95 V, GND = 0 V, unless otherwise noted.
Table 3.
Temperature1
Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V
On Resistance (RON) 1 Ω typ VDD = 1.8 V, VS = 0 V to VDD, IS = 100 mA;
1.4 2.2 2.2 Ω max Figure 19
2 4 4 Ω max
VDD = 1.65 V, VS = 0 V to VDD,
IS = 100 mA; Figure 19
On Resistance Match Between 0.1 Ω typ VDD = 1.65 V, VS = 0.7 V, IS = 100 mA
Channels (∆RON)
LEAKAGE CURRENTS VDD = 1.95 V
Source Off Leakage IS (OFF) ±0.2 nA typ VS = 0.6 V/1.65 V, VD = 1.65 V/0.6 V;
Figure 20
Channel On Leakage ID, IS (ON) ±0.2 nA typ VS = VD = 0.6 V or 1.65 V; Figure 21
DIGITAL INPUTS
Input High Voltage, VINH 0.65 VDD V min
Input Low Voltage, VINL 0.35 VDD V max
Input Current
IINL or IINH 0.005 µA typ VIN = VINL or VINH
±0.1 µA max
CIN, Digital Input Capacitance 4 pF typ
DYNAMIC CHARACTERISTICS2
tON 28 ns typ RL = 50 Ω, CL = 35 pF
37 38 39 ns max VS = 1.5 V/0 V; Figure 22
tOFF 7 ns typ RL = 50 Ω, CL = 35 pF
9 10 11 ns max VS = 1.5 V; Figure 22
Break-Before-Make Time Delay (tBBM) 21 ns typ RL = 50 Ω, CL = 35 pF
5 ns min VS1 = VS2 = 1 V; Figure 23
Charge Injection 20 pC typ VS = 1 V, RS = 0 V, CL = 1 nF; Figure 24
Off Isolation −67 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz;
Figure 25
Channel-to-Channel Crosstalk −90 dB typ S1A−S2A/S1B−S2B;
RL = 50 Ω, CL = 5 pF, f = 100 kHz;
Figure 28
−67 dB typ S1A−S1B/S2A−S2B;
RL = 50 Ω, CL = 5 pF, f = 100 kHz;
Figure 27
Total Harmonic Distortion, THD 0.14 % RL = 32 Ω, f = 20 Hz to 20 kHz,
VS = 1.2 V p-p
Insertion Loss −0.08 dB typ RL = 50 Ω, CL = 5 pF; Figure 26
–3 dB Bandwidth 57 MHz
typ
RL = 50 Ω, CL = 5 pF; Figure 26
CS (OFF) 25 pF typ
CD, CS (ON) 75 pF typ
POWER REQUIREMENTS VDD = 1.95 V
IDD 0.003 µA typ Digital inputs = 0 V or 1.95 V
1.0 4 µA max
1 Temperature range for Y version is −40°C to +125°C.
2 Guaranteed by design, not subject to production test.
ADG836
Rev. A | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
VDD to GND −0.3 V to +4.6 V
Analog Inputs1 −0.3 V to VDD + 0.3 V
Digital Inputs1 −0.3 V to 4.6 V or 10 mA,
whichever occurs first
Peak Current, S or D
3.3 V Operation 500 mA
2.5 V Operation 460 mA
1.8 V Operation 420 mA (pulsed at 1ms,
10% duty cycle max)
Continuous Current, S or D
3.3 V Operation 300 mA
2.5 V Operation 275 mA
1.8 V Operation 250 mA
Operating Temperature Range
Automotive (Y Version) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
MSOP Package
θJA Thermal Impedance 206°C/W
θJC Thermal Impedance 44°C/W
LFCSP Package
θJA Thermal Impedance (3-Layer
Board)
61.1°C/W
IR Reflow, Peak Temperature <20 sec 235°C
1 Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating may be applied at any one
time.
Table 5. Truth Table
Logic Switch A Switch B
0 Off On
1 On Off
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADG836
Rev. A | Page 7 of 16
PIN CONFIGURATIONS
IN1
1
S1A
2
GND
3
S2A
4
IN2
5
D1
10
S1B
9
V
DD
8
S2B
7
D2
6
ADG836
TOP VIEW
(Not to Scale)
04308-002
Figure 2. 10-Lead MSOP (RM-10)
PIN 1
INDICATOR
NC = NO CONNECT
1S1A
2GND
3S2A
9 S1B
8V
DD
7 S2B
4
NC
5
IN2
6
D2
12NC
11N1
10D1
TOP VIEW
(Not to Scale)
ADG836
04308-003
Figure 3. 12-Lead LFCSP (CP-12)
Table 6. Terminology
VDD Most positive power supply potential.
IDD Positive supply current.
GND Ground (0 V) reference.
S Source terminal. May be an input or output.
D Drain terminal. May be an input or output.
IN Logic control input.
VD (VS) Analog voltage on terminals D, S.
RON Ohmic resistance between D and S.
RFLAT (ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the
specified analog signal range.
∆RON On resistance match between any two channels.
IS (OFF) Source leakage current with the switch off.
ID (OFF) Drain leakage current with the switch off.
ID, IS (ON) Channel leakage current with the switch on.
VINL Maximum input voltage for Logic 0.
VINH Minimum input voltage for Logic 1.
IINL (IINH) Input current of the digital input.
CS (OFF) Off switch source capacitance. Measured with reference to ground.
CD (OFF) Off switch drain capacitance. Measured with reference to ground.
CD, CS (ON) On switch capacitance. Measured with reference to ground.
CIN Digital input capacitance.
tON Delay time between the 50% and the 90% points of the digital input and switch on condition.
tOFF Delay time between the 50% and the 90% points of the digital input and switch off condition.
tBBM On or off time measured between the 80% points of both switches when switching from one to another.
Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during on-off switching.
Off Isolation A measure of unwanted signal coupling through an off switch.
Crosstalk A measure of unwanted signal, which is coupled through from one channel to another, as a result of parasitic
capacitance.
−3 dB Bandwidth The frequency at which the output is attenuated by 3 dB.
On Response The frequency response of the on switch.
Insertion Loss The loss due to the on resistance of the switch.
THD + N The ratio of the harmonics amplitude plus noise of a signal to the fundamental.
ADG836
Rev. A | Page 8 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
0.60
0.55
0.50
0.45
ON RESISTANCE (Ω)
0.40
0.35
0.30
0.25
0.200 0.5 1.0 1.5 2.0 2.5 3.0 3.5
V
D
, V
S
(V)
V
DD
= 2.7V
V
DD
= 3V
T
A
= 25°C
V
DD
= 3.6V V
DD
= 3.3V
04449-0-004
Figure 4. On Resistance vs. VD (VS) VDD = 2.7 to 3.6 V
0.8
ON RESISTANCE (Ω)
0.3
0.4
0.5
0.6
0.7
0.20 0.5 2.5
04308-005
2.01.51.0 V
D
, V
S
(V)
T
A
= 25°C
V
DD
= 2.5V
V
DD
= 2.3V
V
DD
= 2.7V
Figure 5. On Resistance vs. VD (VS) VDD = 2.5 V to 0.2 V
1.8
ON RESISTANCE (Ω)
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.20 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
V
D
, V
S
(V)
T
A
= 25°C
V
DD
= 1.65V
V
DD
= 1.8V
V
DD
= 1.95V
04308-006
Figure 6. On Resistance vs. VD (VS) VDD = 1.8 ± 3.6
1.2
ON RESISTANCE (Ω)
0.2
0.4
0.6
0.8
1.0
00 3.02.52.01.51.00.5 V
D
, V
S
(V)
+125°C
+85°C
+25°C
–40°C
V
DD
= 3.3V
04308-007
Figure 7. On Resistance vs. VD (VS) for Different Temperature, 3.3 V
1.2
ON RESISTANCE (Ω)
0.2
0.4
0.6
0.8
1.0
00 2.52.01.51.00.5 V
D
, V
S
(V)
+125°C
+25°C
V
DD
= 2.5V
+85°C
–40°C
04308-008
Figure 8. On Resistance vs. VD (VS) for Different Temperature, 2.5 V
1.4
ON RESISTANCE (Ω)
0.2
0.5
0.7
0.8
1.0
1.2
00 1.80.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
V
D
, V
S
(V)
+25°C
–40°C
+85°C
+125°C
V
DD
= 1.8V
04308-009
Figure 9. On Resistance vs. VD (VS) for Different Temperature, 1.8 V
ADG836
Rev. A | Page 9 of 16
0
–20
–80
–60
20
40
60
80
CURRENT (nA)
–40
020 6040 80 100 120
TEMPERATURE (°C)
ID, IS (ON)
IS (OFF)
VDD = 3.3V
04308-010
Figure 10. Leakage Current vs. Temperature, 3.3 V
60
CURRENT (nA)
–30
–20
–10
0
10
20
30
40
50
–400 12010080604020 TEMPERATURE (°C)
V
DD
= 2.5V
I
D
, I
S
(ON)
I
S
(OFF)
04308-011
Figure 11. Leakage Current vs. Temperature, 2.5 V
50
CURRENT (nA)
–20
–10
10
0
20
30
40
0 12010080604020 TEMPERATURE (°C)
V
DD
= 1.8V
I
S
, I
D
(ON)
I
S
(OFF)
04308-012
Figure 12. Leakage Current vs. Temperature, 1.8 V
0
10
20
30
40
50
60
70
80
90
Q
INJ
(pC)
04308-013
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
V
S
(V)
T
A
= 25°C
V
CC
= 3.3V V
CC
= 2.5V
V
CC
= 1.8V
Figure 13. Charge Injection vs. Source Voltage
0
5
10
15
20
25
30
35
TIME (ns)
6040020–40 –20 80 100 120
TEMPERATURE (°C)
t
ON
t
OFF
V
DD
= 3V
V
DD
= 3V
V
DD
= 2.5V
V
DD
= 2.5V
V
DD
= 1.8V
V
DD
= 1.8V
04308-014
Figure 14. ton/toff Times vs. Temperature
–10
–11
–12
–13
–8
–4
–2
0
1
–6
–9
–5
–3
–1
–7
ATTENUATION (dB)
0.01 0.1 1 10 100 1000
FREQUENCY (MHz)
T
A
= 25°C
V
CC
= 3.3V/2.5V/1.8V
04308-015
Figure 15. Bandwidth
ADG836
Rev. A | Page 10 of 16
–80
–70
–60
–50
–40
–30
–20
–10
0
ATTENUATION (dB)
04308-016
0.01 0.1 1 10 100 1000
FREQUENCY (MHz)
T
A
= 25°C
V
CC
= 3.3V/2.5V/1.8V
Figure 16. Off Isolation vs. Frequency
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
ATTENUATION (dB)
S1A–S1B
S1A–S2A
0.01 0.1 1 10 100 1000
FREQUENCY (MHz)
V
CC
= 3.3V/2.5V/1.8V
T
A
= 25°C
04308-017
Figure 17. Crosstalk vs. Frequency
0.10
THD + N (%)
0
0.02
0.04
0.06
0.08
20 20k10050 200 1k500 2k 10k5k
FREQUENCY (Hz)
V
DD
= 2.5V
T
A
= 25°C
S1A–D1
32V LOAD
1.5V p-p
04308-018
Figure 18. Total Harmonic Distortion + Noise
ADG836
Rev. A | Page 11 of 16
TEST CIRCUITS
SD
V
S
R
ON
= V1/I
DS
I
DS
V1
04308-019
Figure 19. On Resistance
SD
V
S
V
D
I
S
(OFF) I
D
(OFF)
A A
04308-020
Figure 20. Off Leakage
SD
V
D
I
D
(ON)
NC A
04308-021
Figure 21. On Leakage
04308-022
D
IN
GND
RL
50Ω
C
L
35pF
V
DD
V
IN
V
OUT
V
S
V
DD
V
OUT
t
ON
t
OFF
50% 50%
90% 90%
0.1µF
S1B
S1A
Figure 22. Switching Times, tON, tOFF
V
OUT
V
IN
t
BBM
t
BBM
50% 50%
80%
0V
D
IN
GND
RL
50Ω
C
L
35pF
V
DD
V
OUT
V
S
V
DD
0.1µF
S1B
S1A 80%
04308-023
Figure 23. Break-Before-Make Time Delay, tBBM
04308-024
IN
GND
V
DD
V
S
V
IN
V
OUT
1nF
V
OUT
NC
SW ON
Q
INJ
= CL ×∆V
OUT
SW OFF
∆V
OUT
S1B
S1A
D
Figure 24. Charge Injection
ADG836
Rev. A | Page 12 of 16
04308-025
V
DD
V
S
V
DD
NC
NETWORK
ANALYZER
S1B S1A
GND
OFF ISOLATION = 20 LOG
D
50Ω50Ω
V
OUT
R
L
50Ω
0.1µF
V
OUT
VS
Figure 25. Off Isolation
NETWORK
ANALYZER
R
L
GND
V
DD
V
DD
V
OUT
V
S
S1AS1B
0.1µF
D
50Ω
50Ω
INSERTION LOSS = 20 LOG V
OUT
WITH SWITCH
V
OUT
WITHOUT SWITCH
04308-026
Figure 26. Bandwidth
04308-027
V
OUT
V
DD
V
DD
GND
V
S
R
L
50ΩR
L
50Ω
0.1µF
50Ω
S1A
D
S1B
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG V
OUT
VS
NETWORK
ANALYZER
Figure 27. Channel-to-Channel Crosstalk (S1A–S1B)
04308-028
V
OUT
50Ω
50Ω
50Ω
V
S
NETWORK
ANALYZER
S2A
S2B
D1
D2 NC
NC
S1A
S1B
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG V
OUT
VS
Figure 28. Channel-to-Channel Crosstalk (S1A–S2A)
ADG836
Rev. A | Page 13 of 16
OUTLINE DIMENSIONS
0.23
0.08
0.80
0.60
0.40
8°
0°
0.15
0.00 0.27
0.17
0.95
0.85
0.75
SEATING
PLANE
1.10 MAX
10 6
5
1
0.50 BSC
3.00 BSC
3.00 BSC
4.90 BSC
PIN 1
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 29. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
*COMPLIANT TOJEDEC STANDARDS MO-220-VEED-1
EXCEPT FOR EXPOSED PAD DIMENSION.
1
0.50
BSC
0.60 MAX PIN 1
INDICATOR
0.75
0.55
0.35
0.25 MIN
0.45
TOP
VIEW
12 MAX 0.80 MAX
0.65 TYP
PIN 1
INDICATO
R
1.00
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
*1.45
1.30 SQ
1.15
12
4
10
6
7
9
3
2.75
BSC SQ
3.00
BSC SQ
2
5
8
11
COPLANARITY
0.08
EXPOSED PAD
(BOTTOM VIEW)
SEATING
PLANE
Figure 30. 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 x 3 mm Body, Very Thin Quad
(CP-12-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding1
ADG836YRM –40°C to +125°C Mini Small Outline Package (MSOP) RM-10 S9A
ADG836YRM-REEL –40°C to +125°C Mini Small Outline Package (MSOP) RM-10 S9A
ADG836YRM-REEL7 –40°C to +125°C Mini Small Outline Package (MSOP) RM-10 S9A
ADG836YRMZ2 –40°C to +125°C Mini Small Outline Package (MSOP) RM-10 S05
ADG836YRMZ-REEL2 –40°C to +125°C Mini Small Outline Package (MSOP) RM-10 S05
ADG836YRMZ-REEL72 –40°C to +125°C Mini Small Outline Package (MSOP) RM-10 S05
ADG836YCP-REEL –40°C to +125°C Lead Frame Chip Scale Package (LFCSP_VQ) CP-12-1 S9A
ADG836YCP-REEL7 –40°C to +125°C Lead Frame Chip Scale Package (LFCSP_VQ) CP-12-1 S9A
1 Branding on this package is limited to three characters due to space constraints.
2 Z = Pb-free part.
ADG836
Rev. A | Page 14 of 16
NOTES
ADG836
Rev. A | Page 15 of 16
NOTES
ADG836
Rev. A | Page 16 of 16
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C04308-0-4/05(A)
