© Semiconductor Components Industries, LLC, 2016
February, 2016 − Rev. 5 1Publication Order Number:
KAI−11002/D
KAI-11002
4008 (H) x 2672 (V) Interline
CCD Image Sensor
Description
The KAI−11002 Image Sensor is a high-performance 11-million
pixel sensor designed for professional digital still camera applications.
The 9.0 mm square pixels with microlenses provide high sensitivity
and the large full well capacity results in high dynamic range. The two
high-speed outputs and binning capabilities allow for 1−3 frames per
second (fps) video rate for the progressively scanned images.
The vertical overflow drain structure provides anti-blooming
protection and enables electronic shuttering for precise exposure
control. Other features include low dark current, negligible lag and
low smear.
Table 1. GENERAL SPECIFICATIONS
Parameter Typical Value
Architecture Interline CCD, Progressive Scan
Total Number of Pixels 4072 (H) × 2720 (V) = 11.1 M
Number of Effective Pixels 4033 (H) × 2688 (V) = 10.8 M
Number of Active Pixels 4008 (H) × 2672 (V) = 10.7 M
Number of Outputs 1 or 2
Pixel Size 9.0 mm (H) × 9.0 mm (V)
Active Image Size 37.25 mm (H) × 25.70 mm (V),
43.3 mm (Diagonal),
35 mm Optical Format
Aspect Ratio 3:2
Saturation Signal 60,000 e−
Quantum Efficiency
KAI−11002−ABA
KAI−11002−CBA (RGB)
KAI−11002−FBA (RGB)
50%
32%, 34%, 40%
35%, 38%, 40%
Output Sensitivity 13 mV/e−
Total Noise 30 e−
Dark Current < 50 mV/s
Dark Current Doubling
Temperature 7°C
Dynamic Range 66 dB
Charge Transfer Efficiency > 0.99999
Blooming Suppression > 1000X
Smear < −80 dB
Image Lag < 10 e−
Maximum Data Rate 28 MHz
Package 40-pin, CERDIP, 0.070″ Pin Spacing
Cover Glass AR Coated or Clear Glass
NOTE: All Parameters are specified at T = 40°C unless otherwise noted.
Features
•High Resolution
•High Sensitivity
•High Dynamic Range
•Low Noise Architecture
•High Frame Rate
•Binning Capability for Higher Frame Rate
•Electronic Shutter
Applications
•Industrial Inspection
•Aerial Photography
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Figure 1. KAI−11002 Interline CCD
Image Sensor
See detailed ordering and shipping information on page 2 o
f
this data sheet.
ORDERING INFORMATION
KAI−11002
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2
ORDERING INFORMATION
Table 2. ORDERING INFORMATION − KAI−11002 IMAGE SENSOR
Part Number Description Marking Code
KAI−11002−AAA−CR−B1* Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass with AR Coating (2 Sides), Grade 1 KAI−11002−AAA
Serial Number
KAI−11002−AAA−CR−B2* Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass with AR Coating (2 Sides), Grade 2
KAI−11002−AAA−CR−AE* Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass with AR Coating (2 Sides), Engineering Sample
KAI−11002−AAA−CP−B1 Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass, Grade 1
KAI−11002−AAA−CP−B2 Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass, Grade 2
KAI−11002−AAA−CP−AE Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass, Engineering Sample
KAI−11002−ABA−CD−BX Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Special Grade KAI−11002−ABA
Serial Number
KAI−11002−ABA−CD−B0 Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Grade 0
KAI−11002−ABA−CD−B1 Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Grade 1
KAI−11002−ABA−CD−B2 Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Grade 2
KAI−11002−ABA−CD−AE Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Boht Sides), Engineering Sample
KAI−11002−ABA−CR−B1* Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass with AR Coating (2 Sides), Grade 1
KAI−11002−ABA−CR−B2* Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass with AR Coating (2 Sides), Grade 2
KAI−11002−ABA−CR−AE* Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass with AR Coating (2 Sides), Engineering Sample
KAI−11002−ABA−CP−B1 Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass, Grade 1
KAI−11002−ABA−CP−B2 Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass, Grade 2
KAI−11002−ABA−CP−AE Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass, Engineering Sample
KAI−11002−FBA−CD−B1 Gen2 Color (Bayer RGB), Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Grade 1 KAI−11002−FBA
Serial Number
KAI−11002−FBA−CD−B2 Gen2 Color (Bayer RGB), Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Grade 2
KAI−11002−FBA−CD−AE Gen2 Color (Bayer RGB), Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
KAI−11002−CAA−CD−B1* Gen1 Color (Bayer RGB), No Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Grade 1 KAI−11002−CAA
Serial Number
KAI−11002−CAA−CD−B2* Gen1 Color (Bayer RGB), No Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Grade 2
KAI−11002−CAA−CD−AE* Gen1 Color (Bayer RGB), No Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
KAI−11002
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Table 2. ORDERING INFORMATION − KAI−11002 IMAGE SENSOR (continued)
Part Number Marking CodeDescription
KAI−11002−CBA−CD−B1* Gen1 Color (Bayer RGB), Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Grade 1 KAI−11002−CBA
Serial Number
KAI−11002−CBA−CD−B2* Gen1 Color (Bayer RGB), Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Grade 2
KAI−11002−CBA−CD−AE* Gen1 Color (Bayer RGB), Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
*Not recommended for new designs.
Table 3. ORDERING INFORMATION − EVALUATION SUPPORT
Part Number Description
KAI−11002−12−30−A−EVK Evaluation Board (Complete Kit)
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
KAI−11002
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4
DEVICE DESCRIPTION
Architecture
Figure 2. Block Diagram
4008 (H) x 2672 (V)
Active Pixels
GG
R
BGG
R
B
GG
R
B
GG
R
B
Pixel
1,1
8 Buffer Rows
8 Buffer Rows
17 Dark Rows
16 Dark Rows
12 Buffer Columns
13 Buffer Columns
20 Dark Columns
19 Dark Columns
4 Dummy Pixels
4 Dummy Pixels
Dual
or
Video L Video R
4 20 12 4008 13 19 4
Single
4 20 12 2004 2004 13 19 4
Fast Line Dump
There are 17 light shielded rows followed 2,688
photoactive rows and finally 16 more light shielded rows.
The first 8 and the last 8 photoactive rows are buffer rows
giving a total of 2,672 lines of image data.
In the single output mode all pixels are clocked out of the
Video L output in the lower left corner of the sensor. The first
4 empty pixels of each line do not receive charge from the
vertical shift register. The next 20 pixels receive char ge from
the left light shielded edge followed by 4,033 photosensitive
pixels and finally 19 more light shielded pixels from the
right edge of the sensor. The first 12 and last 13
photosensitive pixels are buffer pixels giving a total of 4,008
pixels of image data.
In the dual output mode the clocking of the right half of the
horizontal CCD is reversed. The left half of the image is
clocked out V ideo L and the right half of the image is clocked
out Video R. For the Video L each row consists of 4 empty
pixels followed by 20 light shielded pixels followed by
2,016 photosensitive pixels. For the Video R each row
consists of 4 empty pixels followed by 19 light shielded
pixels followed by 2,017 photosensitive pixels. When
reconstructing the image, data from Video R will have to be
reversed in a line buffer and appended to the Video L data.
The dark rows are not entirely dark and so should not be
used for a dark reference level. Use the dark columns on the
left or right side of the image sensor as a dark reference.
Of the dark columns, the first and last dark columns
should not be used for determining the zero signal level.
Some light does leak into the first and last dark columns.
KAI−11002
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Pixel
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
Figure 3. Pixel Architecture
Top View
Direction
of
Charge
Transfer
True Two Phase Burried Channel VCCD
Lightshield over VCCD not shown
V1
Photodiode
V2
Transfer
Gate
ËËËËË
ËËËËË
Direction of
Charge
Transfer
ÉÉ
ÉÉ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
É
É
V1
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
V2
É
É
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ËËËËË
ËËËËË
V1
n− n
n− n−
p Well (GND)
Cross Section Down Through VCCD
n Substrate
p
V1
n
p+
Light Shield
p
p
n
p
Cross Section Through
Photodiode and VCCD Phase 1
Photodiode
pp
V2
n
p+
Light Shield
p
p
n
n Substrate
p
Cross Section Through Photodiode
and VCCD Phase 2 at Transfer Gate
Transfer
Gate
Cross Section Showing Lenslet
Lenslet
VCCD VCCD
Light Shield Light Shield
Photodiode
Red Color Filter
NOTE: Drawings not scale.
9.0 mm
9.0 mm
n Substrate
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron-hole pairs within the individual silicon
photodiodes. These photoelectrons are collected locally by
the formation of potential wells at each photosite. Below
photodiode saturation, the number of photoelectrons
collected at each pixel is linearly dependent upon light level
and exposure time and non-linearly dependent on
wavelength. When the photodiodes charge capacity is
reached, excess electrons are discharged into the substrate to
prevent blooming.
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Vertical to Horizontal Transfer
Figure 4. Vertical to Horizontal Transfer Architecture
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
Top View
Direction of
Vertical
Charge
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
Transfer
V1
ËËËËËË
ËËËËËË
ËËËËËË
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
V2
V1
Photodiode
ËËËËËË
ËËËËËË
V2
Transfer
Gate
ËËËËËË
ËËËËËË
Fast
Line
Dump
H1S
ËË
ËË
ËË
ËË
ËË
ËË
ËË
ËË
ËË
ËË
ËË
ËË
ËË
ËË
Direction of
Horizontal
Charge Transfer
Lightshield
not shown
H2B
H2S
H1B
When the V1 and V2 timing inputs are pulsed, charge in
every pixel of the VCCD is shifted one row towards the
HCCD. The last row next to the HCCD is shifted into the
HCCD. When the VCCD is shifted, the timing signals to the
HCCD must be stopped. H1 must be stopped in the high state
and H2 must be stopped in the low state. The HCCD
clocking may begin tHD ms after the falling edge of the V1
and V2 pulse.
Charge i s transferred from the last vertical CCD phase into
the H1S horizontal CCD phase. Refer to Figure 26 for an
example of timing that accomplishes the vertical to
horizontal transfer of charge.
If the fast line dump is held at the high level (FDH) during
a vertical to horizontal transfer, then the entire line is
removed and not transferred into the horizontal register.
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Horizontal Register to Floating Diffusion
Figure 5. Horizontal Register to Floating Diffusion Architecture
n+
R OG H1 H2S H2B H1S H1B H2S
ÏÏÏ
ÏÏÏÏ
n−
ÏÏÏÏ
n− n−
RD
Floating
Diffusion
n (burried channel)
nn+
p (GND)
n (SUB)
The HCCD has a total of 4,080 pixels. The 4,072 vertical
shift registers (columns) are shifted into the center 4,072
pixels of the HCCD. There are 4 pixels at both ends of the
HCCD, which receive no charge from a vertical shift
register. The first 4 clock cycles of the HCCD will be empty
pixels (containing no electrons). The next 20 clock cycles
will contain only electrons generated by dark current in the
VCCD and photodiodes. The next 4,033 clock cycles will
contain photo-electrons (image data). Finally, the last 19
clock cycles will contain only electrons generated by dark
current in the VCCD and photodiodes. Of the 20 dark
columns a t the start of the line and the 19 dark columns at the
end of the line, the first and last dark columns should not be
used for determining the zero signal level. Some light does
leak into the first and last dark columns. Only use the center
18 columns of the 20 column dark reference at the start of the
line. Only use the center 17 columns of the 19 column dark
reference at the end of the line.
When the HCCD is shifting valid image data, the timing
inputs to the electronic shutter (SUB), VCCD (V1, V2), and
fast line dump (FD) should be not be pulsed. This prevents
unwanted noise from being introduced. The HCCD i s a type
of charge coupled device known as a pseudo-two phase
CCD. This type of CCD has the ability to shift charge in two
directions. This allows the entire image to be shifted out to
the video L output, or to the video R output (left/right image
reversal). The HCCD is split into two equal halves of 2,040
pixels each. When operating the sensor in single output
mode the two halves of the HCCD are shifted in the same
direction. When operating the sensor in dual output mode
the two halves of the HCCD are shifted in opposite
directions. The direction of charge transfer in each half is
controlled by the H1BL, H2BL, H1BR, and H2BR timing
inputs.
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Horizontal Register Split
Figure 6. Horizontal Register
Single Output
H2SL
H1SL H1BL H2SRH1SR H2BR
H1BR
Pixel
2040 Pixel
2041
H2SL H2BLH1BL
H1 H1 H1 H1 H1H2 H2 H2 H2 H2
H2SL
H1SL H1BL H2SRH1SR H2BR
H1BR
Pixel
2040 Pixel
2041
H2SL H2BLH1BL
H1 H1 H1 H1 H2H2 H2 H2 H1 H2
Dual Output
Single Output Operation
When operating the sensor in single output mode all pixels
of the image sensor will be shifted out the Video L output
(pin 2). To conserve power and lower heat generation the
output amplifier for Video R may be turned off by
connecting VDDR (pin 18) and VOUTR (pin 19) to GND
(zero volts).
The H1 timing from the timing diagrams should be
applied to H1SL, H1BL, H1SR, H2BR, and the H2 timing
should be applied to H2SL, H2BL, H2SR, and H1BR. In
other words, the clock driver generating the H1 timing
should b e connected to pins 8, 9, 13, and 11. The clock driver
generating the H2 timing should be connected to pins 7, 10,
14, and 12. The horizontal CCD should be clocked for 4
empty pixels plus 20 light shielded pixels plus 4,032
photoactive pixels plus 20 light shielded pixels for a total o f
4,076 pixels. H1BINL and H1BINR use the H1 timing, but
should be generated from a separate clock driver for optimal
performance.
Dual Output Operation
In dual output mode the connections to the H1BR and
H2BR pins are swapped from the single output mode to
change the direction of charge transfer of the right side
horizontal shift register. In dual output mode both VDDL
and VDDR (pins 3, 18) should be connected to 15 V. The H1
timing from the timing diagrams should b e applied to H1SL,
H1BL, H1SR, H1BR, and the H2 timing should be applied
to H2SL, H2BL, H2SR, and H2BR. The clock driver
generating the H1 timing should be connected to pins 8, 9,
13, and 12. The clock driver generating the H2 timing should
be connected to pins 7, 10, 14, and 11. The horizontal CCD
should be clocked for 4 empty pixels plus 20 light shielded
pixels plus 2016 photoactive pixels for a total of
2,040 pixels. If the camera is to have the option of dual or
single output mode, the clock driver signals sent to H1BR
and H2BR may be swapped by using a relay. Another
alternative is to have two extra clock drivers for H1BR and
H2BR and invert the signals in the timing logic generator. If
two extra clock drivers are used, care must be taken to ensure
the rising and falling edges of the H1BR and H2BR clocks
occur at the same time (within 3 ns) as the other HCCD
clocks.
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9
Output
Figure 7. Output Architecture
VDD
VOUT
Floating
Diffusion
HCCD
Charge
Transfer
Source
Follower
#1
H1B
H1S
H2B
H2S
H1BIN
OG
R
RD
31 kW
Source
Follower
#2
Source
Follower
#3
Charge packets contained in the horizontal register are
dumped pixel by pixel onto the floating diffusion (FD)
output node whose potential varies linearly with the quantity
of charge in each packet. The amount of potential charge is
determined by the expression DVFD =Q/DCFD.
A three-stage source-follower amplifier is used to buffer
this signal voltage of f chip with slightly less than unity gain.
The translation from the charge domain to the voltage
domain is quantified by the output sensitivity or charge to
voltage conversion in terms of microvolts per electron
(mV/e−). After the signal has been sampled off chip, the reset
clock (R) removes the char ge from the floating dif fusion and
resets its potential to the reset drain voltage (RD).
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Pin Description and Physical Orientation
Figure 8. Pin Description
Pixel 1,1
1
RL
VOUTL
VDDL
OGL
OGR
GND
H1BINL
GND
H2SL
H1SL
H1BL
H2BL
1023456789 11121314151617181920
H2BR
H1BR
H1SR
H2SR
GND
H1BINR
GND
VDDR
VOUTR
RR
2122232425262728293031323334353637383940
FD
VRD
L
V1
V2
GND
SUB
GND
GND
GND
GND
GND
GND
ESD
GND
V1
V2
VRD
R
FD
Table 4. PIN DESCRIPTION
Pin Name Description
1 RL Reset Gate, Left
2 VOUTL Video Output, Left
3 VDDL VDD, Left
4 GND Ground
5 H1BINL H1 Last Phase, Left
6 GND Ground
7 H2SL H2 Storage, Left
8 H1SL H1 Storage, Left
9 H1BL H1 Barrier, Left
10 H2BL H2 Barrier, Left
11 H2BR H2 Barrier, Right
12 H1BR H1 Barrier, Right
13 H1SR H1 Storage, Right
14 H2SR H2 Storage, Right
15 GND Ground
16 H1BINR H1 Last Phase, Right
17 GND Ground
18 VDDR VDD, Right
19 VOUTR Video Output, Right
20 RR Reset Gate, Right
Pin Name Description
21 OGR Output Gate, Right
22 FD Fast Line Dump Gate
23 RDR Reset Drain, Right
24 V2 Vertical Clock, Phase 2
25 V1 Vertical Clock, Phase 1
26 GND Ground
27 ESD ESD Protection
28 GND Ground
29 GND Ground
30 GND Ground
31 GND Ground
32 GND Ground
33 GND Ground
34 SUB Substrate
35 GND Ground
36 V2 Vertical Clock, Phase 2
37 V1 Vertical Clock, Phase 1
38 RDL Reset Drain, Left
39 FD Fast Line Dump Gate
40 OGL Output Gate, Left
NOTE: The pins are on a 0.070″ spacing.
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IMAGING PERFORMANCE
Table 5. IMAGING PERFORMANCE OPERATIONAL CONDITIONS
(Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions.)
Description Condition Notes
Frame Time 1,732 ms 1
Horizontal Clock Frequency 10 MHz
Light Source Continuous Red, Green and Blue LED Illumination Centered at 450, 530 and 650 nm 2, 3
Operation Nominal Operating Voltages and Timing
1. Electronic shutter is not used. Integration time equals frame time.
2. LEDs used: Blue: Nichia NLPB500, Green: Nichia NSPG500S and Red: HP HLMP−8115.
3. For monochrome sensor, only green LED used.
Specifications
Table 6. PERFORMANCE SPECIFICATIONS
Description Symbol Min. Nom. Max. Unit Sample
Plan
Temperature
Tested at
(5C)
ALL CONFIGURATIONS
Maximum Photoresponse
Non-Linearity (Notes 2, 3) NL N/A 2 − % Design
Maximum Gain Difference between
Outputs (Notes 2, 3) DGN/A 10 − % Design
Max. Signal Error due to Non-Linearity
Dif. (Notes 2, 3) DNL N/A 1 − % Design
Horizontal CCD Charge Capacity HNe − 139 − ke−Design
Vertical CCD Charge Capacity VNe 90 91 − ke−Die
Photodiode CCD Charge Capacity PNe 58 60 − ke−Die
Horizontal CCD Charge Transfer
Efficiency HCTE 0.99999 − N/A Design
Vertical CCD Charge Transfer
Efficiency VCTE 0.99999 − N/A Design
Photodiode Dark Current IPD N/A
N/A −
−800
0.15 e/p/s
nA/cm2Die 27, 40
Vertical CCD Dark Current IVD N/A
N/A −
−3,800
0.5 e/p/s
nA/cm2Die 27, 40
Image Lag Lag N/A < 10 50 e−Design
Anti-Blooming Factor XAB 100 300 N/A Design
Vertical Smear Smr N/A −85 −75 dB Design
Total Noise (Note 4) ne−T − 30 − e− rms Design
Dynamic Range (Note 5) DR − 66 − dB Design
Output Amplifier DC Offset VODC 4 9 14 V Die
Output Amplifier Bandwidth (Note 6) f−3dB − 106 − MHz Die
Output Amplifier Impedance ROUT 100 150 200 WDie
Output Amplifier Sensitivity DV/DN− 13 − mV/e−Design
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Table 6. PERFORMANCE SPECIFICATIONS (continued)
Description
Temperature
Tested at
(5C)
Sample
Plan
UnitMax.Nom.Min.Symbol
KAI−11002−ABA CONFIGURATION
Peak Quantum Efficiency QEMAX 45 50 N/A % Design
Peak Quantum Efficiency Wavelength lQE N/A 500 N/A nm
KAI−11002−FBA CONFIGURATION GEN2 COLOR
Peak Quantum Efficiency
Red
Green
Blue
QEMAX −
−
−
35
38
40
N/A
N/A
N/A
% Design
Peak Quantum Efficiency Wavelength
Red
Green
Blue
lQE −
−
−
610
530
460
N/A
N/A
N/A
nm Design
KAI−11002−CBA CONFIGURATION GEN1 COLOR (Note 7)
Peak Quantum Efficiency
Red
Green
Blue
QEMAX −
−
−
32
34
40
N/A
N/A
N/A
% Design
Peak Quantum Efficiency Wavelength
Red
Green
Blue
lQE −
−
−
620
540
460
N/A
N/A
N/A
nm Design
NOTE: N/A = Not Applicable.
1. Per color.
2. Value is over the range of 10% to 90% of photodiode saturation.
3. Value is for the sensor operated without binning.
4. Includes system electronics noise, dark pattern noise and dark current shot noise at 30 MHz.
5. Uses 20LOG (PNe /n
e−T).
6. Last stage only, CLOAD = 10 pF. Then f−3dB = (1 / (2n ⋅ ROUT ⋅ CLOAD)).
7. This color filter set configuration (Gen1) is not recommended for new designs.
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TYPICAL PERFORMANCE CUR VES
Quantum Efficiency
Monochrome with Microlens
Figure 9. Monochrome with Microlens Quantum Efficiency
0.00
0.10
0.20
0.30
0.40
0.50
0.60
300 400 500 600 700 800 900 1000
Wavelength (nm)
Absolute Quantum Efficiency
Monochrome without Microlens
Figure 10. Monochrome without Microlens Quantum Efficiency
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
400 500 600 700 800 900 1000
Wavelength (nm)
Absolute Quantum Efficiency
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14
Color with Microlens
Figure 11. Color with Microlens Quantum Efficiency using AR Glass
0.00
350
Wavelength (nm)
Absolute Quantum Efficiency
400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
Color without Microlens
Figure 12. Color without Microlens Quantum Efficiency using AR Glass
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
400 500 600 700 800 900 1000
Wavelength (nm)
Absolute Quantum Efficiency
Red
Green
Blue
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Angular Quantum Efficiency
For the curves marked “Horizontal”, the incident light angle is varied in a plane parallel to the HCCD.
For the curves marked “Vertical”, the incident light angle is varied in a plane parallel to the VCCD.
Monochrome with Microlens
Figure 13. Monochrome with Microlens Angular Quantum Efficiency
100
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
0 5 10 15 20 25 30
Relative Quantum Efficiency (%)
Angle (degress)
Vertical
Horizontal
Color with Microlens
Figure 14. Color with Microlens Angular Quantum Efficiency
Vertical
Horizontal
0%−25
Relative Quantum Efficiency (%)
Angle (degress)
−20 −15 −10 −5 0 5 10 15 20 25
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
Red
Green
Blue
Vertical
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Power-Estimated
Figure 15. Power
Right Output Disabled
0
50
100
150
200
250
300
350
400
450
500
0 5 10 15 20 25 30
Horizontal Clock Frequency (MHz)
Power (mW)
Output Power One Output (mW)
Horizonatl Power (mW)
Vertical Power One Output (mW)
Total Power One Output (mW)
Frame Rates − Continuous Mode
Figure 16. Frame Rates
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0 5 10 15 20 25 30
Pixel Clock (MHz)
Frame Rate (fps)
Dual output
Single output
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DEFECT DEFINITIONS
Table 7. DEFECT DEFINITIONS (Notes 1, 2)
Description Definition
Class X
Monochrome
with Microlens
Only
Class 0
Monochrome
with Microlens
Only Class 1 Class 2
Color Only
Class 2
Monochrome
Only
Major Dark Field
Defective Pixel Defect ≥ 239 mV 100 100 100 200 200
Major Bright
Field Defective
Pixel
Defect ≥ 15% 100 100 100 200 200
Minor Dark Field
Defective Pixel Defect ≥ 123 mV 1,000 1,000 1,000 2,000 2,000
Cluster Defect A group of 2 to “N”
contiguous major defective
pixels, but no more than “W”
adjacent defects horizontally.
0 1
N=10
W=3
20
N=10
W=3
20
N=10
W=3
20
N=12
W=5
Column Defect A group of more than 10
contiguous major defective
pixels along a single column.
0 0 0 10 2
NOTE: Class X sensors are offered strictly “as available”. ON Semiconductor cannot guarantee delivery dates. Please call for availability.
1. There will be at least two non-defective pixels separating any two major defective pixels.
2. Tested at 27°C and 40°C.
Defect Map
The defect map supplied with each sensor is based upon
testing at an ambient (27°C) temperature. Minor point defects are not included in the defect map. All defective
pixels are reference to pixel 1, 1 in the defect maps.
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TEST DEFINITIONS
Test Regions of Interest
Active Area ROI: Pixel (1, 1) to Pixel (4008, 2672)
Center 100 by 100 ROI: Pixel (1954, 1336) to
Pixel (2053, 1435)
Only the active pixels are used for performance and defect
tests.
Overclocking
The test system timing is configured such that the sensor
is overclocked in both the vertical and horizontal directions.
See Figure 17 for a pictorial representation of the regions.
Figure 17. Overclock Regions of Interest
Pixel 1,1
Vertical Overclock
Horizontal Overclock
H
V
Tests
Dark Field Defect Test
This test is performed under dark field conditions.
The sensor is partitioned into 384 sub regions of interest,
each of which is 167 by 167 pixels in size. In each region of
interest, the median value of all pixels is found. For each
region of interest, a pixel is marked defective if it is greater
than or equal to the median value of that region of interest
plus the defect threshold specified in the “Defect
Definitions” section.
Bright Field Defect Test
This test is performed with the imager illuminated to
a level such that the output is at approximately
40,000 electrons. Prior to this test being performed the
substrate voltage has been set such that the charge capacity
of the sensor is 60,000 electrons. The average signal level of
all active pixels is found. The bright and dark thresholds are
set as:
Dark Defect Threshold = Active Area Signal @Threshold
Bright Defect Threshold = Active Area Signal @Threshold
The sensor is then partitioned into 384 sub regions of
interest, each of which is 167 by 167 pixels in size. In each
region of interest, the average value of all pixels is found.
For each region of interest, a pixel is marked defective if it
is greater than or equal to the median value of that region of
interest plus the bright threshold specified or if it is less than
or equal to the median value of that region of interest minus
the dark threshold specified.
Example for major bright field defective pixels:
•Average value of all active pixels is found to be
520 mV (40,000 electrons).
•Dark defect threshold: 520 mV ⋅ 15% = 78 mV
•Bright defect threshold: 520 mV ⋅ 15% = 78 mV
•Region of interest #1 selected. This region of interest is
pixels 1, 1 to pixels 167, 167.
♦Median of this region of interest is found to be
520 mV.
♦Any pixel in this region of interest that is
≥(520 + 78 mV) 598 mV in intensity will be marked
defective.
♦Any pixel in this region of interest that is
≤(520 − 78 mV) 442 mV in intensity will be marked
defective.
•All remaining 384 sub regions of interest are analyzed
for defective pixels in the same manner.
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19
OPERATION
Absolute Maximum Ratings
Absolute maximum rating is defined as a level or
condition that should not be exceeded at any time per the description. If the level or the condition is exceeded,
the device will be degraded and may be damaged.
Table 8. ABSOLUTE MAXIMUM RATINGS
Description Symbol Minimum Maximum Unit Notes
Operating Temperature TOP −50 70 °C 1
Humidity RH 5 90 % 2
Output Bias Current IOUT 0.0 −40 mA 3
Off-Chip Load CL− 10 pF
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
1. Noise performance will degrade at higher temperatures.
2. T = 25°C. Excessive humidity will degrade MTTF.
3. Total for both outputs. Current is −20 mA for each output. Avoid shorting output pins to ground or any low impedance source during operation.
Amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivity). Operation at these
values will reduce MTTF.
Table 9. MAXIMUM VOLTAGE RATINGS BETWEEN PINS
Description Minimum Maximum Unit Notes
RL, RR, H1BINL, H1BINR, H2SL, H1SL, H1BL, H2BL,
H2BR, H1BR, H1SR, H2SR, OGL, OGR to ESD 0 17 V
Pin to Pin with ESD Protection −17 17 V 1
VDDL, VDDR to GND 0 25 V
1. Pins with ESD protection are: RL, RR, H1BINL, H1BINR, H2SL, H1SL, H1BL, H2BL, H2BR, H1BR, H1SR, H2SR, OGL, and OGR.
Table 10. DC BIAS OPERATING CONDITIONS
Description Symbol Min. Nom. Max. Unit Maximum
DC Current Notes
Output Gate OG −3.0 −2.5 −2.0 V1 mA
Reset Drain RD 10.5 11.5 12.0 V 1 mA
Output Amplifier Supply VDD 14.5 15.0 15.5 V 2 mA 4
Ground GND 0.0 0.0 0.0 V
Substrate SUB 8.0 TBD 17.0 V 1, 5
ESD Protection Disable ESD −9.0 −8.0 −7.0 V 2
Output Bias Current IOUT −−5 −10 mA 3
1. The operating of the substrate voltage, V AB, will be marked on the shipping container for each device. The value of VAB is set such that the
photodiode charge capacity is 60,000 electrons.
2. VESD must be at least 1 V more negative than H1L and H2L during sensor operation AND during camera power turn on.
3. An output load sink must be applied to VOUT to activate output amplifier.
4. The maximum DC current is for one output unloaded. This is the maximum current that the first two stages of one output amplifier will draw.
This value is with VOUT disconnected.
5. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
Power-Up Sequence
1. Substrate
2. ESD Protection
3. All Other Biases and Clocks
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AC Operating Conditions
Table 11. CLOCK LEVELS
Description Symbol Min. Nom. Max. Unit Notes
Vertical CCD Clock High V2H 7.5 8.0 8.5 V
Vertical CCD Clocks Midlevel V1M, V2M −0.2 0.0 0.2 V
Vertical CCD Clocks Low V1L, V2L −9.5 −9.0 −8.5 V
Horizontal CCD Clocks Amplitude H1H, H2H 5.8 6.0 6.2 V
Horizontal CCD Clocks Low H1L, H2L −4.2 −4.0 −3.8 V
Reset Clock High RH 1.3 1.5 1.7 V
Reset Clock Low RL −3.7 −3.5 −3.3 V
Electronic Shutter Voltage VSHUTTER 39 40 48 V 2
Fast Dump High FDH 4.5 5.0 5.5 V
Fast Dump Low FDL −9.5 −9.0 −8.5 V 1
1. FDL can use the same supply as Vertical CCD Clocks Low if desired.
2. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
Table 12. CLOCK LINE CAPACITANCES
Clocks Capacitance Unit Notes
V1 to GND 108 nF 1
V2 to GND 118 nF 1
V1 to V2 56 nF
H1S to GND 27 pF 2
H2S to GND 27 pF 2
H1B to GND 13 pF 2
H2B to GND 4 pF 2
H1S to H2B and H2S 13 pF 2
H1B to H2B and H2S 13 pF 2
H2S to H1B and H1S 13 pF 2
H2B to H1B and H1S 13 pF 2
H1BIN to GND 20 pF 2
R to GND 10 pF
FD to GND 20 pF
1. Gate capacitance to GND is voltage dependent. Value is for nominal VCCD clock voltages.
2. For nominal HCCD clock voltages, these values are for half of the imager (H1SL, H1BL, H2SL, H2BL and H1BINL or H1SR, H1BR, H2SR,
H2BR and H1BINR).
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TIMING
Table 13. TIMING REQUIREMENTS
Description Symbol Min. Nom. Max. Unit
HCCD Delay tHD 3.0 3.5 10.0 ms
VCCD Transfer Time tVCCD 3.0 3.5 20.0 ms
Photodiode Transfer Time tV3rd 8.0 10.0 15.0 ms
VCCD Pedestal Time t3P 100.0 120.0 200.0 ms
VCCD Delay t3D 15.0 20.0 80.0 ms
Reset Pulse Time tR2.5 5.0 − ns
Shutter Pulse Time tS3.0 4.0 10.0 ms
Shutter Pulse Delay tSD 1.0 1.5 10.0 ms
HCCD Clock Period tH33 − 200 ns
VCCD Rise/Fall Time tVR 0.0 0.1 1.0 ms
Fast Dump Gate Delay tFD 0.5 − − ms
Vertical Clock Edge Alignment tVE 0.0 − 100 ns
Main Timing − Continuous Mode
Figure 18. Main Timing − Continuous Mode
Vertical Frame
Timing
Line Timing
Repeat for 2721
Lines
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Frame Timing − Continuous Mode
Frame Timing without Binning
Figure 19. Frame Timing without Binning
H2L
V1
V2
H1, H1BIN
H2
Line 2721 Line 1 H1H, H1BINH
H1L, H1BINL
H2H
V2L
V2M
V1L
V1M
V1H
tL
t3D
t3P
tV3rd
tL
Line 2720
Frame Timing for Vertical Binning by 2
tL
Figure 20. Frame Timing for Vertical Binning by 2
t3D
t3P
tV3rd
tL
V1
V2
H1, H1BIN
H2
Line 1361 Line 1
Line 1360
3 × tVCCD
Frame Timing Edge Alignment
Figure 21. Frame Timing Edge Alignment
V1
V2
V1M
V1L
V2H
V2M
V2L
tVE
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23
Line Timing − Continuous Mode
Line Timing Single Output
Figure 22. Line Timing Single Output
V1
V2
H1, H1BIN
H2
R
23
2
3
4
5
6
24
25
26
27
4053
4054
4055
4057
4058
4074
4075
1
Pixel Count
28
4056
4073
4076
t
L
tVCCD
tHD
Line Timing Dual Output − Left Output
Figure 23. Line Timing Dual Output − Left Output
V1
V2
H1, H1BIN
H2
R
23
2
3
4
5
6
24
25
26
27
2030
2031
2032
2034
2035
2038
2039
1
Pixel Count
28
2033
2037
2040
2036
tL
tVCCD
tHD
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24
Line Timing Dual Output − Right Output
Figure 24. Line Timing Dual Output − Right Output
V1
V2
H1, H1BIN
H2
R
23
2
3
4
5
6
24
25
26
27
2030
2031
2032
2034
2035
2038
2039
1
Pixel Count
28
2033
2037
2040
2036
tL
tVCCD
tHD
Line Timing Vertical Binning by 2
Figure 25. Line Timing Vertical Binning by 2
V1
V2
H1, H1BIN
H2
R
23
2
3
4
5
24
25
26
27
4053
4054
4055
4057
4058
4074
4075
1
Pixel Count
28
4056
4073
4076
tL
tVCCD
tHD
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28
Electronic Shutter
Electronic Shutter Line Timing
Figure 32. Electronic Shutter Line Timing
tHD
tVCCD
VSUB
fV1
fV2
fH2
fH1
tSD
tS
fR
VSHUTTER
Electronic Shutter − Integration Time Definition
Figure 33. Integration Time Definition
VSUB
fV2
VSHUTTER
Integration Time
Electronic Shutter Description
The voltage on the substrate (SUB) determines the charge
capacity of the photodiodes. When SUB is 8 volts the
photodiodes will be at their maximum charge capacity.
Increasing VSUB above 8 volts decreases the charge
capacity of the photodiodes until 40 volts when the
photodiodes have a charge capacity of zero electrons.
Therefore, a short pulse on SUB, with a peak amplitude
greater than 40 volts, empties all photodiodes and provides
the electronic shuttering action.
It may appear the optimal substrate voltage setting is
8 volts to obtain the maximum charge capacity and dynamic
range. While setting VSUB to 8 volts will provide the
maximum dynamic range, it will also provide the minimum
anti-blooming protection.
The KAI−11002 VCCD has a charge capacity of
90,000 electrons ( 9 0 ke−). If the SUB voltage is set such that
the photodiode holds more than 90 ke−, then when the
charge is transferred from a full photodiode to VCCD,
KAI−11002
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29
the VCCD will overflow. This overflow condition manifests
itself in the image by making bright spots appear elongated
in the vertical direction. The size increase of a bright spot is
called blooming when the spot doubles in size.
The blooming can be eliminated by increasing the voltage
on SUB to lower the charge capacity of the photodiode. This
ensures the VCCD charge capacity is greater than the
photodiode capacity. There are cases where an extremely
bright spot will still cause blooming in the VCCD. Normally,
when the photodiode is full, any additional electrons
generated by photons will spill out of the photodiode.
The excess electrons are drained harmlessly out to the
substrate. There is a maximum rate at which the electrons
can be drained to the substrate. If that maximum rate is
exceeded, (for example, by a very bright light source) then
it is possible for the total amount of charge in the photodiode
to exceed the VCCD capacity. This results in blooming.
The amount of anti-blooming protection also decreases
when the integration time is decreased. There is
a compromise between photodiode dynamic range
(controlled by VSUB) and the amount of anti-blooming
protection. A low VSUB voltage provides the maximum
dynamic range and minimum (or no) anti-blooming
protection. A high VSUB voltage provides lower dynamic
range and maximum anti-blooming protection. The optimal
setting of VSUB is written on the container in which each
KAI−11002 is shipped. The given VSUB voltage for each
sensor is selected to provide anti-blooming protection for
bright spots at least 100 times saturation, while maintaining
at least 60 ke− of dynamic range.
The electronic shutter provides a method of precisely
controlling the image exposure time without any
mechanical components. If an integration time of tINT is
desired, then the substrate voltage of the sensor is pulsed to
at least 40 volts tINT seconds before the photodiode to
VCCD transfer pulse on V2. Use of the electronic shutter
does not have to wait until the previously acquired image has
been completely read out of the VCCD.
The figure below shows the DC bias (SUB) and AC clock
(VSHUTTER) applied to the SUB pin. Both the DC bias and
AC clock are referenced to ground.
Figure 34. DC Bias and AC Clock Applied to the SUB Pin
SUB
GND GND
V
SHUTTER
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STORAGE AND HANDLING
Table 14. STORAGE CONDITIONS
Description Symbol Minimum Maximum Unit Notes
Storage Temperature TST −20 80 °C 1
Humidity RH 5 90 % 2
1. Long-term exposure toward the maximum temperature will accelerate color filter degradation.
2. T = 25°C. Excessive humidity will degrade MTTF.
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For information on environmental exposure, please
download the Using Interline CCD Image Sensors in High
Intensity Lighting Conditions Application Note
(AND9183/D) from www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference Manual (SOLDERRM/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
KAI−11002
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33
Glass
Figure 37. Glass Drawing
1. Multi-Layer Anti-Reflective Coating on 2 Sides:
Double Sided Reflectance:
Range (mm)
420−450 nm < 2%
450−630 nm < 1%
630−680 nm < 2%
2. Dust, Scratch Specification − 20 microns max.
3. Substrate − Schott D236T eco or equivalent
4. Epoxy: NCO−150HB
Thickness: 0.002″−0.005″
Notes:
Double Sided AR Coated Glass
1. Materials: Substrate − Schott D236T eco or equivalent
2. No Epoxy
3. Dust, Scratch Count − 20 microns max.
4. Reflectance:
420−435 nm < 10%
435−630 nm < 10%
630−680 nm < 10%
Clear Glass
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Glass Transmission
Figure 38. MAR and Clear Glass Transmission
0
10
20
30
40
50
60
70
80
90
100
200 300 400 500 600 700 800 900
Wavelength (nm)
Transmission (%)
Clear
MAR
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Phone: 421 33 790 2910
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Phone: 81−3−5817−1050
KAI−11002/D
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