LO
UVLO
HO
DRIVER
UVLO LEVEL
SHIFT
HB
HS
DRIVER
VDD
VSS
HI
LI
LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C
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SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013
LM5100A/B/C
LM5101A/B/C 3A, 2A and 1A High Voltage High-Side and Low-Side Gate Drivers
Check for Samples: LM5100A,LM5100B,LM5100C,LM5101A,LM5101B,LM5101C
1FEATURES DESCRIPTION
The LM5100A/B/C and LM5101A/B/C High Voltage
2• Drives Both a High-side and Low-side N- Gate Drivers are designed to drive both the high-side
Channel MOSFETs and the low-side N-Channel MOSFETs in a
• Independent High and Low Driver Logic Inputs synchronous buck or a half-bridge configuration. The
• Bootstrap Supply Voltage up to 118V DC floating high-side driver is capable of operating with
supply voltages up to 100V. The “A” versions provide
• Fast Propagation Times (25 ns Typical) a full 3A of gate drive while the “B” and “C” versions
• Drives 1000 pF Load with 8 ns Rise and Fall provide 2A and 1A respectively. The outputs are
Times independently controlled with CMOS input thresholds
• Excellent Propagation Delay Matching (3 ns (LM5100A/B/C) or TTL input thresholds
(LM5101A/B/C). An integrated high voltage diode is
typical) provided to charge the high-side gate drive bootstrap
• Supply Rail Under-voltage Lockout capacitor. A robust level shifter operates at high
• Low Power Consumption speed while consuming low power and providing
• Pin Compatible with HIP2100/HIP2101 clean level transitions from the control logic to the
high-side gate driver. Under-voltage lockout is
provided on both the low-side and the high-side
TYPICAL APPLICATIONS power rails. These devices are available in the
• Current Fed Push-pull Converters standard SOIC-8 pin, SO PowerPad-8 pin and the
• Half and Full Bridge Power Converters WSON-10 pin packages. The LM5100C and
LM5101C are also available in MSOP-PowerPad-8
• Synchronous Buck Converters package. The LM5101A is also available in WSON-8
• Two Switch Forward Power Converters pin package.
• Forward with Active Clamp Converters Package
• SOIC-8
• SO PowerPad-8
• WSON-8 (4 mm x 4 mm)
• WSON-10 (4 mm x 4 mm)
• MSOP-PowerPad-8
Simplified Block Diagram
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2006–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
VDD
HB
HO
HS
LO
VSS
LI
HI
MSOP-
PowerPad-8
Exposed Pad
Connect to VSS
HO 3
HS 4
VDD 1
HB 2
8 LO
7 VSS
6 LI
5 HI
SO
PowerPad-8
WSON-10
1
2
3
4
9
6
7
8
VDD
HB
HO
HS HI
LI
VSS
LO
NC 5
10
NC
WSON-8
1
2
3
4 5
6
7
8VDD
HB
HO
HS HI
LI
VSS
LO
VDD
HB
HO
HS
LO
VSS
LI
HI
18
27
36
4 5
SOIC-8
LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C
SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013
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Table 1. Input/Output Options
Part Number Input Thresholds Peak Output Current
LM5100A CMOS 3A
LM5101A TTL 3A
LM5100B CMOS 2A
LM5101B TTL 2A
LM5100C CMOS 1A
LM5101C TTL 1A
Connection Diagrams
PIN DESCRIPTIONS(1)
Pin #
SO MSOP- Name Description Application Information
WSON- WSON-
SOIC-8 Power PowerPad
8(1) 10(1)
Pad-8 -8(1)
Positive gate Locally decouple to VSS using low ESR/ESL
1 1 1 1 1 VDD drive supply capacitor located as close to the IC as possible.
Connect the positive terminal of the bootstrap
High-side gate capacitor to HB and the negative terminal to HS. The
2 2 2 2 2 HB driver bootstrap bootstrap capacitor should be placed as close to the
rail IC as possible.
High-side gate Connect to the gate of high-side MOSFET with a
3 3 3 3 3 HO driver output short, low inductance path.
(1) Note: For WSON-8, WSON-10 and MSOP-PowerPad-8 package, it is recommended that the exposed pad on the bottom of the
package is soldered to ground plane on the PC board, and that ground plane should extend out from beneath the IC to help
dissipate heat. For WSON-10 package, pins 5 and 6 have no connection.
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SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013
PIN DESCRIPTIONS(1) (continued)
Pin #
SO MSOP- Name Description Application Information
WSON- WSON-
SOIC-8 Power PowerPad
8(1) 10(1)
Pad-8 -8(1)
High-side
MOSFET Connect to the bootstrap capacitor negative terminal
4 4 4 4 4 HS source and the source of the high-side MOSFET.
connection The LM5100A/B/C inputs have CMOS type
High-side driver thresholds. The LM5101A/B/C inputs have TTL type
5 5 5 7 5 HI control input thresholds. Unused inputs should be tied to ground
and not left open.
The LM5100A/B/C inputs have CMOS type
Low-side driver thresholds. The LM5101A/B/C inputs have TTL type
6 6 6 8 6 LI control input thresholds. Unused inputs should be tied to ground
and not left open.
7 7 7 9 7 VSS Ground return All signals are referenced to this ground.
Low-side gate Connect to the gate of the low-side MOSFET with a
8 8 8 10 8 LO driver output short, low inductance path.
EP (WSON and SO Solder to the ground plane under the IC to aid in heat
EP EP EP EP PowerPad and MSOP- dissipation.
PowerPad packages)
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)(2)
VDD to VSS −0.3V to +18V
HB to HS −0.3V to +18V
LI or HI Input −0.3V to VDD +0.3V
LO Output −0.3V to VDD +0.3V
HO Output VHS −0.3V to VHB +0.3V
HS to VSS (3) −5V to +100V
HB to VSS 118V
Junction Temperature +150°C
Storage Temperature Range −55°C to +150°C
ESD Rating HBM (4) 2 kV
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test
conditions, see the Electrical Characteristics Electrical Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS node will generally not
exceed -1V. However, in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage
transiently. If negative transients occur, the HS voltage must never be more negative than VDD-15V. For example if VDD = 10V, the
negative transients at HS must not exceed -5V.
(4) The Human Body Model (HBM) is a 100 pF capacitor discharged through a 1.5kΩresistor into each pin. 2 kV for all pins except Pin 2,
Pin 3 and Pin 4 which are rated at 1000V for HBM. Machine Model (MM) ratings are : 100V(MM) for Options B and C; 50V(MM) for
Option A.
Recommended Operating Conditions
VDD +9V to +14V
HS −1V to 100V
HB VHS +8V to VHS +14V
HS Slew Rate < 50 V/ns
Junction Temperature −40°C to +125°C
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SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013
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Electrical Characteristics
Limits in standard type are for TJ= 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent
the most likely parametric norm at TJ= 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD =
VHB = 12V, VSS = VHS = 0V, No Load on LO or HO (1).
Symbol Parameter Conditions Min Typ Max Units
SUPPLY CURRENTS
IDD VDD Quiescent Current, LM5100A/B/C LI = HI = 0V 0.1 0.2 mA
VDD Quiescent Current, LM5101A/B/C LI = HI = 0V 0.25 0.4
IDDO VDD Operating Current f = 500 kHz 2.0 3mA
IHB Total HB Quiescent Current LI = HI = 0V 0.06 0.2 mA
IHBO Total HB Operating Current f = 500 kHz 1.6 3mA
IHBS HB to VSS Current, Quiescent HS = HB = 100V 0.1 10 µA
IHBSO HB to VSS Current, Operating f = 500 kHz 0.4 mA
INPUT PINS
VIL Input Voltage Threshold LM5100A/B/C Rising Edge 4.5 5.4 6.3 V
VIL Input Voltage Threshold LM5101A/B/C Rising Edge 1.3 1.8 2.3 V
VIHYS Input Voltage Hysteresis LM5100A/B/C 500 mV
VIHYS Input Voltage Hysteresis LM5101A/B/C 50 mV
RIInput Pulldown Resistance 100 200 400 kΩ
UNDER VOLTAGE PROTECTION
VDDR VDD Rising Threshold 6.0 6.9 7.4 V
VDDH VDD Threshold Hysteresis 0.5 V
VHBR HB Rising Threshold 5.7 6.6 7.1 V
VHBH HB Threshold Hysteresis 0.4 V
BOOT STRAP DIODE
VDL Low-Current Forward Voltage IVDD-HB = 100 µA 0.52 0.85 V
VDH High-Current Forward Voltage IVDD-HB = 100 mA 0.8 1V
RDDynamic Resistance LM5100A/B/C, LM5101A/B/C IVDD-HB = 100 mA 1.0 1.65 Ω
LO & HO GATE DRIVER
VOL Low-Level Output Voltage LM5100A/LM5101A IHO = ILO = 100 mA 0.12 0.25
Low-Level Output Voltage LM5100B/LM5101B 0.16 0.4 V
Low-Level Output Voltage LM5100C/LM5101C 0.28 0.65
VOH High-Level Output Voltage LM5100A/LM5101A IHO = ILO = 100 mA 0.24 0.45
VOH = VDD– LO or
High-Level Output Voltage LM5100B/LM5101B 0.28 0.60 V
VOH = HB - HO
High-Level Output Voltage LM5100C/LM5101C 0.60 1.10
IOHL Peak Pullup Current LM5100A/LM5101A HO, LO = 0V 3
Peak Pullup Current LM5100B/LM5101B 2 A
Peak Pullup Current LM5100C/LM5101C 1
IOLL Peak Pulldown Current LM5100A/LM5101A HO, LO = 12V 3
Peak Pulldown Current LM5100B/LM5101B 2 A
Peak Pulldown Current LM5100C/LM5101C 1
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
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SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013
Electrical Characteristics (continued)
Limits in standard type are for TJ= 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent
the most likely parametric norm at TJ= 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD =
VHB = 12V, VSS = VHS = 0V, No Load on LO or HO (1).
Symbol Parameter Conditions Min Typ Max Units
THERMAL RESISTANCE
SOIC-8 170
WSON-8(3) 40
θJA(2) Junction to Ambient WSON-10 (3) 40 °C/W
SO PowerPad-8 40
MSOP-PowerPad-8 (3) 80
(2) The θJA is not a given constant for the package and depends on the printed circuit board design and the operating environment.
(3) 4 layer board with Cu finished thickness 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm
ground and power planes embedded in PCB. See Application Note AN-1187.
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SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013
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Switching Characteristics
Limits in standard type are for TJ= 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent
the most likely parametric norm at TJ= 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD =
VHB = 12V, VSS = VHS = 0V, No Load on LO or HO (1).
Symbol Parameter Conditions Min Typ Max Units
tLPHL LO Turn-Off Propagation Delay LI Falling to LO Falling 20 45
LM5100A/B/C ns
LO Turn-Off Propagation Delay 22 56
LM5101A/B/C
tLPLH LO Turn-On Propagation Delay LI Rising to LO Rising 20 45
LM5100A/B/C ns
LO Turn-On Propagation Delay 26 56
LM5101A/B/C
tHPHL HO Turn-Off Propagation Delay HI Falling to HO Falling 20 45
LM5100A/B/C ns
HO Turn-Off Propagation Delay 22 56
LM5101A/B/C
tHPLH LO Turn-On Propagation Delay HI Rising to HO Rising 20 45
LM5100A/B/C ns
LO Turn-On Propagation Delay 26 56
LM5101A/B/C
tMON Delay Matching: LO on & HO off 110 ns
LM5100A/B/C
Delay Matching: LO on & HO off 410
LM5101A/B/C
tMOFF Delay Matching: LO off & HO on 110
LM5100A/B/C ns
Delay Matching: LO on & HO off 410
LM5101A/B/C
tRC, tFC Either Output Rise/Fall Time CL= 1000 pF 8 ns
tROutput Rise Time (3V to 9V) CL= 0.1 µF 430
LM5100A/LM5101A ns
Output Rise Time (3V to 9V) 570
LM5100B/LM5101B
Output Rise Time (3V to 9V) 990
LM5100C/LM5101C
tFOutput Fall Time (3V to 9V) CL= 0.1 µF 260
LM5100A/LM5101A
Output Fall Time (3V to 9V) 430 ns
LM5100B/LM5101B
Output Fall Time (3V to 9V) 715
LM5100C/LM5101C
tPW Minimum Input Pulse Width that Changes 50 ns
the Output
tBS Bootstrap Diode Reverse Recovery Time IF= 100 mA, 37 ns
IR= 100 mA
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
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0.1 1 10 100 1000
FREQUENCY (kHz)
10
100
1000
10000
100000
CURRENT (PA)
VDD = 12V
CL = 0 pF
CL = 4400 pF
CL = 1000 pF
0.1 1 10 100 1000
FREQUENCY (kHz)
100
1000
10000
100000
CURRENT (PA)
VDD = 12V CL = 4400 pF
CL = 1000 pF
CL = 0 pF
02 4 68 10 12
OUTPUT VOLTAGE (V)
0.0
3.5
CURRENT (A)
0.5
1.0
1.5
2.0
2.5
3.0
LM5100B/LM5101B
LM5100C/LM5101C
LM5100A/LM5101A
VDD = 12V
02 4 68 10 12
OUTPUT VOLTAGE (V)
0.0
3.5
CURRENT (A)
0.5
1.0
1.5
2.0
2.5
3.0
LM5100B/LM5101B
LM5100C/LM5101C
LM5100A/LM5101A
VDD = 12V
7 8 9 10 11 12 13 14 15
CURRENT (A)
VDD (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
LM5100B/LM5101B
LM5100C/LM5101C
LM5100A/LM5101A
7 8 9 10 11 12 13 14 15
CURRENT (A)
VDD (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
LM5100B/LM5101B
LM5100C/LM5101C
LM5100A/LM5101A
LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C
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SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013
Typical Performance Characteristics
Peak Sourcing Current Peak Sinking Current
vs vs
VDD VDD
Figure 1. Figure 2.
Sink Current Source Current
vs vs
Output Voltage Output Voltage
Figure 3. Figure 4.
LM5100A/B/C IDD LM5101A/B/C IDD
vs vs
Frequency Frequency
Figure 5. Figure 6.
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-25 0_25 50_75_100_125_150_
TEMPERATURE (oC)
0.30
0.35
0.40
0.45
0.50
0.55
0.60
HYSTERESIS (V)
-50
VHBH
VDDH
-50 -25 0 25 50 75 100 125 150
TEMPERATURE (°C)
6.30
6.40
6.50
6.60
6.70
6.80
6.90
7.00
7.10
7.20
7.30
THRESHOLD (V)
VHBR
VDDR
8 9 10 11 12 13 14 15 16
VDD, VHB (V)
0
50
100
150
200
250
300
350
400
CURRENT (PA)
IDD (LM5101A/B/C)
IDD (LM5100A/B/C)
IHB
-50 -25 0 25 50 75 100 125 150
TEMPERATURE (°C)
CURRENT (PA)
IDD (LM5101A/B/C)
IDD (LM5100A/B/C)
IHB
0
50
100
150
200
250
300
350
-50 -25 0 25 50 75 100 125 150
TEMPERATURE (oC)
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
CURRENT (mA)
IDDO (LM5101A/B/C)
IDDO (LM5100A/B/C)
IHBO
0.1 1 10 100 1000
FREQUENCY (kHz)
10
100
1000
10000
100000
CURRENT (PA)
HB = 12V,
HS = 0V
CL = 0 pF
CL = 4400 pF
CL = 1000 pF
LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C
SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013
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Typical Performance Characteristics (continued)
Operating Current IHB
vs vs
Temperature Frequency
Figure 7. Figure 8.
Quiescent Current Quiescent Current
vs vs
Supply Voltage Temperature
Figure 9. Figure 10.
Undervoltage Rising Thresholds Undervoltage Threshold Hysteresis
vs vs
Temperature Temperature
Figure 11. Figure 12.
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-50 -25 0 25 50 75 100 125 150
TEMPERATURE (°C)
15
20
25
30
35
DELAY (ns)
T_PHL
T_PLH
THRESHOLD VOLTAGE (V)
8 9 10 11 12 13 14 15 16
VDD (V)
1.80
1.81
1.82
1.83
1.84
1.85
1.86
1.87
1.88
1.89
1.90
1.91
1.92
Rising
Falling
THRESHOLD VOLTAGE (V)
-50 -25 0 25 50 75 100 125 150
TEMPERATURE (°C)
1.80
1.81
1.82
1.83
1.84
1.85
1.86
1.87
1.88
1.89
1.90
1.91
1.92
Rising
Falling
8 9 10 11 12 13 14 15 16
VDD (V)
40
41
42
43
44
45
46
47
48
49
50
THRESHOLD VOLTAGE (%VDD)
Rising
Falling
1.00E-06
1.00E-05
1.00E-04
1.00E-03
1.00E-02
1.00E-01
ID (A)
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VD (V)
T = 25°C
T = -40°C
T = 150°C
-50 -25 0 25 50 75 100 125 150
TEMPERATURE (°C)
40
41
42
43
44
45
46
47
48
49
50
THRESHOLD VOLTAGE (%VDD)
Rising
Falling
LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C
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SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013
Typical Performance Characteristics (continued)
LM5100A/B/C Input Threshold
vs
Bootstrap Diode Forward Voltage Temperature
Figure 13. Figure 14.
LM5101A/B/C Input Threshold LM5100A/B/C Input Threshold
vs vs
Temperature VDD
Figure 15. Figure 16.
LM5101A/B/C Input Threshold LM5100A/B/C Propagation Delay
vs vs
VDD Temperature
Figure 17. Figure 18.
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78 9 10 11 12 13 14 15
VDD (V)
VOL (V)
0.10
0.15
0.35
0.20
0.25
0.30
LM5100B/LM5101B
LM5100A/LM5101A
IOUT = 100 mA
LM5100C/LM5101C
-50 -25 0 25 50 75 100 125 150
VOL (V)
TEMPERATURE (°C)
0.00
0.50
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
LM5100B/LM5101B
LM5100C/LM5101C
LM5100A/LM5101A
VDD = 12V
78 9 10 11 12 13 14
VDD (V) 15
0.1
0.8
VOH (V)
0.2
0.3
0.4
0.5
0.6
0.7
LM5100B/LM5101B
LM5100C/LM5101C
LM5100A/LM5101A
IOUT = -100 mA
T_PLH
T_PHL
-50 -25 0 25 50 75 100 125 150
TEMPERATURE (°C)
15
25
30
35
40
DELAY (ns)
20
-50 -25 0 25 50 75 100 125 150
VOH (V)
TEMPERATURE (°C)
0.0
1.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
LM5100B/LM5101B
LM5100C/LM5101C
LM5100A/LM5101A
VDD = 12V
LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C
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Typical Performance Characteristics (continued)
LM5101A/B/C Propagation Delay LO & HO Gate Drive - High Level Output Voltage
vs vs
Temperature Temperature
Figure 19. Figure 20.
LO & HO Gate Drive - Low Level Output Voltage LO & HO Gate Drive - Output High Voltage
vs vs
Temperature VDD
Figure 21. Figure 22.
LO & HO Gate Drive - Output Low Voltage
vs
VDD
Figure 23.
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LI
HI
tHPLH
tLPLH tHPHL
tLPHL
LO
HO
LI
HI
tMOFF
tMON
LO
HO
LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C
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SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013
TIMING DIAGRAM
Figure 24.
Layout Considerations
The optimum performance of high and low-side gate drivers cannot be achieved without taking due
considerations during circuit board layout. Following points are emphasized.
1. Low ESR / ESL capacitors must be connected close to the IC, between VDD and VSS pins and between the
HB and HS pins to support the high peak currents being drawn from VDD during turn-on of the external
MOSFET.
2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be
connected between MOSFET drain and ground (VSS).
3. In order to avoid large negative transients on the switch node (HS pin), the parasitic inductances in the
source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized.
4. Grounding Considerations:
– a) The first priority in designing grounding connections is to confine the high peak currents that charge
and discharge the MOSFET gate into a minimal physical area. This will decrease the loop inductance and
minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as
possible to the gate driver.
– b) The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground
referenced bypass capacitor and low-side MOSFET body diode. The bootstrap capacitor is recharged on
a cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor.
The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length
and area on the circuit board is important to ensure reliable operation.
A recommended layout pattern for the driver is shown in the following figure. If possible a single layer placement
is preferred.
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
0.1 1.0 10.0 100.0 1000.0
SWITCHING FREQUENCY (kHz)
0.001
0.010
0.100
1.000
POWER (W)
CL = 4400 pF
CL = 0 pF
CL = 1000 pF
To Hi-Side FET To Low-Side FET
HO
Single Layer
Option
LO
GND
Multi Layer
Option
Recommended Layout for Driver IC and
Passives
VSS
LO
LI
SO
PowerPAD-8
HI
VDD
HB
HO
HS
HO
HS
LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C
SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013
www.ti.com
Power Dissipation Considerations
The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate
driver losses are related to the switching frequency (f), output load capacitance on LO and HO (CL), and supply
voltage (VDD) and can be roughly calculated as:
PDGATES = 2 • f • CL• VDD2(1)
There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and
HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load
capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the
power losses driving the output loads and agrees well with the above equation.Equation 1 This plot can be used
to approximate the power losses due to the gate drivers.
Figure 25. Gate Driver Power Dissipation (LO + HO)
VDD = 12V, Neglecting Diode Losses
12 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
110 100 1000
SWITCHING FREQUENCY (kHz)
POWER (W)
0.001
0.010
0.100
CL = 4400 pF
CL = 0 pF
LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C
www.ti.com
SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013
The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the
bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these
events happens once per cycle, the diode power loss is proportional to frequency. Larger capacitive loads
require more energy to recharge the bootstrap capacitor resulting in more losses. Higher input voltages (VIN) to
the half bridge result in higher reverse recovery losses. The following plot was generated based on calculations
and lab measurements of the diode recovery time and current under several operating conditions. This can be
useful for approximating the diode power dissipation.
The total IC power dissipation can be estimated from the previous plots by summing the gate drive losses with
the bootstrap diode losses for the intended application.
Figure 26. Diode Power Dissipation VIN = 50V
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C
SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013
www.ti.com
REVISION HISTORY
Changes from Revision O (March 2013) to Revision P Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 13
14 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
LM5100AM ACTIVE SOIC D 8 95 TBD Call TI Call TI -40 to 125 L5100
AM
LM5100AM/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5100
AM
LM5100AMR/NOPB ACTIVE SO PowerPAD DDA 8 95 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR L5100
AMR
LM5100AMRX/NOPB ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS
& no Sb/Br) SN Level-3-260C-168 HR L5100
AMR
LM5100AMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5100
AM
LM5100ASD ACTIVE WSON DPR 10 1000 TBD Call TI Call TI -40 to 125 5100ASD
LM5100ASD/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 5100ASD
LM5100ASDX ACTIVE WSON DPR 10 4500 TBD Call TI Call TI -40 to 125 5100ASD
LM5100ASDX/NOPB ACTIVE WSON DPR 10 4500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 5100ASD
LM5100BMA ACTIVE SOIC D 8 95 TBD Call TI Call TI -40 to 125 L5100
BMA
LM5100BMA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5100
BMA
LM5100BMAX ACTIVE SOIC D 8 2500 TBD Call TI Call TI -40 to 125 L5100
BMA
LM5100BMAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5100
BMA
LM5100BSD ACTIVE WSON DPR 10 1000 TBD Call TI Call TI -40 to 125 5100BSD
LM5100BSD/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 5100BSD
LM5100BSDX ACTIVE WSON DPR 10 4500 TBD Call TI Call TI -40 to 125 5100BSD
LM5100BSDX/NOPB ACTIVE WSON DPR 10 4500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 5100BSD
LM5100CMA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5100
CMA
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
LM5100CMAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5100
CMA
LM5100CMY/NOPB ACTIVE MSOP-
PowerPAD DGN 8 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM SXCB
LM5100CMYE/NOPB ACTIVE MSOP-
PowerPAD DGN 8 250 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM SXCB
LM5100CMYX/NOPB ACTIVE MSOP-
PowerPAD DGN 8 3500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM SXCB
LM5100CSD/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 5100CSD
LM5100CSDX/NOPB ACTIVE WSON DPR 10 4500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 5100CSD
LM5101AM ACTIVE SOIC D 8 95 TBD Call TI Call TI -40 to 125 L5101
AM
LM5101AM/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5101
AM
LM5101AMR/NOPB ACTIVE SO PowerPAD DDA 8 95 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR L5101
AMR
LM5101AMRX/NOPB ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR L5101
AMR
LM5101AMX ACTIVE SOIC D 8 2500 TBD Call TI Call TI -40 to 125 L5101
AM
LM5101AMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5101
AM
LM5101ASD ACTIVE WSON DPR 10 1000 TBD Call TI Call TI -40 to 125 5101ASD
LM5101ASD-1/NOPB ACTIVE WSON NGT 8 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM 5101A-1
LM5101ASD/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 5101ASD
LM5101ASDX ACTIVE WSON DPR 10 4500 TBD Call TI Call TI -40 to 125 5101ASD
LM5101ASDX-1/NOPB ACTIVE WSON NGT 8 4500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM 5101A-1
LM5101ASDX/NOPB ACTIVE WSON DPR 10 4500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 5101ASD
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 3
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
LM5101BMA ACTIVE SOIC D 8 95 TBD Call TI Call TI -40 to 125 L5101
BMA
LM5101BMA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5101
BMA
LM5101BMAX ACTIVE SOIC D 8 2500 TBD Call TI Call TI -40 to 125 L5101
BMA
LM5101BMAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5101
BMA
LM5101BSD ACTIVE WSON DPR 10 1000 TBD Call TI Call TI -40 to 125 5101BSD
LM5101BSD/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 5101BSD
LM5101BSDX ACTIVE WSON DPR 10 4500 TBD Call TI Call TI -40 to 125 5101BSD
LM5101BSDX/NOPB ACTIVE WSON DPR 10 4500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 5101BSD
LM5101CMA ACTIVE SOIC D 8 95 TBD Call TI Call TI -40 to 125 L5101
CMA
LM5101CMA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5101
CMA
LM5101CMAX ACTIVE SOIC D 8 2500 TBD Call TI Call TI -40 to 125 L5101
CMA
LM5101CMAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5101
CMA
LM5101CMY/NOPB ACTIVE MSOP-
PowerPAD DGN 8 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM SXDB
LM5101CMYE/NOPB ACTIVE MSOP-
PowerPAD DGN 8 250 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM SXDB
LM5101CMYX/NOPB ACTIVE MSOP-
PowerPAD DGN 8 3500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM SXDB
LM5101CSD ACTIVE WSON DPR 10 1000 TBD Call TI Call TI -40 to 125 5101CSD
LM5101CSD/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 5101CSD
LM5101CSDX ACTIVE WSON DPR 10 4500 TBD Call TI Call TI -40 to 125 5101CSD
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 4
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
LM5101CSDX/NOPB ACTIVE WSON DPR 10 4500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 5101CSD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM5100AMRX/NOPB SO
Power
PAD
DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5100AMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5100ASD WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5100ASD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5100ASDX WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5100ASDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5100BMAX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5100BMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5100BSD WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5100BSD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5100BSDX WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5100BSDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5100CMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5100CMY/NOPB MSOP-
Power
PAD
DGN 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM5100CMYE/NOPB MSOP- DGN 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Mar-2013
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
Power
PAD
LM5100CMYX/NOPB MSOP-
Power
PAD
DGN 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM5100CSD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5100CSDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5101AMRX/NOPB SO
Power
PAD
DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5101AMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5101AMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5101ASD WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5101ASD-1/NOPB WSON NGT 8 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5101ASD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5101ASDX WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5101ASDX-1/NOPB WSON NGT 8 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5101ASDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5101BMAX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5101BMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5101BSD WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5101BSD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5101BSDX WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5101BSDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5101CMAX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5101CMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5101CMY/NOPB MSOP-
Power
PAD
DGN 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM5101CMYE/NOPB MSOP-
Power
PAD
DGN 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM5101CMYX/NOPB MSOP-
Power
PAD
DGN 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM5101CSD WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5101CSD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5101CSDX WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5101CSDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Mar-2013
Pack Materials-Page 2
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM5100AMRX/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0
LM5100AMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM5100ASD WSON DPR 10 1000 210.0 185.0 35.0
LM5100ASD/NOPB WSON DPR 10 1000 210.0 185.0 35.0
LM5100ASDX WSON DPR 10 4500 367.0 367.0 35.0
LM5100ASDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0
LM5100BMAX SOIC D 8 2500 367.0 367.0 35.0
LM5100BMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM5100BSD WSON DPR 10 1000 210.0 185.0 35.0
LM5100BSD/NOPB WSON DPR 10 1000 210.0 185.0 35.0
LM5100BSDX WSON DPR 10 4500 367.0 367.0 35.0
LM5100BSDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0
LM5100CMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM5100CMY/NOPB MSOP-PowerPAD DGN 8 1000 210.0 185.0 35.0
LM5100CMYE/NOPB MSOP-PowerPAD DGN 8 250 210.0 185.0 35.0
LM5100CMYX/NOPB MSOP-PowerPAD DGN 8 3500 367.0 367.0 35.0
LM5100CSD/NOPB WSON DPR 10 1000 210.0 185.0 35.0
LM5100CSDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0
LM5101AMRX/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0
LM5101AMX SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Mar-2013
Pack Materials-Page 3
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM5101AMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM5101ASD WSON DPR 10 1000 210.0 185.0 35.0
LM5101ASD-1/NOPB WSON NGT 8 1000 210.0 185.0 35.0
LM5101ASD/NOPB WSON DPR 10 1000 210.0 185.0 35.0
LM5101ASDX WSON DPR 10 4500 367.0 367.0 35.0
LM5101ASDX-1/NOPB WSON NGT 8 4500 367.0 367.0 35.0
LM5101ASDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0
LM5101BMAX SOIC D 8 2500 367.0 367.0 35.0
LM5101BMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM5101BSD WSON DPR 10 1000 210.0 185.0 35.0
LM5101BSD/NOPB WSON DPR 10 1000 210.0 185.0 35.0
LM5101BSDX WSON DPR 10 4500 367.0 367.0 35.0
LM5101BSDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0
LM5101CMAX SOIC D 8 2500 367.0 367.0 35.0
LM5101CMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM5101CMY/NOPB MSOP-PowerPAD DGN 8 1000 210.0 185.0 35.0
LM5101CMYE/NOPB MSOP-PowerPAD DGN 8 250 210.0 185.0 35.0
LM5101CMYX/NOPB MSOP-PowerPAD DGN 8 3500 367.0 367.0 35.0
LM5101CSD WSON DPR 10 1000 210.0 185.0 35.0
LM5101CSD/NOPB WSON DPR 10 1000 210.0 185.0 35.0
LM5101CSDX WSON DPR 10 4500 367.0 367.0 35.0
LM5101CSDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Mar-2013
Pack Materials-Page 4
MECHANICAL DATA
DGN0008A
www.ti.com
MUY08A (Rev A)
BOTTOM VIEW
MECHANICAL DATA
DDA0008B
www.ti.com
MRA08B (Rev B)
MECHANICAL DATA
NGT0008A
www.ti.com
SDC08A (Rev A)
MECHANICAL DATA
DPR0010A
www.ti.com
SDC10A (Rev A)
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
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