1
2
3
4
8
7
6
5
GND
IN
IN
EN
OUT
OUT
OUT
OC
D PACKAGE
(TOP VIEW)
TPS2020-Q1, TPS2021-Q1
TPS2022-Q1, TPS2024-Q1
www.ti.com
SGLS260G –SEPTEMBER 2004–REVISED JUNE 2010
POWER-DISTRIBUTION SWITCHES
Check for Samples: TPS2020-Q1,TPS2021-Q1,TPS2022-Q1,TPS2024-Q1
1FEATURES
• Qualified for Automotive Applications • Ambient Temperature Range: –40°C to 85°C
• 33-mΩ(5-V Input) High-Side MOSFET Switch • ESD Protection: 2-kV Human-Body Model,
200-V Machine Model
• Short-Circuit and Thermal Protection • UL Listed - File No. E169910
• Overcurrent Logic Output
• Operating Range: 2.7 V to 5.5 V
• Logic-Level Enable Input
• Typical Rise Time: 6.1 ms
• Undervoltage Lockout
• Maximum Standby Supply Current: 10 mA
• No Drain-Source Back-Gate Diode
• Available in 8-Pin SOIC Package
DESCRIPTION
The TPS202x family of power distribution switches is intended for applications where heavy capacitive loads and
short circuits are likely to be encountered. These devices are 50-mΩN-channel MOSFET high-side power
switches. The switch is controlled by a logic enable compatible with 5-V logic and 3-V logic. Gate drive is
provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize
current surges during switching. The charge pump requires no external components and allows operation from
supplies as low as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, the TPS202x limits the output
current to a safe level by switching into a constant-current mode, pulling the overcurrent (OC) logic output low.
When continuous heavy overloads and short circuits increase the power dissipation in the switch, causing the
junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a
thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures the switch
remains off until valid input voltage is present.
The TPS202x devices differ only in short-circuit current threshold. The TPS2020 limits at 0.3-A load, the
TPS2021 at 0.9-A load, the TPS2022 at 1.5-A load, and the TPS2024 at 3-A load. The TPS202x is available in
an 8-pin small-outline integrated-circuit (SOIC) package and operates over a junction temperature range of
–40°C to 125°C.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2004–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
OUT
OC
IN
EN
GND
Current
Limit
Driver
UVLO
Charge
Pump
CS
Thermal
Sense
Power Switch
†
†Current Sense
TPS2020-Q1, TPS2021-Q1
TPS2022-Q1, TPS2024-Q1
SGLS260G –SEPTEMBER 2004–REVISED JUNE 2010
www.ti.com
ORDERING INFORMATION(1)
RECOMMENDED MAXIMUM PACKAGED DEVICES(2)
TYPICAL SHORT-CIRCUIT
CONTINUOUS LOAD
TAENABLE CURRENT LIMIT AT 25°C SMALL OUTLINE
CURRENT (A) (D)
(A)
0.2 0.3 TPS2020IDRQ1
0.6 0.9 TPS2021IDRQ1
–40°C to 85°C Active low 1 1.5 TPS2022DRQ1
2 3 TPS2024IDRQ1
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
FUNCTIONAL BLOCK DIAGRAM
TERMINAL FUNCTIONS
TERMINAL I/O DESCRIPTION
NAME NO.
EN 4 I Enable input. Logic-low turns on power switch.
GND 1 I Ground
IN 2, 3 I Input voltage
OC 5 O Overcurrent. Logic output, active-low
OUT 6, 7, 8 O Power-switch output
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TPS2022-Q1, TPS2024-Q1
www.ti.com
SGLS260G –SEPTEMBER 2004–REVISED JUNE 2010
DETAILED DESCRIPTION
Power Switch
The power switch is an N-channel MOSFET with a maximum on-state resistance of 50 mΩ(VI(IN) = 5 V).
Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when
disabled.
Charge Pump
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
very little supply current.
Driver
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall
times of the output voltage. The rise and fall times are typically in the 2-ms to 9-ms range.
Enable (EN)
The logic enable disables the power switch, the bias for the charge pump, driver, and other circuitry to reduce the
supply current to less than 10 mA when a logic-high is present on EN. A logic-zero input on EN restores bias to
the drive and control circuits and turns the power on. The enable input is compatible with both TTL and CMOS
logic levels.
Overcurrent (OC)
The OC open drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output remains asserted until the overcurrent or overtemperature condition is removed.
Current Sense
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver, in turn, reduces the gate voltage and drives the power FET into
its saturation region, which switches the output into a constant-current mode and holds the current constant while
varying the voltage on the load.
Thermal Sense
An internal thermal-sense circuit shuts off the power switch when the junction temperature rises to approximately
140°C. Hysteresis is built into the thermal sense circuit. After the device has cooled approximately 20°C, the
switch turns back on. The switch continues to cycle off and on until the fault is removed.
Undervoltage Lockout
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control
signal turns off the power switch.
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SGLS260G –SEPTEMBER 2004–REVISED JUNE 2010
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VI(IN) (2) Input voltage range –0.3 V to 6 V
VO(OUT) (2) Output voltage range –0.3 V to VI(IN) + 0.3 V
VI(EN) Input voltage range –0.3 V to 6 V
IO(OUT) Continuous output current Internally limited
Continuous total power dissipation See Dissipation Rating Table
TJOperating virtual junction temperature range –40°C to 125°C
Tstg Storage temperature range –65°C to 150°C
Human body model 2 kV
ESD Electrostatic discharge protection Machine model 200 V
Charged device model (CDM) 750 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND.
DISSIPATION RATINGS
TA≤25°C DERATING FACTOR TA= 70°C TA= 85°C
PACKAGE POWER RATING ABOVE TA= 25°C POWER RATING POWER RATING
D 725 mW 5.8 mW/°C 464 mW 377 mW
RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT
VI(IN) 2.7 5.5 V
Input voltage
VI(EN) 0 5.5 V
TPS2020 0 0.2
TPS2021 0 0.6
IOContinuous output current A
TPS2022 0 1
TPS2024 0 2
TJOperating virtual junction temperature –40 125 °C
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TPS2022-Q1, TPS2024-Q1
www.ti.com
SGLS260G –SEPTEMBER 2004–REVISED JUNE 2010
ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature range, VI(IN) = 5.5 V, IO= rated current, EN = 0 V (unless otherwise noted)
PARAMETER TEST CONDITIONS(1) TJ(2) MIN TYP MAX UNIT
Power Switch
25°C 33 43.5
VI(IN) = 5 V, IO= 1.8 A 85°C 38 57.5
125°C 44 62.5
25°C 37 48.5
VI(IN) = 3.3 V, IO= 1.8 A 85°C 43 68.5
125°C 51 87
25°C 30 43.5
VI(IN) = 5 V, IO= 1 A 125°C 43 62.5
25°C 31 48.5
VI(IN) = 3.3 V, IO= 1 A 125°C 48 87
Static drain-source on-state
rDS(on) mΩ
resistance 25°C 30 34
VI(IN) = 5 V, IO= 0.18 A 85°C 35 41
125°C 39 47
25°C 33 37
VI(IN) = 3.3 V, IO= 0.18 A 85°C 39 46
125°C 44 56
25°C 33 36
VI(IN) = 5 V, IO= 0.6 A TPS2021 125°C 44 48
25°C 37 40
VI(IN) = 3.3 V, IO= 0.6 A TPS2021 125°C 51 59
VI(IN) = 5.5 V, CL= 1 mF, RL= 10 Ω6.1
trRise time, output 25°C ms
VI(IN) = 2.7 V, CL= 1 mF, RL= 10 Ω8.6
VI(IN) = 5.5 V, CL= 1 mF, RL= 10 Ω3.4
tfFall time, output 25°C ms
VI(IN) = 2.7 V, CL= 1 mF, RL= 10 Ω3
Enable Input (EN)
VIH High-level input voltage 2.7 V ≤VI(IN) ≤5.5 V Full range 2 V
4.5 V ≤VI(IN) ≤5.5 V Full range 0.8
VIL Low-level input voltage V
2.7 V ≤VI(IN) ≤4.5 V Full range 0.5
IIInput current EN = 0 V or EN = VI(IN) Full range –0.5 0.5 mA
ton Turnon time CL= 100 mF, RL= 10 ΩFull range 20 ms
toff Turnoff time CL= 100 mF, RL= 10 ΩFull range 40
Current Limit
TPS2020 0.22 0.3 0.4
VI= 5.5 V, TPS2021 0.66 0.9 1.1
IOS Short-circuit output current OUT connected to GND, 25°C A
TPS2022 1.1 1.5 1.8
Device enabled into short circuit TPS2024 2 3 4.2
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
(2) Full range TJ= -40°C to 125°C
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TPS2020-Q1, TPS2021-Q1
TPS2022-Q1, TPS2024-Q1
SGLS260G –SEPTEMBER 2004–REVISED JUNE 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating junction temperature range, VI(IN) = 5.5 V, IO= rated current, EN = 0 V (unless otherwise noted)
PARAMETER TEST CONDITIONS(1) TJ(2) MIN TYP MAX UNIT
Supply Current
25°C 0.3 1
Supply current, low-level output No load on OUT, EN = VI(IN) mA
Full range 10
25°C 58 75
Supply current, high-level output No load on OUT, EN = 0 V mA
Full range 75 100
Leakage current OUT connected to ground, EN = VI(IN) Full range 10 mA
Undervoltage Lockout
Low-level input voltage Full range 2 2.5 V
Hysteresis 25°C 100 mV
Overcurrent (OC)
Output low voltage IO= 10 mA, VOL(OC) Full range 0.4 V
Off-state current(3) VO= 5 V, VO= 3.3 V Full range 1 mA
(3) Specified by design.
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RL CL
OUT
trtf
90% 90%
10%
10%
50% 50%
90%
10%
VO(OUT)
VI(EN)
VO(OUT)
VOLTAGE WAVEFORMS
TEST CIRCUIT
ton toff
TPS2020-Q1, TPS2021-Q1
TPS2022-Q1, TPS2024-Q1
www.ti.com
SGLS260G –SEPTEMBER 2004–REVISED JUNE 2010
PARAMETER MEASURMENT INFORMATION
Figure 1. Test Circuit and Voltage Waveforms
Table 1. Timing Diagrams
FIGURE
Turnon Delay and Rise TIme 2
Turnoff Delay and Fall Time 3
Turnon Delay and Rise TIme with 1-mF Load 4
Turnoff Delay and Rise TIme with 1-mF Load 5
Device Enabled into Short 6
TPS2020 Ramped Load on Enabled Device 7
TPS2021 Ramped Load on Enabled Device 8
TPS2022 Ramped Load on Enabled Device 9
TPS2024 Ramped Load on Enabled Device 10
TPS2024, Inrush Current 11
7.9-ΩLoad Connected to an Enabled TPS2020 Device 12
3.7-ΩLoad Connected to an Enabled TPS2020 Device 13
3.7-ΩLoad Connected to an Enabled TPS2021 Device 14
2.6-ΩLoad Connected to an Enabled TPS2021 Device 15
2.6-ΩLoad Connected to an Enabled TPS2022 Device 16
1.2-ΩLoad Connected to an Enabled TPS2022 Device 17
0.9-ΩLoad Connected to an Enabled TPS2024 Device 18
0.5-ΩLoad Connected to an Enabled TPS2024 Device 19
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24 6 8 10 12 14 16 18 20
t − Time − ms
0
VIN = 5 V
RL = 27 Ω
TA = 25°C
VO(OUT) (2 V/div)
VI(EN)
VO(OUT)
VI(EN) (5 V/div)
2 4 6 8 10 12 14 16 18 20
t − Time − ms
VI(EN) (5 V/div)
0
VI(IN) = 5 V
RL = 27 Ω
TA = 25°C
VO(OUT) (2 V/div)
VI(EN)
VO(OUT)
24 6 8 10 12 14 16 18 20
t − Time − ms
VI(EN) (5 V/div)
0
VI(IN) = 5 V
CL = 1 µF
RL = 27 Ω
TA = 25°C
VO(OUT) (2 V/div)
VI(EN)
VO(OUT)
24 6 8 10 12 14 16 18 20
t − Time − ms
VI(EN) (5 V/div)
0
VI(IN) = 5 V
CL = 1 µF
RL = 27 Ω
TA = 25°C
VO(OUT) (2 V/div)
VI(EN)
VO(OUT)
TPS2020-Q1, TPS2021-Q1
TPS2022-Q1, TPS2024-Q1
SGLS260G –SEPTEMBER 2004–REVISED JUNE 2010
www.ti.com
Figure 2. Turnon Delay and Rise Time Figure 3. Turnoff Delay and Fall Time
Figure 4. Turnon Delay and Rise Time with 1-mF Figure 5. Turnoff Delay and Fall Time with 1-mF
Load Load
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12 3 4 5 6 7 8 9 10
t − Time − ms
VI(EN) (5 V/div)
0
IO(OUT) (1 A/div)
VI(EN)
IO(OUT)
VI(IN) = 5 V
TA = 25°CTPS2024
TPS2023
TPS2022
TPS2021
TPS2020
20 40 60 80 100 120 140 160 180 200
t − Time − ms
VO(OC) (5 V/div)
0
IO(OUT) (500 mA/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
TA = 25°C
20 40 60 80 100 120 140 160 180 200
t − Time − ms
VO(OC) (5 V/div)
0
IO(OUT) (1 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
TA = 25°C
20 40 60 80 100 120 140 160 180 200
t − Time − ms
VO(OC) (5 V/div)
0
IO(OUT) (1 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
TA = 25°C
TPS2020-Q1, TPS2021-Q1
TPS2022-Q1, TPS2024-Q1
www.ti.com
SGLS260G –SEPTEMBER 2004–REVISED JUNE 2010
Figure 6. Device Enabled Into Short Figure 7. TPS2020, Ramped Load on Enabled
Device
Figure 8. TPS2021, Ramped Load on Enabled Figure 9. TPS2022, Ramped Load on Enabled
Device Device
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1 2 3 4 5 6 7 8 9 10
t − Time − ms
0
II(IN) (500 mA/div)
VI(EN)
II(IN) RL = 10 Ω
TA = 25°C
VI(EN) (5 V/div)
470 µF
47 µF
150 µF
20 40 60 80 100 120 140 160 180 200
t − Time − ms
VO(OC) (5 V/div)
0
IO(OUT) (1 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
TA = 25°C
200 400 600 800 1000 12001400 1600 1800 2000
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (200 mA/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
RL = 7.9 Ω
TA = 25°C
50 100 150 200 250 300 350 400 450 500
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (500 mA/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
RL = 3.7 Ω
TA = 25°C
TPS2020-Q1, TPS2021-Q1
TPS2022-Q1, TPS2024-Q1
SGLS260G –SEPTEMBER 2004–REVISED JUNE 2010
www.ti.com
Figure 10. TPS2024, Ramped Load on Enabled Figure 11. TPS2024, Inrush Current
Device
Figure 12. 7.9-ΩLoad Connected to an Enabled Figure 13. 3.7-ΩLoad Connected to an Enabled
TPS2020 Device TPS2020 Device
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50 100 150 200 250 300 350 400 450 500
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (1 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
RL = 2.6 Ω
TA = 25°C
200 400 600 800 1000 12001400 1600 1800 2000
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (1 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
RL = 3.7 Ω
TA = 25°C
200 400 600 800 1000 1200 1400 1600 1800 2000
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (1 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
RL = 2.6 Ω
TA = 25°C
100 200 300 400 500 600 700 800 900 1000
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (1 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
RL = 1.2 Ω
TA = 25°C
TPS2020-Q1, TPS2021-Q1
TPS2022-Q1, TPS2024-Q1
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SGLS260G –SEPTEMBER 2004–REVISED JUNE 2010
Figure 14. 3.7-ΩLoad Connected to an Enabled Figure 15. 2.6-ΩLoad Connected to an Enabled
TPS2021 Device TPS2021 Device
Figure 16. 2.6-ΩLoad Connected to an Enabled Figure 17. 1.2-ΩLoad Connected to an Enabled
TPS2022 Device TPS2022 Device
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50 100 150 200 250 300 350 400 450 500
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (5 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
RL = 0.5 Ω
TA = 25°C
100 200 300 400 500 600 700 800 900 1000
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (5 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
RL = 0.9 Ω
TA = 25°C
TPS2020-Q1, TPS2021-Q1
TPS2022-Q1, TPS2024-Q1
SGLS260G –SEPTEMBER 2004–REVISED JUNE 2010
www.ti.com
Figure 18. 0.9-ΩLoad Connected to an Enabled Figure 19. 0.5-ΩLoad Connected to an Enabled
TPS2024 Device TPS2024 Device
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4.5
4
3.5 2.5 3 3.5 4 4.5
− Turn-on Delay Time − ms
5
5.5
7.5
5 5.5 6
VI − Input Voltage − V
td(on)
6
6.5
7TA = 25°C
CL = 1 µF
17
16.5
162.5 3 3.5 4 4.5
17.5
18
5 5.5 6
VI − Input Voltage − V
− Turn-off Delay Time − ms
td(off)
TA = 25°C
CL = 1 µF
TPS2020-Q1, TPS2021-Q1
TPS2022-Q1, TPS2024-Q1
www.ti.com
SGLS260G –SEPTEMBER 2004–REVISED JUNE 2010
TYPICAL CHARACTERISTICS
Table 2. Typical Characteristics Graphs
FIGURE
td(on) Turnon delay time vs Output voltage 23
td(off) Turnoff delay time vs Input voltage 24
trRise time vs Load current 25
tfFall time vs Load current 26
Supply current (enabled) vs Junction temperature 27
Supply current (disabled) vs Junction temperature 28
Supply current (enabled) vs Input voltage 29
Supply current (disabled) vs Input voltage 30
vs Input voltage 31
IOS Short-circuit current limit vs Junction temperature 32
vs Input voltage 33
vs Junction temperature 34
rDS(on) Static drain-source on-state resistance vs Input voltage 35
vs Junction temperature 36
VIInput voltage Undervoltage lockout 37
TURNON DELAY TIME TURNOFF DELAY TIME
vs vs
OUTPUT VOLTAGE INPUT VOLTAGE
Figure 20. Figure 21.
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3.25
2.75
2.5 0 0.5
− Fall Time − ms
3.5
1 1.5 2
3
IL − Load Current − A
tf
TA = 25°C
CL = 1 µF
5.5
50 0.5 1
− Rise Time − ms
6
6.5
1.5 2
IL − Load Current − A
tr
TA = 25°C
CL = 1 µF
55
45
35−50 −25 0 25 50
65
75
75 100 150
TJ − Junction Temperature − °C
Supply Current (Enabled) − Aµ
125
VI(IN) = 3.3 V
VI(IN) = 4 V
VI(IN) = 5 V
VI(IN) = 5.5 V
VI(IN) = 2.7 V
1
0
−1−50 −25 0 25 50
4
5
75 100 150
TJ − Junction Temperature − °C
Supply Current (Disabled) − Aµ
125
3
2
VI(IN) = 4 V
VI(IN) = 2.7 V
VI(IN) = 5 V
VI(IN) = 5.5 V
VI(IN) = 3.3 V
TPS2020-Q1, TPS2021-Q1
TPS2022-Q1, TPS2024-Q1
SGLS260G –SEPTEMBER 2004–REVISED JUNE 2010
www.ti.com
RISE TIME FALL TIME
vs vs
LOAD CURRENT LOAD CURRENT
Figure 22. Figure 23.
SUPPLY CURRENT (ENABLED) SUPPLY CURRENT (DISABLED)
vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 24. Figure 25.
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55
45
35 2.5 3 3.5 4 4.5
65
75
5 5.5 6
VI − Input Voltage − V
Supply Current (Enabled) − Aµ
TJ = 125°C
TJ = 85°C
TJ = 25°C
TJ = 0°C
TJ = −40°C
1
0
−1 2.5 3 3.5 4 4.5
4
5
5 5.5 6
VI − Input Voltage − V
Supply Current (Disabled) − Aµ
3
2TJ = 85°C
TJ = 0°C
TJ = −40°C
TJ = 125°C
TJ = 25°C
1.5
0.5
02 3 4
2.5
3.5
5 6
VI − Input Voltage − V
− Short-Circuit Current Limit − A
IOS
1
2
3
TPS2023
TPS2022
TPS2021
TPS2020
TPS2024
TA = 25°C
1.5
0.5
0
−50 −25 0
2.5
3.5
25 100
TJ − Junction Temperature − °C
− Short-Circuit Current Limit − A
IOS
1
2
3
TPS2023
TPS2022
TPS2021
TPS2020
TPS2024
50 75
TPS2020-Q1, TPS2021-Q1
TPS2022-Q1, TPS2024-Q1
www.ti.com
SGLS260G –SEPTEMBER 2004–REVISED JUNE 2010
SUPPLY CURRENT (ENABLED) SUPPLY CURRENT (DISABLED)
vs vs
INPUT VOLTAGE INPUT VOLTAGE
Figure 26. Figure 27.
SHORT-CIRCUIT CURRENT LIMIT SHORT-CIRCUIT CURRENT LIMIT
vs vs
INPUT VOLTAGE JUNCTION TEMPERATURE
Figure 28. Figure 29.
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS2020-Q1 TPS2021-Q1 TPS2022-Q1 TPS2024-Q1
20
−50 −25 0
40
60
25 150
TJ − Junction Temperature − °C
30
50
VI = 2.7 V
50 75 100 125
VI = 3.3 V
VI = 5.5 V
IO = 0.18 A
Ω
rDS(on) − Static Drain-Source On-State Resistance − m
20
2.5 3 3.5
40
60
4 6
VI − Input Voltage − V
30
50
4.5 5
Ω
rDS(on) − Static Drain-Source On-State Resistance − m
5.5
TJ = 25°C
TJ = 125°C
TJ = −40°C
IO = 0.18 A
20 3 3.5
40
60
4 6
VI − Input Voltage − V
30
50
4.5 5 5.5
TJ = 25°C
TJ = 125°C
IO = 1.8 A
TJ = −40°C
Ω
rDS(on) − Static Drain-Source On-State Resistance − m
20
−50 −25 0
40
60
25 150
TJ − Junction Temperature − °C
30
50 VI = 3.3 V
50 75 100 125
VI = 4 V
VI = 5.5 V
IO = 1.8 A
Ω
rDS(on) − Static Drain-Source On-State Resistance − m
TPS2020-Q1, TPS2021-Q1
TPS2022-Q1, TPS2024-Q1
SGLS260G –SEPTEMBER 2004–REVISED JUNE 2010
www.ti.com
STATIC DRAIN-SOURCE ON-STATE RESISTANCE STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs vs
INPUT VOLTAGE JUNCTION TEMPERATURE
Figure 30. Figure 31.
STATIC DRAIN-SOURCE ON-STATE RESISTANCE STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs vs
INPUT VOLTAGE JUNCTION TEMPERATURE
Figure 32. Figure 33.
16 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS2020-Q1 TPS2021-Q1 TPS2022-Q1 TPS2024-Q1
2−50 0 50 100
2.4
2.5
150
TJ − Temperature − °C
2.3
2.2
Start Threshold
Stop Threshold
2.1
VI− Input Voltage − V
TPS2020-Q1, TPS2021-Q1
TPS2022-Q1, TPS2024-Q1
www.ti.com
SGLS260G –SEPTEMBER 2004–REVISED JUNE 2010
UNDERVOLTAGE LOCKOUT
Figure 34.
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TPS2020-Q1 TPS2021-Q1 TPS2022-Q1 TPS2024-Q1
IN
OC
EN GND
0.1 µF
2,3
5
4
6,7,8
0.1 µF22 µF
Load
1
OUT
TPS2024
Power Supply
2.7 V to 5.5 V 10 kΩ
TPS2020-Q1, TPS2021-Q1
TPS2022-Q1, TPS2024-Q1
SGLS260G –SEPTEMBER 2004–REVISED JUNE 2010
www.ti.com
APPLICATION INFORMATION
Figure 35. Typical Application
Power Supply Considerations
A 0.01-mF to 0.1-mF ceramic bypass capacitor between IN and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output and input pins is recommended when the output load is
heavy. This precaution reduces power supply transients that may cause ringing on the input. Additionally,
bypassing the output with a 0.01-mF to 0.1-mF ceramic capacitor improves the immunity of the device to
short-circuit transients.
Overcurrent
A sense FET checks for overcurrent conditions. Unlike current-sense resistors, sense FETs do not increase the
series resistance of the current path. When an overcurrent condition is detected, the device maintains a constant
output current and reduces the output voltage accordingly. Complete shutdown occurs only if the fault is present
long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before VI(IN) has been applied, see Figure 6. The TPS202x senses the short and
immediately switches into a constant-current output.
In the second condition, the excessive load occurs while the device is enabled. At the instant the excessive load
occurs, very high currents may flow for a short time before the current-limit circuit can react (see Figures 13–22).
After the current-limit circuit has tripped (reached the overcurrent trip threshhold) the device switches into
constant-current mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figures 7–11). The TPS202x is capable of delivering current up to the current-limit threshold
without damaging the device. Once the threshold has been reached, the device switches into its constant-current
mode.
OC Response
The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output remains asserted until the overcurrent or overtemperature condition is removed.
Connecting a heavy capacitive load to an enabled device can cause momentary false overcurrent reporting from
the inrush current flowing through the device, charging the downstream capacitor. An RC filter can be connected
to the OC pin to reduce false overcurrent reporting. Using low-ESR electrolytic capacitors on the output lowers
the inrush current flow through the device during hot-plug events by providing a low impedance energy source,
thereby reducing erroneous overcurrent reporting.
18 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS2020-Q1 TPS2021-Q1 TPS2022-Q1 TPS2024-Q1
GND
IN
IN
EN
OUT
OC
OUT
OUT
TPS202x
GND
IN
IN
EN
OUT
OC
OUT
OUT
TPS202x
Rpullup
V+
Rfilter
Rpullup
Cfilter
V+
TPS2020-Q1, TPS2021-Q1
TPS2022-Q1, TPS2024-Q1
www.ti.com
SGLS260G –SEPTEMBER 2004–REVISED JUNE 2010
Figure 36. Typical Circuit for OC Pin and RC Filter for Damping Inrush OC Responses
Power Dissipation and Junction Temperature
The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass
large currents. The thermal resistances of these packages are high compared to those of power packages; it is
good design practice to check power dissipation and junction temperature. The first step is to find rDS(on) at the
input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of
interest and read rDS(on) from Figures 33–36. Next, calculate the power dissipation using:
PD= rDS(on) × I2(1)
Finally, calculate the junction temperature:
TJ= PD× RqJA + TA(2)
where:
TA= Ambient temperature °C
RqJA = Thermal resistance—SOIC = 172°C/W, PDIP = 106°C/W
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get an acceptable answer.
Thermal Protection
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The faults force the TPS202x into constant current mode, which causes the voltage
across the high-side switch to increase; under short-circuit conditions, the voltage across the switch is equal to
the input voltage. The increased dissipation causes the junction temperature to rise to high levels. The protection
circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the thermal sense
circuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The switch continues
to cycle in this manner until the load fault or input power is removed.
Undervoltage Lockout (UVLO)
An undervoltage lockout ensures that the power switch is in the off state at powerup. Whenever the input voltage
falls below approximately 2 V, the power switch is quickly turned off. This facilitates the design of hot-insertion
systems where it is not possible to turn off the power switch before input power is removed. The UVLO also
keeps the switch from being turned on until the power supply has reached at least 2 V, even if the switch is
enabled. Upon reinsertion, the power switch is turned on, with a controlled rise time to reduce EMI and voltage
overshoots.
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): TPS2020-Q1 TPS2021-Q1 TPS2022-Q1 TPS2024-Q1
Power
Supply Block of
Circuitry
TPS2024
GND
IN
IN
EN
OUT
OUT
OUT
OC
0.1 µF
1000 µF
Optimum
2.7 V to 5.5 V
PC Board
Overcurrent Response
TPS2020-Q1, TPS2021-Q1
TPS2022-Q1, TPS2024-Q1
SGLS260G –SEPTEMBER 2004–REVISED JUNE 2010
www.ti.com
Generic Hot-Plug Applications
In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.
These are considered hot-plug applications (see Figure 37). Such implementations require the control of current
surges seen by the main power supply and the card being inserted. The most effective way to control these
surges is to limit and slowly ramp the current and voltage being applied to the card, similar to the way in which a
power supply normally turns on. Because of the controlled rise times and fall times of the TPS202x series, these
devices can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO
feature of the TPS202x also ensures the switch is off after the card has been removed, and the switch remains
off during the next insertion. The UVLO feature ensures a soft start with a controlled rise time for every insertion
of the card or module.
Figure 37. Typical Hot-Plug Implementation
By placing the TPS202x between the VCC input and the rest of the circuitry, the input power reaches this device
first after insertion. The typical rise time of the switch is approximately 9 ms, providing a slow voltage ramp at the
output of the device. This implementation controls system surge currents and provides a hot-plugging
mechanism for any device.
20 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS2020-Q1 TPS2021-Q1 TPS2022-Q1 TPS2024-Q1
PACKAGE OPTION ADDENDUM
www.ti.com 20-Aug-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS2020IDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS2021IDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS2022DRG4Q1 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS2022DRQ1 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TPS2024IDRG4Q1 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TPS2024IDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 20-Aug-2010
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS2020-Q1, TPS2021-Q1, TPS2022-Q1, TPS2024-Q1 :
•Catalog: TPS2020, TPS2021, TPS2022, TPS2024
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2020IDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Jul-2010
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2020IDRQ1 SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Jul-2010
Pack Materials-Page 2
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