1OCTOBER 2008
DSC 2940/13
©2008 Integrated Device Technology, Inc.
I/O
Control
Address
Decoder MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
I/O
Control
R/W
L
CE
L
OE
L
BUSY
L
A
14L
A
0L
2940 drw 01
I/O
0L
-I/O
7L
CE
L
OE
L
R/W
L
SEM
L
INT
L
M/S
BUSY
R
I/O
0R
-I/O
7R
A
14R
A
0R
SEM
R
INT
R
CE
R
OE
R
(2)
(1,2) (1,2)
(2)
R/W
R
CE
R
OE
R
R/W
R
15
15
HIGH-SPEED
32K x 8 DUAL-PORT
STATIC RAM
Features
◆True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
◆High-speed access
– Military: 25/35/55ns (max.)
– Industrial: 20/25/35/55ns (max.)
– Commercial: 15/20/25/35/55ns (max.)
◆Low-power operation
– IDT7007S
Active: 850mW (typ.)
Standby: 5mW (typ.)
– IDT7007L
Active: 850mW (typ.)
Standby: 1mW (typ.)
◆IDT7007 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
◆M/S = H for BUSY output flag on Master,
M/S = L for BUSY input on Slave
◆Interrupt Flag
◆On-chip port arbitration logic
◆Full on-chip hardware support of semaphore signaling
between ports
◆Fully asynchronous operation from either port
◆TTL-compatible, single 5V (±10%) power supply
◆Available in 68-pin PGA and PLCC and a 80-pin TQFP
◆Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆Green parts available, see ordering information
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
Functional Block Diagram
IDT7007S/L
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
2
– IDT7007S
Description
The IDT7007 is a high-speed 32K x 8 Dual-Port Static RAM. The
IDT7007 is designed to be used as a stand-alone 256K-bit Dual-Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more
word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach
in 16-bit or wider memory system applications results in full-speed, error-
free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by CE permits the on-chip circuitry of each port to enter
a very LOW standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 850mW of power.
The IDT7007 is packaged in a 68-pin pin PGA, a 68-pin PLCC,
and an 80-pin thin quad flatpack, TQFP. Military grade product is
manufactured in compliance with the latest revision of MIL-PRF-38535
QML, Class B, making it ideally suited to military temperature applications
demanding the highest level of performance and reliability.
Pin Configurations(1,2,3)
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately .95 in x .95 in x .17 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.
2940 drw 02
12
13
14
15
16
17
18
INDEX
19
20
21
22
98765432168676665
27 28 29 30 31 32 33 34 35 36 37 38 39
V
CC
V
CC
I/O
1R
I/O
2R
I/O
3R
I/O
4R
INT
L
GND
A
4L
A
3L
A
2L
A
1L
A
0L
A
3R
A
0R
A
1R
A
2R
I/O
2L
A
5L
R/
W
L
11
10
M/S
23
24
25
26 40 41 42 43
58
57
56
55
54
53
52
51
50
49
48
59
60
47
46
45
44
64 63 62 61
I/O
3L
GND
I/O
0R
V
CC
A
4R
BUSY
L
GND
BUSY
R
INT
R
A
12R
I/O
7R
N/C
GND
OE
R
R/
W
R
SEM
R
CE
R
OE
L
CE
L
N/C
I/O
0L
I/O
1L
IDT7007J
J68-1
(4)
68-Pin PLCC
Top View
(5)
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
5R
I/O
6R
A
12L
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
A
13R
A
13L
A
14L
A
14R
SEM
L
11/06/01
3
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.
I
NDEX
I/O2L
VCC
GND
GND
A4R
BUSYL
BUSYR
GND
M/S
OE
L
I/O
1L
R/W
L
CE
L
SEM
L
V
CC
OE
R
CE
R
R/W
R
SEM
R
A
12R
GND
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O
7R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
A3R
A2R
A1R
A0R
A0L
A1L
A2L
A3L
A4L
A
6L
A
7L
A
8L
A
9L
A
10L
A
11L
A
12L
I/O
0L
2940 drw 03
A
13R
A
13L
7007PF
PN80-1
(4)
80-Pin TQFP
Top View
(5)
N/C
N/C
A
14L
N/C
N/C
N/C
N/C
A
14R
N/C
N/C
A5L
N/C
INTL
INTR
N/C
N/C
N/C
I/O6R
N/C
N/C
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
,
11/06/01
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
4
NOTES:
1. All Vcc pins must be connected to power supply
2. All GND pins must be connected to ground.
3. Package body is approximately 1.8 in x 1.8 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.
Pin Names
Pin Configurations(1,2,3) (con't.)
2940 drw 04
51 50 48 46 44 42 40 38 36
53
55
57
59
61
63
65
67
68
66
1357911 13 15
20
22
24
26
28
30
32
35
IDT7007G
G68-1
(4)
68-Pin PGA
Top View
(5)
ABCDEFGHJ
K
L
47 45 43 41 34
21
23
25
27
29
31
33
246810121416
18 19
17
56
58
60
62
64
11
10
09
08
07
06
05
04
03
02
01
52
54
49 39 37
A
5L
INT
L
SEM
L
CE
L
V
CC
OE
L
R/W
L
I/O
0L
N/C
GND GND
I/O
0R
V
CC
N/C
OE
R
R/W
R
SEM
R
CE
R
GND BUSY
R
BUSY
L
M/SINT
R
GND
A
1R
I
NDEX
A
4L
A
2L
A
0L
A
3R
A
2R
A
4R
A
5R
A
7R
A
6R
A
9R
A
8R
A
11R
A
10R
A
12R
A
0R
A
7L
A
6L
A
3L
A
1L
A
9L
A
8L
A
11L
A
10L
A
12L
V
CC
I/O
2R
I/O
3R
I/O
5R
I/O
6R
I/O
1R
I/O
4R
I/O
7R
I/O
1L
I/O
2L
I/O
4L
I/O
7L
I/O
3L
I/O
5L
I/O
6L
A
13R
A
13L
A
14R
A
14L
,
11/06/01
Left Port Right Port Names
CE
L
CE
R
Chip Enables
R/W
L
R/W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
- A
14L
A
0R
- A
14R
Address
I/O
0L
- I/ O
7L
I/O
0R
- I/O
7R
Data Inp ut/ Outp ut
SEM
L
SEM
R
Semaphore Enable
INT
L
INT
R
Inte rrupt Flag
BUSY
L
BUSY
R
Busy Flag
M/SMaster or Slave Select
V
CC
Power
GND Ground
2940 tbl 01
5
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Truth Table II: Semaphore Read/Write Control(1)
Absolute Maximum Ratings(1)
Recommended DC Operating
Conditions
Maximum Operating Temperature
and Supply Voltage(1)
Capacitance (TA = +25°C, f = 1.0Mhz)
NOTE:
1. A0L — A14L ≠ A0R — A14R
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from all I/O's. These eight semaphores are addressed by A0 - A2.
NOTES:
1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sec-tions of this specification is not implied. Exposure
to absolute maxi-mum rating conditions for extended periods may affect
reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
NOTES:
1. This parameter is determined by device characterization but is not production
tested. TQFP package only.
2 . 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
Inputs
(1)
Outputs
Mode
CE R/WOE SEM I/O
0-7
H X X H High-Z De s e le c te d : Po we r-Do wn
LLXHDATA
IN
Write to Memory
LHLHDATA
OUT
Rea d M e mo ry
X X H X High-Z Outputs Disabled
2940 tbl 02
Inputs Outputs
Mode
CE R/WOE SEM I/O
0-7
HHLLDATA
OUT
Read Semap hore Flag Data Out (I/O
0
-I/O
7
)
H
↑
XLDATA
IN
Write I/O
0
into Semaphore Flag
LXXL
______
No t Allowed
2940 tbl 03
Symbol Rating Commercial
& Industrial Military Unit
V
TERM(2)
Te rm inal Vo l tag e
with Respect
to GND
-0.5 to +7.0 -0.5 to +7.0 V
T
BIAS
Temperature
Under Bias -55 to +125 -65 to +135
o
C
T
STG
Storage
Temperature -65 to +150 -65 to +150
o
C
I
OUT
DC Outp ut
Current 50 50 mA
2940 tbl 04
Symbol Parameter
(1)
Conditions
(2)
Max. Unit
C
IN
Inp ut Cap ac itanc e V
IN
= 3dV 9 pF
C
OUT
Output Cap acitanc e V
OUT
= 3dV 10 pF
2940 tbl 07
Grade Ambient
Temperature GND Vcc
Military -55
O
C to+125
O
C0V 5.0V
+
10%
Commercial 0
O
C to +70
O
C0V 5.0V
+
10%
Industrial -40
O
C to +85
O
C0V 5.0V
+
10%
2940 tbl 05
Symbol Parameter Min. Typ. Max. Unit
V
CC
Supply Voltage 4.5 5.0 5.5 V
GND Ground 0 0 0 V
V
IH
Input High Voltage 2.2
____
6.0
(2)
V
V
IL
Input Low Voltage -0.5
(1)
____
0.8 V
2940 tbl 06
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
6
DC Electrical Characteristics Over the Operating
T emperature and Supply V oltage Range(1) (VCC = 5.0V ± 10%)
DC Electrical Characteristics Over the Operating
T emperature and Supply V oltage Range (VCC = 5.0V ± 10%)
NOTES:
1. 'X' in part numbers indicates power rating (S or L)
2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input
levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
NOTE:
1. At Vcc < 2.0V, input leakages are undefined.
Symbol Parameter Test Conditions
7007S 7007L
UnitMin. Max. Min. Max.
|I
LI
| Input Leak age Current
(1)
V
CC
= 5.5V, V
IN
= 0V to V
CC
___
10
___
5µA
|I
LO
| Outp ut Le akag e Curre nt CE = V
IH
, V
OUT
= 0V to V
CC
___
10
___
5µA
V
OL
Outp ut Lo w Vo ltage I
OL
= 4mA
___
0.4
___
0.4 V
V
OH
Output High Voltage I
OH
= -4mA 2.4
___
2.4
___
V
2940 tbl 08
S ymb ol P aram eter Test Co ndition V ersi on
7007X15
Com 'l Onl y 7007X20
Com'l & Ind 7007X25
Com'l, Ind
& Military
UnitTyp.
(2)
Max. Typ.
(2)
Max. Typ.
(2)
Max.
I
CC
Dy nami c Ope rating
Current
(Both Ports Active)
CE = V
IL
, Outputs Disabled
SEM = V
IH
f = f
MAX
(3)
COM'L S
L190
190 325
285 180
180 315
275 170
170 305
265 mA
MIL &
IND S
L
___
___
___
___
___
180
___
315 170
170 345
305
I
SB1
Standby Current
(Bo th Po rts - TTL Leve l
Inputs)
CE
L
= CE
R
= V
IH
SEM
R
= SEM
L
= V
IH
f = f
MAX
(3)
COM'L S
L35
35 85
60 30
30 85
60 25
25 85
60 mA
MIL &
IND S
L
___
___
___
___
___
30
___
80 25
25 100
80
I
SB2
Standby Current
(One Port - TTL Le ve l
Inputs)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(3)
SEM
R
= SEM
L
= V
IH
COM'L S
L125
125 220
190 115
115 210
180 105
105 200
170 mA
MIL &
IND S
L
___
___
___
___
___
115
___
210 105
105 230
200
I
SB3
Full Standb y Current
(Both Ports - All CMOS
Le ve l Inp uts )
Both Ports CE
L
and
CE
R
> V
CC
- 0 .2V
V
IN
> V
CC
- 0.2V or
VIN < 0.2V, f = 0
(4)
SEM
R
= SEM
L
> V
CC
- 0.2V
COM'L S
L1.0
0.2 15
51.0
0.2 15
51.0
0.2 15
5mA
MIL &
IND S
L
___
___
___
___
___
0.2
___
10 1.0
0.2 30
10
I
SB4
Full Standb y Current
(One Po rt - All CMOS
Le ve l Inp uts )
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
SEM
R
= SEM
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V o r V
IN
< 0.2V
Active Port Outputs Disabled
f = f
MAX
(3)
COM'L S
L120
120 190
160 110
110 185
160 100
100 175
160 mA
MIL &
IND S
L
___
___
___
___
___
110
___
185 100
100 200
175
2940 t bl 0 9
7
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (con't.) (VCC = 5.0V ± 10%)
NOTES:
1. 'X' in part numbers indicates power rating (S or L)
2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using
“AC Test Conditions” of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
Symbol Parameter Test Condition Version
7007X35
Com'l, Ind
& Military
7007X55
Com'l, Ind
& Military
UnitTyp.
(2)
Max. Typ.
(2)
Max.
I
CC
Dynamic Operating Current
(Both Ports Ac tive) CE = V
IL
, Outputs Disabled
SEM = V
IH
f = f
MAX
(3)
COM'L S
L160
160 295
255 150
150 270
230 mA
MIL &
IND S
L160
160 335
295 150
150 310
270
I
SB1
Standb y Current
(Both Po rts - TTL Le ve l
Inputs)
CE
L
= CE
R
= V
IH
SEM
R
= SEM
L
= V
IH
f = f
MAX
(3)
COM'L S
L20
20 85
60 20
20 85
60 mA
MIL &
IND S
L20
20 100
80 13
13 100
80
I
SB2
Standb y Current
(One Po rt - TTL Leve l Inputs) CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(3)
SEM
R
= SEM
L
= V
IH
COM'L S
L95
95 185
155 85
85 165
135 mA
MIL &
IND S
L95
95 215
185 85
85 195
165
I
SB3
Full Stand by Current (Bo th
Ports - All CMOS Le ve l
Inputs)
Bo th Po rts CE
L
and
CE
R
> V
CC
- 0. 2V
V
IN
> V
CC
- 0. 2V or
VIN < 0.2V, f = 0
(4)
SEM
R
= SEM
L
> V
CC
- 0. 2V
COM'L S
L1.0
0.2 15
51.0
0.2 15
5mA
MIL &
IND S
L1.0
0.2 30
10 1.0
0.2 30
10
I
SB4
Full Standby Current
(One Port - All CMOS Le ve l
Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0. 2V
(5)
SEM
R
= SEM
L
> V
CC
- 0. 2V
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled
f = f
MAX
(3)
COM'L S
L90
90 160
135 80
80 135
110 mA
MIL &
IND S
L90
90 190
165 80
80 165
140
2940 t bl 1 0
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
8
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
AC Test Conditions
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, t OW)
* Including scope and jig.
Input Pulse Le vels
In p ut Ri se / F al l Time s
Inp ut Ti ming Re fe re nc e Le ve ls
Outp ut Re fe re nce Lev el s
Outp ut Load
GND to 3.0V
5ns Max.
1.5V
1.5V
Fig ures 1 and 2
2940 tbl 11
Figure 1. AC Output Test Load
2940 drw 06
893Ω
30pF
347Ω
5V
DATA
OUT
BUSY
INT
893Ω
5pF*
347Ω
5V
DATA
OUT
2940 drw 05
.
7007X15
Com ' l Onl y 7007X20
Com'l & Ind 7007X25
Com'l, Ind
& Military
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
RE AD CYCLE
t
RC
Re ad Cy cle Time 15
____
20
____
25
____
ns
t
AA
Add ress Access Time
____
15
____
20
____
25 ns
t
ACE
Chip E nable Acc es s Time
(3)
____
15
____
20
____
25 ns
t
AOE
Output Enab le Ac cess Time
____
10
____
12
____
13 ns
t
OH
Output Hold from Ad d ress Chang e 3
____
3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,2)
3
____
3
____
3
____
ns
t
HZ
Output High-Z Time
(1,2)
____
10
____
12
____
15 ns
t
PU
Chip Enable to Power Up Time
(2)
0
____
0
____
0
____
ns
t
PD
Ch ip Disa bl e to Power Down Time
(2)
____
15
____
20
____
25 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)10
____
10
____
12
____
ns
t
SAA
Semaphore Addre ss Acces s Time
____
15
____
20
____
25 ns
2 940 tb l 12a
7007X35
Co m' l, In d
& Military
7007X55
Com'l , Ind
& Military
UnitSymbol Parameter Min.Max.Min.Max.
RE AD CYCLE
t
RC
Re ad Cycl e Tim e 35
____
55
____
ns
t
AA
Address Access Time
____
35
____
55 ns
t
ACE
Chip Enable Access Time
(3)
____
35
____
55 ns
t
AOE
Outp ut Enable A cc es s Tim e
____
20
____
30 ns
t
OH
Output Hold from Address Change 3
____
3
____
ns
t
LZ
Outp ut Lo w-Z Ti me
(1,2)
3
____
3
____
ns
t
HZ
Outp ut Hi g h-Z Time
(1,2)
____
15
____
25 ns
t
PU
Chi p Enable to P o we r Up Ti me
(2)
0
____
0
____
ns
t
PD
Ch ip Disab l e to P o we r Down Tim e
(2)
____
35
____
50 ns
t
SOP
Semapho re Flag Update Pulse (OE or SEM)15
____
15
____
ns
t
SAA
Semaphore Address Access Time
____
35
____
55 ns
2940 tbl 12b
9
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Timing of Power-Up Power-Down
Waveform of Read Cycles(5)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
t
RC
R/W
CE
ADDR
t
AA
OE
2940 drw 07
(4)
t
ACE
(4)
t
AOE
(4)
(1)
t
LZ
t
OH
(2)
t
HZ
(3,4)
t
BDD
DATA
OUT
BUSY
OUT
VALID DATA
(4)
CE
2940 drw 08
t
PU
I
CC
I
SB
t
PD
,
50% 50%
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
10
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4 . The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part numbers indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(5)
Symbol Parameter
7007X15
Com'l Only 7007X20
Com 'l & I nd 7007X25
Com'l, Ind
& Military
UnitMin. Max. Min. Max. Min. Max.
WRITE CYCL E
t
WC
Write Cy cl e Tim e 15
____
20
____
25
____
ns
t
EW
Chip Enable to End-of-Write
(3)
12
____
15
____
20
____
ns
t
AW
Address Valid to End-of-Write 12
____
15
____
20
____
ns
t
AS
Address Set-up Time
(3)
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 12
____
15
____
20
____
ns
t
WR
Write Re cove ry Time 0
____
0
____
0
____
ns
t
DW
Data Val id to End -o f-Wri te 10
____
15
____
15
____
ns
t
HZ
Outp ut Hi g h-Z Ti me
(1,2)
____
10
____
12
____
15 ns
t
DH
Data Ho ld Tim e
(4)
0
____
0
____
0
____
ns
t
WZ
Write Enable to Outp ut i n High-Z
(1,2)
____
10
____
12
____
15 ns
t
OW
Ou tp ut A c ti v e fr o m En d - o f-Wr ite
(1,2,4)
0
____
0
____
0
____
ns
t
SWRD
SEM Flag Write to Read Time 5
____
5
____
5
____
ns
t
SPS
SEM Flag Contention Window 5
____
5
____
5
____
ns
2940 tbl 13a
Symbol Parameter
7007X35
Com'l, Ind
& Military
7007X55
Com'l, Ind
& Military
UnitMin. Max. Min. Max.
WR I T E C YCLE
t
WC
Write Cycle Time 35
____
55
____
ns
t
EW
Chip Enab le to End-of-Write
(3)
30
____
45
____
ns
t
AW
Address Valid to End-of-Write 30
____
45
____
ns
t
AS
Add ress Set-up Time
(3)
0
____
0
____
ns
t
WP
Write Pulse Width 25
____
40
____
ns
t
WR
Wri te Re c o v e ry Tim e 0
____
0
____
ns
t
DW
Data Valid to End -o f-W ri te 15
____
30
____
ns
t
HZ
Outp ut High-Z Time
(1,2)
____
12
____
25 ns
t
DH
Data Ho ld Ti me
(4)
0
____
0
____
ns
t
WZ
Wri te E nable to Output i n Hi gh-Z
(1,2)
____
12
____
25 ns
t
OW
Outp ut A c ti ve fro m End -o f-Write
(1,2,4)
0
____
0
____
ns
t
SWRD
SEM Flag Write to Re ad Tim e 5
____
5
____
ns
t
SPS
SEM Flag Co nte ntio n Windo w 5
____
5
____
ns
2940 tbl 13b
11
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Timing Wa v eform of Write Cyc le No. 1, R/W Controlled Timing(1,5,8)
Timing Wavef orm of Write Cyc le No . 2, CE Controlled Timing(1,5)
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7 . This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure
2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
R/W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
CE or SEM
(6)
(4) (4)
(3)
2940 drw 09
(7)
(7)
(9)
2940 drw 10
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/W
t
AW
t
EW
(3)
(2)
(6)
CE or SEM
(9)
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
12
Timing Wav eform of Semaphore Read after Write Timing, Either Side(1)
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/WA or SEMA going HIGH to R/WB or SEMB going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
Timing Waveform of Semaphore Write Contention(1,3,4)
NOTE:
1. CE = VIH for the duration of the above timing (both write and read cycle).
SEM
2940 drw 11
t
AW
t
EW
D
ATA
0
VALID ADDRESS
t
SAA
R/W
t
WR
t
OH
t
ACE
VALID ADDRESS
DATA
IN
VALID DATA
OUT
VALID
(2)
t
DW
t
WP
t
DH
t
AS
t
SWRD
t
AOE
t
SOP
Read Cycle
Write Cycle
A
0
-A
2
OE
t
SOP
SEM
"A"
2940 drw 12
t
SPS
MATCH
R/W
"A"
MATCH
A
0"A"
-A
2"A"
SIDE "A"
(2)
SEM
"B"
R/W
"B"
A
0"B"
-A
2"B"
SIDE "B"
(2)
,
13
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
Symbol Parameter
7007X15
Com'l Only 7007X20
Co m'l & I nd 7007X25
Com'l, Ind
& Military
UnitMin. Max. Min. Max. Min. Max.
BUSY TIMING (M/S=V
IH
)
t
BAA
BUSY Acce ss Time from Address Match
____
15
____
20
____
20 ns
t
BDA
BUSY Disable Time from Address Not Matched
____
15
____
20
____
20 ns
t
BAC
BUSY Access Time from Chip Enab le Low
____
15
____
20
____
20 ns
t
BDC
BUSY Access Time from Chip Enab le High
____
15
____
17
____
17 ns
t
APS
Arbitration Priority Se t-up Time
(2)
5
____
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3)
____
18
____
30
____
30 ns
t
WH
Write Ho ld Afte r BUSY
(5)
12
____
15
____
17
____
ns
BUSY TIMING (M/S=V
IL
)
t
WB
BUSY Inp ut to Write
(4)
0
____
0
____
0
____
ns
t
WH
Write Ho ld Afte r BUSY
(5)
12
____
15
____
17
____
ns
PORT-TO-PORT DELAY TIMI NG
t
WDD
Wr ite P ul s e to Data De lay
(1)
____
30
____
45
____
50 ns
t
DDD
Write Data Valid to Re ad Data Delay
(1)
____
25
____
30
____
35 ns
2 940 tb l 14 a
Symbol Parameter
7007X35
Com'l, Ind
& Military
7007X55
Com'l, Ind
& Military
UnitMin. Max. Min. Max.
BUSY TIMING (M/S=V
IH
)
t
BAA
BUSY Acce ss Time from Address Match
____
20
____
45 ns
t
BDA
BUSY Disable Time from Address Not Matched
____
20
____
40 ns
t
BAC
BUSY Access Time from Chip Enab le Low
____
20
____
40 ns
t
BDC
BUSY Access Time from Chip Enab le High
____
20
____
35 ns
t
APS
Arbitration Priority Se t-up Time
(2)
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3)
____
35
____
40 ns
t
WH
Write Ho ld Afte r BUSY
(5)
25
____
25
____
ns
BUSY TIMING (M/S=V
IL
)
t
WB
BUSY Inp ut to Write
(4)
0
____
0
____
ns
t
WH
Write Ho ld Afte r BUSY
(5)
25
____
25
____
ns
PORT-TO-PORT DELAY TIMI NG
t
WDD
Wr ite P ul s e to Data De lay
(1)
____
60
____
80 ns
t
DDD
Write Data Valid to Re ad Data Delay
(1)
____
45
____
65 ns
2940 tbl 14b
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
14
Timing W av eform of Write with Port-to-Port R ead and BUSY(2,5)
(M/S = VIH)(4)
Timing Wa v ef orm of W rite with BUSY (M/S = VIL)
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
2940 drw 13
t
DW
t
APS
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD
(3)
t
WDD
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. If M/S = VIL (SLAVE), then BUSY is an input (BUSY"A" = VIH and BUSY"B" = "don't care", for this example).
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
2940 drw 14
R/W
"A"
BUSY
"B"
t
WP
t
WB
R/W
"B"
t
WH
(1)
(2)
,
15
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1,2)
2940 drw 15
ADDR
"A"
and
"B"
ADDRESSES MATCH
CE
"A"
CE
"B"
BUSY
"B"
t
APS
t
BAC
t
BDC
(2)
2940 drw 16
ADDR
"A"
ADDRESS "N"
ADDR
"B"
BUSY
"B"
t
APS
t
BAA
t
BDA
(2)
MATCHING ADDRESS "N"
7007X15
Com'l Only 7007X20
Com'l & Ind 7007X25
Com'l, Ind
& Mil itary
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
INTERRUPT T IMING
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WR
Wri te Rec o ve ry Time 0
____
0
____
0
____
ns
t
INS
In te rr upt S et Ti m e
____
15
____
20
____
20 ns
t
INR
Inte rrup t Re s et Time
____
15
____
20
____
20 ns
2940 tbl 15 a
7007X35
Com 'l , I nd
& Mi l itary
7007X55
Com'l, Ind
& Military
UnitSymbol Parameter Min. Max. Min. Max.
INTERRUPT T IMING
t
AS
Address Set-up Time 0
____
0
____
ns
t
WR
Wri te Rec o ve ry Time 0
____
0
____
ns
t
INS
In te rr upt S et Ti m e
____
25
____
40 ns
t
INR
Inte rrup t Re s et Time
____
25
____
40 ns
2940 tbl 15b
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
16
Truth T able III — Interrupt Flag(1)
Wa v eform of Interrupt Timing(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2 . See Interrupt Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
2940 drw 17
ADDR
"A"
INTERRUPT SET ADDRESS
CE
"A"
R/W
"A"
t
AS
t
WC
t
WR
(3) (4)
t
INS
(3)
INT
"B"
(2)
2940 drw 18
ADDR
"B"
INTERRUPT CLEAR ADDRESS
CE
"B"
OE
"B"
t
AS
t
RC
(3)
t
INR
(3)
INT
"B"
(2)
Left Port Right Port
FunctionR/W
L
CE
L
OE
L
A
14L
-A
0L
INT
L
R/W
R
CE
R
OE
R
A
14R
-A
0R
INT
R
LLX7FFFXXXX X L
(2)
Set Right INT
R
Flag
XXX X XXLL7FFFH
(3)
Re s e t Rig h t INT
R
Flag
XXX XL
(3)
L L X 7FFE X S et Left INT
L
Flag
XLL7FFEH
(2)
XXX X XReset Left INT
L
Flag
2940 tbl 16
17
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Truth Table IV — Address BUSY
Arbitration
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7007 are
push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2 . "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7007.
2. There are eight semaphore flags written to via I/O5(I/O0 - I/O7) and read from all I/O0. These eight semaphores are addressed by A0 - A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Functional Description
The IDT7007 provides two ports with separate control, address and
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT7007 has an automatic power down feature controlled
by CE. The CE controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected (CE HIGH).
When a port is enabled, access to the entire memory array is permitted.
INTERRUPTS
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 7FFE
(HEX), where a write is defined as CE = R/W = VIL per the Truth Table.
The left port clears the interrupt through access of address location 7FFE
when CER = OER = VIL, R/W is a "don't care". Likewise, the right port
interrupt flag (INTR) is asserted when the left port writes to memory location
7FFF (HEX) and to clear the interrupt flag (INTR), the right port must read
the memory location 7FFF. The message (8 bits) at 7FFE or 7FFF is user-
defined since it is an addressable SRAM location. If the interrupt function
is not used, address locations 7FFE and 7FFF are not used as mail boxes,
but as part of the random access memory. Refer to Table III for the interrupt
operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of
the two accesses to proceed and signals the other side that the RAM is
Inputs Outputs
Function
CE
L
CE
R
A
OL
-A
14L
A
OR
-A
14R
BUSY
L
(1)
BUSY
R
(1)
XX NO MATCH H H Normal
H X MATCH H H Normal
X H MATCH H H Normal
L L MATCH (2) (2) Write Inhibi t
(3)
2940 tbl 17
Functions D
0
- D
7
Left D
0
- D
7
Right Status
No Action 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Rig ht Port Write s "0" to Semaphore 0 1 No chang e . Right s ide has no write acc e ss to se map hore
Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token
Left Po rt Write s " 0" to Se map ho re 1 0 No chang e . Le ft port has no write ac ce ss to se map ho re
Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token
Right Port Writes "1" to Semaphore 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
2940 tbl 18
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
18
“busy”. The BUSY pin can then be used to stall the access until the
operation on the other side is completed. If a write operation has been
attempted from the side that receives a BUSY indication, the write signal
is gated internally to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by placing the part in slave
mode with the M/S pin. Once in slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations
can be prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT 7007 RAM in master mode, are push-
pull type outputs and do not require pull up resistors to operate. If these
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
Semaphores
The IDT7007 is an extremely fast Dual-Port 16K x 8 CMOS Static RAM
with an additional 8 address locations dedicated to binary semaphore flags.
These flags allow either processor on the left or right side of the Dual-Port
RAM to claim a privilege over the other processor for functions defined by
the system designer’s software. As an example, the semaphore can be
used by one processor to inhibit the other from accessing a portion of the
Dual-Port RAM or any other shared resource.
The Dual-Port RAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
or written to, at the same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port RAM. These devices have
an automatic power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM pins control
on-chip power down circuitry that permits the respective port to go into
standby mode when not selected. This is the condition which is shown in
Truth Table I where CE and SEM are both HIGH.
Systems which can best use the IDT7007 contain multiple proces-
sors or controllers and are typically very high-speed systems which
are software controlled or software intensive. These systems can
benefit from a performance increase offered by the IDT7007 hardware
semaphores, which provide a lockout mechanism without requiring
complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in varying
configurations. The IDT7007 does not use its semaphore flags to control
any resources through hardware, thus allowing the system designer total
flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred in
either processor. This can prove to be a major advantage in very high-
speed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent
of the Dual-Port RAM. These latches can be used to pass a flag, or token,
from one port to the other to indicate that a shared resource is in use. The
semaphores provide a hardware assist for a use assignment method
called “Token Passing Allocation.” In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in use. If the left
processor wants to use this resource, it requests the token by setting the
latch. This processor then verifies its success in setting the latch by reading
it. If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and is using the
shared resource. The left processor can then either repeatedly request
that semaphore’s status or remove its request for that semaphore to perform
another task and occasionally attempt again to gain control of the token via
the set and test sequence. Once the right side has relinquished the token,
the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by writing
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7007 RAMs.
When expanding an IDT7007 RAM array in width while using BUSY
logic, one master part is used to decide which side of the RAMs array will
receive a BUSY indication, and to output that indication. Any number of
slaves to be addressed in the same address range as the master, use the
BUSY signal as a write inhibit signal. Thus on the IDT7007 RAM the BUSY
pin is an output if the part is used as a master (M/S pin = H), and the BUSY
pin is an input if the part used as a slave (M/S pin = L) as shown in
Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with the R/W signal. Failure to observe this timing can
result in a glitched internal write inhibit signal and corrupted data in the
slave.
2940 drw 19
MASTER
Dual Port
RAM BUSY (R)
CE
MASTER
Dual Port
RAM BUSY (R)
SLAVE
Dual Port
RAM BUSY (R)
SLAVE
Dual Port
RAM BUSY (R)
BUSY (L) BUSY (R)
DECODER
CE
CE
CE
BUSY (L)
BUSY (L)
BUSY (L)
BUSY (L)
,
19
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
a zero into a semaphore latch and is released when the same side writes
a one to that latch.
The eight semaphore flags reside within the IDT7007 in a separate
memory space from the Dual-Port RAM. This address space is accessed
by placing a LOW input on the SEM pin (which acts as a chip select for the
semaphore flags) and using the other control pins (Address, OE, and
R/W) as they would be used in accessing a standard Static RAM. Each
of the flags has a unique address which can be accessed by either side
through address pins A0 – A2. When accessing the semaphores, none of
the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If a LOW level
is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Truth Table V). That
semaphore can now only be modified by the side showing the zero. When
a one is written into the same location from the same side, the flag will be
set to a one for both sides (unless a semaphore request from the other side
is pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out writes
from the other side is what makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side will be
stored in the semaphore request latch for that side until the semaphore is
freed by the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side’s output
register when that side's semaphore select (SEM) and output enable (OE)
signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal (SEM or OE) to go inactive or the output will never
change.
A sequence WRITE/READ must be used by the semaphore in order
to guarantee that no system level contention will occur. A processor
requests access to shared resources by attempting to write a zero into a
semaphore location. If the semaphore is already in use, the semaphore
request latch will contain a zero, yet the semaphore flag will appear as one,
a fact which the processor will verify by the subsequent read (see Truth
Table V). As an example, assume a processor writes a zero to the left port
at a free semaphore location. On a subsequent read, the processor will
verify that it has written successfully to that location and will assume control
over the resource in question. Meanwhile, if a processor on the right side
attempts to write a zero to the same semaphore flag it will fail, as will be
verified by the fact that a one will be read from that semaphore on the right
side during subsequent read. Had a sequence of READ/WRITE been
used instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be followed
by either repeated reads or by writing a one into the same location. The
reason for this is easily understood by looking at the simple logic diagram
of the semaphore flag in Figure 4. Two semaphore request latches feed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag LOW and the other
side HIGH. This condition will continue until a one is written to the same
semaphore request latch. Should the other side’s semaphore request latch
have been written to a zero in the meantime, the semaphore flag will flip
over to the other side as soon as a one is written into the first side’s request
latch. The second side’s flag will now stay low until its semaphore request
latch is written to a one. From this it is easy to understand that, if a semaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides request a
single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If simulta-
neous requests are made, the logic guarantees that only one side receives
the token. If one side is earlier than the other in making the request, the
first side to make the request will receive the token. If both requests arrive
at the same time, the assignment will be arbitrarily made to one port or
Figure 4. IDT7007 Semaphore Logic
the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is secure.
As with any powerful programming technique, if semaphores are misused
or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be handled
via the initialization program at power-up. Since any semaphore request
flag which contains a zero must be reset to a one, all semaphores on both
sides should have a one written into them at initialization from both sides
to assure that they will be free when needed.
Using Semaphores—Some Examples
Perhaps the simplest application of semaphores is their application as
resource markers for the IDT7007’s Dual-Port RAM. Say the 32K x 8 RAM
was to be divided into two 16K x 8 blocks which were to be dedicated at
any one time to servicing either the left or right port. Semaphore 0 could
be used to indicate the side which would control the lower section of
memory, and Semaphore 1 could be defined as the indicator for the upper
section of memory.
To take a resource, in this example the lower 16K of Dual-Port RAM,
the processor on the left port could write and then read a zero in to
Semaphore 0. If this task were successfully completed (a zero was read
back rather than a one), the left processor would assume control of the
lower 16K. Meanwhile the right processor was attempting to gain control
of the resource after the left processor, it would read back a one in response
to the zero it had attempted to write into Semaphore 0. At this point, the
software could choose to try and gain control of the second 16K section
by writing, then reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
D
2940 drw 20
0DQ
WRITE D
0
D
Q
WRITE
SEMAPHORE
REQUEST FLIP FLOP SEMAPHORE
REQUEST FLIP FLOP
LPORT RPORT
SEMAPHORE
READ SEMAPHORE
READ
,
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
20
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could undo
its semaphore request and perform other tasks until it was able to write, then
read a zero into Semaphore 1. If the right processor performs a similar task
with Semaphore 0, this protocol would allow the two processors to swap
16K blocks of Dual-Port RAM with each other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the Dual-
Port RAM or other shared resources into eight parts. Semaphores can
even be assigned different meanings on different sides rather than being
given a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory during
a transfer and the I/O device cannot tolerate any wait states. With the use
of semaphores, once the two devices has determined which memory area
was “off-limits” to the CPU, both the CPU and the I/O devices could access
their assigned portions of memory continuously without any wait states.
Semaphores are also useful in applications where no memory “WAIT”
state is available on one or both sides. Once a semaphore handshake has
been performed, both processors can access their assigned RAM
segments at full speed.
Another application is in the area of complex data structures. In this
case, block arbitration is very important. For this application one processor
may be responsible for building and updating a data structure. The other
processor then reads and interprets that data structure. If the interpreting
processor reads an incomplete data structure, a major error condition may
exist. Therefore, some sort of arbitration must be used between the two
different processors. The building processor arbitrates for the block, locks
it and then is able to go in and update the data structure. When the update
is completed, the data structure block is released. This allows the
interpreting processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
21
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Ordering Information
2940 drw 21
A
Power
999
Speed
A
Package
A
Process/
Temperature
Range
Blank
I
B
Commercial (0°Cto+70°C)
Industrial (-40°Cto+85°C)
Military (-55°C to +125°C)
Compliant to MIL-PRF-38535 QML
PF
G
J
80-pin TQFP (PN80-1)
68-pin PGA (G68-1)
68-pin PLCC (J68-1)
15
20
25
35
55
Commercial Only
Commercial & Industrial
Commercial, Industrial & Military
Commercial, Industrial & Military
Commercial, Industrial & Military
S
LStandard Power
Low Power
XXXXX
Device
Type
256K (32K x 8) Dual-Port RAM
7007
Speed in nanoseconds
,
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794
San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
01/05/99: Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Pages 2, 3, 4 Added additional notes to pin configurations
06/03/99: Changed drawing forma3/24/00:
Added Industrial Temperature Ranges and removed related notes
Replaced IDT logo
Changed ±200mV to 0mV in notes
05/08/00: Page 1 Added copyright info
Page 5 Fixed Absolute Maximum Ratings chart, corrected typos
Page 9 Updated drawings
Page 12 Corrected waveform drawing
Page 5 Increased storage temperature parameter
Clarified TA parameter
Pages 6, 7 DC Electrical parameters–changed working from open to disabled
09/11/01: Page 2 - 4 Added date revision for pin configurations
Page 6 Removed standard power offering for Industrial temp for 20ns from DC Electrical Characteristics
01/31/06: Page 1 Added green availability to features
Page 21 Added green indicator to ordering information
10/21/08: Page 21 Removed "IDT" from orderable part number
NOTES:
1. Contact your local sales office for industrial temp. range for other speeds, packages and powers.
2. Green parts available. For specific speeds, packages and powers contact your local sales office.
