NT1GT72B89D2BD-3C / NT2GT72B8PD2BD-3C / NT4GT72B4ND2BD-3C 1GB: 128Mx72 / 2GB: 256Mx72 / 4GB: 512Mx72 240pin DDR2 SDRAM Fully Buffered DIMM Based on 128Mx8 (1GB/2GB), 256Mx4 (4GB), and 512Mx4 (8GB) DDR2 SDRAM Features * 1GB 128Mx72 and 2GB 256Mx72 DDR2 Fully Buffered DIMM based on 128Mx8 DDR2 SDRAM (NT5TB128M8DE-3C) * 4GB 512Mx72 DDR2 Fully Buffered DIMM based on 256Mx4 DDR2 SDRAM (NT5TB256M4DE-3C) * JEDEC Standard 240-pin Fully Buffered ECC Dual In-Line Memory Module. * Performance: Speed Sort DIMM Latency* * Intended for 333MHz applications. * Inputs and outputs are SSTL-18 compatible. * VDD = 1.55V 0.075V, VDDQ = 1.55V 0.075V * Host Interface and AMB component industry standard compliant. * Support SMBus protocol interface for access to the AMB configuration registers. * Detects errors on the channel and reports them to the host memory controller. * Automatic DDR2 DRAM Bus Calibration. * Full Host Control of the DDR2 DRAMs. * Over-Temperature Detection and Alert. * MBIST & IBIST Test Functions. * Transparent Mode for DRAM Test Support. * Serial Presence Detect (SPD) * Gold contacts * RoHS Compliant products * SDRAMs in 60-ball BGA Package PC2-5300 -3C Unit 5 f CK Clock Frequency 333 MHz t CK Clock Cycle 3 ns f DQ DQ Burst Frequency 667 Mbps Description Fully Buffered 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Dual In-Line Memory Module (DIMM), organized as an eight bank 128Mx72 (1GB), 256Mx72 (2GB), or 512Mx72 (4GB) high-speed memory array. The module uses nine 128Mx8 (1GB), eighteen 128Mx8 (2GB), or thirty-six 256Mx4 (4GB) DDR2 SDRAMs in BGA packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint. The DIMM is intended for use in applications operating up to 333MHz clock speeds and achieves high-speed data transfer rates of up to 667 Mbps. Prior to any access operation, the device latency and burst type/length/operation type must be programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0, BA1, and BA2 using the mode register set cycle. REV 1.0 06/2008 1 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72B89D2BD-3C / NT2GT72B8PD2BD-3C / NT4GT72B4ND2BD-3C 1GB: 128Mx72 / 2GB: 256Mx72 / 4GB: 512Mx72 Ordering Information Part Number NT1GT72B89D2BD-3C AMB Speed Organization IDTAMB+ NT2GT72B8PD2BD-3C IDTAMB+ NT4GT72B4ND2BD-3C IDTAMB+ Leads Power 128Mx72 333MHz (3ns @ CL = 5) DDR2-667 PC2-5300 256Mx72 1.55V 512Mx72 Note: FBDIMM module revision will change if AMB, PCB, or Heat spreader version changes. Ex: REV 1.0 06/2008 2 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72B89D2BD-3C / NT2GT72B8PD2BD-3C / NT4GT72B4ND2BD-3C 1GB: 128Mx72 / 2GB: 256Mx72 / 4GB: 512Mx72 DIMM Connector Pin Description Pin Name SCK Pin Description 1 System Clock Input, negative line 1 PN0-PN13 Primary Northbound Data, positive lines - Primary Northbound Data, negative lines PS0-PS9 Primary Southbound Data, positive lines - Primary Southbound Data, negative lines SN0-SN13 Secondary Northbound Data, positive lines - Secondary Northbound Data, negative lines SS0-SS9 Secondary Southbound Data, positive lines - Secondary Southbound Data, negative lines SCL Serial Presence Detect (SPD) Clock Input SDA SPD Data Input / Output S0-S1 VID0-VID1 Note System Clock Input, positive line SPD Address Inputs, also used to select the DIMM number in the AMB Voltage ID: These pins must be unconnected for DDR2-based Fully Buffered DIMMs VID0 is VDD value: OPEN=1.8V, GND=1.5V; VID1 is VCC value: OPEN=1.5V, GND=1.2V AMB reset signal RFU Reserved for Future Use VCC AMB Core Power and AMB Channel Interface Power (1.5V) VDD DRAM Power and AMB DRAM I/O Power (1.8V) VTT DRAM Address/Command/Clock Termination Power (VDD/2) VDDSPD VSS DNU/M_TEST Note: 1. 2. SPD Power (3.3V) Ground It provides an external connection on R/Cs A-D for testing the margin of Vref which is produced by a voltage divider on the module. It is not intended to be used in normal system operation and must not be connected (DNU) in a system. This test pin may have other features on future card designs and if it does, will be included in this specification at that time. 1 System Clock Signals SCK and SCK switch at one half the DRAM CK/ frequency Eight pins reserved for forwarded clocks, eight pins reserved for future architecture flexibility REV 1.0 06/2008 2 3 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72B89D2BD-3C / NT2GT72B8PD2BD-3C / NT4GT72B4ND2BD-3C 1GB: 128Mx72 / 2GB: 256Mx72 / 4GB: 512Mx72 DDR2 240-pin FBDIMM Pinout Pin Front Side Pin Front Side Pin Front Side Pin Back Side Pin Back Side Pin Back Side 1 VDD 42 VSS 82 PS4 121 VDD 162 VSS 202 SS4 2 VDD 43 VSS 83 122 VDD 163 VSS 203 3 VDD 44 RFU* 84 VSS 123 VDD 164 RFU* 204 VSS 4 VSS 45 RFU* 85 VSS 124 VSS 165 RFU* 205 VSS 5 VDD 46 VSS 86 RFU* 125 VDD 166 VSS 206 RFU* 6 VDD 47 VSS 87 RFU* 126 VDD 167 VSS 207 RFU* 7 VDD 48 PN12 88 VSS 127 VDD 168 SN12 208 VSS 8 VSS 49 89 VSS 128 VSS 169 209 VSS 9 VCC 50 VSS 90 PS9 129 VCC 170 VSS 210 SS9 10 VCC 51 PN6 91 SN6 211 11 VSS 52 12 VCC 53 13 VCC 54 14 VSS 55 15 VTT 56 16 VID1 57 17 130 VCC 171 92 VSS 131 VSS 172 212 VSS VSS 93 PS5 132 VCC 173 VSS 213 SS5 PN7 94 SN7 214 133 VCC 174 95 VSS 134 VSS 175 215 VSS VSS 96 PS6 135 VTT 176 VSS 216 SS6 PN8 97 136 VID0 177 SN8 217 58 18 VSS 59 VSS 19 RFU** 60 PN9 20 RFU** 61 21 VSS 62 22 PN0 63 23 98 VSS 137 DNU/M_TEST 178 218 VSS 99 PS7 138 VSS 179 VSS 219 SS7 SN9 220 139 RFU** 180 101 VSS 140 RFU** 181 221 VSS VSS 102 PS8 141 VSS 182 VSS 222 SS8 PN10 103 142 SN0 183 SN10 223 64 100 224 VSS 24 VSS 65 VSS 105 RFU** 144 VSS 185 VSS 225 RFU** 25 PN1 66 PN11 106 RFU** 145 SN1 186 SN11 226 RFU** 107 VSS 146 227 VSS 108 VDD 147 VSS 228 SCK 109 VDD 148 SN2 26 67 27 VSS 28 PN2 29 68 VSS KEY 104 VSS 143 184 187 188 VSS KEY 229 69 VSS 110 VSS 149 189 VSS 230 VSS 30 VSS 70 PS0 111 VDD 150 VSS 190 SS0 231 VDD 31 PN3 71 SN3 191 32 112 VDD 151 72 VSS 113 VDD 152 PS1 114 VSS 153 115 VDD 154 33 VSS 73 34 PN4 74 35 232 VDD 192 VSS 233 VDD VSS 193 SS1 234 VSS SN4 194 235 VDD VDD 75 VSS 116 VDD 155 195 VSS 236 36 VSS 76 PS2 117 VTT 156 VSS 196 SS2 237 VTT 37 PN5 77 118 SA2 157 SN5 197 238 VDDSPD 38 78 VSS 119 SDA 158 198 VSS 239 SA0 39 VSS 79 PS3 120 SCL 159 VSS 199 SS3 240 SA1 40 PN13 80 160 SN13 200 41 81 VSS 161 201 Note: RFU = Reserved Future Use * These pin positions are reserved for forwarded clocks to be used in future module implementation ** These pin positions are reserved for future architecture flexibility The following signals are CRC bits and thus appear out of the normal sequence: PN12/ , SN12/ PS9/ , SS9/ REV 1.0 06/2008 VSS , PN13/ , SN13/ , 4 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72B89D2BD-3C / NT2GT72B8PD2BD-3C / NT4GT72B4ND2BD-3C 1GB: 128Mx72 / 2GB: 256Mx72 / 4GB: 512Mx72 Functional Block Diagram (1GB, 1Rank, 128Mx8 DDR2 SDRAMs) REV 1.0 06/2008 5 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72B89D2BD-3C / NT2GT72B8PD2BD-3C / NT4GT72B4ND2BD-3C 1GB: 128Mx72 / 2GB: 256Mx72 / 4GB: 512Mx72 Functional Block Diagram (2GB, 2Ranks, 128Mx8 DDR2 SDRAMs) # # # 1 # 3 # 3 # 2 7% # # # # #2 #3 #5 #4 # % # # 7% # # $%& $%& $%& $%& 2 $%& 3 $%& 5 $%& 4 $%& % # # $%& $%& $%& $%& 2 $%& 3 $%& 5 $%& 4 $%& 7% # # #2 #22 #23 #25 #24 #2 #26 #21 1 # % # # # 3 2 3 5 4 7% # % # $%& $%& $%& $%& 2 $%& 3 $%& 5 $%& 4 $%& # # # # # # # # # # 2 # 5 # 5 # 3 # # 7% # #6 #1 # # # # 2 # 3 # 5 $%& $%& $%& $%& $%& $%& $%& $%& % # # 7% # # % # # 7% # # #3 #3 #3 #32 #33 #35 #34 #3 $%& $%& $%& $%& 2 $%& 3 $%& 5 $%& 4 $%& 2 3 5 4 # $%& $%& $%& $%& $%& $%& $%& $%& % # # # 5 2 3 5 4 7% # % # $%& $%& $%& $%& 2 $%& 3 $%& 5 $%& 4 $%& 3 # 4 # 4 # 5 # # 7% # # # # # # # # # $%& $%& $%& $%& $%& $%& $%& $%& 4 $%& $%& $%& $%& $%& $%& $%& $%& 6 1 2 % # # 7% # # % # # 7% # # #36 #31 #5 #5 #5 #52 #53 #55 $%& $%& $%& $%& 2 $%& 3 $%& 5 $%& 4 $%& 2 3 5 4 # 2 $%& $%& $%& $%& $%& $%& $%& $%& % # # # 4 2 3 5 4 7% # % # $%& $%& $%& $%& 2 $%& 3 $%& 5 $%& 4 $%& 5 # # # 4 # 2 # 7% # # 3 # 5 # 4 # # 6 # 1 #2 #2 $%& $%& $%& $%& $%& $%& $%& $%& % # 7% # # # 2 2 3 5 4 % # # 7% # # #54 #5 #56 #51 #4 #4 #4 #42 $%& $%& $%& $%& 2 $%& 3 $%& 5 $%& 4 $%& $%& $%& $%& $%& $%& $%& $%& $%& % # # # 7% # % # $%& $%& $%& $%& 2 $%& 3 $%& 5 $%& 4 $%& 2 3 5 4 4 # 6 # 6 6% # 2 2 1 1 # # # 1 1 9 9 8% 8 : -- ! REV 1.0 06/2008 2 3 5 4 8 8 %+ -%+ 7% # # : 6; 6; 9 8 : : 1 ; ; 8 9 8 : 1 & 9& : ; : ; 5: ; : ; : ; : ; #42 # # 6 8% 2 2 $%& $%& $%& $%& $%& $%& $%& $%& 2 3 5 4 % # # 6 # 7% # % # $%& $%& $%& $%& 2 $%& 3 $%& 5 $%& 4 $%& ; %+ +0 " # $%& ' ( ) * +, ( -' , *) " , ' .,) + + . / +, -%+ + %+ +0 -% 6 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72B89D2BD-3C / NT2GT72B8PD2BD-3C / NT4GT72B4ND2BD-3C 1GB: 128Mx72 / 2GB: 256Mx72 / 4GB: 512Mx72 Functional Block Diagram (4GB, 2Ranks, 256Mx4 DDR2 SDRAMs) REV 1.0 06/2008 7 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72B89D2BD-3C / NT2GT72B8PD2BD-3C / NT4GT72B4ND2BD-3C 1GB: 128Mx72 / 2GB: 256Mx72 / 4GB: 512Mx72 Absolute Maximum DC Ratings Symbol DRAM VDD / VDDQ, AMB VDDQ Min Typical Max Units 1.475 1.55 1.625 V AMB VCC / VCCFBD DRAM Interface VTT 1.46 1.5 1.54 V 0.48 x VDD 0.5 x VDD 0.52 x VDD V 3.0 3.3 3.6 V VDDSPD Notes 1 Note 1: Estimate Operating Temperature Range Symbol Parameter Min Max Units Notes 1 Tcase DRAM Component Operating Temperature (Ambient) 0 +95 C Tcase AMB Component Operating Temperature (Ambient) 0 +110 C Note 1: Within the DRAM Temperature range all DRAM will be support. Electrical Characteristics and Operating Conditions Symbol VDD, VDDQ Parameter Supply Voltage, I/O Supply Voltage Min Max Units Notes 1.475 1.625 V 1 VIH (DC) Input High (Logic1) Voltage VREF + 0.125 VDDQ V 1 VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.125 V 1 VIH (AC) Input High (Logic1) Voltage VREF + 0.2 VDDQ V VIL (AC) Input Low (Logic0) Voltage -0.3 VREF - 0.2 V 0.5 VDDQ + 0.6 V VID (AC) AC differential input voltage VIX (AC) AC Differential cross point input Voltage 0.5* VDDQ - 0.175 0.5* VDDQ + 0.175 VOX (AC) AC Differential cross point output Voltage 0.5* VDDQ - 0.125 0.5* VDDQ + 0.125 VSS, VSSQ VREF VTT Supply Voltage, I/O Supply Voltage V V 0 0 V I/O Reference Voltage 0.49 x VDDQ 0.51 x VDDQ V 1, 2 I/O Termination Voltage (System) VREF - 0.04 VREF + 0.04 V 1, 3 Note: 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. REV 1.0 06/2008 8 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72B89D2BD-3C / NT2GT72B8PD2BD-3C / NT4GT72B4ND2BD-3C 1GB: 128Mx72 / 2GB: 256Mx72 / 4GB: 512Mx72 Serial Presence Detect -- Part 1 of 2 Byte Note 1GB 2GB 4GB 0 Number of Serial PD Bytes in CRC 92 92 92 1 SPD Revision 11 11 11 2 Key Byte / DRAM Device Type 09 09 09 3 Voltage Levels of this Assembly 42 42 42 4 SDRAM Addressing 45 45 49 5 Module Physical Attributes 24 24 24 6 Modules Type 07 07 07 7 Module Organization 09 11 10 8 Fine Timebase Dividend and Divisor 52 52 52 9 Medium Timebase Dividend 01 01 01 10 Medium Timebase Divisor 04 04 04 11 SDRAM Minimum Cycle Time (tCKmin) 0C 0C 0C 12 SDRAM Maximum Cycle Time (tCKmax) 20 20 20 13 SDRAM 43 43 43 14 SDRAM Minimum CAS Latency Time (tAA) 3C 3C 3C 15 SDRAM Write Recovery Times Supported 42 42 42 16 SDRAM Write Recovery Time (tWR) 3C 3C 3C 17 SDRAM Write Latencies Supported 42 42 42 18 SDRAM Additive Latencies Supported 60 60 60 19 SDRAM Minimum 3C 3C 3C 20 SDRAM Minimum Row Active to Row Active Delay (tRRD) 1E 1E 1E 21 SDRAM Minimum Row Precharge Time (tRP) 3C 3C 3C 22 SDRAM Upper Nibbles for tRAS and tRC 00 00 00 23 SDRAM Minimum Active to Precharge Time (tRAS) B4 B4 B4 24 SDRAM Minimum Auto-Refresh to Active/Auto-Refresh Time (tRC) F0 F0 F0 25~26 SDRAM Minimum Auto-Refresh to Active/Auto-Refresh Command Period (tRFC) FE01 FE01 FE01 27 SDRAM Internal Write to Read Command Delay (tWTR) 1E 1E 1E 28 SDRAM Internal Read to Precharge Command Delay (tRTP) 1E 1E 1E 29 SDRAM Burst Lengths Supported 03 03 03 30 SDRAM Terminations Supported 07 07 07 31 SDRAM Drivers Supported 01 01 01 32 SDRAM Average Refresh Interval (tREFI)/Double Refresh mode bit/High Temperature self-refresh rate support indication C2 C2 C2 33 Tcasemax 00 00 00 34 Thermal resistance of SDRAM device package from top (case0 to ambient (Psi T-A SDRAM) 00 00 00 REV 1.0 06/2008 Serial PD Data Entry (Hexadecimal) Description Latencies Supported to Delay (tRCD) 9 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72B89D2BD-3C / NT2GT72B8PD2BD-3C / NT4GT72B4ND2BD-3C 1GB: 128Mx72 / 2GB: 256Mx72 / 4GB: 512Mx72 Serial Presence Detect -- Part 2 of 2 Byte Note 1GB 2GB 4GB -- 35-41 Delta Temperature -- -- 42-80 Reserved -- -- -- 81~82 FB-DIMM Channel Protocols Supported 0200 0200 0200 83 Additional Back to Back Access Turnaround Time 10 10 10 84 AMB Read Access Time for DDR2-800 36 36 36 85 AMB Read Access Time for DDR2-667 34 34 34 86 AMB Read Access Time for DDR2-533 32 32 32 87 Thermal Resistance of AMB Package from top (case) to ambient (Psi T-A SDRAM) at still air condition. 2A 2A 2A 88 AMB DT Idle_0 56 56 5E 89 AMB DT Idle_1 6B 6B 73 90 AMB DT Idle_2 5C 5C 5C 91 AMB DT Active_1 91 91 9B 92 AMB DT Active _2 76 76 80 93 AMB DT L0s 00 00 00 Reserved -- -- -- 115~116 AMB Manufacturer ID Code 7FB3 7FB3 7FB3 117-118 Module ID: Module Manufacture's JEDEC ID Code 830B 830B 830B 119-125 Reserved for Module ID -- -- -- 126-127 Cyclical Redundancy Code -- -- -- 128-145 Module Part Number -- -- -- 146-147 Module Revision Code 148-149 SDRAM Manufacture's JEDEC ID Code 150-255 Reserved 94~114 REV 1.0 06/2008 Serial PD Data Entry (Hexadecimal) Description -- -- -- 830B 830B 830B -- -- -- 10 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72B89D2BD-3C / NT2GT72B8PD2BD-3C / NT4GT72B4ND2BD-3C 1GB: 128Mx72 / 2GB: 256Mx72 / 4GB: 512Mx72 Environmental Requirements Symbol Parameter TOPR Operating temperature HOPR Operating humidity (relative) TSTG Storage temperature HSTG Storage humidity (without condensation) PBAR Barometric pressure (operating & Storage) Note: 1. 2. Units - Note 1 10 to 90 % 2 -50 to +100 C 2 5 to 95 % 2 105 to 69 K pascal 2 The designer must meet the case temperature specifications for individual module components. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. REV 1.0 06/2008 Rating 11 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72B89D2BD-3C / NT2GT72B8PD2BD-3C / NT4GT72B4ND2BD-3C 1GB: 128Mx72 / 2GB: 256Mx72 / 4GB: 512Mx72 Operating, Standby, and Refresh Currents Definition table Symbol Parameter/Condition Idd_Idle_0 Icc_Idle_0 Idle Current, single or last DIMM. L0 state, idle (0BW). Primary channel enabled; Secondary Channel disabled. CKE high. Command and address line stable. DRAM clock active. Idd_Idle_1 Icc_Idle_1 Idle Current, first DIMM. L0 stage, idle (0BW). Primary and Secondary channels enabled. CKE high. Command and address line stable. DRAM clock active. Idd_Idle_2 Icc_Idle_2 Idle Current, DRAM power down. L0 stage, idle (0BW). Primary and Secondary channels enabled CKE low. Command and address lines floated. DRAM clock active, ODT and CKE driven low. Idd_Active_1 Icc_Active_1 (Write) Active Power. L0 state. 50% DRAM BW to downstream DIMM, 67% read, 33% write. Primary and Secondary channels enabled. DRAM clock active, CKE high. Idd_Active_1 Icc_Active_1 (Read) Active Power. L0 state. 50% DRAM BW to downstream DIMM, 100% read. Primary and Secondary channels enabled. DRAM clock active, CKE high. Idd_Active_2 Icc_Active_2 Active Power, data pass through. L0 state. 50% DRAM BW to downstream DIMM, 67% read, 33% write. Primary and Secondary channels enabled. CKE high. Command and address lines stable. DRAM clock active. Idd_Training Icc_Training Primary and Secondary channels enabled. 100% toggle on all channel lanes. DRAMs idle. 0BW. CKE high, Command and address line stable. DRAM clock active. Part Number Idle_0 Idd Icc Idle_1 Idd Idle_2 Icc Idd Active_1 (W) Active_1 (R) Icc Idd Icc Idd Icc Active_2 Idd Icc Training Idd Unit Icc NT1GT72B89D2BD-3C 0.825 1.87 0.825 2.31 0.847 2.31 0.836 2.31 0.825 2.299 0.836 2.31 0.825 2.266 A NT2GT72B8PD2BD-3C 1.155 1.925 1.155 2.42 1.21 2.431 1.21 2.442 1.21 2.431 1.155 2.431 1.155 2.398 A NT4GT72B4ND2BD-3C 1.969 1.98 1.969 2.475 2.046 2.486 2.035 2.486 2.057 2.497 1.958 2.497 1.958 2.464 A REV 1.0 06/2008 12 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72B89D2BD-3C / NT2GT72B8PD2BD-3C / NT4GT72B4ND2BD-3C 1GB: 128Mx72 / 2GB: 256Mx72 / 4GB: 512Mx72 AC Timing Specifications for DDR2 SDRAM Devices Used on Module (Part 1 of 2) Symbol tAC DQ output access time from CK/ Max. -0.45 +0.45 Unit -0.4 +0.4 ns tCH 0.48 0.52 tCK tCL CK low-level width 0.48 0.52 tCK tHP Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time Min (tCH, tCL) - tCK tCK Clock Cycle Time 3 8 ns tDH DQ and DM input hold time 175 - ps tDS DQ and DM input setup time 100 - ps tIPW Input pulse width 0.6 - tCK DQ and DM input pulse width (each input) 0.35 - tCK - tAC max ns tAC max ns tAC min tAC max ns tHZ Data-out high-impedance time from CK/ tLZ(DQ) Data-out low-impedance time from CK/ tLZ(DQS) DQS/ tDQSQ low-impedance time from CK/ DQS-DQ skew (DQS & associated DQ signals) min - 0.24 ns - 0.34 ns Data output hold time from DQS tHP tQHS - ns tDQSS Write command to 1st DQS latching transition -0.25 0.25 tCK tDQSL,(H) DQS input low (high) pulse width (write cycle) 0.35 - tCK tDSS DQS falling edge to CK setup time (write cycle) 0.2 - tCK tDSH DQS falling edge hold time from CK (write cycle) 0.2 - tCK tMRD Mode register set command cycle time 2 - tCK tWPST Write postamble 0.40 0.60 tCK tWPRE Write preamble 0.35 - tCK tIH Address and control input hold time 0.275 - ps tIS Address and control input setup time 0.2 - ps tRPRE Read preamble 0.9 1.1 tCK tRPST Read postamble 0.4 0.6 tCK tQHS tQH Data hold Skew Factor 2tAC tDelay Minimum time clocks remains ON after CKE asynchronously drops Low tRFC Refresh to active/Refresh command time tREFI tRRD tIS + tCK + tIH ns 127.5 ns Average Periodic Refresh Interval (85C < TCASE < 95C) 3.9 =s Average Periodic Refresh Interval (0C < TCASE < 85C) 7.8 =s Active bank A to Active bank B command 7.5 Notes ns DQS output access time from CK/ tDIPW 06/2008 Min. CK high-level width tDQSCK REV 1.0 -3C Parameter - ns 13 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72B89D2BD-3C / NT2GT72B8PD2BD-3C / NT4GT72B4ND2BD-3C 1GB: 128Mx72 / 2GB: 256Mx72 / 4GB: 512Mx72 AC Timing Specifications for DDR2 SDRAM Devices Used on Module (Part 2 of 2) Symbol tCCD Write recovery time WR Write recovery time with Auto-Precharge Unit Min. Max. 2 - tCK 15 - ns tWR/tCK tDAL Auto precharge write recovery + precharge time tWTR Internal write to read command delay 7.5 tRTP Internal read to precharge command delay 7.5 ns tXSNR Exit self refresh to a Non-read command tRFC +10 ns tXSRD Exit self refresh to a Read command 200 tCK - tCK - ns Exit precharge power down to any Non- read command 2 - tCK tXARD Exit active power down to read command 2 - tCK tXARDS Exit active power down to read command 7-AL tCK tCK tCKE CKE minimum pulse width 3 tOIT OCD drive mode output delay 0 ODT turn-on delay tAON tAONPD ODT turn-on 12 ns 2 2 tCK tAC tAC (min) ODT turn-on (Power down mode) 2tCK + tAC(min) tAC(max) +2 +1 ns ns 2.5 tCK ODT turn-off tAC(min) tAC(max) +0.6 ns tAOFPD ODT turn-off (Power down mode) 2.5tCK + tAC(min) +2 tAC(max) +1 ns tANPD ODT to power down entry latency 3 tCK tAXPD ODT power down exit latency 8 tCK tRAS Row Active Time 45 70000 ns tRCD RAS to CAS delay 15 - ns tRC Row Cycle Time 60 - ns tRP Row Precharge Time 15 - ns tAOF ODT turn-off delay (max) +1 2.5 tAOFD Notes ns WR +tRP tAOND 06/2008 to tWR tXP REV 1.0 -3C Parameter 14 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72B89D2BD-3C / NT2GT72B8PD2BD-3C / NT4GT72B4ND2BD-3C 1GB: 128Mx72 / 2GB: 256Mx72 / 4GB: 512Mx72 Package Dimensions Max. 8.20 B 51 A 67 12 0 9.5 30.35 +/-0.15 17.3 133.35 +/- 0.15 1.27 +/- 0.10 74.67 Detail A Detail B 2.50 3.80 2.5 0.80 +/- 0.1 Width 1.00 Pitch 1.50+/- 0.10 REV 1.0 06/2008 Unit: mm 15 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72B89D2BD-3C / NT2GT72B8PD2BD-3C / NT4GT72B4ND2BD-3C 1GB: 128Mx72 / 2GB: 256Mx72 / 4GB: 512Mx72 Revision Log Rev Date 0.1 05/2008 Preliminary Release 1.0 06/2008 Official release REV 1.0 06/2008 Modification 16 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.