June 2007 Rev 14 1/53
1
M25P40
4 Mbit, low voltage, serial Flash memory
with 50 MHz SPI bus interface
Features
■4 Mbit of Flash memory
■2.3 V to 3.6 V single supply voltage
■SPI bus compatible serial interface
■50 MHz clock rate (maximum)
■Page Program (up to 25 6 by te s) in 1. 5 ms
(typical)
■Sector Erase (512 Kbit) in 1 s (typical)
■Bulk Erase (4 Mbit) in 4.5 s (typical)
■Deep Power-down mode 1 µA (typical)
■Hardware Write Protection: protected area size
defined by three non-volatile bits (BP0, BP1
and BP2)
■Electronic signatures
– JEDEC standard two-byte signature
(2013h)
– RES instruction, one-byte, signature (12h),
for backward compatibility
■Packages
– ECOPACK® (RoHS compliant)
SO8 (MN)
150 mil width
VFQFPN8 (MP)
(MLP8)
www.st.com
Contents M25P40
2/53
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 12
4.4 Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 12
4.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.6 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.7 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.3 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.4 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4.3 BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
M25P40 Contents
3/53
6.4.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.5 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.6 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.7 Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 27
6.8 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.9 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.10 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.11 Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.12 Release from Deep Power-down and Read Electronic Signature (RES) . 33
7 Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10 DC and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
11 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
12 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
List of tables M25P40
4/53
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Protected area sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3. Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Read Identification (RDID) data-out sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 7. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 8. Power-up ti ming and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 10. Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 11. Data retention and endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 12. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 13. DC characteristics (device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 14. DC characteristics (device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 15. Instruction times (device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 16. Instruction times (device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 17. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 18. Which AC characteristics to use?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1
Table 19. AC characteristics (25 MHz operation, device grade 3, VCC min = 2.7 V) . . . . . . . . . . . . . 42
Table 20. AC characteristics (50 MHz operation, device grade 6, VCC min = 2.7 V) . . . . . . . . . . . . . 43
Table 21. AC characteristics (40 MHz operation, device grade 6, VCC min = 2.3 V) . . . . . . . . . . . . . 44
Table 22. SO8 narrow – 8 lead plastic Small Outline, 150 mils body width,
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 23. VFQFPN8 (MLP8) 8-lead Very thin Fine pitch Quad Flat Package No lead,
6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 24. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 25. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
M25P40 List of figures
5/53
List of figures
Figure 1. Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. SO and VFQFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Bus Master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. Write Enable (WREN) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 21
Figure 10. Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 23
Figure 11. Write Status Register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 26
Figure 13. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence
and data-out sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14. Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 15. Sector Erase (SE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 16. Bulk Erase (BE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 17. Deep Power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) instruction
sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 19. Release from Deep Power-down (RES) instruction sequence. . . . . . . . . . . . . . . . . . . . . . 34
Figure 20. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 21. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 22. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 23. Write Protect setup and hold timing during WRSR when SRWD = 1. . . . . . . . . . . . . . . . . 45
Figure 24. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 25. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 26. SO8 narrow – 8 lead plastic Small Outline, 150 mils body width, package ou tlin e . . . . . . . 47
Figure 27. VFQFPN8 (MLP8) 8-lead Very thin Fine pitch Quad Flat Package No lead,
6 × 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Description M25P40
6/53
1 Description
The M25P40 is a 4 Mbit (512 K × 8) Serial Flash memory, with advanced write protection
mechanisms, accessed by a high speed SPI-co mpa tible bus.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program
instruction.
The memory is organized as 8 sectors, each containing 256 pages. Each page is 256 bytes
wide. Thus, the whole memory can be viewed as co nsisting of 2048 pages, or 524,288
bytes.
The whole memory can be erased using the Bulk Erase instruction, or a sector at a time,
using the Sector Erase instruction.
In order to meet environmental requirements, ST offers the M25P40 in ECOPACK®
packages. ECOPACK® packages are Lead-free and RoHS compliant.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 1. Logic diagram
Table 1. Signal names
Signal name Function Direction
C Serial Clo ck Input
D Serial Data inp ut Input
Q Serial Data output Output
SChip Select Input
WWrite Protect Input
HOLD Hold Input
VCC Supply voltage
VSS Ground
AI04090
S
VCC
M25P40
HOLD
VSS
W
Q
C
D
M25P40 Description
7/53
Figure 2. SO and VFQFPN connections
1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to
VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB.
2. See Section 11: Package mechanical for package dimensions, and how to identify pin-1.
1
AI04091B
2
3
4
8
7
6
5DVSS C
HOLDQ
SV
CC
W
M25P40
Signal description M25P40
8/53
2 Signal description
2.1 Serial Data output (Q)
This output signal is used to tr ansf er data serially out of the de vice . Data is shifted out on the
falling edge of Serial Clock (C).
2.2 Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Value s are latched on the rising edge of Serial
Clock (C).
2.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data output (Q) changes after the falling edge of Serial Clock (C).
2.4 Chip Select (S)
When this input signal is High, the de vice is deselected and Serial Data out put (Q) is at high
impedance. Unless an internal Program, Erase or Write Status Register cycle is in progr ess,
the device will be in the Standby Power mode (this is not the Deep Power-down mode).
Driving Chip Select (S) Low selects the device, placing it in the Active Power mode.
After Power-up, a falling edge on Chip Select (S) is required prior to th e start of any
instruction.
2.5 Hold (HOLD)
The Hold (HOLD) signal is used to pause any se rial communications with the de vice without
deselecting the device.
During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data
input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven Lo w.
2.6 Write Protect (W)
The main purpose of this input signa l is to free ze the size of the area of memory that is
protected against pro g ram or er ase instructions (as specified by the values in t he BP2, BP1
and BP0 bits of the Status Re gister).
M25P40 Signal description
9/53
2.7 VCC supply voltage
VCC is the supply voltage.
2.8 VSS ground
VSS is the reference for the VCC supply voltage.
SPI modes M25P40
10/53
3 SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two follo wing modes:
●CPOL=0, CPHA=0
●CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between t he t w o mod es, as shown in Figure 4, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
●C remains at 0 for (CPOL=0, CPHA=0)
●C remains at 1 for (CPOL=1, CPHA=1)
Figure 3. Bus Master and memory devices on th e SPI bus
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 3 shows a n examp le of three de vices connected t o an MCU , on an SPI bus . Only one
device is selected at a time, so only one device drives the Serial Data output (Q) line at a
time, the other devices are high impedance. Resistors R (represented in Figure 3) ensure
that the M25P40 is not selected if the Bus Master leaves the S line in the high impedance
state . As the Bus Master may enter a state where all inputs/outputs are in high impedance
at the same time (for e xample, when the Bus Master is reset), the clock line (C) must be
connected to an external pull-down resistor so that, when all inputs/outputs become high
impedance, the S line is pulled High while the C line is pulled Lo w ( thus ensuring that S a nd
C do not become High at the same time , and so, that the tSHCH requirement is met). The
typical v alue of R is 100 kΩ, assuming that the time constant R*Cp (Cp = parasitic
capacitance of the bus line) is shorter than the time during which the Bus Master leaves the
SPI bus in high impe dance.
AI12836b
SPI Bus Master
SPI Memory
Device
SDO
SDI
SCK
CQD
S
SPI Memory
Device
CQD
S
SPI Memory
Device
CQD
S
CS3 CS2 CS1
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
WHOLD WHOLD WHOLD
RR R
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
R
M25P40 SPI modes
11/53
Example: Cp = 50 pF, that is R*Cp = 5 µs <=> the application must ensure that the Bus
Master never leaves the SPI bus in the high impedance state for a time period shorter than
5µs.
Figure 4. SPI modes supported
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
Operating features M25P40
12/53
4 Operating features
4.1 Page Programming
To prog ram one data b yte, two in structions are required: Write Enable (WREN), which is one
byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is
followed by the internal Program cycle (of duration t PP).
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be
programmed at a time (changing bits from 1 to 0), pro vided that they lie in consecutive
addresses on the same page of memory.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Progr am (PP) sequences with each containing only a few bytes (see Page Program (PP),
Instruction times (device g rade 6) and Table 16: Instruction times (device grade 3)).
4.2 Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be
applied, the bytes of memory need to have been er ased to all 1s (FFh). This can be
achie v ed either a se ctor at a time, using the Sector Erase (SE) instruction, or throughout the
entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of
duration tSE or tBE).
The Erase instruction must be preceded by a Write Enable (WREN) instruction.
4.3 Polling during a Write, Program or Erase cycle
A further improvement in the t ime to Write Status Regi ster (WRSR) , Prog r am (PP) or Era se
(SE or BE) can be achieved b y no t waiting for the worst case delay (tW, tPP
, tSE, or tBE). The
Write In Progress (WIP) bit is pro vided in the Status Register so t hat the application progr am
can monitor its v alue , polling it to establish when the previous Write cycle, Prog r am cycle or
Erase cycle is complete.
4.4 Active Power, Standby Power and Deep Power-down modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.
When Chip Select (S) is High, the de vice is deselected, b ut could remain in the Activ e Pow er
mode until all internal cycles have completed (Program, Erase, Write Status Register). The
device then goes in to the Standby Power mode. The device consumption drops to ICC1.
The Deep Power-down mode is entered when the specific instruction (the Deep Power-
down (DP) instruction) is executed. The device consumption drops further to ICC2. The
device remains in this mode until another specific instruction (the Release fro m Deep
Power-down and Read Electronic Signature (RES) instruction) is executed.
All other instructions are ignored while the d evice is in the Deep Power-down mode. This
can be used as an extra software protection mechanism, when the device is not in active
use, to protect the device from inadvertent Write, Program or Erase instructions.
M25P40 Operating features
13/53
4.5 Status Register
The Status Regist er conta ins a n umber o f stat us and cont rol bit s that can be rea d or set (a s
appropriate) by specific instructions. For a detailed description of the Status Register bits,
see Section 6.4 : Re ad Status Register (RDSR).
4.6 Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25P40 features the following data protection mechanisms:
●P ow er On Reset and an internal timer (tPUW) can provide pr otection against inadv ertent
changes while the power supply is outside the operating specification.
●Progr am, Er ase and Write Status Regist er instructions are chec ked that the y consist of
a number of clock pulses that is a multiple of eight, before they are accepted for
execution.
●All instructions that modify data m ust be preceded by a Write Enab le (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is re turned to its re set state
by the following events:
–Power-up
– Write Disable (WRDI) instruction completion
– Write Status Register (WRSR) instruction completion
– Page Program (PP) instruction completion
– Sector Erase ( SE) instruction co mpletion
– Bulk Erase (BE) instruction completion
●The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be config ur ed as
read-only. This is the Software Protected Mode (SPM).
●The Write Protect (W) signal allows the Block Protect (BP2, BP1, BP0) bits and Status
Register Write Disable (SRW D) bit to be protected. This is the Hardware Protected
Mode (HPM).
●In addition to the low power consumption feature, the Deep Power-down mode offers
e xtra softw are protection from inadv ertent Write , Program and Erase instructions, as all
instructions are ignored except one particular instruction (the Release from Deep
Power-down instruction).
Operating features M25P40
14/53
4.7 Hold condition
The Hold (HOLD) signal is used to pause any se rial communications with the de vice without
resetting the clocking seque nce. However, taking this signal Low does not terminate any
Write Status Register, Program or Erase cycle that is current ly in progress.
To enter th e Hold condition, the device must be selected, with Chip Select (S) Low.
The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low (as shown in Figure 5).
The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition
starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes
Low. (This is shown in Figure 5).
During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data
input (D) and Serial Clock (C) are Don’t Care.
Normally, the device is kept selected, with Chip Select (S) driv en Lo w, f or the whole dur ation
of the Hold conditi on. This is to ensure that the state of the internal logic remains unchanged
from the moment of entering the Hold condition.
If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of
resetting the internal logic of the device. To restart communication with the device, it is
necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents
the device from going back to the Hold condition.
Table 2. Protected area sizes
Status Register
content Memory cont en t
BP2
bit BP1
bit BP0
bit Protected area Unprotected area
0 0 0 none All sectors(1) (eight sectors: 0 to 7)
1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are
0.
0 0 1 Upper eighth (Sector 7) Lower seven-eighths (seven sectors: 0 to
6)
0 1 0 Upper quarter (two sectors: 6 and 7) Lower three-quarters (six sectors: 0 to 5)
0 1 1 Upper half (four sectors: 4 to 7) Lower half (four sectors: 0 to 3)
1 0 0 All sectors (eight sectors: 0 to 7) none
1 0 1 All sectors (eight sectors: 0 to 7) none
1 1 0 All sectors (eight sectors: 0 to 7) none
1 1 1 All sectors (eight sectors: 0 to 7) none
M25P40 Operating features
15/53
Figure 5. Hold condition activ ation
AI02029D
HOLD
C
Hold
Condition
(standard use)
Hold
Condition
(non-standard use)
Memory organization M25P40
16/53
5 Memory organization
The memory is organized as:
●524,288 bytes (8 bits each)
●8 sectors (512 Kbits, 65536 bytes each)
●2048 pages (256 bytes each).
Each page can be individually pro grammed (bits are prog rammed from 1 to 0). The de vice is
Sector or Bulk Er asable (bits are erased from 0 to 1) but not Page Erasable.
Table 3. Memory organization
Sector Address range
7 70000h 7FFFFh
6 60000h 6FFFFh
5 50000h 5FFFFh
4 40000h 4FFFFh
3 30000h 3FFFFh
2 20000h 2FFFFh
1 10000h 1FFFFh
0 00000h 0FFFFh
M25P40 Memory organization
17/53
Figure 6. Block diagram
AI04986
HOLD
S
WControl Logic High Voltage
Generator
I/O Shift Register
Address Register
and Counter 256 Byte
Data Buffer
256 Bytes (Page Size)
X Decoder
Y Decoder
Size of the
read-only
memory area
C
D
Q
Status
Register
00000h
7FFFFh
000FFh
Instructions M25P40
18/53
6 Instructions
All instruct ion s, addresses and dat a are shifted in and out of the device, most significan t bit
first.
Serial Data input (D) is sampled on the first rising edge of Serial Clock (C ) aft er Ch ip Se lect
(S) is drive n L ow. Then, t he on e- byte i nstruction code must be shifte d in to t he device, most
significant bit first, on Serial Data input (D), each bit being latched on the rising edges of
Serial Clock (C).
The instruction set is listed in Table 4.
Every instruction sequence st arts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
Chip Select (S) must be driven High after the last bit of the instruction sequence has been
shifted in.
In the case of a Read Data Bytes (READ) , Read Data Bytes at Higher Speed (Fast_Read),
Read Identification (RDID), Read Status Register (RDSR) or Release from Deep Power-
down, an d Read Electronic Signature (RES) instruction, the shifted-in instruction sequence
is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the
data-out se quence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status
Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP)
instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the
instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when
the number of clock pulses after Chip Select (S) being driven Low is an ex act multiple of
eight.
All attempts to access the memory array during a Write Status Register cycle, Program
cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program
cycle or Erase cycle continues unaffected.
M25P40 Instructions
19/53
6.1 Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 7) sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector
Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entere d b y driving Chip Select (S) Lo w, sending the
instruction code, an d then driving Chip Select (S) High.
Figure 7. Write Enable (WREN) instruction sequence
Table 4. Instruction set
Instruction Description One-byte instruction
code Address
bytes Dummy
bytes Data
bytes
WREN Write Enable 0000 0110 06h 0 0 0
WRDI Write Disable 0000 0100 04h 0 0 0
RDID(1)
1. The Read Identification (RDID) instruction is available only in products with Process Technology code X
(see Application Note AN1995).
Read Identification 1001 1111 9Fh 0 0 1 to 3
RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞
WRSR Write Statu s Register 0000 0001 01h 0 0 1
READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞
FAST_READ Read Data Bytes at Higher
Speed 0000 1011 0Bh 3 1 1 to ∞
PP Page Program 0000 0010 02h 3 0 1 to 256
SE Se ctor Erase 1101 1000 D8h 3 0 0
BE Bulk Erase 1100 0111 C7h 0 0 0
DP Deep Power-down 1011 1001 B9h 0 0 0
RES
Release from Deep Power-
down, and Read Electronic
Signature 1010 1011 ABh 0 3 1 to ∞
Release from Deep Power-
down 0 0 0
C
D
AI02281E
S
Q
21 34567
High Impedance
0
Instruction
Instructions M25P40
20/53
6.2 Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 8) resets the Write Enable Latch (WEL) bit.
The Write Disab le (WRDI) instruction is entered b y driving Chip Select (S) Low, sending the
instruction code, an d then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under the following conditions:
●Power-up
●Write Disable (WRDI) instruction completion
●Write Status Register (WRSR) instruction completion
●Page Program (PP) instruction completion
●Sector Erase (SE) instruction completion
●Bulk Erase (BE) instruction completion
Figure 8. Write Disable (WRDI) instruction sequence
C
D
AI03750D
S
Q
21 34567
High Impedance
0
Instruction
M25P40 Instructions
21/53
6.3 Read Identification (RDID)
The Read Identification (RDID) instruction is available in products with Process Technology
code X only.
The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be
read, followed by two bytes of device identification. The manufacturer identification is
assigned b y JEDEC, and has the v alue 20h f or STMicroe lectronics. T he de vice identification
is assigned b y the device manuf acturer, and indicates the memory type in the first byte
(20h), and the memory capacity of the device in the second byte (13h).
Any Read Id entification (RDID) instruction while an Erase or Pr ogram cycle is in progress , is
not decoded, and has no effect on the cycle that is in progress.
The Read Identification (RDID) instruction should not be issued while the device is in Deep
Pow er-down mode.
The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code
for the instruction is shifted in. This is followed by the 24-bit device identification, stored in
the memory, being shifted out on Serial Data output (Q), each bit being shifted out during
the falling edge o f Serial Clock (C).
The instruction sequence is shown in Figure 9.
The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at
any time during data output.
When Chip Select (S) is driven High, th e de vice is pu t in the Sta nd-b y Pow er mode . On ce in
the Stand-by Power mode, the device waits to be selected, so that it can rec eive, decode
and execute instructions.
Figure 9. Read Identification (RDID) instruction sequence and da ta-out sequence
Table 5. Read Identification (RDID) d ata-out sequence
Manufacturer identification Device identification
Memory type Memory capacity
20h 20h 13h
C
D
S
21 3456789101112131415
Instruction
0
AI06809b
Q
Manufacturer Identification
High Impedance
MSB
15 1413 3210
Device Identification
MSB
16 17 18 28 29 30 31
Instructions M25P40
22/53
6.4 Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. Th e
Status Register may be read at any time, even while a Program, Er ase or Write Status
Register cycle is in progress . When one of these cycles is in progress , it is recommended to
check the Write In Progress (WIP) bit before sending a new instruction to the device. It is
also possible to read the Status Register continuously, as show n in Figure 10.
The status and control bits of the Status Register are as follows:
6.4.1 WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to
0 no such cycle is in progress.
6.4.2 WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the inte rnal Write Enable Latch is set, when set to 0 t he internal Write Enable
Latch is reset and no Write Status Register, Program or Erase instruction is accepted.
6.4.3 BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to
be software protected against Program and Erase instructions. These bits ar e written with
the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2,
BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 2) becomes
protected against P age Program (PP) and Sector Erase (SE) instructions. The Block Protect
(BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not
been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2,
BP1, BP0) bits are 0.
6.4.4 SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with th e Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Prot ect ( W ) is driv en Lo w). In this mode, the
non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) be come read-only bits an d
the Write Status Register (WRSR) instruction is no longer accepted for e xecution.
Table 6. Status Register f ormat
b7 b0
SRWD 0 0 BP2 BP1 BP0 WEL WIP
Status Register Write Protect
Block Protect bits
Write Enable Latc h bi t
Write In Progress bit
M25P40 Instructions
23/53
Figure 10. Read Status Registe r (RDSR) instruction sequence and data-out
sequence
C
D
S
21 3456789101112131415
Instruction
0
AI02031E
Q76543210
Status Register Out
High Impedance
MSB
76543210
Status Register Out
MSB
7
Instructions M25P40
24/53
6.5 Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must pre viously
have been executed. After the Write Enable (WREN) instruction has been decoded an d
executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data input (D).
The instruction sequence is shown in Figure 11.
The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the
Status Register. b6 and b5 are always read as 0.
Chip Select (S) must be driv en Hig h after the eighth bit of the d ata b yte has bee n latched in.
If not, the Write Status Register ( WRSR) instruction is not e x e cuted. As soon as Chip Sele ct
(S) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is
initiated. While the Write Status Register cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enab le Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allo ws the user to change the values of the
Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as
read-only, as defined in Table 2. The Write Status Register (WRSR) ins truction also allows
the user to set or reset th e Status Register Write Disable (SR WD) bit in accordance with the
Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect
(W) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write
Status Register (WRSR) instruction is not executed once the Hardware Protected Mode
(HPM) is entered.
Figure 11. Write Status Register (WRSR) instruction sequence
C
D
AI02282D
S
Q
21 3456789101112131415
High Impedance
Instruction Status
Register In
0
765432 0
1
MSB
M25P40 Instructions
25/53
The protection features of the device are summarized in Table 7.
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provid ed that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W) is driven High or Low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W):
●If Write Protect (W) is driven High, it is possible to write to the St atus Register p rov ided
that the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction.
●If Write Protect (W) is driven Low, it is not possible to write to the Status Register even
if the Write Enable Lat ch (WEL) bi t has previously been set by a Write Enab le (WREN)
instruction. (Attempts to write to the Status Register are reject ed, and ar e not accepte d
for execution). As a consequence, all the data bytes in the memory area t hat are
software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status
Register, are also hardware protect ed again st da ta mo dification.
Regardless of the order of the two events , the Hardware Protected Mode (HPM) can be
entered:
●by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)
Low
●or by driving Write Protect (W) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write
Protect (W) High.
If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can
never be activated, and only the Software Protected Mode (SPM), using the Block Protect
(BP2, BP1, BP0) bits of the Status Register, can be used.
Table 7. Protection modes
W
signal SRWD
bit Mode Write Prot ectio n of the
Status Register
Memory content
Protected area(1)
1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in
Table 2.
Unprotected area(1)
10
Software
Protected
(SPM)
Status Register is
Writable (if the WREN
instruction has set the
WEL bit)
The values in the SRWD,
BP2, BP1 and BP0 bits
can be changed
Protec ted against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept Page
Program and Sector
Erase instructions
00
11
01
Hardware
Protected
(HPM)
Status Register is
Hardware write protected
The values in the SRWD,
BP2, BP1 and BP0 bits
cannot be changed
Protec ted against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept Page
Program and Sector
Erase instructions
Instructions M25P40
26/53
6.6 Read Data Bytes (READ)
The de vice is first selected by driving Chip Select (S) Low. Th e instruction code f or the Read
Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on Serial Data output (Q), each bit being shifted out, at a maximum
frequency fR, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 12.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated b y driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)
instruction, while an Erase , Prog ra m or Write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
Figure 12. Read Data Bytes (READ) instruction sequence and data-out sequence
1. Address bits A23 to A19 are Don’t Care.
C
D
AI03748D
S
Q
23
21 345678910 2829303132333435
2221 3210
36 37 38
76543 1 7
0
High Impedance Data Out 1
Instruction 24-Bit Address
0
MSB
MSB
2
39
Data Out 2
M25P40 Instructions
27/53
6.7 Read Data Bytes at Higher Speed (FAST_READ)
The de vice is first selected by driving Chip Select (S) Low. Th e instruction code f or the Read
Data Bytes at Higher Speed (FAST_READ) instruction is f ollo w ed by a 3-byte address (A23-
A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).
Then the memo ry contents , at that address , is shifted out on Serial Data output (Q), each bit
being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 13.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Byte s at Higher Speed (FAST_READ)
instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving
Chip Select (S) High. Chip Select (S) can be driv en High at an y time during data output. An y
Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in
progress.
Figure 13. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence
and data-out sequence
1. Address bits A23 to A19 are Don’t Care.
C
D
AI04006
S
Q
23
21 345678910 28293031
2221 3210
High Impedance
Instruction 24 BIT ADDRESS
0
C
D
S
Q
32 33 34 36 37 38 39 40 41 42 43 44 45 46
765432 0
1
DATA OUT 1
Dummy Byte
MSB
76543210
DATA OUT 2
MSB MSB
7
47
765432 0
1
35
Instructions M25P40
28/53
6.8 Page Program (PP)
The Page Program (PP) instruction allows b ytes to be programmed in the mem ory
(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed . After the Write Enable (WREN) instruction has been
decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, three address b ytes and at least one data byte on Serial Data input ( D).
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes
beyond the end of the current page are programmed from the start address of the same
page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)
must be driven Low for the entir e duration of the sequence .
The instruction sequence is shown in Figure 14.
If more tha n 256 bytes are se nt t o the device, previously latched data are discard ed an d the
last 256 dat a bytes ar e guaranteed to be progr ammed corr ectly within the same pag e. If less
than 256 Data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Progr am (PP) sequences with each containing only a few bytes (see Instruction times
(device grade 6) and Table 16: Instruction times (device grade 3)).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Page Prog ram cycle is in progre ss, th e Status Register
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0) bits (see Table 3 and Table 2) is not executed.
M25P40 Instructions
29/53
Figure 14. Page Program (PP) instruction sequence
1. Address bits A23 to A19 are Don’t Care.
C
D
AI04082B
S
4241 43 44 45 46 47 48 49 50 52 53 54 5540
C
D
S
23
21 345678910 2829303132333435
2221 3210
36 37 38
Instruction 24-Bit Address
0
765432 0
1
Data Byte 1
39
51
765432 0
1
Data Byte 2
765432 0
1
Data Byte 3 Data Byte 256
2079
2078
2077
2076
2075
2074
2073
765432 0
1
2072
MSB MSB
MSB MSB MSB
Instructions M25P40
30/53
6.9 Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded, the device sets the Write
Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (S) Lo w, followed by the
instruction code, and three address bytes on Serial Data input (D). Any address inside the
Sector (see Table 3) is a valid address for the Sector Erase (SE) instruction. Chip Select ( S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 15.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Sector Erase (S E) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is
initiated. While the Sector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle , and is 0 when it is completed. At some unspe cified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0) bits (see Table 3 and Table 2) is not executed.
Figure 15. Secto r Erase (SE) instruction sequence
1. Address bits A23 to A19 are Don’t Care.
24 Bit Address
C
D
AI03751D
S
21 3456789 293031
Instruction
0
23 22 2 0
1
MSB
M25P40 Instructions
31/53
6.10 Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in Figure 16.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S)
is driven High, the self-timed Bulk Erase cycle (whose dur ation is tBE) is initiated. While the
Bulk Erase cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progre ss (WIP) bit is 1 during the self-timed Bulk
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Bulk Era se (BE) instruction is e x ecuted only if all Bloc k Protect (BP2, BP1, BP0) bits are
0. The Bulk Erase (BE) instruction is ignored if one, o r more, sectors are protected.
Figure 16. Bulk Erase (BE) instruction sequence
C
D
AI03752D
S
21 345670
Instruction
Instructions M25P40
32/53
6.11 Deep Power-down (DP)
Executing the Deep Po wer-down (DP) instruction is the only way to put the device in the
lowest consumption mode (the Deep Power-down mode). It can also be used as an extra
softwar e protecti on mechanism, wh ile the device is not in activ e use , since in this m ode , the
device ignores all Write, Program and Erase instructions.
Driving Chip Select (S) High d eselects the de vice, and puts the de vice in t he Standb y P o wer
mode (if there is no internal cycle currently in progress). But this mode is not the Deep
Power-down mode. The Deep Power-down mode can only be entered by executing the
Deep P o wer-do wn (DP) instruction, subsequently reducing th e standby current (from ICC1 to
ICC2, as specified in Table 13).
Once the device has entered the Deep Power-down mode, all instructions are ignored
except the Release from Deep Power-down and Read Electronic Signature (RES)
instruction. This releases the device from this mode. The Release from Deep Power-down
and Read Electronic Signature (RES) instruction and the Read Identificat ion (RDID)
instru ctio n als o allow the Electron i c Signat ur e of th e device to be output on Ser ial Da ta
output (Q).
The Deep Power-down mode automatically stops at Power-down, and the device always
Powers-up in the Stan d by Power mode.
The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed
by the instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 17.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as
Chip Select (S) is driven High, it requires a delay of tDP bef ore t he supply curr ent is redu ced
to ICC2 and the Deep Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 17. Deep Power-down (DP) instruction sequence
C
D
AI03753D
S
21 345670t
DP
Deep Power-down Mode
Stand-by Mode
Instruction
M25P40 Instructions
33/53
6.12 Release from Deep Power-down and Read Electronic
Signature (RES)
Once the device has entered the Deep Power-down mode, all instructions are ignored
except the Release from Deep Power-down and Read Electronic Signature (RES)
instruction. Executing this instruction takes the device out of the Deep Power-down mode.
The instruction can also be used to read, on Serial Data output (Q), the 8-bit Electronic
Signature, whose value for the M25P40 is 12h.
Except while an Erase, Program or Write Status Register cycle is in progress, the Release
from Deep Power-do wn and Read Electronic Signature (RES) instruction always provides
access to the 8-bit Electronic Signature of the device, and can be applied even if the Deep
Power-down mode has not been entered.
Any Relea se from Deep P o wer-do wn and Read Ele ctronic Signature (R ES) instruction while
an Erase , Progr am or Write Status Register cycle is in progress, is not decoded, and has no
effect on the cycle that is in progress.
The device is first selected by driving Chip Select (S) Low. The instruction code is followed
by 3 dummy bytes, each bit being latched-in on Serial Data input (D) during the rising edge
of Serial Clock ( C). The n, the 8-bit Electronic Sig natu re , sto red in t he memory, is shifted out
on Serial Data output (Q), each bit being shifted out during the falling edge of Serial Clock
(C).
The instruction sequence is shown in Figure 18.
The Release from Deep Power-down and Read Electronic Signature (RES) instruction is
terminated by driving Chip Select (S) High after the Electronic Signature has been read at
least once. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is
driven Low, cause the Electronic Signature to be output repeatedly.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. If the
device was not previously in the Deep Power-down mode, the transition to the Stan dby
Power mode is immediate. If the device was previously in the Deep Pow er-down mode,
though, the transition to the Standby Power mode is delayed by tRES2, and Chip Select (S)
must remain High for at least tRES2(max), as specified in Table 19. Once in the Standby
Power mode, the device waits to be selected, so that it can receive, decode and execute
instructions.
Driving Chip Select (S) High after the 8-bit inst ruction byte has been received by the device,
but before the whole of the 8-bit Electronic Signature has been transmitted for the first time
(as shown in Figure 19), still ensures that the device is put into Standby Power mode. If the
device was not previously in the Deep Power-down mode, the transition to the Stan dby
Power mode is immediate. If the device was previously in the Deep Pow er-down mode,
though, the transition to the Standby Power mode is delayed by tRES1, and Chip Select (S)
must remain High for at least tRES1(max), as specified in Table 19. Once in the Standby
Power mode, the device waits to be selected, so that it can receive, decode and execute
instructions.
Instructions M25P40
34/53
Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) instruction
sequence and data -out sequence
1. The value of the 8-bit Electronic Signature, for the M25P40, is 12h.
Figure 19. Release from Deep Power-down (RES) instruction sequence
C
D
AI04047C
S
Q
23
21 345678910 2829303132333435
2221 3210
36 37 38
765432 0
1
High Impedance Electronic Signature Out
Instruction 3 Dummy Bytes
0
MSB
Stand-by Mode
Deep Power-down Mode
MSB
tRES2
C
D
AI04078B
S
21 345670tRES1
Stand-by Mode
Deep Power-down Mode
QHigh Impedance
Instruction
M25P40 Power-up and Power-down
35/53
7 Power-up and Power-down
At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on VCC) until VCC reaches the correct value:
●VCC(min) at Power-up, and then for a further delay of tVSL
●VSS at Powe r-down
A safe configuration is provided in Section 3: SPI modes.
To avoid data corruption and inadvertent write operations during power-up, a Power On
Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less
than the Power On Reset (POR) threshold voltage, VWI – all operations are disabled, and
the device does not respond to any instruction.
Moreover, the de vice ignores all Write Enable (WREN), Page Program (PP), Sector Erase
(SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of
tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the
correct opera tion of t he device is not guaranteed if, by this time, V CC is still belo w VCC(min).
No Write Status Register, Program or Erase instructions should be sent until the later of:
●tPUW after VCC passed the VWI threshold
●tVSL after VCC passed the VCC(min) level
These values are specified in Table 9.
If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be
selected for READ instructions even if the tPUW delay is not yet fully elapsed.
At Power-up, the device is in the following state:
●The device is in the Standby Power mode (not the De ep Power-down mode).
●The Write Enable Latch (WEL) bit is reset.
●The Write In Progress (WIP) bit is reset.
Normal precautions must be taken for supply rail decoupling, to stabilize the VCC supply.
Each de vice in a system should ha v e the V CC rail decoupled b y a suitab le capacitor close to
the package pins. (Gener ally, this capacitor is of the order of 100 nF).
At Power-down, when VCC drops from the operating voltage, to below the Power On Reset
(POR) threshold voltage, VWI, all operations are disabled and the device does not respond
to any instruction. (The designer needs to be aware that if a Power-down occurs while a
Write, Program or Erase cycle is in prog ress, some data corruption can result.)
Power-up and Power-down M25P40
36/53
Figure 20. Power-up timing
Table 8. Power-up timing and VWI threshold
Symbol Parameter Min. Max. Unit
tVSL(1)
1. These parameters are characterized only.
VCC(min) to S low 10 µs
tPUW(1) Time delay to Write instruction 1 10 ms
VWI(1) Write Inhibit voltage (device grade 6) 1 2 V
Write Inhibit voltage (device grade 3) 1 2.2 V
VCC
AI04009C
VCC(min)
VWI
Reset State
of the
Device
Chip Selection Not Allowed
Program, Erase and Write Commands are Rejected by the Device
tVSL
tPUW
time
Read Access allowed Device fully
accessible
VCC(max)
M25P40 Initial delivery st at e
37/53
8 Initial delivery state
The device is delivered with the memory array erased: all bits are set to 1 (each byte
contains FFh). The Status Register contains 00h (all Status Reg ister bits are 0).
9 Maximum rating
Stressing the device above the rating listed in the Absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exp osur e to abso lute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant qu ality documents.
Table 9. Absolute maximum ratings
Symbol Parameter Min. Max. Unit
TSTG Storage temperature –65 150 °C
TLEAD Lead temperature during soldering see (1)
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
°C
VIO Input and output voltage (with respect to Ground) –0.6 VCC +
0.6 V
VCC Supply voltage –0.6 4.0 V
VESD Electrostatic Discharge voltage (Human Body model)(2)
2. JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).
–2000 2000 V
DC and ac parameters M25P40
38/53
10 DC and ac parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the Measurement Conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurem ent conditions when relying on the quoted parameters.
Table 10. Operating conditions
Symbol Parameter Min. Max. Unit
VCC Supply voltage 2.7 3.6 V
2.3 3.6 V
TAAmbient operating temperature (device grade 6) –40 85 °C
Ambient operating temp erature (device grade 3) –40 125
Table 11. D ata retention and endu rance
Parameter Condition Min. Max. Unit
Erase/Program
cycles Device grade 6 100,000 cycles per sector
Device gr ade 3 10,000
Data Retention at 55°C 20 years
Table 12. Capacitance(1)
1. Sampled only, not 100% tested, at TA=25 °C and a frequency of 25 MHz.
Symbol Parameter Test condition Min. Max. Unit
COUT Output capacitance (Q) VOUT = 0 V 8 pF
CIN Input capacitance (other pins) VIN = 0 V 6 pF
M25P40 DC and ac parameters
39/53
Table 13. DC characteristics (device grade 6)
Symbol Parameter T est condition (in ad dition to
those in Table 10)Min. Max. Unit
ILI Input leakage current ± 2 µA
ILO Output leakage current ± 2 µA
ICC1 Standby current S = VCC, VIN = VSS or VCC 50 µA
ICC2 Deep Power-down current S = VCC, VIN = VSS or VCC 10 µA
ICC3 Operating current (READ)
C = 0.1VCC / 0.9.VCC at
40 MHz and 50 MHz, Q = open 8mA
C = 0.1VCC / 0.9.VCC at
25 MHz, Q = open 4mA
ICC4 Operating current (PP) S = VCC 15 mA
ICC5 Operating current (WRSR) S = VCC 15 mA
ICC6 Operating current (SE) S = VCC 15 mA
ICC7 Operating current (BE) S = VCC 15 mA
VIL Input low voltage –0.5 0.3VCC V
VIH Input high voltage 0.7VCC VCC+0.4 V
VOL Output low voltage IOL = 1.6 mA 0.4 V
VOH Output high voltage IOH = –100 µA VCC–0.2 V
DC and ac parameters M25P40
40/53
Table 14. DC characteristics (device grade 3)
Symbol Parameter Test condition (in addition to
those in Table 10)Min(1)
1. This is preliminary data.
Max(1) Unit
ILI Input leakage current ± 2 µA
ILO Output leakage current ± 2 µA
ICC1 Standby current S = VCC, VIN = VSS or VCC 100 µA
ICC2 Deep Power-down current S = VCC, VIN = VSS or VCC 50 µA
ICC3 Operating current (READ)
C = 0.1VCC / 0.9.VCC at 25 MHz,
Q = open 8mA
C = 0.1VCC / 0.9.VCC at 20 MHz,
Q = open 4mA
ICC4 Operating current (PP) S = VCC 15 mA
ICC5 Operating current (WRSR) S = VCC 15 mA
ICC6 Operating current (SE) S = VCC 15 mA
ICC7 Operating current (BE) S = VCC 15 mA
VIL Input low voltage – 0.5 0.3VCC V
VIH Input high voltage 0.7VCC VCC+0.4 V
VOL Output low voltage IOL = 1.6 mA 0.4 V
VOH Output high voltage IOH = –100 µA VCC–0.2 V
Table 15. Instruction times (device grade 6)
Test conditions specified in Table 10 and Table 17
Symbol Alt. Parameter Min. Typ. Max. Unit
tWWrite Status Register cycle time 5 15 ms
tPP (1)
1. When using the Page Program (PP) instruction to program consecutive bytes, optimized timings are
obtained with one sequence including all the bytes versus several sequences of only a few bytes. (1 ≤ n ≤
256)
Page Program cycle time (256 bytes) 1.4 5ms
Page Program cycle time (n bytes) 0.4+
n*1/256
tSE Sector Erase cycle time 1 3 s
tBE Bulk Erase cycle time 4.5 10 s
M25P40 DC and ac parameters
41/53
1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 21. AC measurement I/O waveform
Table 16. Instruction times (device grade 3)
Test conditions specified in Table 10 and Table 17
Symbol Alt. Parameter Min. Typ.(1) (2)
1. At 85 °C
2. Preliminary data.
Max.(2) Unit
tWWrite Status Register cycle time 8 15 ms
tPP(3)
3. When using the Page Program (PP) instruction to program consecutive bytes, optimized timings are
obtained with one sequence including all the bytes versus several sequences of only a few bytes. (1 ≤ n ≤
256)
Page Program cycle time (256 bytes) 1.5 5ms
Page Program cycle time (n bytes) 0.4+
n*1.1/256
tSE Sector Erase cycle time 1 3 s
tBE Bulk Erase cycle time 4.5 10 s
Table 17. AC measurement conditions
Symbol Parameter Min. Max. Unit
CLLoad capacitance 30 pF
Input rise and fall times 5 ns
Input pulse voltages 0.2VCC to 0.8VCC V
Input timing reference voltages 0.3VCC to 0.7VCC V
Output timing reference voltages VCC / 2 V
Table 18. Which AC characteristics to use?
Device grade VCC = 2.3 V to 3.6 V VCC = 2.7 V to 3.6 V
Device grade 3 N/A(1)
1. Not applicable.
A C char acteristics at 25 MHz (Table 19)
De vice grade 6 AC char acteristics at 40 MHz (Table 21) AC characteristics at 50 MHz (Table 20)
AI07455
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Input and Output
Timing Reference Levels
Input Levels
0.5VCC
DC and ac parameters M25P40
42/53
Table 19. AC characteristics (25 MHz operation, device grade 3, VCC min = 2.7 V)
Test conditions specified in Table 10 and Table 17
Symbol Alt. Parameter Min. Typ. Max. Unit
fCfC
Clock frequency for the following
instructions: FAST_READ, PP, SE, BE, DP,
RES, WREN, WRDI, RDSR, WRSR D.C. 25 MHz
fRClock frequency for READ instructions D.C. 20 MHz
tCH(1)
1. tCH + tCL must be greater than or equal to 1/ fC
tCLH Clock High time 18 ns
tCL(1) tCLL Clock Low time 18 ns
tCLCH(2)
2. Value guaranteed by characterization, not 100% tested in production.
Clock Rise time(3) (peak to peak)
3. Expressed as a slew-rate.
0.1 V/ns
tCHCL(2) Clock Fall time(3) (peak to peak) 0.1 V/ns
tSLCH tCSS S Active Setup time (relati ve to C) 10 ns
tCHSL S Not Active Hold time (relative to C) 10 ns
tDVCH tDSU Data In Setup time 5 ns
tCHDX tDH Data In Hold time 5 ns
tCHSH S Active Hold time (relative to C) 10 ns
tSHCH S Not Active Setup time (relative to C) 10 ns
tSHSL tCSH S Deselect time 100 ns
tSHQZ(2) tDIS Output Disable time 15 ns
tCLQV tVClock Low to Output Valid 15 ns
tCLQX tHO Output Hold time 0 ns
tHLCH HOLD Setup time (relative to C) 10 ns
tCHHH HOLD Hold time (relative to C) 10 ns
tHHCH HOLD Setup time (relative to C) 10 ns
tCHHL HOLD Hold time (relative to C) 10 ns
tHHQX(2) tLZ HOLD to Output Low-Z 15 ns
tHLQZ(2) tHZ HOLD to Output High-Z 20 ns
tWHSL(4)
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
Write Protect Setup time 20 ns
tSHWL(4) Write Protect Hold time 100 ns
tDP(2) S High to Deep Power-down mode 3 µs
tRES1(2) S High to Standby Power mode without
Electronic Signature Read 3 or 30(5)
5. It is 30 µs in devices produced with the “X” process technology (grade 3 devices are only produced using
the “X” process technology). Details of how to find the process letter on the device marking are given in the
Application note AN1995.
µs
tRES2(2) S High to Standby Power mode with
Electronic Signature Read 1.8 or 30(5) µs
M25P40 DC and ac parameters
43/53
Table 20. AC characteristics (50 MHz operation, device grade 6, VCC min = 2.7 V)
50 MHz available only in products with Process Technology code X(1)
Test conditions specified in Table 10 and Table 17
1. Details of how to find the date of marking are given in Application Note, AN1995.
Symbol Alt. Parameter Min. Typ. Max. Unit
fCfC
Clock frequency for the following
instructions: FAST_READ, PP, SE, BE, DP,
RES, WREN, RDID, WRDI, RDSR, WRSR D.C. 50 MHz
fRClock frequency for READ instructions D.C. 25 MH z
tCH(2)
2. tCH + tCL must be greater than or equal to 1/ fC
tCLH Clock High time 9 ns
tCL(2) tCLL Clock Low time 9 ns
tCLCH(3)
3. Value guaranteed by characterization, not 100% tested in production.
Clock Rise time(4) (peak to peak)
4. Expressed as a slew-rate.
0.1 V/ns
tCHCL(3) Clock Fall time(4) (peak to peak) 0.1 V/ns
tSLCH tCSS S Active Setup time (relative to C) 5 ns
tCHSL S Not Active Hold time (relative to C) 5 ns
tDVCH tDSU Data In Setup time 2 ns
tCHDX tDH Data In Hold time 5 ns
tCHSH S Active Hold time (relative to C) 5 ns
tSHCH S Not Active Setup time (relative to C) 5 ns
tSHSL tCSH S Deselect time 100 ns
tSHQZ(3) tDIS Output Disable time 8 ns
tCLQV tVClock Low to Output Valid 8 ns
tCLQX tHO Output Hold time 0 ns
tHLCH HOLD Setup time (relative to C) 5 ns
tCHHH HOLD Hold time (relative to C) 5 ns
tHHCH HOLD Setup time (relative to C) 5 ns
tCHHL HOLD Hold time (relative to C) 5 ns
tHHQX(3) tLZ HOLD to Output Low-Z 8 ns
tHLQZ(3) tHZ HOLD to Output High-Z 8 ns
tWHSL(5)
5. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
Write Protect Setup time 20 ns
tSHWL(5) Write Protect Hold time 100 ns
tDP(3) S High to Deep Power-down mode 3 µs
tRES1(3) S High to Standby Power mode without
Electronic Signature Read 30 µs
tRES2(3) S High to Standby Power mode with
Electronic Signature Read 30 µs
DC and ac parameters M25P40
44/53
Table 21. AC characteristics (40 MHz operation, device grade 6, VCC min = 2.3 V)
Extended VCC range available only in products with Process Technology code X(1)
Test conditions specified in Table 10 and Table 17
1. Details of how to find the date of marking are given in Application Note, AN1995.
Symbol Alt. Parameter Min. Typ. Max. Unit
fCfC
Clock frequency for the following
instructions: FAST_READ, PP, SE, BE, DP,
RES, WREN, RDID, WRDI, RDSR, WRSR D.C. 40 MHz
fRClock frequency for READ instructions D.C. 25 MHz
tCH(2)
2. tCH + tCL must be greater than or equal to 1/ fC
tCLH Clock High time 11 ns
tCL(2) tCLL Clock Low time 11 ns
tCLCH(3)
3. Value guaranteed by characterization, not 100% tested in production.
Clock Rise time(4) (peak to peak)
4. Expressed as a slew-rate.
0.1 V/ns
tCHCL(3) Clock Fall time(4) (peak to peak) 0.1 V/ns
tSLCH tCSS S Active Setup time (relative to C) 5 ns
tCHSL S Not Active Hold time (relative to C) 5 ns
tDVCH tDSU Data In Setup time 2 n s
tCHDX tDH Data In Hold time 5 ns
tCHSH S Active Hold time (relative to C) 5 ns
tSHCH S Not Active Setup time (relative to C) 5 ns
tSHSL tCSH S Deselect time 100 ns
tSHQZ(3) tDIS Output Disable time 8 ns
tCLQV tVClock Low to Output Valid 8 ns
tCLQX tHO Output Hold time 0 ns
tHLCH HOLD Setup time (relative to C) 5 ns
tCHHH HOLD Hold time (relative to C) 5 ns
tHHCH HOLD Setup time (relative to C) 5 ns
tCHHL HOLD Hold time (relative to C) 5 ns
tHHQX(3) tLZ HOLD to Output Low-Z 8 ns
tHLQZ(3) tHZ HOLD to Output High-Z 8 ns
tWHSL(5)
5. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
Write Protect Setup time 20 ns
tSHWL(5) Write Protect Hold time 100 ns
tDP(3) S High to Deep Power-down mode 3 µs
tRES1(3) S High to Standby Power mode without
Electronic Signature Read 30 µs
tRES2(3) S High to Standby Power mode with
Electronic Signature Read 30 µs
M25P40 DC and ac parameters
45/53
Figure 22. Serial input timing
Figure 23. Write Protect setup and hold timing during WRSR when SRWD = 1
C
D
S
MSB IN
Q
tDVCH
High Impedance
LSB IN
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
C
D
S
Q
High Impedance
W
tWHSL tSHWL
AI07439
DC and ac parameters M25P40
46/53
Figure 24. Hold timing
Figure 25. Output timing
C
Q
AI02032
S
D
HOLD
tCHHL
tHLCH
tHHCH
tCHHH
tHHQXtHLQZ
C
Q
AI01449e
S
LSB OUT
DADDR.
LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCLQX
tCLQV
tCLQX
tCLQV
M25P40 Package mechanical
47/53
11 Package mechanical
Figure 26. SO8 narrow – 8 lead plastic Small Outline, 150 mils body width, package
outline
1. Drawing is not to scale.
2. The ‘1’ that appears in the top view of the package shows the position of pin 1.
Table 22. SO8 narrow – 8 l ead plastic Small Outline, 150 mils body width,
package mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A1.750.069
A1 0.10 0.25 0.004 0.010
A2 1.25 0.049
b 0.28 0.48 0.011 0.019
c 0.17 0.23 0.007 0.009
ccc 0.10 0.004
D 4.90 4.80 5.00 0.193 0.189 0.197
E 6.00 5.80 6.20 0.236 0.228 0.244
E1 3.90 3.80 4.00 0.154 0.150 0.157
e1.27– –0.050– –
h 0.25 0.50 0.010 0.020
k0°8°0°8°
L 0.40 1.27 0.016 0.050
L1 1.04 0.041
SO-A
E1
8
ccc
be
A
D
c
1E
h x 45˚
A2
k
0.25 mm
L
L1
A1
GAUGE PLANE
Package mechanical M25P40
48/53
Figure 27. VFQFPN8 (MLP8) 8-lead Very thin Fine pitch Quad Flat Package No lead,
6 × 5 mm, package outline
1. Drawing is not to scale.
2. The circle in the top view of the package indicates the position of pin 1.
Table 23. VFQFPN8 (MLP8) 8-lead Very thin Fine pitch Quad Flat Package No lead,
6 × 5 mm, package mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 0.85 0.80 1.00 0.0335 0.0315 0.0394
A1 0.00 0.05 0.0000 0.0020
A2 0.65 0.0256
A3 0.20 0.0079
b 0.40 0.35 0.48 0.0157 0.0138 0.0189
D 6.00 0.2362
D1 5.75 0.2264
D2 3.40 3.20 3.60 0.1339 0.1260 0.1417
E 5.00 0.1969
E1 4.75 0.1870
E2 4.00 3.80 4.30 0.1575 0.1496 0.1693
e1.27– –0.0500– –
R1 0.10 0.00 0.0039 0.0000
L 0.60 0.50 0.75 0.0236 0.0197 0.0295
Q 12° 12°
aaa 0.15 0.0059
bbb 0.10 0.0039
ddd 0.05 0.0020
D
E
70-ME
A2
AA3
A1
E1
D1
eE2
D2
L
b
θ
R1
ddd
bbb
C
CAB
aaa CAA
B
aaa CB
M
0.10 CA
0.10 CB
2x
M25P40 Part numbering
49/53
12 Part numbering
F o r a list of availab le opt ions (s peed, package, etc.) or for further inf ormation on an y aspect
of this device, ple ase contact your nearest ST Sales Office.
The category of second-Level Interconnect is marked on the package and on the inner box
label, in compliance with JEDEC Standar d JESD97. The maximu m ratings relat ed to
soldering conditions are also marked on the inner box label.
Table 24. Ordering information scheme
Example: M25P40 – V MN 6 T P /X
Device Type
M25P = Serial Flas h memory for Code Storage
Device Function
40 = 4 Mbit (512 K x 8)
Operating Voltag e
V = VCC = 2.3 V to 3.6 V
Package
MN = SO8 (150 mil width)
MP = VFQFPN8 6 x 5 mm (MLP8)
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
3(1) = Device tested with High Reliability Cer tified Flow(2).
A u tomotive temperature range (–40 to 125 °C)
1. Device grade 3 available in an SO8 ECOPACK® (RoHS compliant) package.
2. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.
The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your
nearest ST sales office for a copy.
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating technology
P or G = ECOPA CK® (RoHS compliant)
Process(3)
3. The process letter (/X) is specified in the ordering information of grade 3 devices only.
For grade 6 devices, the process letter does not appear in the Ordering Information, it only appears on the
device package (marking) and on the shipment box. Please contact your nearest ST Sales Office.
For more information on how to identify products by the Process Identification Letter, please refer to
AN1995: Serial Flash Memory Device Marking.
/X = T7Y
Revision history M25P40
50/53
13 Revision history
Table 25. Document revision history
Date Revision Changes
12-Apr-2001 1.0 Document written.
25-May-2001 1.1 Serial Paged Flash Memory renamed as Serial Flash Memory.
11-Sep-2001 1.2
Changes to te xt: Signal Description/Chip Select; Hold Condition/1st para;
Protection modes; Release from Power-down and Read Electronic
Signature (RES); Power-up.
Repositionin g of several tables and illustrations without changing their
contents.
Power-up timing illustration; SO8W package removed.
Changes to tables: Abs Max Ratings/VIO; DC Characteristics/VIL.
16-Jan-2002 1.3
FAST_READ instruction added. Document revised with new timings , VWI,
ICC3 and clock slew rate. Descriptions of Polling, Hold Condition, Page
Programming, Release for Deep Power-down made more precise. Value
of tW(max) modified.
12-Sep-2002 1.4
Clarification of descriptions of entering Standb y Power mode from Deep
Power-down mode, and of terminating an instruction sequence or data-
out sequence.
VFQFPN8 package (MLP8) added. Document promoted to Preliminary
Data.
13-Dec-2002 1.5
Typical Page Program time improved. Deep Power-down current
changed. Write Protect setup and hold times specified, for applications
that switch Write Protect to exit the Hardware Protection mode
immediately before a WRSR, and to enter the Hardware Protection mode
again immediately after.
12-Jun-2003 1.6 Document promoted from Preliminary Data to full Datasheet.
24-Nov-2003 2.0
Table of contents, warning about exposed paddle on MLP8, and Pb-free
options added.
40 MHz AC Characteristics table included as well as 25 MHz. ICC3(max),
tSE(typ) and tBE(typ) values improved. Change of naming for VDFPN8
package.
12-Mar-2004 3.0 Automotiv e range added. Soldering temperature information clarified for
RoHS compliant devices.
05-Aug-2004 4.0 Device grade information clarified. Data-retention measurement
temperature corrected. Details of how to find the date of marking added.
03-Jan-2005 5.0 Small text changes. Notes 2 and 3 removed from Table 24: Ordering
inf ormation scheme.
End timing line of tSHQZ modified in Figure 25: Output timing.
01-Aug-2005 6.0 Updated Page Program (PP) instructions in Page Programming, Page
Program (PP), Instruction times (device grade 6) and Instruction times
(device grade 3).
M25P40 Revision history
51/53
24-Oct-2005 7.0
50 MHz operation added (see Table 20: AC characteristics (50 MHz
operation, device grade 6, VCC min = 2.7 V)). All packages are
ECOPACK®. Blank option removed from under Plating technology in
Table 24: Ordering information scheme . MLP package renamed as
VFQFPN, silhouette and pac kage mechanical drawing updated (see on
page 1 and Figure 27: VFQFPN8 (MLP8) 8-lead Very thin Fine pitch
Quad Flat Package No lead, 6 × 5 mm, package outline.
22-Dec-2005 8.0
Note 2 added below Figure 26 and note 1 added below Figure 27
tRES1 and tRES2 modified in Table 20: AC characteristics (50 MHz
operation, device grade 6, VCC min = 2.7 V).
Read Identification (RDID) added. Titles of Figure 27 and Table 23
corrected.
14-Apr-2006 9
The data contained in Table 11, Table 16 and Table 19 is no longer
preliminary data.
Figure 3: Bus Master and memory devices on the SPI bus modified and
Note 2 added.
40 MHz frequency condition modified for ICC3 in Table 14: DC
character istics (device grade 3).
Table 16: Instru ction times (device grade 3) shows preliminary data.
Condition changed for the Data Retention parameter in Table 11: Data
retention and endu rance. VWI parameter for device grade 3 added to
Table 8: Power-up timing and VWI threshold.
SO8 package specifications updated (see Figure 26 and Table 22).
/X Process added to Table 24: Ordering information scheme.
05-Jun-2006 10
tRES1 and tRES2 parameter timings changed for de vices produced with the
“X” process technology in Table 19 and Table 19.
SO8 Narrow package specifications updated (see Figure 26 and
Table 22).
18-Dec-2006 11
Hardware Write Protection feature added on page 1. Small text changes.
Section 2.7: VCC supply voltage and Section 2.8: VSS ground added.
Figure 3: Bus Master and memory devices on the SPI bus modified,
note 2 removed and replaced by explanatory paragraph.
WIP bit behavior specified at Power-up in Section 7: Power-up and
Power-down. TLEAD added to Table 9: Absolute maximu m ratings and VIO
max modified.
VFQFPN8 package specifications updated (see Table 23 and Figure 27).
25-Jan-2007 12
VCC voltage range from W17 2007 is extended to 2.3 V to 3.6 V.
Table 21: AC characteristics (33 MHz operation, device g r ade 6, VCCmin
=2.3 V) added.
Table 18: Which AC characteristics to use? added. AC characteristics at
40 MHz remove d.
Table 25. Document revision history (continued)
Date Revision Changes
Revision history M25P40
52/53
15-May-2007 13
40 MHz operation added (see Table 21: AC characteristics (40 MHz
operation, device grade 6, VCC min = 2.3 V).
Removed the note below Table 10.
Removed “AC characteristics (33 MHz operation, device grade 6,
VCCmin =2.3 V)” Table.
26-Jun-2007 14 Modified the note below Table 12.
Changed test condition for ICC3 in Table 13.
Changed clock frequency, from 20 to 25 MHz, in Table 20 and Table 21.
Table 25. Document revision history (continued)
Date Revision Changes
M25P40
53/53
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and co nditions of sale.
Purchasers a re so lel y res ponsibl e fo r th e choic e, se lecti on an d use o f th e ST pr oduc ts and s ervi ces d escr ibed he rein , and ST as sumes no
liability whatsoever relating to the choice, se lection or use of the ST products and ser vices described he rein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document ref er s to an y t hi rd pa rt y p roduc t s or serv ic es it sh al l n ot be dee med a li ce nse gr an t by ST for t he use of su ch t hi rd party products
or services, or any intel lectual pro perty conta ined therei n or considere d as a warranty covering the use in any mann er whatsoev er of such
third party products or services or any intellectual property co ntained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTAB ILIT Y, FITNESS F OR A PARTI CULAR PURPOS E (AND THEIR EQUIVALE NTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warrant y granted by ST for the S T product or se rvice descr ibed herein a nd shall no t create or e xtend in any manner whatsoe ver, any
liability of ST.
ST and the ST lo go are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2007 STMicroelectronics - All rights reserved
STMicroele ctr on ic s gr ou p of companies
Australia - Belgium - Brazil - Canad a - China - Czech Republic - Finland - France - Ger many - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
