85
TM
March 1997
HM-6518/883
1024 x 1 CMOS RAM
Features
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provi sions of
Paragraph 1.2.1.
• Low Power Standby. . . . . . . . . . . . . . . . . . . . 50µW Max
• L o w Power O pe r a tio n . . . . . . . . . . . . . .20m W/MH z Max
• Fast Access Time . . . . . . . . . . . . . . . . . . . . . 180ns Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min
• TTL Compatible I nput/Output
• High Output Drive - 2 TTL Loads
• High Noise Immunity
• On-Chip Address Register
• Two-Chip Selects for Easy Arr ay Expansion
• Three-State Output
Description
The HM-6518/883 is a 1024 x 1 static CMOS RAM
fabricated using self-aligned silicon gate technology.
Synchronous circuit design techniques are employed to
achieve high perf ormance and low power operati on.
On chip latches are provided for address and data outputs
allowing efficient interfacing with microprocessor systems.
The data output buffers can be forced to a high impedance
state for use in expanded memory arrays.
The HM-6518/883 is a fully static RAM and may be
maintained in any state for an indefinite period of time. Data
retention supply voltage and supply current are guaranteed
over temperatur e.
Pinout
HM-6518/883
(CERDIP)
TOP VIEW
Ordering Information
PACKAGE TEMP. RANGE PART
NUMBER PKG. NO.
CERDIP -55oC to +125oC HM1-6518/883 F18.3
PIN DESCRIPTION
A A ddr ess Input
EChip Enable
WWrite Enable
S C hi p Sel ec t
D Data Input
Q Data Output
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1VCC
D
W
A9
A8
A7
A6
S2
A5
S1
E
A0
A1
A2
A3
Q
A4
GND
FN2986.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1- 888-IN TER SIL or 321-724-7143 |Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
86
Functional Dia gram
NOTES:
1. All line s posi tive logi c - active h igh.
2. Three-state buffers: A high → output active.
3. Data latches: L high → Q = D; Q Latches on rising edge of L.
4. Address lat ches and gated decoders: Latch on falling edg e of E an d ga te on falling edg e of E.
5
A
LATCHED ADDRESS
REGISTER
LATCHED
ADDRESS
REGISTER
GATED
ROW
DECODER
32
GATED COLUMN
DECODER
AND DATA I/O
E
W
Q
A5
A4A3A2A1A0
32 x 32
MATRIX
55
AA
32
5
A
A6
A7
A8
A9
DA
A
G
LATCH
D
L
Q
S1,
S2
HM-6518/883
87
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Ope rat i ng Condit io ns
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . .VCC -2.0V to VCC
Input Rise and Fall Time. . . . . . . . . . . . . . . . . . . . . . . . . . .40ns Max
Thermal Resistance (Typical, Note 1) θJA θJC
CERDIP Package . . . . . . . . . . . . . . . . 75oC/W 15oC/W
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1936 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only r ating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is me asured with the compon ent mounted on an evaluation PC board in free air.
TABLE 1. HM-6518/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER SYMBOL (NOTE 1)
CONDITIONS GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
Output Low Voltage VOL VCC = 4.5V,
IOL = 3.2mA 1, 2, 3 -55oC ≤ TA ≤ +125oC- 0.4 V
Output High Voltage VOH VCC = 4.5V,
IOH = -0.4mA 1, 2, 3 -55oC ≤ TA ≤ +125oC2.4 - V
Input Leakage Current II VCC = 5.5V,
VI = GND or VCC 1, 2, 3 -55oC ≤ TA ≤ +125oC -1.0 +1.0 µA
Output Leakage Current IOZ VCC = 5.5V,
VO = GND or VCC 1, 2, 3 -55oC ≤ TA ≤ +125oC -1.0 +1.0 µA
Data Retention Supply Current ICCDR VCC = 2.0V,
E = VCC,
IO = 0mA,
VI = VCC or GND
1, 2, 3 -55oC ≤ TA ≤ +125oC
-5µAHM-6518B/883
HM-6518/883 -10µA
Operating Supply Current ICCOP VCC = 5.5V,
(No te 2),
E = 1MHz,
IO = 0mA,
VI = VCC or GND
1, 2, 3 -55oC ≤ TA ≤ +125oC- 4 mA
Standby Supply Current ICCSB VCC = 5.5V,
IO = 0mA,
VI = VCC or GND
1, 2, 3 -55oC ≤ TA ≤ +125oC- 10 µA
NOTES:
1. Al l voltages r eferenced to device GND.
2. Typical derating 1.5mA/MHz increase in ICCOP.
HM-6518/883
88
TABLE 2. HM-6518/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER SYMBOL (NOTE S 1, 2)
CONDITIONS
GROUP A
SUB-
GROUPS TEMPERATURE
LIMITS
UNITS
HM-6518B/883 HM-6518/883
MIN MAX MIN MAX
Chip Enable
Access Time (1) TELQV VCC = 4.5 and
5.5V 9, 10, 11 -55oC ≤ TA ≤ +125 oC- 180 - 250 ns
Address Access
Time (2) TAVQV VCC = 4.5 and
5.5V, Note 3 9, 10, 11 -55oC ≤ TA ≤ +125 oC- 180 - 250 ns
Chip Select
Output Enable
Time
(3) TSLQX VCC = 4.5 and
5.5V 9, 10, 11 -55oC ≤ TA ≤ +125 oC5-5-ns
Write Enable
Output Disable
Time
(4) TWLQZ VCC = 4.5 and
5.5V 9, 10, 11 -55oC ≤ TA ≤ +125 oC- 120 - 160 ns
Chip Select
Output Disable
Time
(5) TSHQZ VCC = 4.5 and
5.5V 9, 10, 11 -55oC ≤ TA ≤ +125 oC- 120 - 160 ns
Chip Enable P ulse
Negative Width (6) TELEH VCC = 4.5 and
5.5V 9, 10, 11 -55oC ≤ TA ≤ +125 oC180 - 250 - ns
Chip Enable P ulse
Positive Widt h (7) TE HEL VCC = 4.5 and
5.5V 9, 10, 11 -55oC ≤ TA ≤ +125 oC100 - 100 - ns
Address Setup
Time (8) TAVEL VCC = 4.5 and
5.5V 9, 10, 11 -55oC ≤ TA ≤ +125 oC0-0-ns
Address Hold Time (9) TELAX VCC = 4.5 and
5.5V 9, 10, 11 -55oC ≤ TA ≤ +125 oC40 - 50 - ns
Data Setup Time (10) T DV WH VCC = 4.5 and
5.5V 9, 10, 11 -55oC ≤ TA ≤ +125 oC80 - 110 - ns
Data Hold Time (11) T WHDX VCC = 4.5 and
5.5V 9, 10, 11 -55oC ≤ TA ≤ +125 oC0-0-ns
Chip Se lect Write
Pulse Setup Time (12) TW LSH VCC = 4.5 and
5.5V 9, 10, 11 -55oC ≤ TA ≤ +125 oC100 - 130 - ns
Chip Enable Write
Pulse Setup Time (13) TW LEH VCC = 4.5 and
5.5V 9, 10, 11 -55oC ≤ TA ≤ +125 oC100 - 130 - ns
Chip Se lect Write
Pu lse Hold Ti me (1 4) TS LWH VCC = 4.5 and
5.5V 9, 10, 11 -55oC ≤ TA ≤ +125 oC100 - 130 - ns
Chip Enable Write
Pu lse Hold Ti me (1 5) TE LWH VCC = 4.5 and
5.5V 9, 10, 11 -55oC ≤ TA ≤ +125 oC100 - 130 - ns
Write Enable Pulse
Width (1 6) TWL-
WH VCC = 4.5 and
5.5V 9, 10, 11 -55oC ≤ TA ≤ +125 oC100 - 130 - ns
Read or Write
Cycle Time (17) TELEL VCC = 4.5 and
5.5V 9, 10, 11 -55oC ≤ TA ≤ +125 oC280 - 350 - ns
NOTES:
1. All v oltages refere nced to device GND.
2. Input pulse levels: 0.8V to VCC -2.0V; input rise and fall times: 5ns (max); input and output timing reference level: 1.5V; output lo ad:
-1TTL gate equivalent, CL = 50pF (min ) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
3. TAVQV = TELQV + TAVEL.
HM-6518/883
89
Timing Waveforms
TABLE 3. HM-6518/883 ELECTRICAL PERFORMANCE SPECIFICATIONS
PARAMETER SYMBOL CONDITIONS NOTE TEMPERATURE
LIMITS
UNITSMIN MAX
Input Capacita nce CI VCC = Op en, f = 1MHz , All Measure-
ments Referenced to Device Ground 1T
A = +25oC-6pF
Out put Capacita nce CO VCC = Open, f = 1MHz, A ll Measure -
ments Referenced to Device Ground 1T
A = +25oC - 10 pF
NOTE: 1. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design an d afte r
major process and/or design changes.
TABLE 4 . A PPLICABLE SUBGROUPS
CONFORMANCE GROUPS METHOD SUBGROUPS
Initial Test 100%/5004 -
I nte r i m Tes t 100%/5 00 4 1, 7, 9
PDA 100%/5004 1
Final Test 100%/5004 2, 3, 8A, 8B, 10, 11
Group A Samples/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Groups C & D Samples/5005 1, 7, 9
FIGURE 1. READ CYCLE
(8)
TAVEL
(9)
TELAX
TEHEL (7) TELEH (6)
(8)
TAVEL
TELEL (17)
HIGH
NEXT
PREVIOUS
DATA HIGH Z HIGH Z
VALID OUTPUT LATCHED
TAVQV (2)
TSHQZ (5) TSLOX
(3) (5) TSHQZ
-1
TIME
012345
REFERENCE
1
A
E
W
D
Q
TELQV (1)
S1,
S2
TEHEL (7)
VALID
HM-6518/883
90
In the HM-6518/883 re ad cycle the ad dress information is
latched into the on chip registers on the falling edge of E
(T = 0). Minimum address setup and hold time require-
ments must be met. After the required hold time the
addresses may change state without affecting device
operation. In order fo r the output to be read S1, S2 and E
must
be low, W must be high. Wh en E goes high the output data
is latched into an on chip register. Taking either or both S1
or S2 high, forces the output buffer to a high impedance
state. The output data may be re-enabled at any time by
Timing Waveforms
TRUTH TABLE
TIME
REFERENCE
INPUTS OUTPUTS
FUNCTIONES1 WAD Q
-1 H H X X X Z Memory Disabled
0 X H V X Z Cycle Begins, Addresses are Latched
1 L L H X X X Output Enabled
2 L L H X X V Output Valid
3 L H X X V O u tp ut La tc he d
4 H H X X X Z D evice Disabled, Prepare for Next Cycle
(Same as -1)
5 X H V X Z Cycle Ends, Next Cycle Begins
(Same as 0)
NOTE: 1. Device selected only if both S1 and S2 are low, and deselected if ei ther S1 or S 2 are high.
TIME
REFERENCE
(8) TAVEL TELAX
(9)
(8) TAVEL
NEXT
TELEL (17) TEHEL (7)TELEH (6)TEHEL (7)
TWLEH (13)
TWLWH (16)
VALID DATA
TDVWH (10) TWHDX (11)
HIGH Z
-1 01 2345
A
E
W
D
Q
VALID
FIGURE 2. WRITE CYCLE
TELWH (15)
TWLSH (12)
TSLWH (14)
S1,
S2
HM-6518/883
91
The write cycle is initiated by the falling edge of E which
latches the address information into the on chip registers.
The write portion of the cycle is defined as E, W, S1 and S2
being low simultaneously. W may go low anytime during the
cycle provided that the write enable pulse setup time
(TWLEH) is met. The write portion of the cycle is terminated
by the first rising edge of either E, W, S1 or S2. Data se tup
and hold times must be referenced to the terminating signal.
If a series of consecutive write cycles are to be performed,
the W line may remain low until all desired locations have
been writte n. When th is method is used, data setup and hold
times must be refer enced to the ris ing edge of E.
By posit ioning the W pulse at different times within the E low
time (TELEH), various types of write cycles may be
performed. If the E low time (TELEH) is greater than the W
pulse (TWLWH), plus an output enable time (TSLQX), a
combination read write cycle is executed. Data may be
modified an indefin it e num ber of ti m es during any write cycle
(TELEH).
The data input and data output pins may be tied together for
use with a common I/O data bus structure. When using the
RAM in this method allow a minimum of one output disable
time (TWLQZ) after W go es low before applying input data to
the bus. This will ensure that the output buffers are not
active.
Test Lo ad Circuit
NOTE:
1. Test head capacitance includes stray and jig capacitance.
TRUTH TABLE
TIME
REFERENCE
INPUTS OUTPUTS
FUNCTIONES1 W AD Q
-1 HXXXX ZMemory Disabled
0 XXVX ZCycle Begins, Addresses are Latched
1 L L L X V Z Write Mode has Begun
2 L L X V Z Data is Written
3 XXXX ZWrite Completed
4 HXXXX ZPrepare for Next Cycle (Same as -1)
5 XXVX ZCycle Ends, Next Cycle Begins (Same as 0)
NOTE: 1. Device selected only if both S1 and S2 are low, and dese lected if either S1 or S 2 are high.
DUT
1.5V IOLIOH +
-
(NOTE 1) CL
EQUIVALENT CIRCUIT
HM-6518/883
92
Burn-In Circuit
HM-6518/883 CERDIP
NOTES:
All resistors 47kΩ ±5%.
F0 = 100kHz ±10%.
F1 = F0 ÷ 2, F2 = F1 ÷ 2, F3 = F2 ÷ 2. . . . F1 2 = F11 ÷ 2.
VCC = 5.5V ±0.5V.
VIH = 4.5V ±10%.
VIL = -0.2V to +0.4V.
C1 = 0.01µF Min.
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
A0
A1
A2
A3
A4
GND
VCC
D
A9
A8
A7
A6
C1
VCC
Q
A5
S1
ES2
W
F0
F0
F3
F4
F5
F6
F7
F2
F0
F2
F1
F12
F11
F10
F9
F8
HM-6518/883
93
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Intersil Corporati on’s quali ty certifi cations can be viewed at www. int ersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsi diaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Die Charact eris tics
DIE DIMENSIONS:
130 x 150 x 19 ±1mils
METALLIZATION:
Type: Si - Al
Thickness: 11kÅ ±2kÅ
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
1.342 x 105 A/cm2
Metallization Mask Layout
HM-6518/883
NOTE: Pin numbers correspond to DIP package only.
ES1 VCC S2
D
W
A9
A8
A7
A6
A5GNDQ
A4
A3
A2
A1
A0
HM-6518/883